Sam Shi
customized font for Unyte
Dependencies: Adafruit_GFX_customizedfont BLE_API USBDevice mbed
Fork of
mbed-os-example-mbed5-blinky
by 
mbed-os-examples
max32600.h@32:a1b2391b0c35, 2017-07-18 (annotated)
- Committer:
- SamShiSS
- Date:
- Tue Jul 18 14:57:27 2017 +0000
- Revision:
- 32:a1b2391b0c35
customized Unyte font
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| SamShiSS | 32:a1b2391b0c35 | 1 | /******************************************************************************* |
| SamShiSS | 32:a1b2391b0c35 | 2 | * Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved. |
| SamShiSS | 32:a1b2391b0c35 | 3 | * |
| SamShiSS | 32:a1b2391b0c35 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| SamShiSS | 32:a1b2391b0c35 | 5 | * copy of this software and associated documentation files (the "Software"), |
| SamShiSS | 32:a1b2391b0c35 | 6 | * to deal in the Software without restriction, including without limitation |
| SamShiSS | 32:a1b2391b0c35 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| SamShiSS | 32:a1b2391b0c35 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| SamShiSS | 32:a1b2391b0c35 | 9 | * Software is furnished to do so, subject to the following conditions: |
| SamShiSS | 32:a1b2391b0c35 | 10 | * |
| SamShiSS | 32:a1b2391b0c35 | 11 | * The above copyright notice and this permission notice shall be included |
| SamShiSS | 32:a1b2391b0c35 | 12 | * in all copies or substantial portions of the Software. |
| SamShiSS | 32:a1b2391b0c35 | 13 | * |
| SamShiSS | 32:a1b2391b0c35 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| SamShiSS | 32:a1b2391b0c35 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| SamShiSS | 32:a1b2391b0c35 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| SamShiSS | 32:a1b2391b0c35 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| SamShiSS | 32:a1b2391b0c35 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| SamShiSS | 32:a1b2391b0c35 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| SamShiSS | 32:a1b2391b0c35 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| SamShiSS | 32:a1b2391b0c35 | 21 | * |
| SamShiSS | 32:a1b2391b0c35 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| SamShiSS | 32:a1b2391b0c35 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| SamShiSS | 32:a1b2391b0c35 | 24 | * Products, Inc. Branding Policy. |
| SamShiSS | 32:a1b2391b0c35 | 25 | * |
| SamShiSS | 32:a1b2391b0c35 | 26 | * The mere transfer of this software does not imply any licenses |
| SamShiSS | 32:a1b2391b0c35 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| SamShiSS | 32:a1b2391b0c35 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| SamShiSS | 32:a1b2391b0c35 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| SamShiSS | 32:a1b2391b0c35 | 30 | * ownership rights. |
| SamShiSS | 32:a1b2391b0c35 | 31 | ******************************************************************************* |
| SamShiSS | 32:a1b2391b0c35 | 32 | */ |
| SamShiSS | 32:a1b2391b0c35 | 33 | |
| SamShiSS | 32:a1b2391b0c35 | 34 | /* $Revision: 4395 $ $Date: 2015-02-17 15:52:32 -0600 (Tue, 17 Feb 2015) $ */ |
| SamShiSS | 32:a1b2391b0c35 | 35 | |
| SamShiSS | 32:a1b2391b0c35 | 36 | #include <stdint.h> |
| SamShiSS | 32:a1b2391b0c35 | 37 | |
| SamShiSS | 32:a1b2391b0c35 | 38 | #ifndef _MAX32600_H_ |
| SamShiSS | 32:a1b2391b0c35 | 39 | #define _MAX32600_H_ |
| SamShiSS | 32:a1b2391b0c35 | 40 | |
| SamShiSS | 32:a1b2391b0c35 | 41 | #ifndef FALSE |
| SamShiSS | 32:a1b2391b0c35 | 42 | #define FALSE (0) |
| SamShiSS | 32:a1b2391b0c35 | 43 | #endif |
| SamShiSS | 32:a1b2391b0c35 | 44 | |
| SamShiSS | 32:a1b2391b0c35 | 45 | #ifndef TRUE |
| SamShiSS | 32:a1b2391b0c35 | 46 | #define TRUE (1) |
| SamShiSS | 32:a1b2391b0c35 | 47 | #endif |
| SamShiSS | 32:a1b2391b0c35 | 48 | |
| SamShiSS | 32:a1b2391b0c35 | 49 | #define __NVIC_PRIO_BITS 3 |
| SamShiSS | 32:a1b2391b0c35 | 50 | |
| SamShiSS | 32:a1b2391b0c35 | 51 | typedef enum IRQn_Type { |
| SamShiSS | 32:a1b2391b0c35 | 52 | NonMaskableInt_IRQn = -14, |
| SamShiSS | 32:a1b2391b0c35 | 53 | HardFault_IRQn = -13, |
| SamShiSS | 32:a1b2391b0c35 | 54 | MemoryManagement_IRQn = -12, |
| SamShiSS | 32:a1b2391b0c35 | 55 | BusFault_IRQn = -11, |
| SamShiSS | 32:a1b2391b0c35 | 56 | UsageFault_IRQn = -10, |
| SamShiSS | 32:a1b2391b0c35 | 57 | SVCall_IRQn = -5, |
| SamShiSS | 32:a1b2391b0c35 | 58 | DebugMonitor_IRQn = -4, |
| SamShiSS | 32:a1b2391b0c35 | 59 | PendSV_IRQn = -2, |
| SamShiSS | 32:a1b2391b0c35 | 60 | SysTick_IRQn = -1, |
| SamShiSS | 32:a1b2391b0c35 | 61 | |
| SamShiSS | 32:a1b2391b0c35 | 62 | /* Maxim 32600 Externals interrupts */ |
| SamShiSS | 32:a1b2391b0c35 | 63 | UART0_IRQn = 0, /* 16:01 UART0 */ |
| SamShiSS | 32:a1b2391b0c35 | 64 | UART1_IRQn, /* 17: 2 UART1 */ |
| SamShiSS | 32:a1b2391b0c35 | 65 | I2CM0_IRQn, /* 18: 3 I2C Master 0 */ |
| SamShiSS | 32:a1b2391b0c35 | 66 | I2CS_IRQn, /* 19: 4 I2C Slave */ |
| SamShiSS | 32:a1b2391b0c35 | 67 | USB_IRQn, /* 20: 5 USB */ |
| SamShiSS | 32:a1b2391b0c35 | 68 | PMU_IRQn, /* 21: 6 DMA */ |
| SamShiSS | 32:a1b2391b0c35 | 69 | AFE_IRQn, /* 22: 7 AFE */ |
| SamShiSS | 32:a1b2391b0c35 | 70 | MAA_IRQn, /* 23: 8 MAA */ |
| SamShiSS | 32:a1b2391b0c35 | 71 | AES_IRQn, /* 24: 9 AES */ |
| SamShiSS | 32:a1b2391b0c35 | 72 | SPI0_IRQn, /* 25:10 SPI0 */ |
| SamShiSS | 32:a1b2391b0c35 | 73 | SPI1_IRQn, /* 26:11 SPI1 */ |
| SamShiSS | 32:a1b2391b0c35 | 74 | SPI2_IRQn, /* 27:12 SPI2 */ |
| SamShiSS | 32:a1b2391b0c35 | 75 | TMR0_IRQn, /* 28:13 Timer32-0 */ |
| SamShiSS | 32:a1b2391b0c35 | 76 | TMR1_IRQn, /* 29:14 Timer32-1 */ |
| SamShiSS | 32:a1b2391b0c35 | 77 | TMR2_IRQn, /* 30:15 Timer32-1 */ |
| SamShiSS | 32:a1b2391b0c35 | 78 | TMR3_IRQn, /* 31:16 Timer32-2 */ |
| SamShiSS | 32:a1b2391b0c35 | 79 | RSVD0_IRQn, /* 32:17 RSVD */ |
| SamShiSS | 32:a1b2391b0c35 | 80 | RSVD1_IRQn, /* 33:18 RSVD */ |
| SamShiSS | 32:a1b2391b0c35 | 81 | DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */ |
| SamShiSS | 32:a1b2391b0c35 | 82 | DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */ |
| SamShiSS | 32:a1b2391b0c35 | 83 | DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */ |
| SamShiSS | 32:a1b2391b0c35 | 84 | DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */ |
| SamShiSS | 32:a1b2391b0c35 | 85 | ADC_IRQn, /* 38:23 ADC */ |
| SamShiSS | 32:a1b2391b0c35 | 86 | FLC_IRQn, /* 39:24 Flash Controller */ |
| SamShiSS | 32:a1b2391b0c35 | 87 | PWRMAN_IRQn, /* 40:25 PWRMAN */ |
| SamShiSS | 32:a1b2391b0c35 | 88 | CLKMAN_IRQn, /* 41:26 CLKMAN */ |
| SamShiSS | 32:a1b2391b0c35 | 89 | RTC0_IRQn, /* 42:27 RTC INT0 */ |
| SamShiSS | 32:a1b2391b0c35 | 90 | RTC1_IRQn, /* 43:28 RTC INT1 */ |
| SamShiSS | 32:a1b2391b0c35 | 91 | RTC2_IRQn, /* 44:29 RTC INT2 */ |
| SamShiSS | 32:a1b2391b0c35 | 92 | RTC3_IRQn, /* 45:30 RTC INT3 */ |
| SamShiSS | 32:a1b2391b0c35 | 93 | WDT0_IRQn, /* 46:31 WATCHDOG0 */ |
| SamShiSS | 32:a1b2391b0c35 | 94 | WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */ |
| SamShiSS | 32:a1b2391b0c35 | 95 | WDT1_IRQn, /* 48:33 WATCHDOG1 */ |
| SamShiSS | 32:a1b2391b0c35 | 96 | WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */ |
| SamShiSS | 32:a1b2391b0c35 | 97 | GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */ |
| SamShiSS | 32:a1b2391b0c35 | 98 | GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */ |
| SamShiSS | 32:a1b2391b0c35 | 99 | GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */ |
| SamShiSS | 32:a1b2391b0c35 | 100 | GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */ |
| SamShiSS | 32:a1b2391b0c35 | 101 | GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */ |
| SamShiSS | 32:a1b2391b0c35 | 102 | GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */ |
| SamShiSS | 32:a1b2391b0c35 | 103 | GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */ |
| SamShiSS | 32:a1b2391b0c35 | 104 | GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */ |
| SamShiSS | 32:a1b2391b0c35 | 105 | TMR16_0_IRQn, /* 58:43 Timer16-s0 */ |
| SamShiSS | 32:a1b2391b0c35 | 106 | TMR16_1_IRQn, /* 59:44 Timer16-s1 */ |
| SamShiSS | 32:a1b2391b0c35 | 107 | TMR16_2_IRQn, /* 60:45 Timer16-s2 */ |
| SamShiSS | 32:a1b2391b0c35 | 108 | TMR16_3_IRQn, /* 61:46 Timer16-s3 */ |
| SamShiSS | 32:a1b2391b0c35 | 109 | I2CM1_IRQn, /* 62:47 I2C Master 1 */ |
| SamShiSS | 32:a1b2391b0c35 | 110 | MXC_IRQ_EXT_COUNT, |
| SamShiSS | 32:a1b2391b0c35 | 111 | } IRQn_Type; |
| SamShiSS | 32:a1b2391b0c35 | 112 | |
| SamShiSS | 32:a1b2391b0c35 | 113 | #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) |
| SamShiSS | 32:a1b2391b0c35 | 114 | |
| SamShiSS | 32:a1b2391b0c35 | 115 | #include "core_cm3.h" |
| SamShiSS | 32:a1b2391b0c35 | 116 | #include "system_max32600.h" |
| SamShiSS | 32:a1b2391b0c35 | 117 | |
| SamShiSS | 32:a1b2391b0c35 | 118 | /* |
| SamShiSS | 32:a1b2391b0c35 | 119 | Base addresses and configuration settings for all MAX32600 peripheral modules. |
| SamShiSS | 32:a1b2391b0c35 | 120 | */ |
| SamShiSS | 32:a1b2391b0c35 | 121 | |
| SamShiSS | 32:a1b2391b0c35 | 122 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 123 | /* General Purpose I/O Ports (GPIO) */ |
| SamShiSS | 32:a1b2391b0c35 | 124 | |
| SamShiSS | 32:a1b2391b0c35 | 125 | |
| SamShiSS | 32:a1b2391b0c35 | 126 | #define MXC_BASE_GPIO ((uint32_t)0x40000000UL) |
| SamShiSS | 32:a1b2391b0c35 | 127 | #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO) |
| SamShiSS | 32:a1b2391b0c35 | 128 | #define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL) |
| SamShiSS | 32:a1b2391b0c35 | 129 | |
| SamShiSS | 32:a1b2391b0c35 | 130 | |
| SamShiSS | 32:a1b2391b0c35 | 131 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 132 | /* Pulse Train Generation */ |
| SamShiSS | 32:a1b2391b0c35 | 133 | |
| SamShiSS | 32:a1b2391b0c35 | 134 | #define MXC_CFG_PT_INSTANCES (13) |
| SamShiSS | 32:a1b2391b0c35 | 135 | |
| SamShiSS | 32:a1b2391b0c35 | 136 | #define MXC_BASE_PTG ((uint32_t)0x40001000UL) |
| SamShiSS | 32:a1b2391b0c35 | 137 | #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG) |
| SamShiSS | 32:a1b2391b0c35 | 138 | #define MXC_BASE_PT ((uint32_t)0x40001008UL) |
| SamShiSS | 32:a1b2391b0c35 | 139 | #define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT) |
| SamShiSS | 32:a1b2391b0c35 | 140 | #define MXC_BASE_PT0 ((uint32_t)0x40001008UL) |
| SamShiSS | 32:a1b2391b0c35 | 141 | #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0) |
| SamShiSS | 32:a1b2391b0c35 | 142 | #define MXC_BASE_PT1 ((uint32_t)0x40001010UL) |
| SamShiSS | 32:a1b2391b0c35 | 143 | #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1) |
| SamShiSS | 32:a1b2391b0c35 | 144 | #define MXC_BASE_PT2 ((uint32_t)0x40001018UL) |
| SamShiSS | 32:a1b2391b0c35 | 145 | #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2) |
| SamShiSS | 32:a1b2391b0c35 | 146 | #define MXC_BASE_PT3 ((uint32_t)0x40001020UL) |
| SamShiSS | 32:a1b2391b0c35 | 147 | #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3) |
| SamShiSS | 32:a1b2391b0c35 | 148 | #define MXC_BASE_PT4 ((uint32_t)0x40001028UL) |
| SamShiSS | 32:a1b2391b0c35 | 149 | #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4) |
| SamShiSS | 32:a1b2391b0c35 | 150 | #define MXC_BASE_PT5 ((uint32_t)0x40001030UL) |
| SamShiSS | 32:a1b2391b0c35 | 151 | #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5) |
| SamShiSS | 32:a1b2391b0c35 | 152 | #define MXC_BASE_PT6 ((uint32_t)0x40001038UL) |
| SamShiSS | 32:a1b2391b0c35 | 153 | #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6) |
| SamShiSS | 32:a1b2391b0c35 | 154 | #define MXC_BASE_PT7 ((uint32_t)0x40001040UL) |
| SamShiSS | 32:a1b2391b0c35 | 155 | #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7) |
| SamShiSS | 32:a1b2391b0c35 | 156 | #define MXC_BASE_PT8 ((uint32_t)0x40001048UL) |
| SamShiSS | 32:a1b2391b0c35 | 157 | #define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8) |
| SamShiSS | 32:a1b2391b0c35 | 158 | #define MXC_BASE_PT9 ((uint32_t)0x40001050UL) |
| SamShiSS | 32:a1b2391b0c35 | 159 | #define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9) |
| SamShiSS | 32:a1b2391b0c35 | 160 | #define MXC_BASE_PT10 ((uint32_t)0x40001058UL) |
| SamShiSS | 32:a1b2391b0c35 | 161 | #define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10) |
| SamShiSS | 32:a1b2391b0c35 | 162 | #define MXC_BASE_PT11 ((uint32_t)0x40001060UL) |
| SamShiSS | 32:a1b2391b0c35 | 163 | #define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11) |
| SamShiSS | 32:a1b2391b0c35 | 164 | |
| SamShiSS | 32:a1b2391b0c35 | 165 | /* PT12, PT13, PT14 are not used */ |
| SamShiSS | 32:a1b2391b0c35 | 166 | |
| SamShiSS | 32:a1b2391b0c35 | 167 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 168 | /* CRC-16/CRC-32 Engine */ |
| SamShiSS | 32:a1b2391b0c35 | 169 | |
| SamShiSS | 32:a1b2391b0c35 | 170 | #define MXC_BASE_CRC ((uint32_t)0x40010000UL) |
| SamShiSS | 32:a1b2391b0c35 | 171 | #define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC) |
| SamShiSS | 32:a1b2391b0c35 | 172 | |
| SamShiSS | 32:a1b2391b0c35 | 173 | #define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL) |
| SamShiSS | 32:a1b2391b0c35 | 174 | #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA) |
| SamShiSS | 32:a1b2391b0c35 | 175 | |
| SamShiSS | 32:a1b2391b0c35 | 176 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 177 | /* Trust Protection Unit (TPU) */ |
| SamShiSS | 32:a1b2391b0c35 | 178 | |
| SamShiSS | 32:a1b2391b0c35 | 179 | #define MXC_BASE_TPU ((uint32_t)0x40011000UL) |
| SamShiSS | 32:a1b2391b0c35 | 180 | #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU) |
| SamShiSS | 32:a1b2391b0c35 | 181 | |
| SamShiSS | 32:a1b2391b0c35 | 182 | #define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL) |
| SamShiSS | 32:a1b2391b0c35 | 183 | #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR) |
| SamShiSS | 32:a1b2391b0c35 | 184 | |
| SamShiSS | 32:a1b2391b0c35 | 185 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 186 | /* AES Cryptographic Engine */ |
| SamShiSS | 32:a1b2391b0c35 | 187 | |
| SamShiSS | 32:a1b2391b0c35 | 188 | #define MXC_BASE_AES ((uint32_t)0x40011400UL) |
| SamShiSS | 32:a1b2391b0c35 | 189 | #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) |
| SamShiSS | 32:a1b2391b0c35 | 190 | |
| SamShiSS | 32:a1b2391b0c35 | 191 | #define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL) |
| SamShiSS | 32:a1b2391b0c35 | 192 | #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM) |
| SamShiSS | 32:a1b2391b0c35 | 193 | |
| SamShiSS | 32:a1b2391b0c35 | 194 | |
| SamShiSS | 32:a1b2391b0c35 | 195 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 196 | /* MAA Cryptographic Engine */ |
| SamShiSS | 32:a1b2391b0c35 | 197 | |
| SamShiSS | 32:a1b2391b0c35 | 198 | #define MXC_BASE_MAA ((uint32_t)0x40011800UL) |
| SamShiSS | 32:a1b2391b0c35 | 199 | #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA) |
| SamShiSS | 32:a1b2391b0c35 | 200 | |
| SamShiSS | 32:a1b2391b0c35 | 201 | #define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL) |
| SamShiSS | 32:a1b2391b0c35 | 202 | #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM) |
| SamShiSS | 32:a1b2391b0c35 | 203 | |
| SamShiSS | 32:a1b2391b0c35 | 204 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 205 | /* 32-Bit PWM Timer/Counter */ |
| SamShiSS | 32:a1b2391b0c35 | 206 | |
| SamShiSS | 32:a1b2391b0c35 | 207 | #define MXC_CFG_TMR_INSTANCES (4) |
| SamShiSS | 32:a1b2391b0c35 | 208 | |
| SamShiSS | 32:a1b2391b0c35 | 209 | #define MXC_BASE_TMR0 ((uint32_t)0x40012000UL) |
| SamShiSS | 32:a1b2391b0c35 | 210 | #define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL) |
| SamShiSS | 32:a1b2391b0c35 | 211 | #define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0) |
| SamShiSS | 32:a1b2391b0c35 | 212 | |
| SamShiSS | 32:a1b2391b0c35 | 213 | #define MXC_BASE_TMR1 ((uint32_t)0x40013000UL) |
| SamShiSS | 32:a1b2391b0c35 | 214 | #define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL) |
| SamShiSS | 32:a1b2391b0c35 | 215 | #define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1) |
| SamShiSS | 32:a1b2391b0c35 | 216 | |
| SamShiSS | 32:a1b2391b0c35 | 217 | #define MXC_BASE_TMR2 ((uint32_t)0x40014000UL) |
| SamShiSS | 32:a1b2391b0c35 | 218 | #define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL) |
| SamShiSS | 32:a1b2391b0c35 | 219 | #define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2) |
| SamShiSS | 32:a1b2391b0c35 | 220 | |
| SamShiSS | 32:a1b2391b0c35 | 221 | #define MXC_BASE_TMR3 ((uint32_t)0x40015000UL) |
| SamShiSS | 32:a1b2391b0c35 | 222 | #define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL) |
| SamShiSS | 32:a1b2391b0c35 | 223 | #define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3) |
| SamShiSS | 32:a1b2391b0c35 | 224 | |
| SamShiSS | 32:a1b2391b0c35 | 225 | |
| SamShiSS | 32:a1b2391b0c35 | 226 | #define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 227 | (i) == 1 ? TMR1_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 228 | (i) == 2 ? TMR2_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 229 | (i) == 3 ? TMR3_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 230 | |
| SamShiSS | 32:a1b2391b0c35 | 231 | #define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 232 | (i) == 1 ? TMR1_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 233 | (i) == 2 ? TMR2_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 234 | (i) == 3 ? TMR3_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 235 | (i) == 4 ? TMR16_0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 236 | (i) == 5 ? TMR16_1_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 237 | (i) == 6 ? TMR16_2_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 238 | (i) == 7 ? TMR16_3_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 239 | |
| SamShiSS | 32:a1b2391b0c35 | 240 | #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 241 | (i) == 1 ? MXC_BASE_TMR1 : \ |
| SamShiSS | 32:a1b2391b0c35 | 242 | (i) == 2 ? MXC_BASE_TMR2 : \ |
| SamShiSS | 32:a1b2391b0c35 | 243 | (i) == 3 ? MXC_BASE_TMR3 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 244 | |
| SamShiSS | 32:a1b2391b0c35 | 245 | #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 246 | (i) == 1 ? MXC_TMR1 : \ |
| SamShiSS | 32:a1b2391b0c35 | 247 | (i) == 2 ? MXC_TMR2 : \ |
| SamShiSS | 32:a1b2391b0c35 | 248 | (i) == 3 ? MXC_TMR3 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 249 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 250 | /* Watchdog Timer */ |
| SamShiSS | 32:a1b2391b0c35 | 251 | |
| SamShiSS | 32:a1b2391b0c35 | 252 | #define MXC_CFG_WDT_INSTANCES (2) |
| SamShiSS | 32:a1b2391b0c35 | 253 | |
| SamShiSS | 32:a1b2391b0c35 | 254 | #define MXC_BASE_WDT0 ((uint32_t)0x40021000UL) |
| SamShiSS | 32:a1b2391b0c35 | 255 | #define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL) |
| SamShiSS | 32:a1b2391b0c35 | 256 | #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0) |
| SamShiSS | 32:a1b2391b0c35 | 257 | |
| SamShiSS | 32:a1b2391b0c35 | 258 | #define MXC_BASE_WDT1 ((uint32_t)0x40022000UL) |
| SamShiSS | 32:a1b2391b0c35 | 259 | #define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL) |
| SamShiSS | 32:a1b2391b0c35 | 260 | #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1) |
| SamShiSS | 32:a1b2391b0c35 | 261 | |
| SamShiSS | 32:a1b2391b0c35 | 262 | #define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 263 | (i) == 1 ? WDT1_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 264 | |
| SamShiSS | 32:a1b2391b0c35 | 265 | #define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 266 | (i) == 1 ? WDT1_P_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 267 | |
| SamShiSS | 32:a1b2391b0c35 | 268 | #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 269 | (i) == 1 ? MXC_BASE_WDT1 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 270 | |
| SamShiSS | 32:a1b2391b0c35 | 271 | #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 272 | (i) == 1 ? MXC_WDT1 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 273 | |
| SamShiSS | 32:a1b2391b0c35 | 274 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 275 | /* SPI Interface */ |
| SamShiSS | 32:a1b2391b0c35 | 276 | |
| SamShiSS | 32:a1b2391b0c35 | 277 | #define MXC_CFG_SPI_INSTANCES (3) |
| SamShiSS | 32:a1b2391b0c35 | 278 | #define MXC_CFG_SPI_FIFO_DEPTH (16) |
| SamShiSS | 32:a1b2391b0c35 | 279 | |
| SamShiSS | 32:a1b2391b0c35 | 280 | |
| SamShiSS | 32:a1b2391b0c35 | 281 | #define MXC_BASE_SPI0 ((uint32_t)0x40030000UL) |
| SamShiSS | 32:a1b2391b0c35 | 282 | #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0) |
| SamShiSS | 32:a1b2391b0c35 | 283 | |
| SamShiSS | 32:a1b2391b0c35 | 284 | #define MXC_BASE_SPI0_FIFO ((uint32_t)0x40100000UL) |
| SamShiSS | 32:a1b2391b0c35 | 285 | #define MXC_SPI0_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI0_FIFO) |
| SamShiSS | 32:a1b2391b0c35 | 286 | |
| SamShiSS | 32:a1b2391b0c35 | 287 | #define MXC_BASE_SPI1 ((uint32_t)0x40031000UL) |
| SamShiSS | 32:a1b2391b0c35 | 288 | #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1) |
| SamShiSS | 32:a1b2391b0c35 | 289 | |
| SamShiSS | 32:a1b2391b0c35 | 290 | #define MXC_BASE_SPI1_FIFO ((uint32_t)0x40101000UL) |
| SamShiSS | 32:a1b2391b0c35 | 291 | #define MXC_SPI1_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI1_FIFO) |
| SamShiSS | 32:a1b2391b0c35 | 292 | |
| SamShiSS | 32:a1b2391b0c35 | 293 | #define MXC_BASE_SPI2 ((uint32_t)0x40032000UL) |
| SamShiSS | 32:a1b2391b0c35 | 294 | #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2) |
| SamShiSS | 32:a1b2391b0c35 | 295 | |
| SamShiSS | 32:a1b2391b0c35 | 296 | #define MXC_BASE_SPI2_FIFO ((uint32_t)0x40102000UL) |
| SamShiSS | 32:a1b2391b0c35 | 297 | #define MXC_SPI2_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI2_FIFO) |
| SamShiSS | 32:a1b2391b0c35 | 298 | |
| SamShiSS | 32:a1b2391b0c35 | 299 | |
| SamShiSS | 32:a1b2391b0c35 | 300 | #define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 301 | (i) == 1 ? SPI1_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 302 | (i) == 2 ? SPI2_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 303 | |
| SamShiSS | 32:a1b2391b0c35 | 304 | #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 305 | (i) == 1 ? MXC_BASE_SPI1 : \ |
| SamShiSS | 32:a1b2391b0c35 | 306 | (i) == 2 ? MXC_BASE_SPI2 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 307 | |
| SamShiSS | 32:a1b2391b0c35 | 308 | #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 309 | (i) == 1 ? MXC_SPI1 : \ |
| SamShiSS | 32:a1b2391b0c35 | 310 | (i) == 2 ? MXC_SPI2 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 311 | |
| SamShiSS | 32:a1b2391b0c35 | 312 | #define MXC_SPI_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPI0_FIFO : \ |
| SamShiSS | 32:a1b2391b0c35 | 313 | (i) == 1 ? MXC_BASE_SPI1_FIFO : \ |
| SamShiSS | 32:a1b2391b0c35 | 314 | (i) == 2 ? MXC_BASE_SPI2_FIFO : 0) |
| SamShiSS | 32:a1b2391b0c35 | 315 | |
| SamShiSS | 32:a1b2391b0c35 | 316 | #define MXC_SPI_GET_SPI_FIFO(i) ((i) == 0 ? MXC_SPI0_FIFO : \ |
| SamShiSS | 32:a1b2391b0c35 | 317 | (i) == 1 ? MXC_SPI1_FIFO : \ |
| SamShiSS | 32:a1b2391b0c35 | 318 | (i) == 2 ? MXC_SPI2_FIFO : 0) |
| SamShiSS | 32:a1b2391b0c35 | 319 | |
| SamShiSS | 32:a1b2391b0c35 | 320 | |
| SamShiSS | 32:a1b2391b0c35 | 321 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 322 | /* UART Interface */ |
| SamShiSS | 32:a1b2391b0c35 | 323 | |
| SamShiSS | 32:a1b2391b0c35 | 324 | #define MXC_CFG_UART_INSTANCES (2) |
| SamShiSS | 32:a1b2391b0c35 | 325 | |
| SamShiSS | 32:a1b2391b0c35 | 326 | #define MXC_BASE_UART0 ((uint32_t)0x40038000UL) |
| SamShiSS | 32:a1b2391b0c35 | 327 | #define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL) |
| SamShiSS | 32:a1b2391b0c35 | 328 | #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0) |
| SamShiSS | 32:a1b2391b0c35 | 329 | |
| SamShiSS | 32:a1b2391b0c35 | 330 | #define MXC_BASE_UART1 ((uint32_t)0x40039000UL) |
| SamShiSS | 32:a1b2391b0c35 | 331 | #define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL) |
| SamShiSS | 32:a1b2391b0c35 | 332 | #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1) |
| SamShiSS | 32:a1b2391b0c35 | 333 | |
| SamShiSS | 32:a1b2391b0c35 | 334 | |
| SamShiSS | 32:a1b2391b0c35 | 335 | #define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 336 | (i) == 1 ? UART1_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 337 | |
| SamShiSS | 32:a1b2391b0c35 | 338 | #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 339 | (i) == 1 ? MXC_BASE_UART1 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 340 | |
| SamShiSS | 32:a1b2391b0c35 | 341 | #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 342 | (i) == 1 ? MXC_UART1 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 343 | |
| SamShiSS | 32:a1b2391b0c35 | 344 | #define MXC_CFG_UART_FIFO_DEPTH (8) |
| SamShiSS | 32:a1b2391b0c35 | 345 | |
| SamShiSS | 32:a1b2391b0c35 | 346 | |
| SamShiSS | 32:a1b2391b0c35 | 347 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 348 | /* I2C Master Interface */ |
| SamShiSS | 32:a1b2391b0c35 | 349 | |
| SamShiSS | 32:a1b2391b0c35 | 350 | #define MXC_CFG_I2CM_INSTANCES (2) |
| SamShiSS | 32:a1b2391b0c35 | 351 | |
| SamShiSS | 32:a1b2391b0c35 | 352 | #define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL) |
| SamShiSS | 32:a1b2391b0c35 | 353 | #define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL) |
| SamShiSS | 32:a1b2391b0c35 | 354 | #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0) |
| SamShiSS | 32:a1b2391b0c35 | 355 | |
| SamShiSS | 32:a1b2391b0c35 | 356 | #define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40103000UL) |
| SamShiSS | 32:a1b2391b0c35 | 357 | |
| SamShiSS | 32:a1b2391b0c35 | 358 | #define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL) |
| SamShiSS | 32:a1b2391b0c35 | 359 | #define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL) |
| SamShiSS | 32:a1b2391b0c35 | 360 | #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1) |
| SamShiSS | 32:a1b2391b0c35 | 361 | |
| SamShiSS | 32:a1b2391b0c35 | 362 | #define MXC_BASE_I2CM1_FIFO ((uint32_t)0x4010D000UL) |
| SamShiSS | 32:a1b2391b0c35 | 363 | |
| SamShiSS | 32:a1b2391b0c35 | 364 | |
| SamShiSS | 32:a1b2391b0c35 | 365 | #define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 366 | (i) == 1 ? I2CM1_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 367 | |
| SamShiSS | 32:a1b2391b0c35 | 368 | #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 369 | (i) == 1 ? MXC_BASE_I2CM1 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 370 | |
| SamShiSS | 32:a1b2391b0c35 | 371 | #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 372 | (i) == 1 ? MXC_I2CM1 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 373 | |
| SamShiSS | 32:a1b2391b0c35 | 374 | #define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \ |
| SamShiSS | 32:a1b2391b0c35 | 375 | (i) == 1 ? MXC_BASE_I2CM1_FIFO : 0) |
| SamShiSS | 32:a1b2391b0c35 | 376 | |
| SamShiSS | 32:a1b2391b0c35 | 377 | |
| SamShiSS | 32:a1b2391b0c35 | 378 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 379 | /* I2C Slave Interface */ |
| SamShiSS | 32:a1b2391b0c35 | 380 | |
| SamShiSS | 32:a1b2391b0c35 | 381 | #define MXC_CFG_I2CS_INSTANCES (1) |
| SamShiSS | 32:a1b2391b0c35 | 382 | |
| SamShiSS | 32:a1b2391b0c35 | 383 | #define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL) |
| SamShiSS | 32:a1b2391b0c35 | 384 | #define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL) |
| SamShiSS | 32:a1b2391b0c35 | 385 | #define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0) |
| SamShiSS | 32:a1b2391b0c35 | 386 | |
| SamShiSS | 32:a1b2391b0c35 | 387 | #define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL) |
| SamShiSS | 32:a1b2391b0c35 | 388 | #define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0) |
| SamShiSS | 32:a1b2391b0c35 | 389 | |
| SamShiSS | 32:a1b2391b0c35 | 390 | |
| SamShiSS | 32:a1b2391b0c35 | 391 | |
| SamShiSS | 32:a1b2391b0c35 | 392 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 393 | /* DACs */ |
| SamShiSS | 32:a1b2391b0c35 | 394 | |
| SamShiSS | 32:a1b2391b0c35 | 395 | #define MXC_CFG_DAC_INSTANCES (4) |
| SamShiSS | 32:a1b2391b0c35 | 396 | #define MXC_CFG_DAC_FIFO_DEPTH (32) |
| SamShiSS | 32:a1b2391b0c35 | 397 | |
| SamShiSS | 32:a1b2391b0c35 | 398 | #define MXC_BASE_DAC0 ((uint32_t)0x40050000UL) |
| SamShiSS | 32:a1b2391b0c35 | 399 | #define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0) |
| SamShiSS | 32:a1b2391b0c35 | 400 | #define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL) |
| SamShiSS | 32:a1b2391b0c35 | 401 | #define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO) |
| SamShiSS | 32:a1b2391b0c35 | 402 | #define MXC_DAC0_WIDTH ((uint8_t)(2)) |
| SamShiSS | 32:a1b2391b0c35 | 403 | |
| SamShiSS | 32:a1b2391b0c35 | 404 | #define MXC_BASE_DAC1 ((uint32_t)0x40051000UL) |
| SamShiSS | 32:a1b2391b0c35 | 405 | #define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1) |
| SamShiSS | 32:a1b2391b0c35 | 406 | #define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL) |
| SamShiSS | 32:a1b2391b0c35 | 407 | #define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO) |
| SamShiSS | 32:a1b2391b0c35 | 408 | #define MXC_DAC1_WIDTH ((uint8_t)(2)) |
| SamShiSS | 32:a1b2391b0c35 | 409 | |
| SamShiSS | 32:a1b2391b0c35 | 410 | #define MXC_BASE_DAC2 ((uint32_t)0x40052000UL) |
| SamShiSS | 32:a1b2391b0c35 | 411 | #define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2) |
| SamShiSS | 32:a1b2391b0c35 | 412 | #define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL) |
| SamShiSS | 32:a1b2391b0c35 | 413 | #define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO) |
| SamShiSS | 32:a1b2391b0c35 | 414 | #define MXC_DAC2_WIDTH ((uint8_t)(1)) |
| SamShiSS | 32:a1b2391b0c35 | 415 | |
| SamShiSS | 32:a1b2391b0c35 | 416 | #define MXC_BASE_DAC3 ((uint32_t)0x40053000UL) |
| SamShiSS | 32:a1b2391b0c35 | 417 | #define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3) |
| SamShiSS | 32:a1b2391b0c35 | 418 | #define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL) |
| SamShiSS | 32:a1b2391b0c35 | 419 | #define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO) |
| SamShiSS | 32:a1b2391b0c35 | 420 | #define MXC_DAC3_WIDTH ((uint8_t)(1)) |
| SamShiSS | 32:a1b2391b0c35 | 421 | |
| SamShiSS | 32:a1b2391b0c35 | 422 | |
| SamShiSS | 32:a1b2391b0c35 | 423 | #define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 424 | (i) == 1 ? DAC1_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 425 | (i) == 2 ? DAC2_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 426 | (i) == 3 ? DAC3_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 427 | |
| SamShiSS | 32:a1b2391b0c35 | 428 | |
| SamShiSS | 32:a1b2391b0c35 | 429 | #define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 430 | i == 1 ? MXC_BASE_DAC1 : \ |
| SamShiSS | 32:a1b2391b0c35 | 431 | i == 2 ? MXC_BASE_DAC2 : \ |
| SamShiSS | 32:a1b2391b0c35 | 432 | i == 3 ? MXC_BASE_DAC3 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 433 | |
| SamShiSS | 32:a1b2391b0c35 | 434 | #define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \ |
| SamShiSS | 32:a1b2391b0c35 | 435 | i == 1 ? MXC_BASE_DAC1_FIFO : \ |
| SamShiSS | 32:a1b2391b0c35 | 436 | i == 2 ? MXC_BASE_DAC2_FIFO : \ |
| SamShiSS | 32:a1b2391b0c35 | 437 | i == 3 ? MXC_BASE_DAC3_FIFO : 0) |
| SamShiSS | 32:a1b2391b0c35 | 438 | |
| SamShiSS | 32:a1b2391b0c35 | 439 | #define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \ |
| SamShiSS | 32:a1b2391b0c35 | 440 | i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \ |
| SamShiSS | 32:a1b2391b0c35 | 441 | i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \ |
| SamShiSS | 32:a1b2391b0c35 | 442 | i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0) |
| SamShiSS | 32:a1b2391b0c35 | 443 | |
| SamShiSS | 32:a1b2391b0c35 | 444 | #define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \ |
| SamShiSS | 32:a1b2391b0c35 | 445 | i == 1 ? MXC_DAC1 : \ |
| SamShiSS | 32:a1b2391b0c35 | 446 | i == 2 ? MXC_DAC2 : \ |
| SamShiSS | 32:a1b2391b0c35 | 447 | i == 3 ? MXC_DAC3 : 0) |
| SamShiSS | 32:a1b2391b0c35 | 448 | |
| SamShiSS | 32:a1b2391b0c35 | 449 | #define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \ |
| SamShiSS | 32:a1b2391b0c35 | 450 | i == 1 ? MXC_DAC1_WIDTH : \ |
| SamShiSS | 32:a1b2391b0c35 | 451 | i == 2 ? MXC_DAC2_WIDTH : \ |
| SamShiSS | 32:a1b2391b0c35 | 452 | i == 3 ? MXC_DAC3_WIDTH : 0) |
| SamShiSS | 32:a1b2391b0c35 | 453 | |
| SamShiSS | 32:a1b2391b0c35 | 454 | |
| SamShiSS | 32:a1b2391b0c35 | 455 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 456 | /* Analog Front End */ |
| SamShiSS | 32:a1b2391b0c35 | 457 | |
| SamShiSS | 32:a1b2391b0c35 | 458 | #define MXC_BASE_AFE ((uint32_t)0x4005401CUL) |
| SamShiSS | 32:a1b2391b0c35 | 459 | #define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE) |
| SamShiSS | 32:a1b2391b0c35 | 460 | |
| SamShiSS | 32:a1b2391b0c35 | 461 | |
| SamShiSS | 32:a1b2391b0c35 | 462 | |
| SamShiSS | 32:a1b2391b0c35 | 463 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 464 | /* ADC */ |
| SamShiSS | 32:a1b2391b0c35 | 465 | |
| SamShiSS | 32:a1b2391b0c35 | 466 | #define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32)) |
| SamShiSS | 32:a1b2391b0c35 | 467 | |
| SamShiSS | 32:a1b2391b0c35 | 468 | #define MXC_BASE_ADC ((uint32_t)0x40054000UL) |
| SamShiSS | 32:a1b2391b0c35 | 469 | #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC) |
| SamShiSS | 32:a1b2391b0c35 | 470 | |
| SamShiSS | 32:a1b2391b0c35 | 471 | #define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL) |
| SamShiSS | 32:a1b2391b0c35 | 472 | #define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG) |
| SamShiSS | 32:a1b2391b0c35 | 473 | |
| SamShiSS | 32:a1b2391b0c35 | 474 | #define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL) |
| SamShiSS | 32:a1b2391b0c35 | 475 | |
| SamShiSS | 32:a1b2391b0c35 | 476 | |
| SamShiSS | 32:a1b2391b0c35 | 477 | |
| SamShiSS | 32:a1b2391b0c35 | 478 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 479 | /* LCD */ |
| SamShiSS | 32:a1b2391b0c35 | 480 | #define MXC_BASE_LCD ((uint32_t)0x40060000) |
| SamShiSS | 32:a1b2391b0c35 | 481 | #define MXC_LCD ((mxc_lcd_regs_t *)MXC_BASE_LCD) |
| SamShiSS | 32:a1b2391b0c35 | 482 | |
| SamShiSS | 32:a1b2391b0c35 | 483 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 484 | /* Peripheral Management Unit (PMU) - formerly DMA Controller */ |
| SamShiSS | 32:a1b2391b0c35 | 485 | |
| SamShiSS | 32:a1b2391b0c35 | 486 | #define MXC_CFG_PMU_CHANNELS (6) |
| SamShiSS | 32:a1b2391b0c35 | 487 | |
| SamShiSS | 32:a1b2391b0c35 | 488 | #define MXC_BASE_PMU0 ((uint32_t)0x40070000UL) |
| SamShiSS | 32:a1b2391b0c35 | 489 | #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0) |
| SamShiSS | 32:a1b2391b0c35 | 490 | #define MXC_BASE_PMU1 ((uint32_t)0x40070020UL) |
| SamShiSS | 32:a1b2391b0c35 | 491 | #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1) |
| SamShiSS | 32:a1b2391b0c35 | 492 | #define MXC_BASE_PMU2 ((uint32_t)0x40070040UL) |
| SamShiSS | 32:a1b2391b0c35 | 493 | #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2) |
| SamShiSS | 32:a1b2391b0c35 | 494 | #define MXC_BASE_PMU3 ((uint32_t)0x40070060UL) |
| SamShiSS | 32:a1b2391b0c35 | 495 | #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3) |
| SamShiSS | 32:a1b2391b0c35 | 496 | #define MXC_BASE_PMU4 ((uint32_t)0x40070080UL) |
| SamShiSS | 32:a1b2391b0c35 | 497 | #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4) |
| SamShiSS | 32:a1b2391b0c35 | 498 | #define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL) |
| SamShiSS | 32:a1b2391b0c35 | 499 | #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5) |
| SamShiSS | 32:a1b2391b0c35 | 500 | |
| SamShiSS | 32:a1b2391b0c35 | 501 | #define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL) |
| SamShiSS | 32:a1b2391b0c35 | 502 | #define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL) |
| SamShiSS | 32:a1b2391b0c35 | 503 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 504 | |
| SamShiSS | 32:a1b2391b0c35 | 505 | typedef enum { |
| SamShiSS | 32:a1b2391b0c35 | 506 | PMU_IRQ_DAC0_FIFO_AE, |
| SamShiSS | 32:a1b2391b0c35 | 507 | PMU_IRQ_DAC1_FIFO_AE, |
| SamShiSS | 32:a1b2391b0c35 | 508 | PMU_IRQ_DAC2_FIFO_AE, |
| SamShiSS | 32:a1b2391b0c35 | 509 | PMU_IRQ_DAC3_FIFO_AE, |
| SamShiSS | 32:a1b2391b0c35 | 510 | PMU_IRQ_DAC0_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 511 | PMU_IRQ_DAC1_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 512 | PMU_IRQ_DAC2_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 513 | PMU_IRQ_DAC3_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 514 | PMU_IRQ_ADC_FIFO_AF, |
| SamShiSS | 32:a1b2391b0c35 | 515 | PMU_IRQ_ADC_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 516 | PMU_IRQ_I2C_MST0_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 517 | PMU_IRQ_I2C_MST1_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 518 | PMU_IRQ_SPI0_RSLTS_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 519 | PMU_IRQ_SPI1_RSLTS_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 520 | PMU_IRQ_SPI2_RSLTS_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 521 | PMU_IRQ_MAA_DONE, |
| SamShiSS | 32:a1b2391b0c35 | 522 | PMU_IRQ_SPI0_TX_FIFO_AE, |
| SamShiSS | 32:a1b2391b0c35 | 523 | PMU_IRQ_SPI0_RSLTS_FIFO_AF, |
| SamShiSS | 32:a1b2391b0c35 | 524 | PMU_IRQ_SPI1_TX_FIFO_AE, |
| SamShiSS | 32:a1b2391b0c35 | 525 | PMU_IRQ_SPI1_RSLTS_FIFO_AF, |
| SamShiSS | 32:a1b2391b0c35 | 526 | PMU_IRQ_SPI2_TX_FIFO_AE, |
| SamShiSS | 32:a1b2391b0c35 | 527 | PMU_IRQ_SPI3_RSLTS_FIFO_AF, |
| SamShiSS | 32:a1b2391b0c35 | 528 | PMU_IRQ_I2C_MST0_TRANS_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 529 | PMU_IRQ_I2C_MST0_RSLT_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 530 | PMU_IRQ_I2C_MST1_TRANS_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 531 | PMU_IRQ_I2C_MST2_RSLT_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 532 | PMU_IRQ_I2C_SLV_TRANS_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 533 | PMU_IRQ_I2C_SLV_RSLT_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 534 | PMU_IRQ_UART0_TX_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 535 | PMU_IRQ_UART0_RX_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 536 | PMU_IRQ_UART1_TX_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 537 | PMU_IRQ_UART1_RX_FIFO, |
| SamShiSS | 32:a1b2391b0c35 | 538 | PMU_IRQ_SPI0_EXCP, |
| SamShiSS | 32:a1b2391b0c35 | 539 | PMU_IRQ_SPI1_EXCP, |
| SamShiSS | 32:a1b2391b0c35 | 540 | PMU_IRQ_SPI2_EXCP, |
| SamShiSS | 32:a1b2391b0c35 | 541 | PMU_IRQ_RSVD0, |
| SamShiSS | 32:a1b2391b0c35 | 542 | PMU_IRQ_I2C_MST0_EXCP, |
| SamShiSS | 32:a1b2391b0c35 | 543 | PMU_IRQ_I2C_MST1_EXCP, |
| SamShiSS | 32:a1b2391b0c35 | 544 | PMU_IRQ_I2C_SLV_EXCP, |
| SamShiSS | 32:a1b2391b0c35 | 545 | PMU_IRQ_RSVD1, |
| SamShiSS | 32:a1b2391b0c35 | 546 | PMU_IRQ_GPIO0, |
| SamShiSS | 32:a1b2391b0c35 | 547 | PMU_IRQ_GPIO1, |
| SamShiSS | 32:a1b2391b0c35 | 548 | PMU_IRQ_GPIO2, |
| SamShiSS | 32:a1b2391b0c35 | 549 | PMU_IRQ_GPIO3, |
| SamShiSS | 32:a1b2391b0c35 | 550 | PMU_IRQ_GPIO4, |
| SamShiSS | 32:a1b2391b0c35 | 551 | PMU_IRQ_GPIO5, |
| SamShiSS | 32:a1b2391b0c35 | 552 | PMU_IRQ_GPIO6, |
| SamShiSS | 32:a1b2391b0c35 | 553 | PMU_IRQ_GPIO7, |
| SamShiSS | 32:a1b2391b0c35 | 554 | PMU_IRQ_GPIO8, |
| SamShiSS | 32:a1b2391b0c35 | 555 | PMU_IRQ_AFE_COMP_NMI, |
| SamShiSS | 32:a1b2391b0c35 | 556 | PMU_IRQ_AES_ENGINE, |
| SamShiSS | 32:a1b2391b0c35 | 557 | } pmu_int_mask_t; |
| SamShiSS | 32:a1b2391b0c35 | 558 | |
| SamShiSS | 32:a1b2391b0c35 | 559 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 560 | /* USB */ |
| SamShiSS | 32:a1b2391b0c35 | 561 | |
| SamShiSS | 32:a1b2391b0c35 | 562 | #define MXC_BASE_USB ((uint32_t)0x4010C000UL) |
| SamShiSS | 32:a1b2391b0c35 | 563 | #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB) |
| SamShiSS | 32:a1b2391b0c35 | 564 | |
| SamShiSS | 32:a1b2391b0c35 | 565 | #define MXC_USB_MAX_PACKET (64) |
| SamShiSS | 32:a1b2391b0c35 | 566 | #define MXC_USB_NUM_EP (8) |
| SamShiSS | 32:a1b2391b0c35 | 567 | |
| SamShiSS | 32:a1b2391b0c35 | 568 | |
| SamShiSS | 32:a1b2391b0c35 | 569 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 570 | /* Instruction Cache Controller */ |
| SamShiSS | 32:a1b2391b0c35 | 571 | |
| SamShiSS | 32:a1b2391b0c35 | 572 | #define MXC_BASE_ICC ((uint32_t)0x40080000UL) |
| SamShiSS | 32:a1b2391b0c35 | 573 | #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC) |
| SamShiSS | 32:a1b2391b0c35 | 574 | |
| SamShiSS | 32:a1b2391b0c35 | 575 | /* System Manager */ |
| SamShiSS | 32:a1b2391b0c35 | 576 | |
| SamShiSS | 32:a1b2391b0c35 | 577 | #define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL) |
| SamShiSS | 32:a1b2391b0c35 | 578 | |
| SamShiSS | 32:a1b2391b0c35 | 579 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 580 | /* Clock Manager */ |
| SamShiSS | 32:a1b2391b0c35 | 581 | |
| SamShiSS | 32:a1b2391b0c35 | 582 | #define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL) |
| SamShiSS | 32:a1b2391b0c35 | 583 | #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN) |
| SamShiSS | 32:a1b2391b0c35 | 584 | |
| SamShiSS | 32:a1b2391b0c35 | 585 | |
| SamShiSS | 32:a1b2391b0c35 | 586 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 587 | /* Power Manager */ |
| SamShiSS | 32:a1b2391b0c35 | 588 | |
| SamShiSS | 32:a1b2391b0c35 | 589 | #define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL) |
| SamShiSS | 32:a1b2391b0c35 | 590 | #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN) |
| SamShiSS | 32:a1b2391b0c35 | 591 | |
| SamShiSS | 32:a1b2391b0c35 | 592 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 593 | /* I/O Manager */ |
| SamShiSS | 32:a1b2391b0c35 | 594 | |
| SamShiSS | 32:a1b2391b0c35 | 595 | #define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL) |
| SamShiSS | 32:a1b2391b0c35 | 596 | #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN) |
| SamShiSS | 32:a1b2391b0c35 | 597 | |
| SamShiSS | 32:a1b2391b0c35 | 598 | |
| SamShiSS | 32:a1b2391b0c35 | 599 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 600 | /* RTC: Timer/Alarms */ |
| SamShiSS | 32:a1b2391b0c35 | 601 | |
| SamShiSS | 32:a1b2391b0c35 | 602 | #define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL) |
| SamShiSS | 32:a1b2391b0c35 | 603 | #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR) |
| SamShiSS | 32:a1b2391b0c35 | 604 | |
| SamShiSS | 32:a1b2391b0c35 | 605 | #define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 606 | i == 1 ? RTC1_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 607 | i == 2 ? RTC2_IRQn : \ |
| SamShiSS | 32:a1b2391b0c35 | 608 | i == 3 ? RTC3_IRQn : 0) |
| SamShiSS | 32:a1b2391b0c35 | 609 | |
| SamShiSS | 32:a1b2391b0c35 | 610 | #define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL) |
| SamShiSS | 32:a1b2391b0c35 | 611 | #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG) |
| SamShiSS | 32:a1b2391b0c35 | 612 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 613 | /* RTC: Power Sequencer */ |
| SamShiSS | 32:a1b2391b0c35 | 614 | |
| SamShiSS | 32:a1b2391b0c35 | 615 | #define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL) |
| SamShiSS | 32:a1b2391b0c35 | 616 | #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ) |
| SamShiSS | 32:a1b2391b0c35 | 617 | |
| SamShiSS | 32:a1b2391b0c35 | 618 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 619 | |
| SamShiSS | 32:a1b2391b0c35 | 620 | /* Trim Shadow Registers */ |
| SamShiSS | 32:a1b2391b0c35 | 621 | |
| SamShiSS | 32:a1b2391b0c35 | 622 | #define MXC_BASE_TRIM ((uint32_t)0x400E0000UL) |
| SamShiSS | 32:a1b2391b0c35 | 623 | #define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM) |
| SamShiSS | 32:a1b2391b0c35 | 624 | |
| SamShiSS | 32:a1b2391b0c35 | 625 | |
| SamShiSS | 32:a1b2391b0c35 | 626 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 627 | /* Flash Memory Controller / Security */ |
| SamShiSS | 32:a1b2391b0c35 | 628 | |
| SamShiSS | 32:a1b2391b0c35 | 629 | #define MXC_BASE_FLC ((uint32_t)0x400F0000UL) |
| SamShiSS | 32:a1b2391b0c35 | 630 | #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) |
| SamShiSS | 32:a1b2391b0c35 | 631 | #define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL) |
| SamShiSS | 32:a1b2391b0c35 | 632 | #define MXC_FLC_PAGE_SIZE_SHIFT 11 |
| SamShiSS | 32:a1b2391b0c35 | 633 | #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT) |
| SamShiSS | 32:a1b2391b0c35 | 634 | #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT |
| SamShiSS | 32:a1b2391b0c35 | 635 | |
| SamShiSS | 32:a1b2391b0c35 | 636 | |
| SamShiSS | 32:a1b2391b0c35 | 637 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 638 | |
| SamShiSS | 32:a1b2391b0c35 | 639 | #define BITBAND(reg, bit) ((0xf0000000 & reg) + 0x2000000 + ((reg & 0x0fffffff) << 5) + (bit << 2)) |
| SamShiSS | 32:a1b2391b0c35 | 640 | #define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0; |
| SamShiSS | 32:a1b2391b0c35 | 641 | #define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1; |
| SamShiSS | 32:a1b2391b0c35 | 642 | #define BITBAND_GetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) |
| SamShiSS | 32:a1b2391b0c35 | 643 | |
| SamShiSS | 32:a1b2391b0c35 | 644 | /*******************************************************************************/ |
| SamShiSS | 32:a1b2391b0c35 | 645 | #endif /* _MAX32600_H_ */ |
| SamShiSS | 32:a1b2391b0c35 | 646 |