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ITG3200.h@0:f075e92ce8d2, 2012-06-01 (annotated)

Committer:: SED9008
Date:: Fri Jun 01 08:17:03 2012 +0000
Revision:: 0:f075e92ce8d2

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User	Revision	Line number	New contents of line
SED9008	0:f075e92ce8d2	1	/**
SED9008	0:f075e92ce8d2	2	* @author Aaron Berk
SED9008	0:f075e92ce8d2	3	*
SED9008	0:f075e92ce8d2	4	* @section LICENSE
SED9008	0:f075e92ce8d2	5	*
SED9008	0:f075e92ce8d2	6	* Copyright (c) 2010 ARM Limited
SED9008	0:f075e92ce8d2	7	*
SED9008	0:f075e92ce8d2	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
SED9008	0:f075e92ce8d2	9	* of this software and associated documentation files (the "Software"), to deal
SED9008	0:f075e92ce8d2	10	* in the Software without restriction, including without limitation the rights
SED9008	0:f075e92ce8d2	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
SED9008	0:f075e92ce8d2	12	* copies of the Software, and to permit persons to whom the Software is
SED9008	0:f075e92ce8d2	13	* furnished to do so, subject to the following conditions:
SED9008	0:f075e92ce8d2	14	*
SED9008	0:f075e92ce8d2	15	* The above copyright notice and this permission notice shall be included in
SED9008	0:f075e92ce8d2	16	* all copies or substantial portions of the Software.
SED9008	0:f075e92ce8d2	17	*
SED9008	0:f075e92ce8d2	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
SED9008	0:f075e92ce8d2	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
SED9008	0:f075e92ce8d2	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
SED9008	0:f075e92ce8d2	21	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
SED9008	0:f075e92ce8d2	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
SED9008	0:f075e92ce8d2	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
SED9008	0:f075e92ce8d2	24	* THE SOFTWARE.
SED9008	0:f075e92ce8d2	25	*
SED9008	0:f075e92ce8d2	26	* @section DESCRIPTION
SED9008	0:f075e92ce8d2	27	*
SED9008	0:f075e92ce8d2	28	* ITG-3200 triple axis, digital interface, gyroscope.
SED9008	0:f075e92ce8d2	29	*
SED9008	0:f075e92ce8d2	30	* Datasheet:
SED9008	0:f075e92ce8d2	31	*
SED9008	0:f075e92ce8d2	32	* http://invensense.com/mems/gyro/documents/PS-ITG-3200-00-01.4.pdf
SED9008	0:f075e92ce8d2	33	*/
SED9008	0:f075e92ce8d2	34
SED9008	0:f075e92ce8d2	35	#ifndef ITG3200_H
SED9008	0:f075e92ce8d2	36	#define ITG3200_H
SED9008	0:f075e92ce8d2	37
SED9008	0:f075e92ce8d2	38	/**
SED9008	0:f075e92ce8d2	39	* Includes
SED9008	0:f075e92ce8d2	40	*/
SED9008	0:f075e92ce8d2	41	#include "mbed.h"
SED9008	0:f075e92ce8d2	42
SED9008	0:f075e92ce8d2	43	/**
SED9008	0:f075e92ce8d2	44	* Defines
SED9008	0:f075e92ce8d2	45	*/
SED9008	0:f075e92ce8d2	46	#define ITG3200_I2C_ADDRESS 0x68 //7-bit address.
SED9008	0:f075e92ce8d2	47
SED9008	0:f075e92ce8d2	48	//-----------
SED9008	0:f075e92ce8d2	49	// Registers
SED9008	0:f075e92ce8d2	50	//-----------
SED9008	0:f075e92ce8d2	51	#define WHO_AM_I_REG 0x00
SED9008	0:f075e92ce8d2	52	#define SMPLRT_DIV_REG 0x15
SED9008	0:f075e92ce8d2	53	#define DLPF_FS_REG 0x16
SED9008	0:f075e92ce8d2	54	#define INT_CFG_REG 0x17
SED9008	0:f075e92ce8d2	55	#define INT_STATUS 0x1A
SED9008	0:f075e92ce8d2	56	#define TEMP_OUT_H_REG 0x1B
SED9008	0:f075e92ce8d2	57	#define TEMP_OUT_L_REG 0x1C
SED9008	0:f075e92ce8d2	58	#define GYRO_XOUT_H_REG 0x1D
SED9008	0:f075e92ce8d2	59	#define GYRO_XOUT_L_REG 0x1E
SED9008	0:f075e92ce8d2	60	#define GYRO_YOUT_H_REG 0x1F
SED9008	0:f075e92ce8d2	61	#define GYRO_YOUT_L_REG 0x20
SED9008	0:f075e92ce8d2	62	#define GYRO_ZOUT_H_REG 0x21
SED9008	0:f075e92ce8d2	63	#define GYRO_ZOUT_L_REG 0x22
SED9008	0:f075e92ce8d2	64	#define PWR_MGM_REG 0x3E
SED9008	0:f075e92ce8d2	65
SED9008	0:f075e92ce8d2	66	//----------------------------
SED9008	0:f075e92ce8d2	67	// Low Pass Filter Bandwidths
SED9008	0:f075e92ce8d2	68	//----------------------------
SED9008	0:f075e92ce8d2	69	#define LPFBW_256HZ 0x00
SED9008	0:f075e92ce8d2	70	#define LPFBW_188HZ 0x01
SED9008	0:f075e92ce8d2	71	#define LPFBW_98HZ 0x02
SED9008	0:f075e92ce8d2	72	#define LPFBW_42HZ 0x03
SED9008	0:f075e92ce8d2	73	#define LPFBW_20HZ 0x04
SED9008	0:f075e92ce8d2	74	#define LPFBW_10HZ 0x05
SED9008	0:f075e92ce8d2	75	#define LPFBW_5HZ 0x06
SED9008	0:f075e92ce8d2	76
SED9008	0:f075e92ce8d2	77	/**
SED9008	0:f075e92ce8d2	78	* ITG-3200 triple axis digital gyroscope.
SED9008	0:f075e92ce8d2	79	*/
SED9008	0:f075e92ce8d2	80	class ITG3200 {
SED9008	0:f075e92ce8d2	81
SED9008	0:f075e92ce8d2	82	public:
SED9008	0:f075e92ce8d2	83
SED9008	0:f075e92ce8d2	84	/**
SED9008	0:f075e92ce8d2	85	* Constructor.
SED9008	0:f075e92ce8d2	86	*
SED9008	0:f075e92ce8d2	87	* Sets FS_SEL to 0x03 for proper opertaion.
SED9008	0:f075e92ce8d2	88	*
SED9008	0:f075e92ce8d2	89	* @param sda - mbed pin to use for the SDA I2C line.
SED9008	0:f075e92ce8d2	90	* @param scl - mbed pin to use for the SCL I2C line.
SED9008	0:f075e92ce8d2	91	*/
SED9008	0:f075e92ce8d2	92	ITG3200(PinName sda, PinName scl);
SED9008	0:f075e92ce8d2	93
SED9008	0:f075e92ce8d2	94	/**
SED9008	0:f075e92ce8d2	95	* Get the identity of the device.
SED9008	0:f075e92ce8d2	96	*
SED9008	0:f075e92ce8d2	97	* @return The contents of the Who Am I register which contains the I2C
SED9008	0:f075e92ce8d2	98	* address of the device.
SED9008	0:f075e92ce8d2	99	*/
SED9008	0:f075e92ce8d2	100	char getWhoAmI(void);
SED9008	0:f075e92ce8d2	101
SED9008	0:f075e92ce8d2	102	/**
SED9008	0:f075e92ce8d2	103	* Set the address of the device.
SED9008	0:f075e92ce8d2	104	*
SED9008	0:f075e92ce8d2	105	* @param address The I2C slave address to write to the Who Am I register
SED9008	0:f075e92ce8d2	106	* on the device.
SED9008	0:f075e92ce8d2	107	*/
SED9008	0:f075e92ce8d2	108	void setWhoAmI(char address);
SED9008	0:f075e92ce8d2	109
SED9008	0:f075e92ce8d2	110	/**
SED9008	0:f075e92ce8d2	111	* Get the sample rate divider.
SED9008	0:f075e92ce8d2	112	*
SED9008	0:f075e92ce8d2	113	* @return The sample rate divider as a number from 0-255.
SED9008	0:f075e92ce8d2	114	*/
SED9008	0:f075e92ce8d2	115	char getSampleRateDivider(void);
SED9008	0:f075e92ce8d2	116
SED9008	0:f075e92ce8d2	117	/**
SED9008	0:f075e92ce8d2	118	* Set the sample rate divider.
SED9008	0:f075e92ce8d2	119	*
SED9008	0:f075e92ce8d2	120	* Fsample = Finternal / (divider + 1), where Finternal = 1kHz or 8kHz,
SED9008	0:f075e92ce8d2	121	* as decidied by the DLPF_FS register.
SED9008	0:f075e92ce8d2	122	*
SED9008	0:f075e92ce8d2	123	* @param The sample rate divider as a number from 0-255.
SED9008	0:f075e92ce8d2	124	*/
SED9008	0:f075e92ce8d2	125	void setSampleRateDivider(char divider);
SED9008	0:f075e92ce8d2	126
SED9008	0:f075e92ce8d2	127	/**
SED9008	0:f075e92ce8d2	128	* Get the internal sample rate.
SED9008	0:f075e92ce8d2	129	*
SED9008	0:f075e92ce8d2	130	* @return The internal sample rate in kHz - either 1 or 8.
SED9008	0:f075e92ce8d2	131	*/
SED9008	0:f075e92ce8d2	132	int getInternalSampleRate(void);
SED9008	0:f075e92ce8d2	133
SED9008	0:f075e92ce8d2	134	/**
SED9008	0:f075e92ce8d2	135	* Set the low pass filter bandwidth.
SED9008	0:f075e92ce8d2	136	*
SED9008	0:f075e92ce8d2	137	* Also used to set the internal sample rate.
SED9008	0:f075e92ce8d2	138	* Pass the #define bandwidth codes as a parameter.
SED9008	0:f075e92ce8d2	139	*
SED9008	0:f075e92ce8d2	140	* 256Hz -> 8kHz internal sample rate.
SED9008	0:f075e92ce8d2	141	* Everything else -> 1kHz internal rate.
SED9008	0:f075e92ce8d2	142	*
SED9008	0:f075e92ce8d2	143	* @param bandwidth Low pass filter bandwidth code
SED9008	0:f075e92ce8d2	144	*/
SED9008	0:f075e92ce8d2	145	void setLpBandwidth(char bandwidth);
SED9008	0:f075e92ce8d2	146
SED9008	0:f075e92ce8d2	147	/**
SED9008	0:f075e92ce8d2	148	* Get the interrupt configuration.
SED9008	0:f075e92ce8d2	149	*
SED9008	0:f075e92ce8d2	150	* See datasheet for register contents details.
SED9008	0:f075e92ce8d2	151	*
SED9008	0:f075e92ce8d2	152	* 7 6 5 4
SED9008	0:f075e92ce8d2	153	* +------+------+--------------+------------------+
SED9008	0:f075e92ce8d2	154	* \| ACTL \| OPEN \| LATCH_INT_EN \| INT_ANYRD_2CLEAR \|
SED9008	0:f075e92ce8d2	155	* +------+------+--------------+------------------+
SED9008	0:f075e92ce8d2	156	*
SED9008	0:f075e92ce8d2	157	* 3 2 1 0
SED9008	0:f075e92ce8d2	158	* +---+------------+------------+---+
SED9008	0:f075e92ce8d2	159	* \| 0 \| ITG_RDY_EN \| RAW_RDY_EN \| 0 \|
SED9008	0:f075e92ce8d2	160	* +---+------------+------------+---+
SED9008	0:f075e92ce8d2	161	*
SED9008	0:f075e92ce8d2	162	* ACTL Logic level for INT output pin; 1 = active low, 0 = active high.
SED9008	0:f075e92ce8d2	163	* OPEN Drive type for INT output pin; 1 = open drain, 0 = push-pull.
SED9008	0:f075e92ce8d2	164	* LATCH_INT_EN Latch mode; 1 = latch until interrupt is cleared,
SED9008	0:f075e92ce8d2	165	* 0 = 50us pulse.
SED9008	0:f075e92ce8d2	166	* INT_ANYRD_2CLEAR Latch clear method; 1 = any register read,
SED9008	0:f075e92ce8d2	167	* 0 = status register read only.
SED9008	0:f075e92ce8d2	168	* ITG_RDY_EN Enable interrupt when device is ready,
SED9008	0:f075e92ce8d2	169	* (PLL ready after changing clock source).
SED9008	0:f075e92ce8d2	170	* RAW_RDY_EN Enable interrupt when data is available.
SED9008	0:f075e92ce8d2	171	* 0 Bits 1 and 3 of the INT_CFG register should be zero.
SED9008	0:f075e92ce8d2	172	*
SED9008	0:f075e92ce8d2	173	* @return the contents of the INT_CFG register.
SED9008	0:f075e92ce8d2	174	*/
SED9008	0:f075e92ce8d2	175	char getInterruptConfiguration(void);
SED9008	0:f075e92ce8d2	176
SED9008	0:f075e92ce8d2	177	/**
SED9008	0:f075e92ce8d2	178	* Set the interrupt configuration.
SED9008	0:f075e92ce8d2	179	*
SED9008	0:f075e92ce8d2	180	* See datasheet for configuration byte details.
SED9008	0:f075e92ce8d2	181	*
SED9008	0:f075e92ce8d2	182	* 7 6 5 4
SED9008	0:f075e92ce8d2	183	* +------+------+--------------+------------------+
SED9008	0:f075e92ce8d2	184	* \| ACTL \| OPEN \| LATCH_INT_EN \| INT_ANYRD_2CLEAR \|
SED9008	0:f075e92ce8d2	185	* +------+------+--------------+------------------+
SED9008	0:f075e92ce8d2	186	*
SED9008	0:f075e92ce8d2	187	* 3 2 1 0
SED9008	0:f075e92ce8d2	188	* +---+------------+------------+---+
SED9008	0:f075e92ce8d2	189	* \| 0 \| ITG_RDY_EN \| RAW_RDY_EN \| 0 \|
SED9008	0:f075e92ce8d2	190	* +---+------------+------------+---+
SED9008	0:f075e92ce8d2	191	*
SED9008	0:f075e92ce8d2	192	* ACTL Logic level for INT output pin; 1 = active low, 0 = active high.
SED9008	0:f075e92ce8d2	193	* OPEN Drive type for INT output pin; 1 = open drain, 0 = push-pull.
SED9008	0:f075e92ce8d2	194	* LATCH_INT_EN Latch mode; 1 = latch until interrupt is cleared,
SED9008	0:f075e92ce8d2	195	* 0 = 50us pulse.
SED9008	0:f075e92ce8d2	196	* INT_ANYRD_2CLEAR Latch clear method; 1 = any register read,
SED9008	0:f075e92ce8d2	197	* 0 = status register read only.
SED9008	0:f075e92ce8d2	198	* ITG_RDY_EN Enable interrupt when device is ready,
SED9008	0:f075e92ce8d2	199	* (PLL ready after changing clock source).
SED9008	0:f075e92ce8d2	200	* RAW_RDY_EN Enable interrupt when data is available.
SED9008	0:f075e92ce8d2	201	* 0 Bits 1 and 3 of the INT_CFG register should be zero.
SED9008	0:f075e92ce8d2	202	*
SED9008	0:f075e92ce8d2	203	* @param config Configuration byte to write to INT_CFG register.
SED9008	0:f075e92ce8d2	204	*/
SED9008	0:f075e92ce8d2	205	void setInterruptConfiguration(char config);
SED9008	0:f075e92ce8d2	206
SED9008	0:f075e92ce8d2	207	/**
SED9008	0:f075e92ce8d2	208	* Check the ITG_RDY bit of the INT_STATUS register.
SED9008	0:f075e92ce8d2	209	*
SED9008	0:f075e92ce8d2	210	* @return True if the ITG_RDY bit is set, corresponding to PLL ready,
SED9008	0:f075e92ce8d2	211	* false if the ITG_RDY bit is not set, corresponding to PLL not
SED9008	0:f075e92ce8d2	212	* ready.
SED9008	0:f075e92ce8d2	213	*/
SED9008	0:f075e92ce8d2	214	bool isPllReady(void);
SED9008	0:f075e92ce8d2	215
SED9008	0:f075e92ce8d2	216	/**
SED9008	0:f075e92ce8d2	217	* Check the RAW_DATA_RDY bit of the INT_STATUS register.
SED9008	0:f075e92ce8d2	218	*
SED9008	0:f075e92ce8d2	219	* @return True if the RAW_DATA_RDY bit is set, corresponding to new data
SED9008	0:f075e92ce8d2	220	* in the sensor registers, false if the RAW_DATA_RDY bit is not
SED9008	0:f075e92ce8d2	221	* set, corresponding to no new data yet in the sensor registers.
SED9008	0:f075e92ce8d2	222	*/
SED9008	0:f075e92ce8d2	223	bool isRawDataReady(void);
SED9008	0:f075e92ce8d2	224
SED9008	0:f075e92ce8d2	225	/**
SED9008	0:f075e92ce8d2	226	* Get the temperature of the device.
SED9008	0:f075e92ce8d2	227	*
SED9008	0:f075e92ce8d2	228	* @return The temperature in degrees celsius.
SED9008	0:f075e92ce8d2	229	*/
SED9008	0:f075e92ce8d2	230	float getTemperature(void);
SED9008	0:f075e92ce8d2	231
SED9008	0:f075e92ce8d2	232	/**
SED9008	0:f075e92ce8d2	233	* Get the output for the x-axis gyroscope.
SED9008	0:f075e92ce8d2	234	*
SED9008	0:f075e92ce8d2	235	* Typical sensitivity is 14.375 LSB/(degrees/sec).
SED9008	0:f075e92ce8d2	236	*
SED9008	0:f075e92ce8d2	237	* @return The output on the x-axis in raw ADC counts.
SED9008	0:f075e92ce8d2	238	*/
SED9008	0:f075e92ce8d2	239	int getGyroX(void);
SED9008	0:f075e92ce8d2	240
SED9008	0:f075e92ce8d2	241	/**
SED9008	0:f075e92ce8d2	242	* Get the output for the y-axis gyroscope.
SED9008	0:f075e92ce8d2	243	*
SED9008	0:f075e92ce8d2	244	* Typical sensitivity is 14.375 LSB/(degrees/sec).
SED9008	0:f075e92ce8d2	245	*
SED9008	0:f075e92ce8d2	246	* @return The output on the y-axis in raw ADC counts.
SED9008	0:f075e92ce8d2	247	*/
SED9008	0:f075e92ce8d2	248	int getGyroY(void);
SED9008	0:f075e92ce8d2	249
SED9008	0:f075e92ce8d2	250	/**
SED9008	0:f075e92ce8d2	251	* Get the output on the z-axis gyroscope.
SED9008	0:f075e92ce8d2	252	*
SED9008	0:f075e92ce8d2	253	* Typical sensitivity is 14.375 LSB/(degrees/sec).
SED9008	0:f075e92ce8d2	254	*
SED9008	0:f075e92ce8d2	255	* @return The output on the z-axis in raw ADC counts.
SED9008	0:f075e92ce8d2	256	*/
SED9008	0:f075e92ce8d2	257	int getGyroZ(void);
SED9008	0:f075e92ce8d2	258
SED9008	0:f075e92ce8d2	259	/**
SED9008	0:f075e92ce8d2	260	* Get the power management configuration.
SED9008	0:f075e92ce8d2	261	*
SED9008	0:f075e92ce8d2	262	* See the datasheet for register contents details.
SED9008	0:f075e92ce8d2	263	*
SED9008	0:f075e92ce8d2	264	* 7 6 5 4
SED9008	0:f075e92ce8d2	265	* +---------+-------+---------+---------+
SED9008	0:f075e92ce8d2	266	* \| H_RESET \| SLEEP \| STBY_XG \| STBY_YG \|
SED9008	0:f075e92ce8d2	267	* +---------+-------+---------+---------+
SED9008	0:f075e92ce8d2	268	*
SED9008	0:f075e92ce8d2	269	* 3 2 1 0
SED9008	0:f075e92ce8d2	270	* +---------+----------+----------+----------+
SED9008	0:f075e92ce8d2	271	* \| STBY_ZG \| CLK_SEL2 \| CLK_SEL1 \| CLK_SEL0 \|
SED9008	0:f075e92ce8d2	272	* +---------+----------+----------+----------+
SED9008	0:f075e92ce8d2	273	*
SED9008	0:f075e92ce8d2	274	* H_RESET Reset device and internal registers to the power-up-default settings.
SED9008	0:f075e92ce8d2	275	* SLEEP Enable low power sleep mode.
SED9008	0:f075e92ce8d2	276	* STBY_XG Put gyro X in standby mode (1=standby, 0=normal).
SED9008	0:f075e92ce8d2	277	* STBY_YG Put gyro Y in standby mode (1=standby, 0=normal).
SED9008	0:f075e92ce8d2	278	* STBY_ZG Put gyro Z in standby mode (1=standby, 0=normal).
SED9008	0:f075e92ce8d2	279	* CLK_SEL Select device clock source:
SED9008	0:f075e92ce8d2	280	*
SED9008	0:f075e92ce8d2	281	* CLK_SEL \| Clock Source
SED9008	0:f075e92ce8d2	282	* --------+--------------
SED9008	0:f075e92ce8d2	283	* 0 Internal oscillator
SED9008	0:f075e92ce8d2	284	* 1 PLL with X Gyro reference
SED9008	0:f075e92ce8d2	285	* 2 PLL with Y Gyro reference
SED9008	0:f075e92ce8d2	286	* 3 PLL with Z Gyro reference
SED9008	0:f075e92ce8d2	287	* 4 PLL with external 32.768kHz reference
SED9008	0:f075e92ce8d2	288	* 5 PLL with external 19.2MHz reference
SED9008	0:f075e92ce8d2	289	* 6 Reserved
SED9008	0:f075e92ce8d2	290	* 7 Reserved
SED9008	0:f075e92ce8d2	291	*
SED9008	0:f075e92ce8d2	292	* @return The contents of the PWR_MGM register.
SED9008	0:f075e92ce8d2	293	*/
SED9008	0:f075e92ce8d2	294	char getPowerManagement(void);
SED9008	0:f075e92ce8d2	295
SED9008	0:f075e92ce8d2	296	/**
SED9008	0:f075e92ce8d2	297	* Set power management configuration.
SED9008	0:f075e92ce8d2	298	*
SED9008	0:f075e92ce8d2	299	* See the datasheet for configuration byte details
SED9008	0:f075e92ce8d2	300	*
SED9008	0:f075e92ce8d2	301	* 7 6 5 4
SED9008	0:f075e92ce8d2	302	* +---------+-------+---------+---------+
SED9008	0:f075e92ce8d2	303	* \| H_RESET \| SLEEP \| STBY_XG \| STBY_YG \|
SED9008	0:f075e92ce8d2	304	* +---------+-------+---------+---------+
SED9008	0:f075e92ce8d2	305	*
SED9008	0:f075e92ce8d2	306	* 3 2 1 0
SED9008	0:f075e92ce8d2	307	* +---------+----------+----------+----------+
SED9008	0:f075e92ce8d2	308	* \| STBY_ZG \| CLK_SEL2 \| CLK_SEL1 \| CLK_SEL0 \|
SED9008	0:f075e92ce8d2	309	* +---------+----------+----------+----------+
SED9008	0:f075e92ce8d2	310	*
SED9008	0:f075e92ce8d2	311	* H_RESET Reset device and internal registers to the power-up-default settings.
SED9008	0:f075e92ce8d2	312	* SLEEP Enable low power sleep mode.
SED9008	0:f075e92ce8d2	313	* STBY_XG Put gyro X in standby mode (1=standby, 0=normal).
SED9008	0:f075e92ce8d2	314	* STBY_YG Put gyro Y in standby mode (1=standby, 0=normal).
SED9008	0:f075e92ce8d2	315	* STBY_ZG Put gyro Z in standby mode (1=standby, 0=normal).
SED9008	0:f075e92ce8d2	316	* CLK_SEL Select device clock source:
SED9008	0:f075e92ce8d2	317	*
SED9008	0:f075e92ce8d2	318	* CLK_SEL \| Clock Source
SED9008	0:f075e92ce8d2	319	* --------+--------------
SED9008	0:f075e92ce8d2	320	* 0 Internal oscillator
SED9008	0:f075e92ce8d2	321	* 1 PLL with X Gyro reference
SED9008	0:f075e92ce8d2	322	* 2 PLL with Y Gyro reference
SED9008	0:f075e92ce8d2	323	* 3 PLL with Z Gyro reference
SED9008	0:f075e92ce8d2	324	* 4 PLL with external 32.768kHz reference
SED9008	0:f075e92ce8d2	325	* 5 PLL with external 19.2MHz reference
SED9008	0:f075e92ce8d2	326	* 6 Reserved
SED9008	0:f075e92ce8d2	327	* 7 Reserved
SED9008	0:f075e92ce8d2	328	*
SED9008	0:f075e92ce8d2	329	* @param config The configuration byte to write to the PWR_MGM register.
SED9008	0:f075e92ce8d2	330	*/
SED9008	0:f075e92ce8d2	331	void setPowerManagement(char config);
SED9008	0:f075e92ce8d2	332
SED9008	0:f075e92ce8d2	333	private:
SED9008	0:f075e92ce8d2	334
SED9008	0:f075e92ce8d2	335	I2C i2c_;
SED9008	0:f075e92ce8d2	336
SED9008	0:f075e92ce8d2	337	};
SED9008	0:f075e92ce8d2	338
SED9008	0:f075e92ce8d2	339	#endif /* ITG3200_H */

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Type:	Library
Created:	01 Jun 2012
Imports:	4
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ITG3200.h@0:f075e92ce8d2, 2012-06-01 (annotated)

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