LPC_I2C_T Struct Reference
[CHIP: LPC11xx I2C driver]

I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

Definition at line 53 of file i2c_11xx.h.

I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

Definition at line 58 of file i2c_11xx.h.

I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

Definition at line 59 of file i2c_11xx.h.

I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.

Definition at line 60 of file i2c_11xx.h.

I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.

Definition at line 56 of file i2c_11xx.h.

I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.

Definition at line 50 of file i2c_11xx.h.

I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.

Definition at line 52 of file i2c_11xx.h.

Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.

Definition at line 61 of file i2c_11xx.h.

I2C Slave address mask register

Definition at line 62 of file i2c_11xx.h.

Monitor mode control register.

Definition at line 57 of file i2c_11xx.h.

SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.

Definition at line 54 of file i2c_11xx.h.

SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.

Definition at line 55 of file i2c_11xx.h.

I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.

Definition at line 51 of file i2c_11xx.h.