Richard Collins
/
USBHostControllerDriver
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HardwareDefines.h@2:33e7ce63dd6d, 2012-09-19 (annotated)
- Committer:
- RichardUK
- Date:
- Wed Sep 19 16:44:32 2012 +0000
- Revision:
- 2:33e7ce63dd6d
- Parent:
- 1:4461071ed964
Testing lib update to another project.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| RichardUK | 0:63d45df56584 | 1 | /* |
| RichardUK | 0:63d45df56584 | 2 | A host controller driver from the mBed device. |
| RichardUK | 0:63d45df56584 | 3 | Copyright (C) 2012 Richard e Collins - richard.collins@linux.com |
| RichardUK | 0:63d45df56584 | 4 | |
| RichardUK | 0:63d45df56584 | 5 | This program is free software: you can redistribute it and/or modify |
| RichardUK | 0:63d45df56584 | 6 | it under the terms of the GNU General Public License as published by |
| RichardUK | 0:63d45df56584 | 7 | the Free Software Foundation, either version 3 of the License, or |
| RichardUK | 0:63d45df56584 | 8 | (at your option) any later version. |
| RichardUK | 0:63d45df56584 | 9 | |
| RichardUK | 0:63d45df56584 | 10 | This program is distributed in the hope that it will be useful, |
| RichardUK | 0:63d45df56584 | 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| RichardUK | 0:63d45df56584 | 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| RichardUK | 0:63d45df56584 | 13 | GNU General Public License for more details. |
| RichardUK | 0:63d45df56584 | 14 | |
| RichardUK | 0:63d45df56584 | 15 | You should have received a copy of the GNU General Public License |
| RichardUK | 0:63d45df56584 | 16 | along with this program. If not, see <http://www.gnu.org/licenses/>. |
| RichardUK | 0:63d45df56584 | 17 | */ |
| RichardUK | 0:63d45df56584 | 18 | |
| RichardUK | 0:63d45df56584 | 19 | #ifndef __HARDWARE_DEFINES_H__ |
| RichardUK | 0:63d45df56584 | 20 | #define __HARDWARE_DEFINES_H__ |
| RichardUK | 0:63d45df56584 | 21 | |
| RichardUK | 0:63d45df56584 | 22 | //USB interface power/clock control bit in PCONP (Power Control for Peripherals register) |
| RichardUK | 0:63d45df56584 | 23 | #define PCUSB (1U<<31) |
| RichardUK | 0:63d45df56584 | 24 | |
| RichardUK | 0:63d45df56584 | 25 | |
| RichardUK | 0:63d45df56584 | 26 | /** |
| RichardUK | 0:63d45df56584 | 27 | * HcInterruptStatus Register |
| RichardUK | 0:63d45df56584 | 28 | * This register provides status on various events that cause hardware interrupts. When an event |
| RichardUK | 0:63d45df56584 | 29 | * occurs, Host Controller sets the corresponding bit in this register. When a bit becomes set, a |
| RichardUK | 0:63d45df56584 | 30 | * hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register (see |
| RichardUK | 0:63d45df56584 | 31 | * Section 7.1.5) and the MasterInterruptEnable bit is set. The Host Controller Driver may clear |
| RichardUK | 0:63d45df56584 | 32 | * specific bits in this register by writing �1� to bit positions to be cleared. The Host Controller |
| RichardUK | 0:63d45df56584 | 33 | * Driver may not set any of these bits. The Host Controller will never clear the bit. |
| RichardUK | 0:63d45df56584 | 34 | * |
| RichardUK | 0:63d45df56584 | 35 | * This bit is set when the USB schedule for the current Frame |
| RichardUK | 0:63d45df56584 | 36 | * overruns and after the update of HccaFrameNumber. A |
| RichardUK | 0:63d45df56584 | 37 | * scheduling overrun will also cause the |
| RichardUK | 0:63d45df56584 | 38 | * SchedulingOverrunCount of HcCommandStatus to be |
| RichardUK | 0:63d45df56584 | 39 | * incremented. |
| RichardUK | 0:63d45df56584 | 40 | */ |
| RichardUK | 0:63d45df56584 | 41 | #define INTERRUPT_SCHEDULING_OVERRUN (1U<<0) |
| RichardUK | 0:63d45df56584 | 42 | |
| RichardUK | 0:63d45df56584 | 43 | /** |
| RichardUK | 0:63d45df56584 | 44 | * This bit is set immediately after HC has written HcDoneHead to |
| RichardUK | 0:63d45df56584 | 45 | * HccaDoneHead. Further updates of the HccaDoneHead will not |
| RichardUK | 0:63d45df56584 | 46 | * occur until this bit has been cleared. HCD should only clear this |
| RichardUK | 0:63d45df56584 | 47 | * bit after it has saved the content of HccaDoneHead. |
| RichardUK | 0:63d45df56584 | 48 | */ |
| RichardUK | 0:63d45df56584 | 49 | #define INTERRUPT_WRITEBACK_HEAD_DONE (1U<<1) |
| RichardUK | 0:63d45df56584 | 50 | |
| RichardUK | 0:63d45df56584 | 51 | /** |
| RichardUK | 0:63d45df56584 | 52 | * This bit is set by HC at each start of a frame and after the |
| RichardUK | 0:63d45df56584 | 53 | * update of HccaFrameNumber. HC also generates a SOF token |
| RichardUK | 0:63d45df56584 | 54 | * at the same time. |
| RichardUK | 0:63d45df56584 | 55 | */ |
| RichardUK | 0:63d45df56584 | 56 | #define INTERRUPT_START_OF_FRAME (1U<<2) |
| RichardUK | 0:63d45df56584 | 57 | |
| RichardUK | 0:63d45df56584 | 58 | /** |
| RichardUK | 0:63d45df56584 | 59 | * This bit is set when HC detects that a device on the USB is |
| RichardUK | 0:63d45df56584 | 60 | * asserting resume signaling. It is the transition from no resume |
| RichardUK | 0:63d45df56584 | 61 | * signaling to resume signaling causing this bit to be set. This bit |
| RichardUK | 0:63d45df56584 | 62 | * is not set when HCD sets the USBRESUME state. |
| RichardUK | 0:63d45df56584 | 63 | */ |
| RichardUK | 0:63d45df56584 | 64 | #define INTERRUPT_RESUME_DETECTED (1U<<3) |
| RichardUK | 0:63d45df56584 | 65 | |
| RichardUK | 0:63d45df56584 | 66 | /** |
| RichardUK | 0:63d45df56584 | 67 | * This bit is set when HC detects a system error not related to |
| RichardUK | 0:63d45df56584 | 68 | * USB. HC should not proceed with any processing nor signaling |
| RichardUK | 0:63d45df56584 | 69 | * before the system error has been corrected. HCD clears this bit |
| RichardUK | 0:63d45df56584 | 70 | * after HC has been reset. |
| RichardUK | 0:63d45df56584 | 71 | */ |
| RichardUK | 0:63d45df56584 | 72 | #define INTERRUPT_UNRECOVERABLE_ERROR (1U<<4) |
| RichardUK | 0:63d45df56584 | 73 | |
| RichardUK | 0:63d45df56584 | 74 | /** |
| RichardUK | 0:63d45df56584 | 75 | * This bit is set when the MSb of HcFmNumber (bit 15) changes |
| RichardUK | 0:63d45df56584 | 76 | * value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber |
| RichardUK | 0:63d45df56584 | 77 | * has been updated. |
| RichardUK | 0:63d45df56584 | 78 | */ |
| RichardUK | 0:63d45df56584 | 79 | #define INTERRUPT_FRAME_NUMBER_OVERFLOW (1U<<5) |
| RichardUK | 0:63d45df56584 | 80 | |
| RichardUK | 0:63d45df56584 | 81 | /** |
| RichardUK | 0:63d45df56584 | 82 | * This bit is set when the content of HcRhStatus or the content of |
| RichardUK | 0:63d45df56584 | 83 | * any of HcRhPortStatus[NumberofDownstreamPort] has |
| RichardUK | 0:63d45df56584 | 84 | * changed. |
| RichardUK | 0:63d45df56584 | 85 | */ |
| RichardUK | 0:63d45df56584 | 86 | #define INTERRUPT_ROOTHUB_STATUS_CHANGE (1U<<6) |
| RichardUK | 0:63d45df56584 | 87 | |
| RichardUK | 0:63d45df56584 | 88 | /** |
| RichardUK | 0:63d45df56584 | 89 | * This bit is set by HC when HCD sets the |
| RichardUK | 0:63d45df56584 | 90 | * OwnershipChangeRequest field in HcCommandStatus. This |
| RichardUK | 0:63d45df56584 | 91 | * event, when unmasked, will always generate an System |
| RichardUK | 0:63d45df56584 | 92 | * Management Interrupt (SMI) immediately. |
| RichardUK | 0:63d45df56584 | 93 | * This bit is tied to 0b when the SMI pin is not implemented. |
| RichardUK | 0:63d45df56584 | 94 | */ |
| RichardUK | 0:63d45df56584 | 95 | #define INTERRUPT_OWNERSHIP_CHANGED (1U<<30) |
| RichardUK | 0:63d45df56584 | 96 | |
| RichardUK | 0:63d45df56584 | 97 | /** |
| RichardUK | 0:63d45df56584 | 98 | * Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the |
| RichardUK | 0:63d45df56584 | 99 | * HcInterruptStatus register. The HcInterruptEnable register is used to control which events |
| RichardUK | 0:63d45df56584 | 100 | * generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the |
| RichardUK | 0:63d45df56584 | 101 | * corresponding bit in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is |
| RichardUK | 0:63d45df56584 | 102 | * set, then a hardware interrupt is requested on the host bus. |
| RichardUK | 0:63d45df56584 | 103 | * Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this |
| RichardUK | 0:63d45df56584 | 104 | * register leaves the corresponding bit unchanged. On read, the current value of this register is |
| RichardUK | 0:63d45df56584 | 105 | * returned. |
| RichardUK | 0:63d45df56584 | 106 | * |
| RichardUK | 0:63d45df56584 | 107 | * |
| RichardUK | 0:63d45df56584 | 108 | * A �0� written to this field is ignored by HC. A '1' written to this |
| RichardUK | 0:63d45df56584 | 109 | * field enables interrupt generation due to events specified in the |
| RichardUK | 0:63d45df56584 | 110 | * other bits of this register. This is used by HCD as a Master Interrupt Enable. |
| RichardUK | 0:63d45df56584 | 111 | */ |
| RichardUK | 0:63d45df56584 | 112 | #define INTERRUPT_MASTER_INTERRUPT_ENABLE (1U<<31) |
| RichardUK | 0:63d45df56584 | 113 | |
| RichardUK | 0:63d45df56584 | 114 | |
| RichardUK | 0:63d45df56584 | 115 | /** |
| RichardUK | 0:63d45df56584 | 116 | * HcRhPortStatus[1:NDP] Register ROOT HUB, mBed chip only has one. |
| RichardUK | 0:63d45df56584 | 117 | * The HcRhPortStatus[1:NDP] register is used to control and report port events on a per-port |
| RichardUK | 0:63d45df56584 | 118 | * basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are |
| RichardUK | 0:63d45df56584 | 119 | * implemented in hardware. The lower word is used to reflect the port status, whereas the upper |
| RichardUK | 0:63d45df56584 | 120 | * word reflects the status change bits. Some status bits are implemented with special write behavior |
| RichardUK | 0:63d45df56584 | 121 | * (see below). If a transaction (token through handshake) is in progress when a write to change |
| RichardUK | 0:63d45df56584 | 122 | * port status occurs, the resulting port status change must be postponed until the transaction |
| RichardUK | 0:63d45df56584 | 123 | * completes. Reserved bits should always be written '0'. |
| RichardUK | 0:63d45df56584 | 124 | */ |
| RichardUK | 0:63d45df56584 | 125 | |
| RichardUK | 0:63d45df56584 | 126 | /** |
| RichardUK | 0:63d45df56584 | 127 | * This bit reflects the current state of the downstream port. |
| RichardUK | 0:63d45df56584 | 128 | * 0 = no device connected |
| RichardUK | 0:63d45df56584 | 129 | * 1 = device connected |
| RichardUK | 0:63d45df56584 | 130 | * (write) ClearPortEnable |
| RichardUK | 0:63d45df56584 | 131 | * The HCD writes a �1� to this bit to clear the PortEnableStatus bit. |
| RichardUK | 0:63d45df56584 | 132 | * Writing a �0� has no effect. The CurrentConnectStatus is not |
| RichardUK | 0:63d45df56584 | 133 | * affected by any write. |
| RichardUK | 0:63d45df56584 | 134 | * Note: This bit is always read �1b� when the attached device is |
| RichardUK | 0:63d45df56584 | 135 | * nonremovable (DeviceRemoveable[NDP]). |
| RichardUK | 0:63d45df56584 | 136 | */ |
| RichardUK | 0:63d45df56584 | 137 | #define ROOTHUB_CURRENT_CONNECT_STATUS (1U<<0) |
| RichardUK | 0:63d45df56584 | 138 | |
| RichardUK | 0:63d45df56584 | 139 | /** |
| RichardUK | 0:63d45df56584 | 140 | * (read) PortResetStatus |
| RichardUK | 0:63d45df56584 | 141 | * When this bit is set by a write to SetPortReset, port reset |
| RichardUK | 0:63d45df56584 | 142 | * signaling is asserted. When reset is completed, this bit is cleared |
| RichardUK | 0:63d45df56584 | 143 | * when PortResetStatusChange is set. This bit cannot be set if |
| RichardUK | 0:63d45df56584 | 144 | * CurrentConnectStatus is cleared. |
| RichardUK | 0:63d45df56584 | 145 | * 0 = port reset signal is not active |
| RichardUK | 0:63d45df56584 | 146 | * 1 = port reset signal is active |
| RichardUK | 0:63d45df56584 | 147 | * |
| RichardUK | 0:63d45df56584 | 148 | * (write) SetPortReset |
| RichardUK | 0:63d45df56584 | 149 | * The HCD sets the port reset signaling by writing a �1� to this bit. |
| RichardUK | 0:63d45df56584 | 150 | * Writing a �0� has no effect. If CurrentConnectStatus is cleared, |
| RichardUK | 0:63d45df56584 | 151 | * this write does not set PortResetStatus, but instead sets |
| RichardUK | 0:63d45df56584 | 152 | * ConnectStatusChange. This informs the driver that it attempted |
| RichardUK | 0:63d45df56584 | 153 | * to reset a disconnected port. |
| RichardUK | 0:63d45df56584 | 154 | */ |
| RichardUK | 0:63d45df56584 | 155 | #define ROOTHUB_PORT_RESET_STATUS (1U<<4) |
| RichardUK | 0:63d45df56584 | 156 | |
| RichardUK | 0:63d45df56584 | 157 | /** |
| RichardUK | 0:63d45df56584 | 158 | * (read) LowSpeedDeviceAttached |
| RichardUK | 0:63d45df56584 | 159 | * This bit indicates the speed of the device attached to this port. |
| RichardUK | 0:63d45df56584 | 160 | * When set, a Low Speed device is attached to this port. When |
| RichardUK | 0:63d45df56584 | 161 | * clear, a Full Speed device is attached to this port. This field is |
| RichardUK | 0:63d45df56584 | 162 | * valid only when the CurrentConnectStatus is set. |
| RichardUK | 0:63d45df56584 | 163 | * 0 = full speed device attached |
| RichardUK | 0:63d45df56584 | 164 | * 1 = low speed device attached |
| RichardUK | 0:63d45df56584 | 165 | * |
| RichardUK | 0:63d45df56584 | 166 | * (write) ClearPortPower |
| RichardUK | 0:63d45df56584 | 167 | * The HCD clears the PortPowerStatus bit by writing a �1� to this |
| RichardUK | 0:63d45df56584 | 168 | * bit. Writing a �0� has no effect. |
| RichardUK | 0:63d45df56584 | 169 | */ |
| RichardUK | 0:63d45df56584 | 170 | #define ROOTHUB_LOW_SPEED_DEVICE_ATTACHED (1U<<9) |
| RichardUK | 0:63d45df56584 | 171 | |
| RichardUK | 0:63d45df56584 | 172 | /** |
| RichardUK | 0:63d45df56584 | 173 | * ConnectStatusChange. |
| RichardUK | 0:63d45df56584 | 174 | * This bit is set whenever a connect or disconnect event occurs. |
| RichardUK | 0:63d45df56584 | 175 | * The HCD writes a �1� to clear this bit. Writing a �0� has no effect. If |
| RichardUK | 0:63d45df56584 | 176 | * CurrentConnectStatus is cleared when a SetPortReset, |
| RichardUK | 0:63d45df56584 | 177 | * SetPortEnable, or SetPortSuspend write occurs, this bit is set to |
| RichardUK | 0:63d45df56584 | 178 | * force the driver to re-evaluate the connection status since these |
| RichardUK | 0:63d45df56584 | 179 | * writes should not occur if the port is disconnected. |
| RichardUK | 0:63d45df56584 | 180 | * 0 = no change in CurrentConnectStatus |
| RichardUK | 0:63d45df56584 | 181 | * 1 = change in CurrentConnectStatus |
| RichardUK | 0:63d45df56584 | 182 | * Note: If the DeviceRemovable[NDP] bit is set, this bit is set only |
| RichardUK | 0:63d45df56584 | 183 | * after a Root Hub reset to inform the system that the device is |
| RichardUK | 0:63d45df56584 | 184 | * attached. |
| RichardUK | 0:63d45df56584 | 185 | */ |
| RichardUK | 0:63d45df56584 | 186 | #define ROOTHUB_CONNECT_STATUS_CHANGE (1U<<16) |
| RichardUK | 0:63d45df56584 | 187 | |
| RichardUK | 0:63d45df56584 | 188 | /** |
| RichardUK | 0:63d45df56584 | 189 | * PortResetStatusChange |
| RichardUK | 0:63d45df56584 | 190 | * This bit is set at the end of the 10-ms port reset signal. |
| RichardUK | 0:63d45df56584 | 191 | * The HCD writes a �1� to clear this bit. Writing a �0� has no effect. |
| RichardUK | 0:63d45df56584 | 192 | * 0 = port reset is not complete |
| RichardUK | 0:63d45df56584 | 193 | * 1 = port reset is complete |
| RichardUK | 0:63d45df56584 | 194 | */ |
| RichardUK | 0:63d45df56584 | 195 | #define ROOTHUB_PORT_RESET_STATUS_CHANGE (1U<<20) |
| RichardUK | 0:63d45df56584 | 196 | |
| RichardUK | 0:63d45df56584 | 197 | |
| RichardUK | 0:63d45df56584 | 198 | //=================================================================== |
| RichardUK | 0:63d45df56584 | 199 | // Taken from USBHost.cpp written by Copyright (c) 2010 Peter Barrett |
| RichardUK | 0:63d45df56584 | 200 | //=================================================================== |
| RichardUK | 0:63d45df56584 | 201 | // Hardware defines |
| RichardUK | 0:63d45df56584 | 202 | |
| RichardUK | 0:63d45df56584 | 203 | // HcControl |
| RichardUK | 0:63d45df56584 | 204 | |
| RichardUK | 0:63d45df56584 | 205 | #define ControlListEnable 0x00000010 |
| RichardUK | 1:4461071ed964 | 206 | #define BulkListEnable 0x00000020 |
| RichardUK | 0:63d45df56584 | 207 | |
| RichardUK | 0:63d45df56584 | 208 | #define OperationalMask 0x00000080 |
| RichardUK | 0:63d45df56584 | 209 | #define HostControllerFunctionalState 0x000000C0 |
| RichardUK | 0:63d45df56584 | 210 | |
| RichardUK | 0:63d45df56584 | 211 | // HcCommandStatus |
| RichardUK | 0:63d45df56584 | 212 | #define HostControllerReset 0x00000001 |
| RichardUK | 0:63d45df56584 | 213 | #define ControlListFilled 0x00000002 |
| RichardUK | 1:4461071ed964 | 214 | #define BulkListFilled 0x00000004 |
| RichardUK | 0:63d45df56584 | 215 | |
| RichardUK | 0:63d45df56584 | 216 | // HcInterruptStatus Register |
| RichardUK | 0:63d45df56584 | 217 | #define MasterInterruptEnable 0x80000000 |
| RichardUK | 0:63d45df56584 | 218 | |
| RichardUK | 0:63d45df56584 | 219 | // HcRhStatus |
| RichardUK | 0:63d45df56584 | 220 | #define SetGlobalPower 0x00010000 |
| RichardUK | 0:63d45df56584 | 221 | |
| RichardUK | 0:63d45df56584 | 222 | //For the clock stuff. |
| RichardUK | 0:63d45df56584 | 223 | #define FRAMEINTERVAL (12000-1) // 1ms |
| RichardUK | 0:63d45df56584 | 224 | #define DEFAULT_FMINTERVAL ((((6 * (FRAMEINTERVAL - 210)) / 7) << 16) | FRAMEINTERVAL) |
| RichardUK | 0:63d45df56584 | 225 | |
| RichardUK | 0:63d45df56584 | 226 | |
| RichardUK | 0:63d45df56584 | 227 | #endif //__HARDWARE_DEFINES_H__ |