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/*
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A host controller driver from the mBed device.
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Copyright (C) 2012 Richard e Collins - richard.collins@linux.com
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __HARDWARE_DEFINES_H__
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#define __HARDWARE_DEFINES_H__
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//USB interface power/clock control bit in PCONP (Power Control for Peripherals register)
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#define PCUSB (1U<<31)
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/**
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* HcInterruptStatus Register
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* This register provides status on various events that cause hardware interrupts. When an event
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* occurs, Host Controller sets the corresponding bit in this register. When a bit becomes set, a
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* hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register (see
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* Section 7.1.5) and the MasterInterruptEnable bit is set. The Host Controller Driver may clear
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* specific bits in this register by writing �1� to bit positions to be cleared. The Host Controller
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* Driver may not set any of these bits. The Host Controller will never clear the bit.
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*
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* This bit is set when the USB schedule for the current Frame
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* overruns and after the update of HccaFrameNumber. A
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* scheduling overrun will also cause the
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* SchedulingOverrunCount of HcCommandStatus to be
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* incremented.
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*/
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#define INTERRUPT_SCHEDULING_OVERRUN (1U<<0)
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/**
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* This bit is set immediately after HC has written HcDoneHead to
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* HccaDoneHead. Further updates of the HccaDoneHead will not
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* occur until this bit has been cleared. HCD should only clear this
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* bit after it has saved the content of HccaDoneHead.
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*/
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#define INTERRUPT_WRITEBACK_HEAD_DONE (1U<<1)
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/**
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* This bit is set by HC at each start of a frame and after the
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* update of HccaFrameNumber. HC also generates a SOF token
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* at the same time.
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*/
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#define INTERRUPT_START_OF_FRAME (1U<<2)
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/**
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* This bit is set when HC detects that a device on the USB is
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* asserting resume signaling. It is the transition from no resume
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* signaling to resume signaling causing this bit to be set. This bit
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* is not set when HCD sets the USBRESUME state.
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*/
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#define INTERRUPT_RESUME_DETECTED (1U<<3)
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/**
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* This bit is set when HC detects a system error not related to
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* USB. HC should not proceed with any processing nor signaling
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* before the system error has been corrected. HCD clears this bit
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* after HC has been reset.
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*/
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#define INTERRUPT_UNRECOVERABLE_ERROR (1U<<4)
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/**
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* This bit is set when the MSb of HcFmNumber (bit 15) changes
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* value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber
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* has been updated.
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*/
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#define INTERRUPT_FRAME_NUMBER_OVERFLOW (1U<<5)
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/**
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* This bit is set when the content of HcRhStatus or the content of
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* any of HcRhPortStatus[NumberofDownstreamPort] has
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* changed.
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*/
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#define INTERRUPT_ROOTHUB_STATUS_CHANGE (1U<<6)
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/**
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* This bit is set by HC when HCD sets the
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* OwnershipChangeRequest field in HcCommandStatus. This
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* event, when unmasked, will always generate an System
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* Management Interrupt (SMI) immediately.
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* This bit is tied to 0b when the SMI pin is not implemented.
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*/
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#define INTERRUPT_OWNERSHIP_CHANGED (1U<<30)
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/**
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* Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the
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* HcInterruptStatus register. The HcInterruptEnable register is used to control which events
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* generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the
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* corresponding bit in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is
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* set, then a hardware interrupt is requested on the host bus.
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* Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this
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* register leaves the corresponding bit unchanged. On read, the current value of this register is
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* returned.
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*
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*
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* A �0� written to this field is ignored by HC. A '1' written to this
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* field enables interrupt generation due to events specified in the
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* other bits of this register. This is used by HCD as a Master Interrupt Enable.
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*/
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#define INTERRUPT_MASTER_INTERRUPT_ENABLE (1U<<31)
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/**
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* HcRhPortStatus[1:NDP] Register ROOT HUB, mBed chip only has one.
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* The HcRhPortStatus[1:NDP] register is used to control and report port events on a per-port
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* basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are
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* implemented in hardware. The lower word is used to reflect the port status, whereas the upper
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* word reflects the status change bits. Some status bits are implemented with special write behavior
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* (see below). If a transaction (token through handshake) is in progress when a write to change
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* port status occurs, the resulting port status change must be postponed until the transaction
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* completes. Reserved bits should always be written '0'.
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*/
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/**
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* This bit reflects the current state of the downstream port.
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* 0 = no device connected
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* 1 = device connected
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* (write) ClearPortEnable
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* The HCD writes a �1� to this bit to clear the PortEnableStatus bit.
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* Writing a �0� has no effect. The CurrentConnectStatus is not
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* affected by any write.
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* Note: This bit is always read �1b� when the attached device is
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* nonremovable (DeviceRemoveable[NDP]).
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*/
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#define ROOTHUB_CURRENT_CONNECT_STATUS (1U<<0)
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/**
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* (read) PortResetStatus
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* When this bit is set by a write to SetPortReset, port reset
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* signaling is asserted. When reset is completed, this bit is cleared
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* when PortResetStatusChange is set. This bit cannot be set if
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* CurrentConnectStatus is cleared.
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* 0 = port reset signal is not active
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* 1 = port reset signal is active
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*
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* (write) SetPortReset
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* The HCD sets the port reset signaling by writing a �1� to this bit.
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* Writing a �0� has no effect. If CurrentConnectStatus is cleared,
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* this write does not set PortResetStatus, but instead sets
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* ConnectStatusChange. This informs the driver that it attempted
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* to reset a disconnected port.
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*/
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#define ROOTHUB_PORT_RESET_STATUS (1U<<4)
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/**
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* (read) LowSpeedDeviceAttached
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* This bit indicates the speed of the device attached to this port.
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* When set, a Low Speed device is attached to this port. When
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* clear, a Full Speed device is attached to this port. This field is
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* valid only when the CurrentConnectStatus is set.
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* 0 = full speed device attached
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* 1 = low speed device attached
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*
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* (write) ClearPortPower
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* The HCD clears the PortPowerStatus bit by writing a �1� to this
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* bit. Writing a �0� has no effect.
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*/
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#define ROOTHUB_LOW_SPEED_DEVICE_ATTACHED (1U<<9)
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/**
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* ConnectStatusChange.
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* This bit is set whenever a connect or disconnect event occurs.
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* The HCD writes a �1� to clear this bit. Writing a �0� has no effect. If
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* CurrentConnectStatus is cleared when a SetPortReset,
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* SetPortEnable, or SetPortSuspend write occurs, this bit is set to
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* force the driver to re-evaluate the connection status since these
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* writes should not occur if the port is disconnected.
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* 0 = no change in CurrentConnectStatus
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181
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* 1 = change in CurrentConnectStatus
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* Note: If the DeviceRemovable[NDP] bit is set, this bit is set only
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* after a Root Hub reset to inform the system that the device is
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* attached.
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*/
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#define ROOTHUB_CONNECT_STATUS_CHANGE (1U<<16)
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/**
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* PortResetStatusChange
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* This bit is set at the end of the 10-ms port reset signal.
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191
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* The HCD writes a �1� to clear this bit. Writing a �0� has no effect.
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192
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* 0 = port reset is not complete
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* 1 = port reset is complete
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*/
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#define ROOTHUB_PORT_RESET_STATUS_CHANGE (1U<<20)
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//===================================================================
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// Taken from USBHost.cpp written by Copyright (c) 2010 Peter Barrett
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//===================================================================
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// Hardware defines
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// HcControl
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#define ControlListEnable 0x00000010
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#define BulkListEnable 0x00000020
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#define OperationalMask 0x00000080
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#define HostControllerFunctionalState 0x000000C0
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// HcCommandStatus
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#define HostControllerReset 0x00000001
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#define ControlListFilled 0x00000002
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#define BulkListFilled 0x00000004
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215
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// HcInterruptStatus Register
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#define MasterInterruptEnable 0x80000000
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// HcRhStatus
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#define SetGlobalPower 0x00010000
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221
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//For the clock stuff.
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#define FRAMEINTERVAL (12000-1) // 1ms
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#define DEFAULT_FMINTERVAL ((((6 * (FRAMEINTERVAL - 210)) / 7) << 16) | FRAMEINTERVAL)
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#endif //__HARDWARE_DEFINES_H__
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