Motoo Tanaka / SPI_IS25LQ032B

ISSI IS25LQ032B 3V-Quad Serial Flash Memory with Multi-I/O SPI

Dependents:   testSPI_IS25LQ032B SPI_Flash_erase

SPI Flash Memory ISSI IS25LQ032B library.

Although the device has lots of features, only a small portion of commands were implemented. (sorry)

For the data sheet please refer to http://www.issi.com/WW/pdf/25LQ080B-016B-032B.pdf

SPI_IS25LQ032B.cpp@0:3f3dd929e3e5, 2014-12-25 (annotated)

Committer:
Rhyme
Date:
Thu Dec 25 00:46:17 2014 +0000
Revision:
0:3f3dd929e3e5
Commit before publish

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Rhyme 0:3f3dd929e3e5 1 /** SPI_IS25LQ032B ISSI 3V - QUAD SERIAL FLASH MEMORY MULTI-I/O SPI
Rhyme 0:3f3dd929e3e5 2 * Data Sheet: http://www.issi.com/WW/pdf/25LQ080B-016B-032B.pdf
Rhyme 0:3f3dd929e3e5 3 *
Rhyme 0:3f3dd929e3e5 4 */
Rhyme 0:3f3dd929e3e5 5
Rhyme 0:3f3dd929e3e5 6 #include "SPI_IS25LQ032B.h"
Rhyme 0:3f3dd929e3e5 7
Rhyme 0:3f3dd929e3e5 8 #define CMD_RD 0x03
Rhyme 0:3f3dd929e3e5 9 #define CMD_FR 0x0B
Rhyme 0:3f3dd929e3e5 10 #define CMD_FRDIO 0xBB
Rhyme 0:3f3dd929e3e5 11 #define CMD_FRDO 0x3B
Rhyme 0:3f3dd929e3e5 12 #define CMD_FRQIO 0xEB
Rhyme 0:3f3dd929e3e5 13 #define CMD_FRQO 0x6B
Rhyme 0:3f3dd929e3e5 14 #define CMD_PP 0x02
Rhyme 0:3f3dd929e3e5 15 #define CMD_PPQ 0x38
Rhyme 0:3f3dd929e3e5 16 #define CMD_SER 0xD7
Rhyme 0:3f3dd929e3e5 17 #define CMD_SER2 0x20
Rhyme 0:3f3dd929e3e5 18 #define CMD_BER32 0x52
Rhyme 0:3f3dd929e3e5 19 #define CMD_BER64 0xD8
Rhyme 0:3f3dd929e3e5 20 #define CMD_CER 0xC7
Rhyme 0:3f3dd929e3e5 21 #define CMD_WREN 0x06
Rhyme 0:3f3dd929e3e5 22 #define CMD_WRDI 0x04
Rhyme 0:3f3dd929e3e5 23 #define CMD_RDSR 0x05
Rhyme 0:3f3dd929e3e5 24 #define CMD_WRSR 0x01
Rhyme 0:3f3dd929e3e5 25 #define CMD_RDFR 0x48
Rhyme 0:3f3dd929e3e5 26 #define CMD_WRFR 0x42
Rhyme 0:3f3dd929e3e5 27 #define CMD_PERSUS 0x75
Rhyme 0:3f3dd929e3e5 28 #define CMD_PERSUS2 0xB0
Rhyme 0:3f3dd929e3e5 29 #define CMD_PERRSM 0x7A
Rhyme 0:3f3dd929e3e5 30 #define CMD_PERRSM2 0x30
Rhyme 0:3f3dd929e3e5 31 #define CMD_DP 0xB9
Rhyme 0:3f3dd929e3e5 32 #define CMD_RDID 0xAB
Rhyme 0:3f3dd929e3e5 33 #define CMD_RDPD 0xAB
Rhyme 0:3f3dd929e3e5 34 #define CMD_RDUID 0x4B
Rhyme 0:3f3dd929e3e5 35 #define CMD_RDJDID 0x9F
Rhyme 0:3f3dd929e3e5 36 #define CMD_RDMDID 0x90
Rhyme 0:3f3dd929e3e5 37 #define CMD_RDSFDP 0x5A
Rhyme 0:3f3dd929e3e5 38 #define CMD_RSTEN 0x66
Rhyme 0:3f3dd929e3e5 39 #define CMD_RST 0x99
Rhyme 0:3f3dd929e3e5 40 #define CMD_RSTM 0xFF
Rhyme 0:3f3dd929e3e5 41 #define CMD_IRP 0x62
Rhyme 0:3f3dd929e3e5 42 #define CMD_IRRD 0x68
Rhyme 0:3f3dd929e3e5 43
Rhyme 0:3f3dd929e3e5 44 SPI_IS25LQ032B::SPI_IS25LQ032B(PinName mosi, PinName miso, PinName sclk, PinName cs) :
Rhyme 0:3f3dd929e3e5 45 m_spi(mosi, miso, sclk), m_cs(cs) {
Rhyme 0:3f3dd929e3e5 46 // activate the peripheral
Rhyme 0:3f3dd929e3e5 47 }
Rhyme 0:3f3dd929e3e5 48
Rhyme 0:3f3dd929e3e5 49 SPI_IS25LQ032B::~SPI_IS25LQ032B() { }
Rhyme 0:3f3dd929e3e5 50
Rhyme 0:3f3dd929e3e5 51 void SPI_IS25LQ032B::writeEnable(void)
Rhyme 0:3f3dd929e3e5 52 {
Rhyme 0:3f3dd929e3e5 53 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 54 m_spi.write(CMD_WREN) ;
Rhyme 0:3f3dd929e3e5 55 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 56 }
Rhyme 0:3f3dd929e3e5 57
Rhyme 0:3f3dd929e3e5 58 void SPI_IS25LQ032B::writeDisable(void)
Rhyme 0:3f3dd929e3e5 59 {
Rhyme 0:3f3dd929e3e5 60 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 61 m_spi.write(CMD_WRDI) ;
Rhyme 0:3f3dd929e3e5 62 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 63 }
Rhyme 0:3f3dd929e3e5 64
Rhyme 0:3f3dd929e3e5 65 uint8_t SPI_IS25LQ032B::readStatus(void)
Rhyme 0:3f3dd929e3e5 66 {
Rhyme 0:3f3dd929e3e5 67 uint8_t data ;
Rhyme 0:3f3dd929e3e5 68 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 69 m_spi.write(CMD_RDSR) ;
Rhyme 0:3f3dd929e3e5 70 data = m_spi.write(CMD_RDSR) ; // write data is dummy
Rhyme 0:3f3dd929e3e5 71 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 72 return( data ) ;
Rhyme 0:3f3dd929e3e5 73 }
Rhyme 0:3f3dd929e3e5 74
Rhyme 0:3f3dd929e3e5 75 void SPI_IS25LQ032B::writeStatus(uint8_t newStatus)
Rhyme 0:3f3dd929e3e5 76 {
Rhyme 0:3f3dd929e3e5 77 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 78 m_spi.write(CMD_WRSR) ;
Rhyme 0:3f3dd929e3e5 79 m_spi.write(newStatus) ;
Rhyme 0:3f3dd929e3e5 80 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 81 }
Rhyme 0:3f3dd929e3e5 82
Rhyme 0:3f3dd929e3e5 83 uint8_t SPI_IS25LQ032B::readFunc(void)
Rhyme 0:3f3dd929e3e5 84 {
Rhyme 0:3f3dd929e3e5 85 uint8_t data ;
Rhyme 0:3f3dd929e3e5 86 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 87 m_spi.write(CMD_RDFR) ;
Rhyme 0:3f3dd929e3e5 88 data = m_spi.write(CMD_RDFR) ;
Rhyme 0:3f3dd929e3e5 89 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 90 return(data) ;
Rhyme 0:3f3dd929e3e5 91 }
Rhyme 0:3f3dd929e3e5 92
Rhyme 0:3f3dd929e3e5 93 void SPI_IS25LQ032B::writeFunc(uint8_t newValue)
Rhyme 0:3f3dd929e3e5 94 {
Rhyme 0:3f3dd929e3e5 95 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 96 m_spi.write(CMD_WRFR) ;
Rhyme 0:3f3dd929e3e5 97 m_spi.write(newValue) ;
Rhyme 0:3f3dd929e3e5 98 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 99 }
Rhyme 0:3f3dd929e3e5 100
Rhyme 0:3f3dd929e3e5 101 void SPI_IS25LQ032B::programPage(int addr, uint8_t *data, int numData)
Rhyme 0:3f3dd929e3e5 102 {
Rhyme 0:3f3dd929e3e5 103 int i ;
Rhyme 0:3f3dd929e3e5 104 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 105 m_spi.write(CMD_PP) ; // Program Page
Rhyme 0:3f3dd929e3e5 106 m_spi.write((addr >> 16)&0xFF) ;
Rhyme 0:3f3dd929e3e5 107 m_spi.write((addr >> 8)&0xFF) ;
Rhyme 0:3f3dd929e3e5 108 m_spi.write(addr & 0xFF) ;
Rhyme 0:3f3dd929e3e5 109 for (i = 0 ; i < numData ; i++ ) {
Rhyme 0:3f3dd929e3e5 110 m_spi.write(data[i]) ;
Rhyme 0:3f3dd929e3e5 111 }
Rhyme 0:3f3dd929e3e5 112 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 113 // you need to check RDSR WIP bit to be 0 to wait completion
Rhyme 0:3f3dd929e3e5 114 }
Rhyme 0:3f3dd929e3e5 115
Rhyme 0:3f3dd929e3e5 116 void SPI_IS25LQ032B::chipErase(void)
Rhyme 0:3f3dd929e3e5 117 {
Rhyme 0:3f3dd929e3e5 118 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 119 m_spi.write(CMD_CER) ;
Rhyme 0:3f3dd929e3e5 120 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 121 }
Rhyme 0:3f3dd929e3e5 122
Rhyme 0:3f3dd929e3e5 123 uint8_t SPI_IS25LQ032B::read8(int addr)
Rhyme 0:3f3dd929e3e5 124 {
Rhyme 0:3f3dd929e3e5 125 uint8_t data ;
Rhyme 0:3f3dd929e3e5 126 m_cs = 0 ;
Rhyme 0:3f3dd929e3e5 127 m_spi.write(CMD_RD) ;
Rhyme 0:3f3dd929e3e5 128 m_spi.write((addr >> 16)&0xFF) ;
Rhyme 0:3f3dd929e3e5 129 m_spi.write((addr >> 8)&0xFF) ;
Rhyme 0:3f3dd929e3e5 130 m_spi.write(addr & 0xFF) ;
Rhyme 0:3f3dd929e3e5 131 data = m_spi.write(addr & 0xFF) ; // write data is dummy
Rhyme 0:3f3dd929e3e5 132 m_cs = 1 ;
Rhyme 0:3f3dd929e3e5 133 return( data ) ;
Rhyme 0:3f3dd929e3e5 134 }