PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)
Dependents: YATTT sd_map_test cPong SnowDemo ... more
core_cm0plus.h
00001 /**************************************************************************//** 00002 * @file core_cm0plus.h 00003 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File 00004 * @version V3.20 00005 * @date 25. February 2013 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2013 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 #ifndef __CORE_CM0PLUS_H_GENERIC 00047 #define __CORE_CM0PLUS_H_GENERIC 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup Cortex-M0+ 00067 @{ 00068 */ 00069 00070 /* CMSIS CM0P definitions */ 00071 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00072 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ 00074 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __ICCARM__ ) 00085 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00086 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __GNUC__ ) 00090 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00091 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TASKING__ ) 00095 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00096 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00097 #define __STATIC_INLINE static inline 00098 00099 #endif 00100 00101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all 00102 */ 00103 #define __FPU_USED 0 00104 00105 #if defined ( __CC_ARM ) 00106 #if defined __TARGET_FPU_VFP 00107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00108 #endif 00109 00110 #elif defined ( __ICCARM__ ) 00111 #if defined __ARMVFP__ 00112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00113 #endif 00114 00115 #elif defined ( __GNUC__ ) 00116 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00118 #endif 00119 00120 #elif defined ( __TASKING__ ) 00121 #if defined __FPU_VFP__ 00122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00123 #endif 00124 #endif 00125 00126 #include <stdint.h> /* standard types definitions */ 00127 #include <core_cmInstr.h> /* Core Instruction Access */ 00128 #include <core_cmFunc.h> /* Core Function Access */ 00129 00130 #endif /* __CORE_CM0PLUS_H_GENERIC */ 00131 00132 #ifndef __CMSIS_GENERIC 00133 00134 #ifndef __CORE_CM0PLUS_H_DEPENDANT 00135 #define __CORE_CM0PLUS_H_DEPENDANT 00136 00137 /* check device defines and use defaults */ 00138 #if defined __CHECK_DEVICE_DEFINES 00139 #ifndef __CM0PLUS_REV 00140 #define __CM0PLUS_REV 0x0000 00141 #warning "__CM0PLUS_REV not defined in device header file; using default!" 00142 #endif 00143 00144 #ifndef __MPU_PRESENT 00145 #define __MPU_PRESENT 0 00146 #warning "__MPU_PRESENT not defined in device header file; using default!" 00147 #endif 00148 00149 #ifndef __VTOR_PRESENT 00150 #define __VTOR_PRESENT 0 00151 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00152 #endif 00153 00154 #ifndef __NVIC_PRIO_BITS 00155 #define __NVIC_PRIO_BITS 2 00156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00157 #endif 00158 00159 #ifndef __Vendor_SysTickConfig 00160 #define __Vendor_SysTickConfig 0 00161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00162 #endif 00163 #endif 00164 00165 /* IO definitions (access restrictions to peripheral registers) */ 00166 /** 00167 \defgroup CMSIS_glob_defs CMSIS Global Defines 00168 00169 <strong>IO Type Qualifiers</strong> are used 00170 \li to specify the access to peripheral variables. 00171 \li for automatic generation of peripheral register debug information. 00172 */ 00173 #ifdef __cplusplus 00174 #define __I volatile /*!< Defines 'read only' permissions */ 00175 #else 00176 #define __I volatile const /*!< Defines 'read only' permissions */ 00177 #endif 00178 #define __O volatile /*!< Defines 'write only' permissions */ 00179 #define __IO volatile /*!< Defines 'read / write' permissions */ 00180 00181 /*@} end of group Cortex-M0+ */ 00182 00183 00184 00185 /******************************************************************************* 00186 * Register Abstraction 00187 Core Register contain: 00188 - Core Register 00189 - Core NVIC Register 00190 - Core SCB Register 00191 - Core SysTick Register 00192 - Core MPU Register 00193 ******************************************************************************/ 00194 /** \defgroup CMSIS_core_register Defines and Type Definitions 00195 \brief Type definitions and defines for Cortex-M processor based devices. 00196 */ 00197 00198 /** \ingroup CMSIS_core_register 00199 \defgroup CMSIS_CORE Status and Control Registers 00200 \brief Core Register type definitions. 00201 @{ 00202 */ 00203 00204 /** \brief Union type to access the Application Program Status Register (APSR). 00205 */ 00206 typedef union 00207 { 00208 struct 00209 { 00210 #if (__CORTEX_M != 0x04) 00211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00212 #else 00213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00216 #endif 00217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00222 } b; /*!< Structure used for bit access */ 00223 uint32_t w; /*!< Type used for word access */ 00224 } APSR_Type; 00225 00226 00227 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00228 */ 00229 typedef union 00230 { 00231 struct 00232 { 00233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00235 } b; /*!< Structure used for bit access */ 00236 uint32_t w; /*!< Type used for word access */ 00237 } IPSR_Type; 00238 00239 00240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00241 */ 00242 typedef union 00243 { 00244 struct 00245 { 00246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00247 #if (__CORTEX_M != 0x04) 00248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00249 #else 00250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00253 #endif 00254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00261 } b; /*!< Structure used for bit access */ 00262 uint32_t w; /*!< Type used for word access */ 00263 } xPSR_Type; 00264 00265 00266 /** \brief Union type to access the Control Registers (CONTROL). 00267 */ 00268 typedef union 00269 { 00270 struct 00271 { 00272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00276 } b; /*!< Structure used for bit access */ 00277 uint32_t w; /*!< Type used for word access */ 00278 } CONTROL_Type; 00279 00280 /*@} end of group CMSIS_CORE */ 00281 00282 00283 /** \ingroup CMSIS_core_register 00284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00285 \brief Type definitions for the NVIC Registers 00286 @{ 00287 */ 00288 00289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00290 */ 00291 typedef struct 00292 { 00293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00294 uint32_t RESERVED0[31]; 00295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00296 uint32_t RSERVED1[31]; 00297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00298 uint32_t RESERVED2[31]; 00299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00300 uint32_t RESERVED3[31]; 00301 uint32_t RESERVED4[64]; 00302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00303 } NVIC_Type; 00304 00305 /*@} end of group CMSIS_NVIC */ 00306 00307 00308 /** \ingroup CMSIS_core_register 00309 \defgroup CMSIS_SCB System Control Block (SCB) 00310 \brief Type definitions for the System Control Block Registers 00311 @{ 00312 */ 00313 00314 /** \brief Structure type to access the System Control Block (SCB). 00315 */ 00316 typedef struct 00317 { 00318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00320 #if (__VTOR_PRESENT == 1) 00321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00322 #else 00323 uint32_t RESERVED0; 00324 #endif 00325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00328 uint32_t RESERVED1; 00329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00331 } SCB_Type; 00332 00333 /* SCB CPUID Register Definitions */ 00334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00336 00337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00339 00340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00342 00343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00345 00346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00348 00349 /* SCB Interrupt Control State Register Definitions */ 00350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00352 00353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00355 00356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00358 00359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00361 00362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00364 00365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00367 00368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00370 00371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00373 00374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00376 00377 #if (__VTOR_PRESENT == 1) 00378 /* SCB Interrupt Control State Register Definitions */ 00379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ 00380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00381 #endif 00382 00383 /* SCB Application Interrupt and Reset Control Register Definitions */ 00384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00386 00387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00389 00390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00392 00393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00395 00396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00398 00399 /* SCB System Control Register Definitions */ 00400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00402 00403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00405 00406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00408 00409 /* SCB Configuration Control Register Definitions */ 00410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00412 00413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00415 00416 /* SCB System Handler Control and State Register Definitions */ 00417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00419 00420 /*@} end of group CMSIS_SCB */ 00421 00422 00423 /** \ingroup CMSIS_core_register 00424 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00425 \brief Type definitions for the System Timer Registers. 00426 @{ 00427 */ 00428 00429 /** \brief Structure type to access the System Timer (SysTick). 00430 */ 00431 typedef struct 00432 { 00433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00437 } SysTick_Type; 00438 00439 /* SysTick Control / Status Register Definitions */ 00440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00442 00443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00445 00446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00448 00449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00451 00452 /* SysTick Reload Register Definitions */ 00453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00455 00456 /* SysTick Current Register Definitions */ 00457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00459 00460 /* SysTick Calibration Register Definitions */ 00461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00463 00464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00466 00467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ 00469 00470 /*@} end of group CMSIS_SysTick */ 00471 00472 #if (__MPU_PRESENT == 1) 00473 /** \ingroup CMSIS_core_register 00474 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00475 \brief Type definitions for the Memory Protection Unit (MPU) 00476 @{ 00477 */ 00478 00479 /** \brief Structure type to access the Memory Protection Unit (MPU). 00480 */ 00481 typedef struct 00482 { 00483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00488 } MPU_Type; 00489 00490 /* MPU Type Register */ 00491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 00492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00493 00494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 00495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00496 00497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 00498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 00499 00500 /* MPU Control Register */ 00501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 00502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00503 00504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 00505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00506 00507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 00508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 00509 00510 /* MPU Region Number Register */ 00511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 00512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 00513 00514 /* MPU Region Base Address Register */ 00515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ 00516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00517 00518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 00519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00520 00521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 00522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 00523 00524 /* MPU Region Attribute and Size Register */ 00525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 00526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00527 00528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 00529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00530 00531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 00532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00533 00534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 00535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00536 00537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 00538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00539 00540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 00541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00542 00543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 00544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00545 00546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 00547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00548 00549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 00550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00551 00552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 00553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 00554 00555 /*@} end of group CMSIS_MPU */ 00556 #endif 00557 00558 00559 /** \ingroup CMSIS_core_register 00560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) 00562 are only accessible over DAP and not via processor. Therefore 00563 they are not covered by the Cortex-M0 header file. 00564 @{ 00565 */ 00566 /*@} end of group CMSIS_CoreDebug */ 00567 00568 00569 /** \ingroup CMSIS_core_register 00570 \defgroup CMSIS_core_base Core Definitions 00571 \brief Definitions for base addresses, unions, and structures. 00572 @{ 00573 */ 00574 00575 /* Memory mapping of Cortex-M0+ Hardware */ 00576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00580 00581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00584 00585 #if (__MPU_PRESENT == 1) 00586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00588 #endif 00589 00590 /*@} */ 00591 00592 00593 00594 /******************************************************************************* 00595 * Hardware Abstraction Layer 00596 Core Function Interface contains: 00597 - Core NVIC Functions 00598 - Core SysTick Functions 00599 - Core Register Access Functions 00600 ******************************************************************************/ 00601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00602 */ 00603 00604 00605 00606 /* ########################## NVIC functions #################################### */ 00607 /** \ingroup CMSIS_Core_FunctionInterface 00608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00609 \brief Functions that manage interrupts and exceptions via the NVIC. 00610 @{ 00611 */ 00612 00613 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00614 /* The following MACROS handle generation of the register offset and byte masks */ 00615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 00616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 00617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 00618 00619 00620 /** \brief Enable External Interrupt 00621 00622 The function enables a device-specific interrupt in the NVIC interrupt controller. 00623 00624 \param [in] IRQn External interrupt number. Value cannot be negative. 00625 */ 00626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00627 { 00628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00629 } 00630 00631 00632 /** \brief Disable External Interrupt 00633 00634 The function disables a device-specific interrupt in the NVIC interrupt controller. 00635 00636 \param [in] IRQn External interrupt number. Value cannot be negative. 00637 */ 00638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00639 { 00640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00641 } 00642 00643 00644 /** \brief Get Pending Interrupt 00645 00646 The function reads the pending register in the NVIC and returns the pending bit 00647 for the specified interrupt. 00648 00649 \param [in] IRQn Interrupt number. 00650 00651 \return 0 Interrupt status is not pending. 00652 \return 1 Interrupt status is pending. 00653 */ 00654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00655 { 00656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 00657 } 00658 00659 00660 /** \brief Set Pending Interrupt 00661 00662 The function sets the pending bit of an external interrupt. 00663 00664 \param [in] IRQn Interrupt number. Value cannot be negative. 00665 */ 00666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00667 { 00668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00669 } 00670 00671 00672 /** \brief Clear Pending Interrupt 00673 00674 The function clears the pending bit of an external interrupt. 00675 00676 \param [in] IRQn External interrupt number. Value cannot be negative. 00677 */ 00678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00679 { 00680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 00681 } 00682 00683 00684 /** \brief Set Interrupt Priority 00685 00686 The function sets the priority of an interrupt. 00687 00688 \note The priority cannot be set for every core interrupt. 00689 00690 \param [in] IRQn Interrupt number. 00691 \param [in] priority Priority to set. 00692 */ 00693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00694 { 00695 if(IRQn < 0) { 00696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00698 else { 00699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00701 } 00702 00703 00704 /** \brief Get Interrupt Priority 00705 00706 The function reads the priority of an interrupt. The interrupt 00707 number can be positive to specify an external (device specific) 00708 interrupt, or negative to specify an internal (core) interrupt. 00709 00710 00711 \param [in] IRQn Interrupt number. 00712 \return Interrupt Priority. Value is aligned automatically to the implemented 00713 priority bits of the microcontroller. 00714 */ 00715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00716 { 00717 00718 if(IRQn < 0) { 00719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 00720 else { 00721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 00722 } 00723 00724 00725 /** \brief System Reset 00726 00727 The function initiates a system reset request to reset the MCU. 00728 */ 00729 __STATIC_INLINE void NVIC_SystemReset(void) 00730 { 00731 __DSB(); /* Ensure all outstanding memory accesses included 00732 buffered write are completed before reset */ 00733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 00734 SCB_AIRCR_SYSRESETREQ_Msk); 00735 __DSB(); /* Ensure completion of memory access */ 00736 while(1); /* wait until reset */ 00737 } 00738 00739 /*@} end of CMSIS_Core_NVICFunctions */ 00740 00741 00742 00743 /* ################################## SysTick function ############################################ */ 00744 /** \ingroup CMSIS_Core_FunctionInterface 00745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00746 \brief Functions that configure the System. 00747 @{ 00748 */ 00749 00750 #if (__Vendor_SysTickConfig == 0) 00751 00752 /** \brief System Tick Configuration 00753 00754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00755 Counter is in free running mode to generate periodic interrupts. 00756 00757 \param [in] ticks Number of ticks between two interrupts. 00758 00759 \return 0 Function succeeded. 00760 \return 1 Function failed. 00761 00762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00764 must contain a vendor-specific implementation of this function. 00765 00766 */ 00767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00768 { 00769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 00770 00771 SysTick->LOAD = ticks - 1; /* set reload register */ 00772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 00773 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 00774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00775 SysTick_CTRL_TICKINT_Msk | 00776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00777 return (0); /* Function successful */ 00778 } 00779 00780 #endif 00781 00782 /*@} end of CMSIS_Core_SysTickFunctions */ 00783 00784 00785 00786 00787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */ 00788 00789 #endif /* __CMSIS_GENERIC */ 00790 00791 #ifdef __cplusplus 00792 } 00793 #endif
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