Jonne Valola / PokittoLib Featured

PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)

Dependents:   YATTT sd_map_test cPong SnowDemo ... more

PokittoLib

Library for programming Pokitto hardware

How to Use

  1. Import this library to online compiler (see button "import" on the right hand side
  2. DO NOT import mbed-src anymore, a better version is now included inside PokittoLib
  3. Change My_settings.h according to your project
  4. Start coding!

mbed-pokitto/targets/cmsis/core_cm0plus.h@71:531419862202, 2019-12-25 (annotated)

Committer:
Pokitto
Date:
Wed Dec 25 23:59:52 2019 +0000
Revision:
71:531419862202
Parent:
5:ea7377f3d1af 
Changed Mode2 C++ refresh code (graphical errors)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pokitto 5:ea7377f3d1af 1 /**************************************************************************//**
Pokitto 5:ea7377f3d1af 2 * @file core_cm0plus.h
Pokitto 5:ea7377f3d1af 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Pokitto 5:ea7377f3d1af 4 * @version V3.20
Pokitto 5:ea7377f3d1af 5 * @date 25. February 2013
Pokitto 5:ea7377f3d1af 6 *
Pokitto 5:ea7377f3d1af 7 * @note
Pokitto 5:ea7377f3d1af 8 *
Pokitto 5:ea7377f3d1af 9 ******************************************************************************/
Pokitto 5:ea7377f3d1af 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Pokitto 5:ea7377f3d1af 11
Pokitto 5:ea7377f3d1af 12 All rights reserved.
Pokitto 5:ea7377f3d1af 13 Redistribution and use in source and binary forms, with or without
Pokitto 5:ea7377f3d1af 14 modification, are permitted provided that the following conditions are met:
Pokitto 5:ea7377f3d1af 15 - Redistributions of source code must retain the above copyright
Pokitto 5:ea7377f3d1af 16 notice, this list of conditions and the following disclaimer.
Pokitto 5:ea7377f3d1af 17 - Redistributions in binary form must reproduce the above copyright
Pokitto 5:ea7377f3d1af 18 notice, this list of conditions and the following disclaimer in the
Pokitto 5:ea7377f3d1af 19 documentation and/or other materials provided with the distribution.
Pokitto 5:ea7377f3d1af 20 - Neither the name of ARM nor the names of its contributors may be used
Pokitto 5:ea7377f3d1af 21 to endorse or promote products derived from this software without
Pokitto 5:ea7377f3d1af 22 specific prior written permission.
Pokitto 5:ea7377f3d1af 23 *
Pokitto 5:ea7377f3d1af 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Pokitto 5:ea7377f3d1af 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Pokitto 5:ea7377f3d1af 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Pokitto 5:ea7377f3d1af 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Pokitto 5:ea7377f3d1af 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Pokitto 5:ea7377f3d1af 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Pokitto 5:ea7377f3d1af 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Pokitto 5:ea7377f3d1af 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Pokitto 5:ea7377f3d1af 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Pokitto 5:ea7377f3d1af 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Pokitto 5:ea7377f3d1af 34 POSSIBILITY OF SUCH DAMAGE.
Pokitto 5:ea7377f3d1af 35 ---------------------------------------------------------------------------*/
Pokitto 5:ea7377f3d1af 36
Pokitto 5:ea7377f3d1af 37
Pokitto 5:ea7377f3d1af 38 #if defined ( __ICCARM__ )
Pokitto 5:ea7377f3d1af 39 #pragma system_include /* treat file as system include file for MISRA check */
Pokitto 5:ea7377f3d1af 40 #endif
Pokitto 5:ea7377f3d1af 41
Pokitto 5:ea7377f3d1af 42 #ifdef __cplusplus
Pokitto 5:ea7377f3d1af 43 extern "C" {
Pokitto 5:ea7377f3d1af 44 #endif
Pokitto 5:ea7377f3d1af 45
Pokitto 5:ea7377f3d1af 46 #ifndef __CORE_CM0PLUS_H_GENERIC
Pokitto 5:ea7377f3d1af 47 #define __CORE_CM0PLUS_H_GENERIC
Pokitto 5:ea7377f3d1af 48
Pokitto 5:ea7377f3d1af 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Pokitto 5:ea7377f3d1af 50 CMSIS violates the following MISRA-C:2004 rules:
Pokitto 5:ea7377f3d1af 51
Pokitto 5:ea7377f3d1af 52 \li Required Rule 8.5, object/function definition in header file.<br>
Pokitto 5:ea7377f3d1af 53 Function definitions in header files are used to allow 'inlining'.
Pokitto 5:ea7377f3d1af 54
Pokitto 5:ea7377f3d1af 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Pokitto 5:ea7377f3d1af 56 Unions are used for effective representation of core registers.
Pokitto 5:ea7377f3d1af 57
Pokitto 5:ea7377f3d1af 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Pokitto 5:ea7377f3d1af 59 Function-like macros are used to allow more efficient code.
Pokitto 5:ea7377f3d1af 60 */
Pokitto 5:ea7377f3d1af 61
Pokitto 5:ea7377f3d1af 62
Pokitto 5:ea7377f3d1af 63 /*******************************************************************************
Pokitto 5:ea7377f3d1af 64 * CMSIS definitions
Pokitto 5:ea7377f3d1af 65 ******************************************************************************/
Pokitto 5:ea7377f3d1af 66 /** \ingroup Cortex-M0+
Pokitto 5:ea7377f3d1af 67 @{
Pokitto 5:ea7377f3d1af 68 */
Pokitto 5:ea7377f3d1af 69
Pokitto 5:ea7377f3d1af 70 /* CMSIS CM0P definitions */
Pokitto 5:ea7377f3d1af 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Pokitto 5:ea7377f3d1af 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Pokitto 5:ea7377f3d1af 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Pokitto 5:ea7377f3d1af 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Pokitto 5:ea7377f3d1af 75
Pokitto 5:ea7377f3d1af 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Pokitto 5:ea7377f3d1af 77
Pokitto 5:ea7377f3d1af 78
Pokitto 5:ea7377f3d1af 79 #if defined ( __CC_ARM )
Pokitto 5:ea7377f3d1af 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Pokitto 5:ea7377f3d1af 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Pokitto 5:ea7377f3d1af 82 #define __STATIC_INLINE static __inline
Pokitto 5:ea7377f3d1af 83
Pokitto 5:ea7377f3d1af 84 #elif defined ( __ICCARM__ )
Pokitto 5:ea7377f3d1af 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Pokitto 5:ea7377f3d1af 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Pokitto 5:ea7377f3d1af 87 #define __STATIC_INLINE static inline
Pokitto 5:ea7377f3d1af 88
Pokitto 5:ea7377f3d1af 89 #elif defined ( __GNUC__ )
Pokitto 5:ea7377f3d1af 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Pokitto 5:ea7377f3d1af 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Pokitto 5:ea7377f3d1af 92 #define __STATIC_INLINE static inline
Pokitto 5:ea7377f3d1af 93
Pokitto 5:ea7377f3d1af 94 #elif defined ( __TASKING__ )
Pokitto 5:ea7377f3d1af 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Pokitto 5:ea7377f3d1af 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Pokitto 5:ea7377f3d1af 97 #define __STATIC_INLINE static inline
Pokitto 5:ea7377f3d1af 98
Pokitto 5:ea7377f3d1af 99 #endif
Pokitto 5:ea7377f3d1af 100
Pokitto 5:ea7377f3d1af 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Pokitto 5:ea7377f3d1af 102 */
Pokitto 5:ea7377f3d1af 103 #define __FPU_USED 0
Pokitto 5:ea7377f3d1af 104
Pokitto 5:ea7377f3d1af 105 #if defined ( __CC_ARM )
Pokitto 5:ea7377f3d1af 106 #if defined __TARGET_FPU_VFP
Pokitto 5:ea7377f3d1af 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto 5:ea7377f3d1af 108 #endif
Pokitto 5:ea7377f3d1af 109
Pokitto 5:ea7377f3d1af 110 #elif defined ( __ICCARM__ )
Pokitto 5:ea7377f3d1af 111 #if defined __ARMVFP__
Pokitto 5:ea7377f3d1af 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto 5:ea7377f3d1af 113 #endif
Pokitto 5:ea7377f3d1af 114
Pokitto 5:ea7377f3d1af 115 #elif defined ( __GNUC__ )
Pokitto 5:ea7377f3d1af 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Pokitto 5:ea7377f3d1af 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto 5:ea7377f3d1af 118 #endif
Pokitto 5:ea7377f3d1af 119
Pokitto 5:ea7377f3d1af 120 #elif defined ( __TASKING__ )
Pokitto 5:ea7377f3d1af 121 #if defined __FPU_VFP__
Pokitto 5:ea7377f3d1af 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Pokitto 5:ea7377f3d1af 123 #endif
Pokitto 5:ea7377f3d1af 124 #endif
Pokitto 5:ea7377f3d1af 125
Pokitto 5:ea7377f3d1af 126 #include <stdint.h> /* standard types definitions */
Pokitto 5:ea7377f3d1af 127 #include <core_cmInstr.h> /* Core Instruction Access */
Pokitto 5:ea7377f3d1af 128 #include <core_cmFunc.h> /* Core Function Access */
Pokitto 5:ea7377f3d1af 129
Pokitto 5:ea7377f3d1af 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
Pokitto 5:ea7377f3d1af 131
Pokitto 5:ea7377f3d1af 132 #ifndef __CMSIS_GENERIC
Pokitto 5:ea7377f3d1af 133
Pokitto 5:ea7377f3d1af 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Pokitto 5:ea7377f3d1af 135 #define __CORE_CM0PLUS_H_DEPENDANT
Pokitto 5:ea7377f3d1af 136
Pokitto 5:ea7377f3d1af 137 /* check device defines and use defaults */
Pokitto 5:ea7377f3d1af 138 #if defined __CHECK_DEVICE_DEFINES
Pokitto 5:ea7377f3d1af 139 #ifndef __CM0PLUS_REV
Pokitto 5:ea7377f3d1af 140 #define __CM0PLUS_REV 0x0000
Pokitto 5:ea7377f3d1af 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Pokitto 5:ea7377f3d1af 142 #endif
Pokitto 5:ea7377f3d1af 143
Pokitto 5:ea7377f3d1af 144 #ifndef __MPU_PRESENT
Pokitto 5:ea7377f3d1af 145 #define __MPU_PRESENT 0
Pokitto 5:ea7377f3d1af 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
Pokitto 5:ea7377f3d1af 147 #endif
Pokitto 5:ea7377f3d1af 148
Pokitto 5:ea7377f3d1af 149 #ifndef __VTOR_PRESENT
Pokitto 5:ea7377f3d1af 150 #define __VTOR_PRESENT 0
Pokitto 5:ea7377f3d1af 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Pokitto 5:ea7377f3d1af 152 #endif
Pokitto 5:ea7377f3d1af 153
Pokitto 5:ea7377f3d1af 154 #ifndef __NVIC_PRIO_BITS
Pokitto 5:ea7377f3d1af 155 #define __NVIC_PRIO_BITS 2
Pokitto 5:ea7377f3d1af 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Pokitto 5:ea7377f3d1af 157 #endif
Pokitto 5:ea7377f3d1af 158
Pokitto 5:ea7377f3d1af 159 #ifndef __Vendor_SysTickConfig
Pokitto 5:ea7377f3d1af 160 #define __Vendor_SysTickConfig 0
Pokitto 5:ea7377f3d1af 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Pokitto 5:ea7377f3d1af 162 #endif
Pokitto 5:ea7377f3d1af 163 #endif
Pokitto 5:ea7377f3d1af 164
Pokitto 5:ea7377f3d1af 165 /* IO definitions (access restrictions to peripheral registers) */
Pokitto 5:ea7377f3d1af 166 /**
Pokitto 5:ea7377f3d1af 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
Pokitto 5:ea7377f3d1af 168
Pokitto 5:ea7377f3d1af 169 <strong>IO Type Qualifiers</strong> are used
Pokitto 5:ea7377f3d1af 170 \li to specify the access to peripheral variables.
Pokitto 5:ea7377f3d1af 171 \li for automatic generation of peripheral register debug information.
Pokitto 5:ea7377f3d1af 172 */
Pokitto 5:ea7377f3d1af 173 #ifdef __cplusplus
Pokitto 5:ea7377f3d1af 174 #define __I volatile /*!< Defines 'read only' permissions */
Pokitto 5:ea7377f3d1af 175 #else
Pokitto 5:ea7377f3d1af 176 #define __I volatile const /*!< Defines 'read only' permissions */
Pokitto 5:ea7377f3d1af 177 #endif
Pokitto 5:ea7377f3d1af 178 #define __O volatile /*!< Defines 'write only' permissions */
Pokitto 5:ea7377f3d1af 179 #define __IO volatile /*!< Defines 'read / write' permissions */
Pokitto 5:ea7377f3d1af 180
Pokitto 5:ea7377f3d1af 181 /*@} end of group Cortex-M0+ */
Pokitto 5:ea7377f3d1af 182
Pokitto 5:ea7377f3d1af 183
Pokitto 5:ea7377f3d1af 184
Pokitto 5:ea7377f3d1af 185 /*******************************************************************************
Pokitto 5:ea7377f3d1af 186 * Register Abstraction
Pokitto 5:ea7377f3d1af 187 Core Register contain:
Pokitto 5:ea7377f3d1af 188 - Core Register
Pokitto 5:ea7377f3d1af 189 - Core NVIC Register
Pokitto 5:ea7377f3d1af 190 - Core SCB Register
Pokitto 5:ea7377f3d1af 191 - Core SysTick Register
Pokitto 5:ea7377f3d1af 192 - Core MPU Register
Pokitto 5:ea7377f3d1af 193 ******************************************************************************/
Pokitto 5:ea7377f3d1af 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
Pokitto 5:ea7377f3d1af 195 \brief Type definitions and defines for Cortex-M processor based devices.
Pokitto 5:ea7377f3d1af 196 */
Pokitto 5:ea7377f3d1af 197
Pokitto 5:ea7377f3d1af 198 /** \ingroup CMSIS_core_register
Pokitto 5:ea7377f3d1af 199 \defgroup CMSIS_CORE Status and Control Registers
Pokitto 5:ea7377f3d1af 200 \brief Core Register type definitions.
Pokitto 5:ea7377f3d1af 201 @{
Pokitto 5:ea7377f3d1af 202 */
Pokitto 5:ea7377f3d1af 203
Pokitto 5:ea7377f3d1af 204 /** \brief Union type to access the Application Program Status Register (APSR).
Pokitto 5:ea7377f3d1af 205 */
Pokitto 5:ea7377f3d1af 206 typedef union
Pokitto 5:ea7377f3d1af 207 {
Pokitto 5:ea7377f3d1af 208 struct
Pokitto 5:ea7377f3d1af 209 {
Pokitto 5:ea7377f3d1af 210 #if (__CORTEX_M != 0x04)
Pokitto 5:ea7377f3d1af 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Pokitto 5:ea7377f3d1af 212 #else
Pokitto 5:ea7377f3d1af 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Pokitto 5:ea7377f3d1af 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Pokitto 5:ea7377f3d1af 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Pokitto 5:ea7377f3d1af 216 #endif
Pokitto 5:ea7377f3d1af 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Pokitto 5:ea7377f3d1af 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Pokitto 5:ea7377f3d1af 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Pokitto 5:ea7377f3d1af 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Pokitto 5:ea7377f3d1af 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Pokitto 5:ea7377f3d1af 222 } b; /*!< Structure used for bit access */
Pokitto 5:ea7377f3d1af 223 uint32_t w; /*!< Type used for word access */
Pokitto 5:ea7377f3d1af 224 } APSR_Type;
Pokitto 5:ea7377f3d1af 225
Pokitto 5:ea7377f3d1af 226
Pokitto 5:ea7377f3d1af 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Pokitto 5:ea7377f3d1af 228 */
Pokitto 5:ea7377f3d1af 229 typedef union
Pokitto 5:ea7377f3d1af 230 {
Pokitto 5:ea7377f3d1af 231 struct
Pokitto 5:ea7377f3d1af 232 {
Pokitto 5:ea7377f3d1af 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Pokitto 5:ea7377f3d1af 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Pokitto 5:ea7377f3d1af 235 } b; /*!< Structure used for bit access */
Pokitto 5:ea7377f3d1af 236 uint32_t w; /*!< Type used for word access */
Pokitto 5:ea7377f3d1af 237 } IPSR_Type;
Pokitto 5:ea7377f3d1af 238
Pokitto 5:ea7377f3d1af 239
Pokitto 5:ea7377f3d1af 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Pokitto 5:ea7377f3d1af 241 */
Pokitto 5:ea7377f3d1af 242 typedef union
Pokitto 5:ea7377f3d1af 243 {
Pokitto 5:ea7377f3d1af 244 struct
Pokitto 5:ea7377f3d1af 245 {
Pokitto 5:ea7377f3d1af 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Pokitto 5:ea7377f3d1af 247 #if (__CORTEX_M != 0x04)
Pokitto 5:ea7377f3d1af 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Pokitto 5:ea7377f3d1af 249 #else
Pokitto 5:ea7377f3d1af 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Pokitto 5:ea7377f3d1af 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Pokitto 5:ea7377f3d1af 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Pokitto 5:ea7377f3d1af 253 #endif
Pokitto 5:ea7377f3d1af 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Pokitto 5:ea7377f3d1af 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Pokitto 5:ea7377f3d1af 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Pokitto 5:ea7377f3d1af 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Pokitto 5:ea7377f3d1af 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Pokitto 5:ea7377f3d1af 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Pokitto 5:ea7377f3d1af 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Pokitto 5:ea7377f3d1af 261 } b; /*!< Structure used for bit access */
Pokitto 5:ea7377f3d1af 262 uint32_t w; /*!< Type used for word access */
Pokitto 5:ea7377f3d1af 263 } xPSR_Type;
Pokitto 5:ea7377f3d1af 264
Pokitto 5:ea7377f3d1af 265
Pokitto 5:ea7377f3d1af 266 /** \brief Union type to access the Control Registers (CONTROL).
Pokitto 5:ea7377f3d1af 267 */
Pokitto 5:ea7377f3d1af 268 typedef union
Pokitto 5:ea7377f3d1af 269 {
Pokitto 5:ea7377f3d1af 270 struct
Pokitto 5:ea7377f3d1af 271 {
Pokitto 5:ea7377f3d1af 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Pokitto 5:ea7377f3d1af 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Pokitto 5:ea7377f3d1af 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Pokitto 5:ea7377f3d1af 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Pokitto 5:ea7377f3d1af 276 } b; /*!< Structure used for bit access */
Pokitto 5:ea7377f3d1af 277 uint32_t w; /*!< Type used for word access */
Pokitto 5:ea7377f3d1af 278 } CONTROL_Type;
Pokitto 5:ea7377f3d1af 279
Pokitto 5:ea7377f3d1af 280 /*@} end of group CMSIS_CORE */
Pokitto 5:ea7377f3d1af 281
Pokitto 5:ea7377f3d1af 282
Pokitto 5:ea7377f3d1af 283 /** \ingroup CMSIS_core_register
Pokitto 5:ea7377f3d1af 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Pokitto 5:ea7377f3d1af 285 \brief Type definitions for the NVIC Registers
Pokitto 5:ea7377f3d1af 286 @{
Pokitto 5:ea7377f3d1af 287 */
Pokitto 5:ea7377f3d1af 288
Pokitto 5:ea7377f3d1af 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Pokitto 5:ea7377f3d1af 290 */
Pokitto 5:ea7377f3d1af 291 typedef struct
Pokitto 5:ea7377f3d1af 292 {
Pokitto 5:ea7377f3d1af 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Pokitto 5:ea7377f3d1af 294 uint32_t RESERVED0[31];
Pokitto 5:ea7377f3d1af 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Pokitto 5:ea7377f3d1af 296 uint32_t RSERVED1[31];
Pokitto 5:ea7377f3d1af 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Pokitto 5:ea7377f3d1af 298 uint32_t RESERVED2[31];
Pokitto 5:ea7377f3d1af 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Pokitto 5:ea7377f3d1af 300 uint32_t RESERVED3[31];
Pokitto 5:ea7377f3d1af 301 uint32_t RESERVED4[64];
Pokitto 5:ea7377f3d1af 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Pokitto 5:ea7377f3d1af 303 } NVIC_Type;
Pokitto 5:ea7377f3d1af 304
Pokitto 5:ea7377f3d1af 305 /*@} end of group CMSIS_NVIC */
Pokitto 5:ea7377f3d1af 306
Pokitto 5:ea7377f3d1af 307
Pokitto 5:ea7377f3d1af 308 /** \ingroup CMSIS_core_register
Pokitto 5:ea7377f3d1af 309 \defgroup CMSIS_SCB System Control Block (SCB)
Pokitto 5:ea7377f3d1af 310 \brief Type definitions for the System Control Block Registers
Pokitto 5:ea7377f3d1af 311 @{
Pokitto 5:ea7377f3d1af 312 */
Pokitto 5:ea7377f3d1af 313
Pokitto 5:ea7377f3d1af 314 /** \brief Structure type to access the System Control Block (SCB).
Pokitto 5:ea7377f3d1af 315 */
Pokitto 5:ea7377f3d1af 316 typedef struct
Pokitto 5:ea7377f3d1af 317 {
Pokitto 5:ea7377f3d1af 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Pokitto 5:ea7377f3d1af 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Pokitto 5:ea7377f3d1af 320 #if (__VTOR_PRESENT == 1)
Pokitto 5:ea7377f3d1af 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Pokitto 5:ea7377f3d1af 322 #else
Pokitto 5:ea7377f3d1af 323 uint32_t RESERVED0;
Pokitto 5:ea7377f3d1af 324 #endif
Pokitto 5:ea7377f3d1af 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Pokitto 5:ea7377f3d1af 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Pokitto 5:ea7377f3d1af 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Pokitto 5:ea7377f3d1af 328 uint32_t RESERVED1;
Pokitto 5:ea7377f3d1af 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Pokitto 5:ea7377f3d1af 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Pokitto 5:ea7377f3d1af 331 } SCB_Type;
Pokitto 5:ea7377f3d1af 332
Pokitto 5:ea7377f3d1af 333 /* SCB CPUID Register Definitions */
Pokitto 5:ea7377f3d1af 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Pokitto 5:ea7377f3d1af 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Pokitto 5:ea7377f3d1af 336
Pokitto 5:ea7377f3d1af 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Pokitto 5:ea7377f3d1af 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Pokitto 5:ea7377f3d1af 339
Pokitto 5:ea7377f3d1af 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Pokitto 5:ea7377f3d1af 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Pokitto 5:ea7377f3d1af 342
Pokitto 5:ea7377f3d1af 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Pokitto 5:ea7377f3d1af 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Pokitto 5:ea7377f3d1af 345
Pokitto 5:ea7377f3d1af 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Pokitto 5:ea7377f3d1af 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Pokitto 5:ea7377f3d1af 348
Pokitto 5:ea7377f3d1af 349 /* SCB Interrupt Control State Register Definitions */
Pokitto 5:ea7377f3d1af 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Pokitto 5:ea7377f3d1af 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Pokitto 5:ea7377f3d1af 352
Pokitto 5:ea7377f3d1af 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Pokitto 5:ea7377f3d1af 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Pokitto 5:ea7377f3d1af 355
Pokitto 5:ea7377f3d1af 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Pokitto 5:ea7377f3d1af 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Pokitto 5:ea7377f3d1af 358
Pokitto 5:ea7377f3d1af 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Pokitto 5:ea7377f3d1af 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Pokitto 5:ea7377f3d1af 361
Pokitto 5:ea7377f3d1af 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Pokitto 5:ea7377f3d1af 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Pokitto 5:ea7377f3d1af 364
Pokitto 5:ea7377f3d1af 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Pokitto 5:ea7377f3d1af 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Pokitto 5:ea7377f3d1af 367
Pokitto 5:ea7377f3d1af 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Pokitto 5:ea7377f3d1af 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Pokitto 5:ea7377f3d1af 370
Pokitto 5:ea7377f3d1af 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Pokitto 5:ea7377f3d1af 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Pokitto 5:ea7377f3d1af 373
Pokitto 5:ea7377f3d1af 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Pokitto 5:ea7377f3d1af 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Pokitto 5:ea7377f3d1af 376
Pokitto 5:ea7377f3d1af 377 #if (__VTOR_PRESENT == 1)
Pokitto 5:ea7377f3d1af 378 /* SCB Interrupt Control State Register Definitions */
Pokitto 5:ea7377f3d1af 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Pokitto 5:ea7377f3d1af 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Pokitto 5:ea7377f3d1af 381 #endif
Pokitto 5:ea7377f3d1af 382
Pokitto 5:ea7377f3d1af 383 /* SCB Application Interrupt and Reset Control Register Definitions */
Pokitto 5:ea7377f3d1af 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Pokitto 5:ea7377f3d1af 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Pokitto 5:ea7377f3d1af 386
Pokitto 5:ea7377f3d1af 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Pokitto 5:ea7377f3d1af 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Pokitto 5:ea7377f3d1af 389
Pokitto 5:ea7377f3d1af 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Pokitto 5:ea7377f3d1af 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Pokitto 5:ea7377f3d1af 392
Pokitto 5:ea7377f3d1af 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Pokitto 5:ea7377f3d1af 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Pokitto 5:ea7377f3d1af 395
Pokitto 5:ea7377f3d1af 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Pokitto 5:ea7377f3d1af 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Pokitto 5:ea7377f3d1af 398
Pokitto 5:ea7377f3d1af 399 /* SCB System Control Register Definitions */
Pokitto 5:ea7377f3d1af 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Pokitto 5:ea7377f3d1af 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Pokitto 5:ea7377f3d1af 402
Pokitto 5:ea7377f3d1af 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Pokitto 5:ea7377f3d1af 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Pokitto 5:ea7377f3d1af 405
Pokitto 5:ea7377f3d1af 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Pokitto 5:ea7377f3d1af 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Pokitto 5:ea7377f3d1af 408
Pokitto 5:ea7377f3d1af 409 /* SCB Configuration Control Register Definitions */
Pokitto 5:ea7377f3d1af 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Pokitto 5:ea7377f3d1af 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Pokitto 5:ea7377f3d1af 412
Pokitto 5:ea7377f3d1af 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Pokitto 5:ea7377f3d1af 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Pokitto 5:ea7377f3d1af 415
Pokitto 5:ea7377f3d1af 416 /* SCB System Handler Control and State Register Definitions */
Pokitto 5:ea7377f3d1af 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Pokitto 5:ea7377f3d1af 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Pokitto 5:ea7377f3d1af 419
Pokitto 5:ea7377f3d1af 420 /*@} end of group CMSIS_SCB */
Pokitto 5:ea7377f3d1af 421
Pokitto 5:ea7377f3d1af 422
Pokitto 5:ea7377f3d1af 423 /** \ingroup CMSIS_core_register
Pokitto 5:ea7377f3d1af 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Pokitto 5:ea7377f3d1af 425 \brief Type definitions for the System Timer Registers.
Pokitto 5:ea7377f3d1af 426 @{
Pokitto 5:ea7377f3d1af 427 */
Pokitto 5:ea7377f3d1af 428
Pokitto 5:ea7377f3d1af 429 /** \brief Structure type to access the System Timer (SysTick).
Pokitto 5:ea7377f3d1af 430 */
Pokitto 5:ea7377f3d1af 431 typedef struct
Pokitto 5:ea7377f3d1af 432 {
Pokitto 5:ea7377f3d1af 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Pokitto 5:ea7377f3d1af 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Pokitto 5:ea7377f3d1af 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Pokitto 5:ea7377f3d1af 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Pokitto 5:ea7377f3d1af 437 } SysTick_Type;
Pokitto 5:ea7377f3d1af 438
Pokitto 5:ea7377f3d1af 439 /* SysTick Control / Status Register Definitions */
Pokitto 5:ea7377f3d1af 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Pokitto 5:ea7377f3d1af 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Pokitto 5:ea7377f3d1af 442
Pokitto 5:ea7377f3d1af 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Pokitto 5:ea7377f3d1af 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Pokitto 5:ea7377f3d1af 445
Pokitto 5:ea7377f3d1af 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Pokitto 5:ea7377f3d1af 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Pokitto 5:ea7377f3d1af 448
Pokitto 5:ea7377f3d1af 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Pokitto 5:ea7377f3d1af 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Pokitto 5:ea7377f3d1af 451
Pokitto 5:ea7377f3d1af 452 /* SysTick Reload Register Definitions */
Pokitto 5:ea7377f3d1af 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Pokitto 5:ea7377f3d1af 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Pokitto 5:ea7377f3d1af 455
Pokitto 5:ea7377f3d1af 456 /* SysTick Current Register Definitions */
Pokitto 5:ea7377f3d1af 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Pokitto 5:ea7377f3d1af 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Pokitto 5:ea7377f3d1af 459
Pokitto 5:ea7377f3d1af 460 /* SysTick Calibration Register Definitions */
Pokitto 5:ea7377f3d1af 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Pokitto 5:ea7377f3d1af 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Pokitto 5:ea7377f3d1af 463
Pokitto 5:ea7377f3d1af 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Pokitto 5:ea7377f3d1af 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Pokitto 5:ea7377f3d1af 466
Pokitto 5:ea7377f3d1af 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Pokitto 5:ea7377f3d1af 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Pokitto 5:ea7377f3d1af 469
Pokitto 5:ea7377f3d1af 470 /*@} end of group CMSIS_SysTick */
Pokitto 5:ea7377f3d1af 471
Pokitto 5:ea7377f3d1af 472 #if (__MPU_PRESENT == 1)
Pokitto 5:ea7377f3d1af 473 /** \ingroup CMSIS_core_register
Pokitto 5:ea7377f3d1af 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Pokitto 5:ea7377f3d1af 475 \brief Type definitions for the Memory Protection Unit (MPU)
Pokitto 5:ea7377f3d1af 476 @{
Pokitto 5:ea7377f3d1af 477 */
Pokitto 5:ea7377f3d1af 478
Pokitto 5:ea7377f3d1af 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
Pokitto 5:ea7377f3d1af 480 */
Pokitto 5:ea7377f3d1af 481 typedef struct
Pokitto 5:ea7377f3d1af 482 {
Pokitto 5:ea7377f3d1af 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Pokitto 5:ea7377f3d1af 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Pokitto 5:ea7377f3d1af 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Pokitto 5:ea7377f3d1af 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Pokitto 5:ea7377f3d1af 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Pokitto 5:ea7377f3d1af 488 } MPU_Type;
Pokitto 5:ea7377f3d1af 489
Pokitto 5:ea7377f3d1af 490 /* MPU Type Register */
Pokitto 5:ea7377f3d1af 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Pokitto 5:ea7377f3d1af 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Pokitto 5:ea7377f3d1af 493
Pokitto 5:ea7377f3d1af 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Pokitto 5:ea7377f3d1af 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Pokitto 5:ea7377f3d1af 496
Pokitto 5:ea7377f3d1af 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Pokitto 5:ea7377f3d1af 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Pokitto 5:ea7377f3d1af 499
Pokitto 5:ea7377f3d1af 500 /* MPU Control Register */
Pokitto 5:ea7377f3d1af 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Pokitto 5:ea7377f3d1af 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Pokitto 5:ea7377f3d1af 503
Pokitto 5:ea7377f3d1af 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Pokitto 5:ea7377f3d1af 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Pokitto 5:ea7377f3d1af 506
Pokitto 5:ea7377f3d1af 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Pokitto 5:ea7377f3d1af 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Pokitto 5:ea7377f3d1af 509
Pokitto 5:ea7377f3d1af 510 /* MPU Region Number Register */
Pokitto 5:ea7377f3d1af 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Pokitto 5:ea7377f3d1af 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Pokitto 5:ea7377f3d1af 513
Pokitto 5:ea7377f3d1af 514 /* MPU Region Base Address Register */
Pokitto 5:ea7377f3d1af 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Pokitto 5:ea7377f3d1af 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Pokitto 5:ea7377f3d1af 517
Pokitto 5:ea7377f3d1af 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Pokitto 5:ea7377f3d1af 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Pokitto 5:ea7377f3d1af 520
Pokitto 5:ea7377f3d1af 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Pokitto 5:ea7377f3d1af 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Pokitto 5:ea7377f3d1af 523
Pokitto 5:ea7377f3d1af 524 /* MPU Region Attribute and Size Register */
Pokitto 5:ea7377f3d1af 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Pokitto 5:ea7377f3d1af 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Pokitto 5:ea7377f3d1af 527
Pokitto 5:ea7377f3d1af 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Pokitto 5:ea7377f3d1af 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Pokitto 5:ea7377f3d1af 530
Pokitto 5:ea7377f3d1af 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Pokitto 5:ea7377f3d1af 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Pokitto 5:ea7377f3d1af 533
Pokitto 5:ea7377f3d1af 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Pokitto 5:ea7377f3d1af 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Pokitto 5:ea7377f3d1af 536
Pokitto 5:ea7377f3d1af 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Pokitto 5:ea7377f3d1af 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Pokitto 5:ea7377f3d1af 539
Pokitto 5:ea7377f3d1af 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Pokitto 5:ea7377f3d1af 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Pokitto 5:ea7377f3d1af 542
Pokitto 5:ea7377f3d1af 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Pokitto 5:ea7377f3d1af 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Pokitto 5:ea7377f3d1af 545
Pokitto 5:ea7377f3d1af 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Pokitto 5:ea7377f3d1af 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Pokitto 5:ea7377f3d1af 548
Pokitto 5:ea7377f3d1af 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Pokitto 5:ea7377f3d1af 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Pokitto 5:ea7377f3d1af 551
Pokitto 5:ea7377f3d1af 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Pokitto 5:ea7377f3d1af 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Pokitto 5:ea7377f3d1af 554
Pokitto 5:ea7377f3d1af 555 /*@} end of group CMSIS_MPU */
Pokitto 5:ea7377f3d1af 556 #endif
Pokitto 5:ea7377f3d1af 557
Pokitto 5:ea7377f3d1af 558
Pokitto 5:ea7377f3d1af 559 /** \ingroup CMSIS_core_register
Pokitto 5:ea7377f3d1af 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Pokitto 5:ea7377f3d1af 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Pokitto 5:ea7377f3d1af 562 are only accessible over DAP and not via processor. Therefore
Pokitto 5:ea7377f3d1af 563 they are not covered by the Cortex-M0 header file.
Pokitto 5:ea7377f3d1af 564 @{
Pokitto 5:ea7377f3d1af 565 */
Pokitto 5:ea7377f3d1af 566 /*@} end of group CMSIS_CoreDebug */
Pokitto 5:ea7377f3d1af 567
Pokitto 5:ea7377f3d1af 568
Pokitto 5:ea7377f3d1af 569 /** \ingroup CMSIS_core_register
Pokitto 5:ea7377f3d1af 570 \defgroup CMSIS_core_base Core Definitions
Pokitto 5:ea7377f3d1af 571 \brief Definitions for base addresses, unions, and structures.
Pokitto 5:ea7377f3d1af 572 @{
Pokitto 5:ea7377f3d1af 573 */
Pokitto 5:ea7377f3d1af 574
Pokitto 5:ea7377f3d1af 575 /* Memory mapping of Cortex-M0+ Hardware */
Pokitto 5:ea7377f3d1af 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Pokitto 5:ea7377f3d1af 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Pokitto 5:ea7377f3d1af 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Pokitto 5:ea7377f3d1af 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Pokitto 5:ea7377f3d1af 580
Pokitto 5:ea7377f3d1af 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Pokitto 5:ea7377f3d1af 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Pokitto 5:ea7377f3d1af 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Pokitto 5:ea7377f3d1af 584
Pokitto 5:ea7377f3d1af 585 #if (__MPU_PRESENT == 1)
Pokitto 5:ea7377f3d1af 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Pokitto 5:ea7377f3d1af 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Pokitto 5:ea7377f3d1af 588 #endif
Pokitto 5:ea7377f3d1af 589
Pokitto 5:ea7377f3d1af 590 /*@} */
Pokitto 5:ea7377f3d1af 591
Pokitto 5:ea7377f3d1af 592
Pokitto 5:ea7377f3d1af 593
Pokitto 5:ea7377f3d1af 594 /*******************************************************************************
Pokitto 5:ea7377f3d1af 595 * Hardware Abstraction Layer
Pokitto 5:ea7377f3d1af 596 Core Function Interface contains:
Pokitto 5:ea7377f3d1af 597 - Core NVIC Functions
Pokitto 5:ea7377f3d1af 598 - Core SysTick Functions
Pokitto 5:ea7377f3d1af 599 - Core Register Access Functions
Pokitto 5:ea7377f3d1af 600 ******************************************************************************/
Pokitto 5:ea7377f3d1af 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Pokitto 5:ea7377f3d1af 602 */
Pokitto 5:ea7377f3d1af 603
Pokitto 5:ea7377f3d1af 604
Pokitto 5:ea7377f3d1af 605
Pokitto 5:ea7377f3d1af 606 /* ########################## NVIC functions #################################### */
Pokitto 5:ea7377f3d1af 607 /** \ingroup CMSIS_Core_FunctionInterface
Pokitto 5:ea7377f3d1af 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Pokitto 5:ea7377f3d1af 609 \brief Functions that manage interrupts and exceptions via the NVIC.
Pokitto 5:ea7377f3d1af 610 @{
Pokitto 5:ea7377f3d1af 611 */
Pokitto 5:ea7377f3d1af 612
Pokitto 5:ea7377f3d1af 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Pokitto 5:ea7377f3d1af 614 /* The following MACROS handle generation of the register offset and byte masks */
Pokitto 5:ea7377f3d1af 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Pokitto 5:ea7377f3d1af 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Pokitto 5:ea7377f3d1af 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Pokitto 5:ea7377f3d1af 618
Pokitto 5:ea7377f3d1af 619
Pokitto 5:ea7377f3d1af 620 /** \brief Enable External Interrupt
Pokitto 5:ea7377f3d1af 621
Pokitto 5:ea7377f3d1af 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
Pokitto 5:ea7377f3d1af 623
Pokitto 5:ea7377f3d1af 624 \param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto 5:ea7377f3d1af 625 */
Pokitto 5:ea7377f3d1af 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Pokitto 5:ea7377f3d1af 627 {
Pokitto 5:ea7377f3d1af 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Pokitto 5:ea7377f3d1af 629 }
Pokitto 5:ea7377f3d1af 630
Pokitto 5:ea7377f3d1af 631
Pokitto 5:ea7377f3d1af 632 /** \brief Disable External Interrupt
Pokitto 5:ea7377f3d1af 633
Pokitto 5:ea7377f3d1af 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
Pokitto 5:ea7377f3d1af 635
Pokitto 5:ea7377f3d1af 636 \param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto 5:ea7377f3d1af 637 */
Pokitto 5:ea7377f3d1af 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Pokitto 5:ea7377f3d1af 639 {
Pokitto 5:ea7377f3d1af 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Pokitto 5:ea7377f3d1af 641 }
Pokitto 5:ea7377f3d1af 642
Pokitto 5:ea7377f3d1af 643
Pokitto 5:ea7377f3d1af 644 /** \brief Get Pending Interrupt
Pokitto 5:ea7377f3d1af 645
Pokitto 5:ea7377f3d1af 646 The function reads the pending register in the NVIC and returns the pending bit
Pokitto 5:ea7377f3d1af 647 for the specified interrupt.
Pokitto 5:ea7377f3d1af 648
Pokitto 5:ea7377f3d1af 649 \param [in] IRQn Interrupt number.
Pokitto 5:ea7377f3d1af 650
Pokitto 5:ea7377f3d1af 651 \return 0 Interrupt status is not pending.
Pokitto 5:ea7377f3d1af 652 \return 1 Interrupt status is pending.
Pokitto 5:ea7377f3d1af 653 */
Pokitto 5:ea7377f3d1af 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Pokitto 5:ea7377f3d1af 655 {
Pokitto 5:ea7377f3d1af 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Pokitto 5:ea7377f3d1af 657 }
Pokitto 5:ea7377f3d1af 658
Pokitto 5:ea7377f3d1af 659
Pokitto 5:ea7377f3d1af 660 /** \brief Set Pending Interrupt
Pokitto 5:ea7377f3d1af 661
Pokitto 5:ea7377f3d1af 662 The function sets the pending bit of an external interrupt.
Pokitto 5:ea7377f3d1af 663
Pokitto 5:ea7377f3d1af 664 \param [in] IRQn Interrupt number. Value cannot be negative.
Pokitto 5:ea7377f3d1af 665 */
Pokitto 5:ea7377f3d1af 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Pokitto 5:ea7377f3d1af 667 {
Pokitto 5:ea7377f3d1af 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Pokitto 5:ea7377f3d1af 669 }
Pokitto 5:ea7377f3d1af 670
Pokitto 5:ea7377f3d1af 671
Pokitto 5:ea7377f3d1af 672 /** \brief Clear Pending Interrupt
Pokitto 5:ea7377f3d1af 673
Pokitto 5:ea7377f3d1af 674 The function clears the pending bit of an external interrupt.
Pokitto 5:ea7377f3d1af 675
Pokitto 5:ea7377f3d1af 676 \param [in] IRQn External interrupt number. Value cannot be negative.
Pokitto 5:ea7377f3d1af 677 */
Pokitto 5:ea7377f3d1af 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Pokitto 5:ea7377f3d1af 679 {
Pokitto 5:ea7377f3d1af 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Pokitto 5:ea7377f3d1af 681 }
Pokitto 5:ea7377f3d1af 682
Pokitto 5:ea7377f3d1af 683
Pokitto 5:ea7377f3d1af 684 /** \brief Set Interrupt Priority
Pokitto 5:ea7377f3d1af 685
Pokitto 5:ea7377f3d1af 686 The function sets the priority of an interrupt.
Pokitto 5:ea7377f3d1af 687
Pokitto 5:ea7377f3d1af 688 \note The priority cannot be set for every core interrupt.
Pokitto 5:ea7377f3d1af 689
Pokitto 5:ea7377f3d1af 690 \param [in] IRQn Interrupt number.
Pokitto 5:ea7377f3d1af 691 \param [in] priority Priority to set.
Pokitto 5:ea7377f3d1af 692 */
Pokitto 5:ea7377f3d1af 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Pokitto 5:ea7377f3d1af 694 {
Pokitto 5:ea7377f3d1af 695 if(IRQn < 0) {
Pokitto 5:ea7377f3d1af 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Pokitto 5:ea7377f3d1af 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Pokitto 5:ea7377f3d1af 698 else {
Pokitto 5:ea7377f3d1af 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Pokitto 5:ea7377f3d1af 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Pokitto 5:ea7377f3d1af 701 }
Pokitto 5:ea7377f3d1af 702
Pokitto 5:ea7377f3d1af 703
Pokitto 5:ea7377f3d1af 704 /** \brief Get Interrupt Priority
Pokitto 5:ea7377f3d1af 705
Pokitto 5:ea7377f3d1af 706 The function reads the priority of an interrupt. The interrupt
Pokitto 5:ea7377f3d1af 707 number can be positive to specify an external (device specific)
Pokitto 5:ea7377f3d1af 708 interrupt, or negative to specify an internal (core) interrupt.
Pokitto 5:ea7377f3d1af 709
Pokitto 5:ea7377f3d1af 710
Pokitto 5:ea7377f3d1af 711 \param [in] IRQn Interrupt number.
Pokitto 5:ea7377f3d1af 712 \return Interrupt Priority. Value is aligned automatically to the implemented
Pokitto 5:ea7377f3d1af 713 priority bits of the microcontroller.
Pokitto 5:ea7377f3d1af 714 */
Pokitto 5:ea7377f3d1af 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Pokitto 5:ea7377f3d1af 716 {
Pokitto 5:ea7377f3d1af 717
Pokitto 5:ea7377f3d1af 718 if(IRQn < 0) {
Pokitto 5:ea7377f3d1af 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Pokitto 5:ea7377f3d1af 720 else {
Pokitto 5:ea7377f3d1af 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Pokitto 5:ea7377f3d1af 722 }
Pokitto 5:ea7377f3d1af 723
Pokitto 5:ea7377f3d1af 724
Pokitto 5:ea7377f3d1af 725 /** \brief System Reset
Pokitto 5:ea7377f3d1af 726
Pokitto 5:ea7377f3d1af 727 The function initiates a system reset request to reset the MCU.
Pokitto 5:ea7377f3d1af 728 */
Pokitto 5:ea7377f3d1af 729 __STATIC_INLINE void NVIC_SystemReset(void)
Pokitto 5:ea7377f3d1af 730 {
Pokitto 5:ea7377f3d1af 731 __DSB(); /* Ensure all outstanding memory accesses included
Pokitto 5:ea7377f3d1af 732 buffered write are completed before reset */
Pokitto 5:ea7377f3d1af 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Pokitto 5:ea7377f3d1af 734 SCB_AIRCR_SYSRESETREQ_Msk);
Pokitto 5:ea7377f3d1af 735 __DSB(); /* Ensure completion of memory access */
Pokitto 5:ea7377f3d1af 736 while(1); /* wait until reset */
Pokitto 5:ea7377f3d1af 737 }
Pokitto 5:ea7377f3d1af 738
Pokitto 5:ea7377f3d1af 739 /*@} end of CMSIS_Core_NVICFunctions */
Pokitto 5:ea7377f3d1af 740
Pokitto 5:ea7377f3d1af 741
Pokitto 5:ea7377f3d1af 742
Pokitto 5:ea7377f3d1af 743 /* ################################## SysTick function ############################################ */
Pokitto 5:ea7377f3d1af 744 /** \ingroup CMSIS_Core_FunctionInterface
Pokitto 5:ea7377f3d1af 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Pokitto 5:ea7377f3d1af 746 \brief Functions that configure the System.
Pokitto 5:ea7377f3d1af 747 @{
Pokitto 5:ea7377f3d1af 748 */
Pokitto 5:ea7377f3d1af 749
Pokitto 5:ea7377f3d1af 750 #if (__Vendor_SysTickConfig == 0)
Pokitto 5:ea7377f3d1af 751
Pokitto 5:ea7377f3d1af 752 /** \brief System Tick Configuration
Pokitto 5:ea7377f3d1af 753
Pokitto 5:ea7377f3d1af 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Pokitto 5:ea7377f3d1af 755 Counter is in free running mode to generate periodic interrupts.
Pokitto 5:ea7377f3d1af 756
Pokitto 5:ea7377f3d1af 757 \param [in] ticks Number of ticks between two interrupts.
Pokitto 5:ea7377f3d1af 758
Pokitto 5:ea7377f3d1af 759 \return 0 Function succeeded.
Pokitto 5:ea7377f3d1af 760 \return 1 Function failed.
Pokitto 5:ea7377f3d1af 761
Pokitto 5:ea7377f3d1af 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Pokitto 5:ea7377f3d1af 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Pokitto 5:ea7377f3d1af 764 must contain a vendor-specific implementation of this function.
Pokitto 5:ea7377f3d1af 765
Pokitto 5:ea7377f3d1af 766 */
Pokitto 5:ea7377f3d1af 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Pokitto 5:ea7377f3d1af 768 {
Pokitto 5:ea7377f3d1af 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Pokitto 5:ea7377f3d1af 770
Pokitto 5:ea7377f3d1af 771 SysTick->LOAD = ticks - 1; /* set reload register */
Pokitto 5:ea7377f3d1af 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Pokitto 5:ea7377f3d1af 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Pokitto 5:ea7377f3d1af 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Pokitto 5:ea7377f3d1af 775 SysTick_CTRL_TICKINT_Msk |
Pokitto 5:ea7377f3d1af 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Pokitto 5:ea7377f3d1af 777 return (0); /* Function successful */
Pokitto 5:ea7377f3d1af 778 }
Pokitto 5:ea7377f3d1af 779
Pokitto 5:ea7377f3d1af 780 #endif
Pokitto 5:ea7377f3d1af 781
Pokitto 5:ea7377f3d1af 782 /*@} end of CMSIS_Core_SysTickFunctions */
Pokitto 5:ea7377f3d1af 783
Pokitto 5:ea7377f3d1af 784
Pokitto 5:ea7377f3d1af 785
Pokitto 5:ea7377f3d1af 786
Pokitto 5:ea7377f3d1af 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Pokitto 5:ea7377f3d1af 788
Pokitto 5:ea7377f3d1af 789 #endif /* __CMSIS_GENERIC */
Pokitto 5:ea7377f3d1af 790
Pokitto 5:ea7377f3d1af 791 #ifdef __cplusplus
Pokitto 5:ea7377f3d1af 792 }
Pokitto 5:ea7377f3d1af 793 #endif