Jonne Valola / PokittoLib Featured

PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)

Dependents:   YATTT sd_map_test cPong SnowDemo ... more

PokittoLib

Library for programming Pokitto hardware

How to Use

  1. Import this library to online compiler (see button "import" on the right hand side
  2. DO NOT import mbed-src anymore, a better version is now included inside PokittoLib
  3. Change My_settings.h according to your project
  4. Start coding!

mbed-pokitto/targets/cmsis/core_caFunc.h@71:531419862202, 2019-12-25 (annotated)

Committer:
Pokitto
Date:
Wed Dec 25 23:59:52 2019 +0000
Revision:
71:531419862202
Parent:
5:ea7377f3d1af 
Changed Mode2 C++ refresh code (graphical errors)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pokitto 5:ea7377f3d1af 1 /**************************************************************************//**
Pokitto 5:ea7377f3d1af 2 * @file core_caFunc.h
Pokitto 5:ea7377f3d1af 3 * @brief CMSIS Cortex-A Core Function Access Header File
Pokitto 5:ea7377f3d1af 4 * @version V3.10
Pokitto 5:ea7377f3d1af 5 * @date 30 Oct 2013
Pokitto 5:ea7377f3d1af 6 *
Pokitto 5:ea7377f3d1af 7 * @note
Pokitto 5:ea7377f3d1af 8 *
Pokitto 5:ea7377f3d1af 9 ******************************************************************************/
Pokitto 5:ea7377f3d1af 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Pokitto 5:ea7377f3d1af 11
Pokitto 5:ea7377f3d1af 12 All rights reserved.
Pokitto 5:ea7377f3d1af 13 Redistribution and use in source and binary forms, with or without
Pokitto 5:ea7377f3d1af 14 modification, are permitted provided that the following conditions are met:
Pokitto 5:ea7377f3d1af 15 - Redistributions of source code must retain the above copyright
Pokitto 5:ea7377f3d1af 16 notice, this list of conditions and the following disclaimer.
Pokitto 5:ea7377f3d1af 17 - Redistributions in binary form must reproduce the above copyright
Pokitto 5:ea7377f3d1af 18 notice, this list of conditions and the following disclaimer in the
Pokitto 5:ea7377f3d1af 19 documentation and/or other materials provided with the distribution.
Pokitto 5:ea7377f3d1af 20 - Neither the name of ARM nor the names of its contributors may be used
Pokitto 5:ea7377f3d1af 21 to endorse or promote products derived from this software without
Pokitto 5:ea7377f3d1af 22 specific prior written permission.
Pokitto 5:ea7377f3d1af 23 *
Pokitto 5:ea7377f3d1af 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Pokitto 5:ea7377f3d1af 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Pokitto 5:ea7377f3d1af 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Pokitto 5:ea7377f3d1af 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Pokitto 5:ea7377f3d1af 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Pokitto 5:ea7377f3d1af 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Pokitto 5:ea7377f3d1af 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Pokitto 5:ea7377f3d1af 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Pokitto 5:ea7377f3d1af 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Pokitto 5:ea7377f3d1af 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Pokitto 5:ea7377f3d1af 34 POSSIBILITY OF SUCH DAMAGE.
Pokitto 5:ea7377f3d1af 35 ---------------------------------------------------------------------------*/
Pokitto 5:ea7377f3d1af 36
Pokitto 5:ea7377f3d1af 37
Pokitto 5:ea7377f3d1af 38 #ifndef __CORE_CAFUNC_H__
Pokitto 5:ea7377f3d1af 39 #define __CORE_CAFUNC_H__
Pokitto 5:ea7377f3d1af 40
Pokitto 5:ea7377f3d1af 41
Pokitto 5:ea7377f3d1af 42 /* ########################### Core Function Access ########################### */
Pokitto 5:ea7377f3d1af 43 /** \ingroup CMSIS_Core_FunctionInterface
Pokitto 5:ea7377f3d1af 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Pokitto 5:ea7377f3d1af 45 @{
Pokitto 5:ea7377f3d1af 46 */
Pokitto 5:ea7377f3d1af 47
Pokitto 5:ea7377f3d1af 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Pokitto 5:ea7377f3d1af 49 /* ARM armcc specific functions */
Pokitto 5:ea7377f3d1af 50
Pokitto 5:ea7377f3d1af 51 #if (__ARMCC_VERSION < 400677)
Pokitto 5:ea7377f3d1af 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Pokitto 5:ea7377f3d1af 53 #endif
Pokitto 5:ea7377f3d1af 54
Pokitto 5:ea7377f3d1af 55 #define MODE_USR 0x10
Pokitto 5:ea7377f3d1af 56 #define MODE_FIQ 0x11
Pokitto 5:ea7377f3d1af 57 #define MODE_IRQ 0x12
Pokitto 5:ea7377f3d1af 58 #define MODE_SVC 0x13
Pokitto 5:ea7377f3d1af 59 #define MODE_MON 0x16
Pokitto 5:ea7377f3d1af 60 #define MODE_ABT 0x17
Pokitto 5:ea7377f3d1af 61 #define MODE_HYP 0x1A
Pokitto 5:ea7377f3d1af 62 #define MODE_UND 0x1B
Pokitto 5:ea7377f3d1af 63 #define MODE_SYS 0x1F
Pokitto 5:ea7377f3d1af 64
Pokitto 5:ea7377f3d1af 65 /** \brief Get APSR Register
Pokitto 5:ea7377f3d1af 66
Pokitto 5:ea7377f3d1af 67 This function returns the content of the APSR Register.
Pokitto 5:ea7377f3d1af 68
Pokitto 5:ea7377f3d1af 69 \return APSR Register value
Pokitto 5:ea7377f3d1af 70 */
Pokitto 5:ea7377f3d1af 71 __STATIC_INLINE uint32_t __get_APSR(void)
Pokitto 5:ea7377f3d1af 72 {
Pokitto 5:ea7377f3d1af 73 register uint32_t __regAPSR __ASM("apsr");
Pokitto 5:ea7377f3d1af 74 return(__regAPSR);
Pokitto 5:ea7377f3d1af 75 }
Pokitto 5:ea7377f3d1af 76
Pokitto 5:ea7377f3d1af 77
Pokitto 5:ea7377f3d1af 78 /** \brief Get CPSR Register
Pokitto 5:ea7377f3d1af 79
Pokitto 5:ea7377f3d1af 80 This function returns the content of the CPSR Register.
Pokitto 5:ea7377f3d1af 81
Pokitto 5:ea7377f3d1af 82 \return CPSR Register value
Pokitto 5:ea7377f3d1af 83 */
Pokitto 5:ea7377f3d1af 84 __STATIC_INLINE uint32_t __get_CPSR(void)
Pokitto 5:ea7377f3d1af 85 {
Pokitto 5:ea7377f3d1af 86 register uint32_t __regCPSR __ASM("cpsr");
Pokitto 5:ea7377f3d1af 87 return(__regCPSR);
Pokitto 5:ea7377f3d1af 88 }
Pokitto 5:ea7377f3d1af 89
Pokitto 5:ea7377f3d1af 90 /** \brief Set Stack Pointer
Pokitto 5:ea7377f3d1af 91
Pokitto 5:ea7377f3d1af 92 This function assigns the given value to the current stack pointer.
Pokitto 5:ea7377f3d1af 93
Pokitto 5:ea7377f3d1af 94 \param [in] topOfStack Stack Pointer value to set
Pokitto 5:ea7377f3d1af 95 */
Pokitto 5:ea7377f3d1af 96 register uint32_t __regSP __ASM("sp");
Pokitto 5:ea7377f3d1af 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Pokitto 5:ea7377f3d1af 98 {
Pokitto 5:ea7377f3d1af 99 __regSP = topOfStack;
Pokitto 5:ea7377f3d1af 100 }
Pokitto 5:ea7377f3d1af 101
Pokitto 5:ea7377f3d1af 102
Pokitto 5:ea7377f3d1af 103 /** \brief Get link register
Pokitto 5:ea7377f3d1af 104
Pokitto 5:ea7377f3d1af 105 This function returns the value of the link register
Pokitto 5:ea7377f3d1af 106
Pokitto 5:ea7377f3d1af 107 \return Value of link register
Pokitto 5:ea7377f3d1af 108 */
Pokitto 5:ea7377f3d1af 109 register uint32_t __reglr __ASM("lr");
Pokitto 5:ea7377f3d1af 110 __STATIC_INLINE uint32_t __get_LR(void)
Pokitto 5:ea7377f3d1af 111 {
Pokitto 5:ea7377f3d1af 112 return(__reglr);
Pokitto 5:ea7377f3d1af 113 }
Pokitto 5:ea7377f3d1af 114
Pokitto 5:ea7377f3d1af 115 /** \brief Set link register
Pokitto 5:ea7377f3d1af 116
Pokitto 5:ea7377f3d1af 117 This function sets the value of the link register
Pokitto 5:ea7377f3d1af 118
Pokitto 5:ea7377f3d1af 119 \param [in] lr LR value to set
Pokitto 5:ea7377f3d1af 120 */
Pokitto 5:ea7377f3d1af 121 __STATIC_INLINE void __set_LR(uint32_t lr)
Pokitto 5:ea7377f3d1af 122 {
Pokitto 5:ea7377f3d1af 123 __reglr = lr;
Pokitto 5:ea7377f3d1af 124 }
Pokitto 5:ea7377f3d1af 125
Pokitto 5:ea7377f3d1af 126 /** \brief Set Process Stack Pointer
Pokitto 5:ea7377f3d1af 127
Pokitto 5:ea7377f3d1af 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Pokitto 5:ea7377f3d1af 129
Pokitto 5:ea7377f3d1af 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Pokitto 5:ea7377f3d1af 131 */
Pokitto 5:ea7377f3d1af 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
Pokitto 5:ea7377f3d1af 133 {
Pokitto 5:ea7377f3d1af 134 ARM
Pokitto 5:ea7377f3d1af 135 PRESERVE8
Pokitto 5:ea7377f3d1af 136
Pokitto 5:ea7377f3d1af 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
Pokitto 5:ea7377f3d1af 138 MRS R1, CPSR
Pokitto 5:ea7377f3d1af 139 CPS #MODE_SYS ;no effect in USR mode
Pokitto 5:ea7377f3d1af 140 MOV SP, R0
Pokitto 5:ea7377f3d1af 141 MSR CPSR_c, R1 ;no effect in USR mode
Pokitto 5:ea7377f3d1af 142 ISB
Pokitto 5:ea7377f3d1af 143 BX LR
Pokitto 5:ea7377f3d1af 144
Pokitto 5:ea7377f3d1af 145 }
Pokitto 5:ea7377f3d1af 146
Pokitto 5:ea7377f3d1af 147 /** \brief Set User Mode
Pokitto 5:ea7377f3d1af 148
Pokitto 5:ea7377f3d1af 149 This function changes the processor state to User Mode
Pokitto 5:ea7377f3d1af 150 */
Pokitto 5:ea7377f3d1af 151 __STATIC_ASM void __set_CPS_USR(void)
Pokitto 5:ea7377f3d1af 152 {
Pokitto 5:ea7377f3d1af 153 ARM
Pokitto 5:ea7377f3d1af 154
Pokitto 5:ea7377f3d1af 155 CPS #MODE_USR
Pokitto 5:ea7377f3d1af 156 BX LR
Pokitto 5:ea7377f3d1af 157 }
Pokitto 5:ea7377f3d1af 158
Pokitto 5:ea7377f3d1af 159
Pokitto 5:ea7377f3d1af 160 /** \brief Enable FIQ
Pokitto 5:ea7377f3d1af 161
Pokitto 5:ea7377f3d1af 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Pokitto 5:ea7377f3d1af 163 Can only be executed in Privileged modes.
Pokitto 5:ea7377f3d1af 164 */
Pokitto 5:ea7377f3d1af 165 #define __enable_fault_irq __enable_fiq
Pokitto 5:ea7377f3d1af 166
Pokitto 5:ea7377f3d1af 167
Pokitto 5:ea7377f3d1af 168 /** \brief Disable FIQ
Pokitto 5:ea7377f3d1af 169
Pokitto 5:ea7377f3d1af 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Pokitto 5:ea7377f3d1af 171 Can only be executed in Privileged modes.
Pokitto 5:ea7377f3d1af 172 */
Pokitto 5:ea7377f3d1af 173 #define __disable_fault_irq __disable_fiq
Pokitto 5:ea7377f3d1af 174
Pokitto 5:ea7377f3d1af 175
Pokitto 5:ea7377f3d1af 176 /** \brief Get FPSCR
Pokitto 5:ea7377f3d1af 177
Pokitto 5:ea7377f3d1af 178 This function returns the current value of the Floating Point Status/Control register.
Pokitto 5:ea7377f3d1af 179
Pokitto 5:ea7377f3d1af 180 \return Floating Point Status/Control register value
Pokitto 5:ea7377f3d1af 181 */
Pokitto 5:ea7377f3d1af 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
Pokitto 5:ea7377f3d1af 183 {
Pokitto 5:ea7377f3d1af 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Pokitto 5:ea7377f3d1af 185 register uint32_t __regfpscr __ASM("fpscr");
Pokitto 5:ea7377f3d1af 186 return(__regfpscr);
Pokitto 5:ea7377f3d1af 187 #else
Pokitto 5:ea7377f3d1af 188 return(0);
Pokitto 5:ea7377f3d1af 189 #endif
Pokitto 5:ea7377f3d1af 190 }
Pokitto 5:ea7377f3d1af 191
Pokitto 5:ea7377f3d1af 192
Pokitto 5:ea7377f3d1af 193 /** \brief Set FPSCR
Pokitto 5:ea7377f3d1af 194
Pokitto 5:ea7377f3d1af 195 This function assigns the given value to the Floating Point Status/Control register.
Pokitto 5:ea7377f3d1af 196
Pokitto 5:ea7377f3d1af 197 \param [in] fpscr Floating Point Status/Control value to set
Pokitto 5:ea7377f3d1af 198 */
Pokitto 5:ea7377f3d1af 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Pokitto 5:ea7377f3d1af 200 {
Pokitto 5:ea7377f3d1af 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Pokitto 5:ea7377f3d1af 202 register uint32_t __regfpscr __ASM("fpscr");
Pokitto 5:ea7377f3d1af 203 __regfpscr = (fpscr);
Pokitto 5:ea7377f3d1af 204 #endif
Pokitto 5:ea7377f3d1af 205 }
Pokitto 5:ea7377f3d1af 206
Pokitto 5:ea7377f3d1af 207 /** \brief Get FPEXC
Pokitto 5:ea7377f3d1af 208
Pokitto 5:ea7377f3d1af 209 This function returns the current value of the Floating Point Exception Control register.
Pokitto 5:ea7377f3d1af 210
Pokitto 5:ea7377f3d1af 211 \return Floating Point Exception Control register value
Pokitto 5:ea7377f3d1af 212 */
Pokitto 5:ea7377f3d1af 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
Pokitto 5:ea7377f3d1af 214 {
Pokitto 5:ea7377f3d1af 215 #if (__FPU_PRESENT == 1)
Pokitto 5:ea7377f3d1af 216 register uint32_t __regfpexc __ASM("fpexc");
Pokitto 5:ea7377f3d1af 217 return(__regfpexc);
Pokitto 5:ea7377f3d1af 218 #else
Pokitto 5:ea7377f3d1af 219 return(0);
Pokitto 5:ea7377f3d1af 220 #endif
Pokitto 5:ea7377f3d1af 221 }
Pokitto 5:ea7377f3d1af 222
Pokitto 5:ea7377f3d1af 223
Pokitto 5:ea7377f3d1af 224 /** \brief Set FPEXC
Pokitto 5:ea7377f3d1af 225
Pokitto 5:ea7377f3d1af 226 This function assigns the given value to the Floating Point Exception Control register.
Pokitto 5:ea7377f3d1af 227
Pokitto 5:ea7377f3d1af 228 \param [in] fpscr Floating Point Exception Control value to set
Pokitto 5:ea7377f3d1af 229 */
Pokitto 5:ea7377f3d1af 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Pokitto 5:ea7377f3d1af 231 {
Pokitto 5:ea7377f3d1af 232 #if (__FPU_PRESENT == 1)
Pokitto 5:ea7377f3d1af 233 register uint32_t __regfpexc __ASM("fpexc");
Pokitto 5:ea7377f3d1af 234 __regfpexc = (fpexc);
Pokitto 5:ea7377f3d1af 235 #endif
Pokitto 5:ea7377f3d1af 236 }
Pokitto 5:ea7377f3d1af 237
Pokitto 5:ea7377f3d1af 238 /** \brief Get CPACR
Pokitto 5:ea7377f3d1af 239
Pokitto 5:ea7377f3d1af 240 This function returns the current value of the Coprocessor Access Control register.
Pokitto 5:ea7377f3d1af 241
Pokitto 5:ea7377f3d1af 242 \return Coprocessor Access Control register value
Pokitto 5:ea7377f3d1af 243 */
Pokitto 5:ea7377f3d1af 244 __STATIC_INLINE uint32_t __get_CPACR(void)
Pokitto 5:ea7377f3d1af 245 {
Pokitto 5:ea7377f3d1af 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Pokitto 5:ea7377f3d1af 247 return __regCPACR;
Pokitto 5:ea7377f3d1af 248 }
Pokitto 5:ea7377f3d1af 249
Pokitto 5:ea7377f3d1af 250 /** \brief Set CPACR
Pokitto 5:ea7377f3d1af 251
Pokitto 5:ea7377f3d1af 252 This function assigns the given value to the Coprocessor Access Control register.
Pokitto 5:ea7377f3d1af 253
Pokitto 5:ea7377f3d1af 254 \param [in] cpacr Coprocessor Acccess Control value to set
Pokitto 5:ea7377f3d1af 255 */
Pokitto 5:ea7377f3d1af 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Pokitto 5:ea7377f3d1af 257 {
Pokitto 5:ea7377f3d1af 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Pokitto 5:ea7377f3d1af 259 __regCPACR = cpacr;
Pokitto 5:ea7377f3d1af 260 __ISB();
Pokitto 5:ea7377f3d1af 261 }
Pokitto 5:ea7377f3d1af 262
Pokitto 5:ea7377f3d1af 263 /** \brief Get CBAR
Pokitto 5:ea7377f3d1af 264
Pokitto 5:ea7377f3d1af 265 This function returns the value of the Configuration Base Address register.
Pokitto 5:ea7377f3d1af 266
Pokitto 5:ea7377f3d1af 267 \return Configuration Base Address register value
Pokitto 5:ea7377f3d1af 268 */
Pokitto 5:ea7377f3d1af 269 __STATIC_INLINE uint32_t __get_CBAR() {
Pokitto 5:ea7377f3d1af 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Pokitto 5:ea7377f3d1af 271 return(__regCBAR);
Pokitto 5:ea7377f3d1af 272 }
Pokitto 5:ea7377f3d1af 273
Pokitto 5:ea7377f3d1af 274 /** \brief Get TTBR0
Pokitto 5:ea7377f3d1af 275
Pokitto 5:ea7377f3d1af 276 This function returns the value of the Translation Table Base Register 0.
Pokitto 5:ea7377f3d1af 277
Pokitto 5:ea7377f3d1af 278 \return Translation Table Base Register 0 value
Pokitto 5:ea7377f3d1af 279 */
Pokitto 5:ea7377f3d1af 280 __STATIC_INLINE uint32_t __get_TTBR0() {
Pokitto 5:ea7377f3d1af 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Pokitto 5:ea7377f3d1af 282 return(__regTTBR0);
Pokitto 5:ea7377f3d1af 283 }
Pokitto 5:ea7377f3d1af 284
Pokitto 5:ea7377f3d1af 285 /** \brief Set TTBR0
Pokitto 5:ea7377f3d1af 286
Pokitto 5:ea7377f3d1af 287 This function assigns the given value to the Translation Table Base Register 0.
Pokitto 5:ea7377f3d1af 288
Pokitto 5:ea7377f3d1af 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
Pokitto 5:ea7377f3d1af 290 */
Pokitto 5:ea7377f3d1af 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Pokitto 5:ea7377f3d1af 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Pokitto 5:ea7377f3d1af 293 __regTTBR0 = ttbr0;
Pokitto 5:ea7377f3d1af 294 __ISB();
Pokitto 5:ea7377f3d1af 295 }
Pokitto 5:ea7377f3d1af 296
Pokitto 5:ea7377f3d1af 297 /** \brief Get DACR
Pokitto 5:ea7377f3d1af 298
Pokitto 5:ea7377f3d1af 299 This function returns the value of the Domain Access Control Register.
Pokitto 5:ea7377f3d1af 300
Pokitto 5:ea7377f3d1af 301 \return Domain Access Control Register value
Pokitto 5:ea7377f3d1af 302 */
Pokitto 5:ea7377f3d1af 303 __STATIC_INLINE uint32_t __get_DACR() {
Pokitto 5:ea7377f3d1af 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Pokitto 5:ea7377f3d1af 305 return(__regDACR);
Pokitto 5:ea7377f3d1af 306 }
Pokitto 5:ea7377f3d1af 307
Pokitto 5:ea7377f3d1af 308 /** \brief Set DACR
Pokitto 5:ea7377f3d1af 309
Pokitto 5:ea7377f3d1af 310 This function assigns the given value to the Domain Access Control Register.
Pokitto 5:ea7377f3d1af 311
Pokitto 5:ea7377f3d1af 312 \param [in] dacr Domain Access Control Register value to set
Pokitto 5:ea7377f3d1af 313 */
Pokitto 5:ea7377f3d1af 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Pokitto 5:ea7377f3d1af 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Pokitto 5:ea7377f3d1af 316 __regDACR = dacr;
Pokitto 5:ea7377f3d1af 317 __ISB();
Pokitto 5:ea7377f3d1af 318 }
Pokitto 5:ea7377f3d1af 319
Pokitto 5:ea7377f3d1af 320 /******************************** Cache and BTAC enable ****************************************************/
Pokitto 5:ea7377f3d1af 321
Pokitto 5:ea7377f3d1af 322 /** \brief Set SCTLR
Pokitto 5:ea7377f3d1af 323
Pokitto 5:ea7377f3d1af 324 This function assigns the given value to the System Control Register.
Pokitto 5:ea7377f3d1af 325
Pokitto 5:ea7377f3d1af 326 \param [in] sctlr System Control Register value to set
Pokitto 5:ea7377f3d1af 327 */
Pokitto 5:ea7377f3d1af 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Pokitto 5:ea7377f3d1af 329 {
Pokitto 5:ea7377f3d1af 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Pokitto 5:ea7377f3d1af 331 __regSCTLR = sctlr;
Pokitto 5:ea7377f3d1af 332 }
Pokitto 5:ea7377f3d1af 333
Pokitto 5:ea7377f3d1af 334 /** \brief Get SCTLR
Pokitto 5:ea7377f3d1af 335
Pokitto 5:ea7377f3d1af 336 This function returns the value of the System Control Register.
Pokitto 5:ea7377f3d1af 337
Pokitto 5:ea7377f3d1af 338 \return System Control Register value
Pokitto 5:ea7377f3d1af 339 */
Pokitto 5:ea7377f3d1af 340 __STATIC_INLINE uint32_t __get_SCTLR() {
Pokitto 5:ea7377f3d1af 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Pokitto 5:ea7377f3d1af 342 return(__regSCTLR);
Pokitto 5:ea7377f3d1af 343 }
Pokitto 5:ea7377f3d1af 344
Pokitto 5:ea7377f3d1af 345 /** \brief Enable Caches
Pokitto 5:ea7377f3d1af 346
Pokitto 5:ea7377f3d1af 347 Enable Caches
Pokitto 5:ea7377f3d1af 348 */
Pokitto 5:ea7377f3d1af 349 __STATIC_INLINE void __enable_caches(void) {
Pokitto 5:ea7377f3d1af 350 // Set I bit 12 to enable I Cache
Pokitto 5:ea7377f3d1af 351 // Set C bit 2 to enable D Cache
Pokitto 5:ea7377f3d1af 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Pokitto 5:ea7377f3d1af 353 }
Pokitto 5:ea7377f3d1af 354
Pokitto 5:ea7377f3d1af 355 /** \brief Disable Caches
Pokitto 5:ea7377f3d1af 356
Pokitto 5:ea7377f3d1af 357 Disable Caches
Pokitto 5:ea7377f3d1af 358 */
Pokitto 5:ea7377f3d1af 359 __STATIC_INLINE void __disable_caches(void) {
Pokitto 5:ea7377f3d1af 360 // Clear I bit 12 to disable I Cache
Pokitto 5:ea7377f3d1af 361 // Clear C bit 2 to disable D Cache
Pokitto 5:ea7377f3d1af 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Pokitto 5:ea7377f3d1af 363 __ISB();
Pokitto 5:ea7377f3d1af 364 }
Pokitto 5:ea7377f3d1af 365
Pokitto 5:ea7377f3d1af 366 /** \brief Enable BTAC
Pokitto 5:ea7377f3d1af 367
Pokitto 5:ea7377f3d1af 368 Enable BTAC
Pokitto 5:ea7377f3d1af 369 */
Pokitto 5:ea7377f3d1af 370 __STATIC_INLINE void __enable_btac(void) {
Pokitto 5:ea7377f3d1af 371 // Set Z bit 11 to enable branch prediction
Pokitto 5:ea7377f3d1af 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
Pokitto 5:ea7377f3d1af 373 __ISB();
Pokitto 5:ea7377f3d1af 374 }
Pokitto 5:ea7377f3d1af 375
Pokitto 5:ea7377f3d1af 376 /** \brief Disable BTAC
Pokitto 5:ea7377f3d1af 377
Pokitto 5:ea7377f3d1af 378 Disable BTAC
Pokitto 5:ea7377f3d1af 379 */
Pokitto 5:ea7377f3d1af 380 __STATIC_INLINE void __disable_btac(void) {
Pokitto 5:ea7377f3d1af 381 // Clear Z bit 11 to disable branch prediction
Pokitto 5:ea7377f3d1af 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Pokitto 5:ea7377f3d1af 383 }
Pokitto 5:ea7377f3d1af 384
Pokitto 5:ea7377f3d1af 385
Pokitto 5:ea7377f3d1af 386 /** \brief Enable MMU
Pokitto 5:ea7377f3d1af 387
Pokitto 5:ea7377f3d1af 388 Enable MMU
Pokitto 5:ea7377f3d1af 389 */
Pokitto 5:ea7377f3d1af 390 __STATIC_INLINE void __enable_mmu(void) {
Pokitto 5:ea7377f3d1af 391 // Set M bit 0 to enable the MMU
Pokitto 5:ea7377f3d1af 392 // Set AFE bit to enable simplified access permissions model
Pokitto 5:ea7377f3d1af 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Pokitto 5:ea7377f3d1af 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Pokitto 5:ea7377f3d1af 395 __ISB();
Pokitto 5:ea7377f3d1af 396 }
Pokitto 5:ea7377f3d1af 397
Pokitto 5:ea7377f3d1af 398 /** \brief Disable MMU
Pokitto 5:ea7377f3d1af 399
Pokitto 5:ea7377f3d1af 400 Disable MMU
Pokitto 5:ea7377f3d1af 401 */
Pokitto 5:ea7377f3d1af 402 __STATIC_INLINE void __disable_mmu(void) {
Pokitto 5:ea7377f3d1af 403 // Clear M bit 0 to disable the MMU
Pokitto 5:ea7377f3d1af 404 __set_SCTLR( __get_SCTLR() & ~1);
Pokitto 5:ea7377f3d1af 405 __ISB();
Pokitto 5:ea7377f3d1af 406 }
Pokitto 5:ea7377f3d1af 407
Pokitto 5:ea7377f3d1af 408 /******************************** TLB maintenance operations ************************************************/
Pokitto 5:ea7377f3d1af 409 /** \brief Invalidate the whole tlb
Pokitto 5:ea7377f3d1af 410
Pokitto 5:ea7377f3d1af 411 TLBIALL. Invalidate the whole tlb
Pokitto 5:ea7377f3d1af 412 */
Pokitto 5:ea7377f3d1af 413
Pokitto 5:ea7377f3d1af 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Pokitto 5:ea7377f3d1af 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Pokitto 5:ea7377f3d1af 416 __TLBIALL = 0;
Pokitto 5:ea7377f3d1af 417 __DSB();
Pokitto 5:ea7377f3d1af 418 __ISB();
Pokitto 5:ea7377f3d1af 419 }
Pokitto 5:ea7377f3d1af 420
Pokitto 5:ea7377f3d1af 421 /******************************** BTB maintenance operations ************************************************/
Pokitto 5:ea7377f3d1af 422 /** \brief Invalidate entire branch predictor array
Pokitto 5:ea7377f3d1af 423
Pokitto 5:ea7377f3d1af 424 BPIALL. Branch Predictor Invalidate All.
Pokitto 5:ea7377f3d1af 425 */
Pokitto 5:ea7377f3d1af 426
Pokitto 5:ea7377f3d1af 427 __STATIC_INLINE void __v7_inv_btac(void) {
Pokitto 5:ea7377f3d1af 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Pokitto 5:ea7377f3d1af 429 __BPIALL = 0;
Pokitto 5:ea7377f3d1af 430 __DSB(); //ensure completion of the invalidation
Pokitto 5:ea7377f3d1af 431 __ISB(); //ensure instruction fetch path sees new state
Pokitto 5:ea7377f3d1af 432 }
Pokitto 5:ea7377f3d1af 433
Pokitto 5:ea7377f3d1af 434
Pokitto 5:ea7377f3d1af 435 /******************************** L1 cache operations ******************************************************/
Pokitto 5:ea7377f3d1af 436
Pokitto 5:ea7377f3d1af 437 /** \brief Invalidate the whole I$
Pokitto 5:ea7377f3d1af 438
Pokitto 5:ea7377f3d1af 439 ICIALLU. Instruction Cache Invalidate All to PoU
Pokitto 5:ea7377f3d1af 440 */
Pokitto 5:ea7377f3d1af 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
Pokitto 5:ea7377f3d1af 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Pokitto 5:ea7377f3d1af 443 __ICIALLU = 0;
Pokitto 5:ea7377f3d1af 444 __DSB(); //ensure completion of the invalidation
Pokitto 5:ea7377f3d1af 445 __ISB(); //ensure instruction fetch path sees new I cache state
Pokitto 5:ea7377f3d1af 446 }
Pokitto 5:ea7377f3d1af 447
Pokitto 5:ea7377f3d1af 448 /** \brief Clean D$ by MVA
Pokitto 5:ea7377f3d1af 449
Pokitto 5:ea7377f3d1af 450 DCCMVAC. Data cache clean by MVA to PoC
Pokitto 5:ea7377f3d1af 451 */
Pokitto 5:ea7377f3d1af 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Pokitto 5:ea7377f3d1af 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Pokitto 5:ea7377f3d1af 454 __DCCMVAC = (uint32_t)va;
Pokitto 5:ea7377f3d1af 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:ea7377f3d1af 456 }
Pokitto 5:ea7377f3d1af 457
Pokitto 5:ea7377f3d1af 458 /** \brief Invalidate D$ by MVA
Pokitto 5:ea7377f3d1af 459
Pokitto 5:ea7377f3d1af 460 DCIMVAC. Data cache invalidate by MVA to PoC
Pokitto 5:ea7377f3d1af 461 */
Pokitto 5:ea7377f3d1af 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Pokitto 5:ea7377f3d1af 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Pokitto 5:ea7377f3d1af 464 __DCIMVAC = (uint32_t)va;
Pokitto 5:ea7377f3d1af 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:ea7377f3d1af 466 }
Pokitto 5:ea7377f3d1af 467
Pokitto 5:ea7377f3d1af 468 /** \brief Clean and Invalidate D$ by MVA
Pokitto 5:ea7377f3d1af 469
Pokitto 5:ea7377f3d1af 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Pokitto 5:ea7377f3d1af 471 */
Pokitto 5:ea7377f3d1af 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Pokitto 5:ea7377f3d1af 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Pokitto 5:ea7377f3d1af 474 __DCCIMVAC = (uint32_t)va;
Pokitto 5:ea7377f3d1af 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:ea7377f3d1af 476 }
Pokitto 5:ea7377f3d1af 477
Pokitto 5:ea7377f3d1af 478 /** \brief Clean and Invalidate the entire data or unified cache
Pokitto 5:ea7377f3d1af 479
Pokitto 5:ea7377f3d1af 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Pokitto 5:ea7377f3d1af 481 */
Pokitto 5:ea7377f3d1af 482 #pragma push
Pokitto 5:ea7377f3d1af 483 #pragma arm
Pokitto 5:ea7377f3d1af 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
Pokitto 5:ea7377f3d1af 485 ARM
Pokitto 5:ea7377f3d1af 486
Pokitto 5:ea7377f3d1af 487 PUSH {R4-R11}
Pokitto 5:ea7377f3d1af 488
Pokitto 5:ea7377f3d1af 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
Pokitto 5:ea7377f3d1af 490 ANDS R3, R6, #0x07000000 // Extract coherency level
Pokitto 5:ea7377f3d1af 491 MOV R3, R3, LSR #23 // Total cache levels << 1
Pokitto 5:ea7377f3d1af 492 BEQ Finished // If 0, no need to clean
Pokitto 5:ea7377f3d1af 493
Pokitto 5:ea7377f3d1af 494 MOV R10, #0 // R10 holds current cache level << 1
Pokitto 5:ea7377f3d1af 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
Pokitto 5:ea7377f3d1af 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
Pokitto 5:ea7377f3d1af 497 AND R1, R1, #7 // Isolate those lower 3 bits
Pokitto 5:ea7377f3d1af 498 CMP R1, #2
Pokitto 5:ea7377f3d1af 499 BLT Skip // No cache or only instruction cache at this level
Pokitto 5:ea7377f3d1af 500
Pokitto 5:ea7377f3d1af 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
Pokitto 5:ea7377f3d1af 502 ISB // ISB to sync the change to the CacheSizeID reg
Pokitto 5:ea7377f3d1af 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
Pokitto 5:ea7377f3d1af 504 AND R2, R1, #7 // Extract the line length field
Pokitto 5:ea7377f3d1af 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
Pokitto 5:ea7377f3d1af 506 LDR R4, =0x3FF
Pokitto 5:ea7377f3d1af 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
Pokitto 5:ea7377f3d1af 508 CLZ R5, R4 // R5 is the bit position of the way size increment
Pokitto 5:ea7377f3d1af 509 LDR R7, =0x7FFF
Pokitto 5:ea7377f3d1af 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
Pokitto 5:ea7377f3d1af 511
Pokitto 5:ea7377f3d1af 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
Pokitto 5:ea7377f3d1af 513
Pokitto 5:ea7377f3d1af 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
Pokitto 5:ea7377f3d1af 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
Pokitto 5:ea7377f3d1af 516 CMP R0, #0
Pokitto 5:ea7377f3d1af 517 BNE Dccsw
Pokitto 5:ea7377f3d1af 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
Pokitto 5:ea7377f3d1af 519 B cont
Pokitto 5:ea7377f3d1af 520 Dccsw CMP R0, #1
Pokitto 5:ea7377f3d1af 521 BNE Dccisw
Pokitto 5:ea7377f3d1af 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
Pokitto 5:ea7377f3d1af 523 B cont
Pokitto 5:ea7377f3d1af 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
Pokitto 5:ea7377f3d1af 525 cont SUBS R9, R9, #1 // Decrement the Way number
Pokitto 5:ea7377f3d1af 526 BGE Loop3
Pokitto 5:ea7377f3d1af 527 SUBS R7, R7, #1 // Decrement the Set number
Pokitto 5:ea7377f3d1af 528 BGE Loop2
Pokitto 5:ea7377f3d1af 529 Skip ADD R10, R10, #2 // Increment the cache number
Pokitto 5:ea7377f3d1af 530 CMP R3, R10
Pokitto 5:ea7377f3d1af 531 BGT Loop1
Pokitto 5:ea7377f3d1af 532
Pokitto 5:ea7377f3d1af 533 Finished
Pokitto 5:ea7377f3d1af 534 DSB
Pokitto 5:ea7377f3d1af 535 POP {R4-R11}
Pokitto 5:ea7377f3d1af 536 BX lr
Pokitto 5:ea7377f3d1af 537
Pokitto 5:ea7377f3d1af 538 }
Pokitto 5:ea7377f3d1af 539 #pragma pop
Pokitto 5:ea7377f3d1af 540
Pokitto 5:ea7377f3d1af 541
Pokitto 5:ea7377f3d1af 542 /** \brief Invalidate the whole D$
Pokitto 5:ea7377f3d1af 543
Pokitto 5:ea7377f3d1af 544 DCISW. Invalidate by Set/Way
Pokitto 5:ea7377f3d1af 545 */
Pokitto 5:ea7377f3d1af 546
Pokitto 5:ea7377f3d1af 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
Pokitto 5:ea7377f3d1af 548 __v7_all_cache(0);
Pokitto 5:ea7377f3d1af 549 }
Pokitto 5:ea7377f3d1af 550
Pokitto 5:ea7377f3d1af 551 /** \brief Clean the whole D$
Pokitto 5:ea7377f3d1af 552
Pokitto 5:ea7377f3d1af 553 DCCSW. Clean by Set/Way
Pokitto 5:ea7377f3d1af 554 */
Pokitto 5:ea7377f3d1af 555
Pokitto 5:ea7377f3d1af 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
Pokitto 5:ea7377f3d1af 557 __v7_all_cache(1);
Pokitto 5:ea7377f3d1af 558 }
Pokitto 5:ea7377f3d1af 559
Pokitto 5:ea7377f3d1af 560 /** \brief Clean and invalidate the whole D$
Pokitto 5:ea7377f3d1af 561
Pokitto 5:ea7377f3d1af 562 DCCISW. Clean and Invalidate by Set/Way
Pokitto 5:ea7377f3d1af 563 */
Pokitto 5:ea7377f3d1af 564
Pokitto 5:ea7377f3d1af 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Pokitto 5:ea7377f3d1af 566 __v7_all_cache(2);
Pokitto 5:ea7377f3d1af 567 }
Pokitto 5:ea7377f3d1af 568
Pokitto 5:ea7377f3d1af 569 #include "core_ca_mmu.h"
Pokitto 5:ea7377f3d1af 570
Pokitto 5:ea7377f3d1af 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
Pokitto 5:ea7377f3d1af 572
Pokitto 5:ea7377f3d1af 573 #error IAR Compiler support not implemented for Cortex-A
Pokitto 5:ea7377f3d1af 574
Pokitto 5:ea7377f3d1af 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Pokitto 5:ea7377f3d1af 576 /* GNU gcc specific functions */
Pokitto 5:ea7377f3d1af 577
Pokitto 5:ea7377f3d1af 578 #define MODE_USR 0x10
Pokitto 5:ea7377f3d1af 579 #define MODE_FIQ 0x11
Pokitto 5:ea7377f3d1af 580 #define MODE_IRQ 0x12
Pokitto 5:ea7377f3d1af 581 #define MODE_SVC 0x13
Pokitto 5:ea7377f3d1af 582 #define MODE_MON 0x16
Pokitto 5:ea7377f3d1af 583 #define MODE_ABT 0x17
Pokitto 5:ea7377f3d1af 584 #define MODE_HYP 0x1A
Pokitto 5:ea7377f3d1af 585 #define MODE_UND 0x1B
Pokitto 5:ea7377f3d1af 586 #define MODE_SYS 0x1F
Pokitto 5:ea7377f3d1af 587
Pokitto 5:ea7377f3d1af 588
Pokitto 5:ea7377f3d1af 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Pokitto 5:ea7377f3d1af 590 {
Pokitto 5:ea7377f3d1af 591 __ASM volatile ("cpsie i");
Pokitto 5:ea7377f3d1af 592 }
Pokitto 5:ea7377f3d1af 593
Pokitto 5:ea7377f3d1af 594 /** \brief Disable IRQ Interrupts
Pokitto 5:ea7377f3d1af 595
Pokitto 5:ea7377f3d1af 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Pokitto 5:ea7377f3d1af 597 Can only be executed in Privileged modes.
Pokitto 5:ea7377f3d1af 598 */
Pokitto 5:ea7377f3d1af 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
Pokitto 5:ea7377f3d1af 600 {
Pokitto 5:ea7377f3d1af 601 uint32_t result;
Pokitto 5:ea7377f3d1af 602
Pokitto 5:ea7377f3d1af 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
Pokitto 5:ea7377f3d1af 604 __ASM volatile ("cpsid i");
Pokitto 5:ea7377f3d1af 605 return(result & 0x80);
Pokitto 5:ea7377f3d1af 606 }
Pokitto 5:ea7377f3d1af 607
Pokitto 5:ea7377f3d1af 608
Pokitto 5:ea7377f3d1af 609 /** \brief Get APSR Register
Pokitto 5:ea7377f3d1af 610
Pokitto 5:ea7377f3d1af 611 This function returns the content of the APSR Register.
Pokitto 5:ea7377f3d1af 612
Pokitto 5:ea7377f3d1af 613 \return APSR Register value
Pokitto 5:ea7377f3d1af 614 */
Pokitto 5:ea7377f3d1af 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Pokitto 5:ea7377f3d1af 616 {
Pokitto 5:ea7377f3d1af 617 #if 1
Pokitto 5:ea7377f3d1af 618 register uint32_t __regAPSR;
Pokitto 5:ea7377f3d1af 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
Pokitto 5:ea7377f3d1af 620 #else
Pokitto 5:ea7377f3d1af 621 register uint32_t __regAPSR __ASM("apsr");
Pokitto 5:ea7377f3d1af 622 #endif
Pokitto 5:ea7377f3d1af 623 return(__regAPSR);
Pokitto 5:ea7377f3d1af 624 }
Pokitto 5:ea7377f3d1af 625
Pokitto 5:ea7377f3d1af 626
Pokitto 5:ea7377f3d1af 627 /** \brief Get CPSR Register
Pokitto 5:ea7377f3d1af 628
Pokitto 5:ea7377f3d1af 629 This function returns the content of the CPSR Register.
Pokitto 5:ea7377f3d1af 630
Pokitto 5:ea7377f3d1af 631 \return CPSR Register value
Pokitto 5:ea7377f3d1af 632 */
Pokitto 5:ea7377f3d1af 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
Pokitto 5:ea7377f3d1af 634 {
Pokitto 5:ea7377f3d1af 635 #if 1
Pokitto 5:ea7377f3d1af 636 register uint32_t __regCPSR;
Pokitto 5:ea7377f3d1af 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
Pokitto 5:ea7377f3d1af 638 #else
Pokitto 5:ea7377f3d1af 639 register uint32_t __regCPSR __ASM("cpsr");
Pokitto 5:ea7377f3d1af 640 #endif
Pokitto 5:ea7377f3d1af 641 return(__regCPSR);
Pokitto 5:ea7377f3d1af 642 }
Pokitto 5:ea7377f3d1af 643
Pokitto 5:ea7377f3d1af 644 #if 0
Pokitto 5:ea7377f3d1af 645 /** \brief Set Stack Pointer
Pokitto 5:ea7377f3d1af 646
Pokitto 5:ea7377f3d1af 647 This function assigns the given value to the current stack pointer.
Pokitto 5:ea7377f3d1af 648
Pokitto 5:ea7377f3d1af 649 \param [in] topOfStack Stack Pointer value to set
Pokitto 5:ea7377f3d1af 650 */
Pokitto 5:ea7377f3d1af 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
Pokitto 5:ea7377f3d1af 652 {
Pokitto 5:ea7377f3d1af 653 register uint32_t __regSP __ASM("sp");
Pokitto 5:ea7377f3d1af 654 __regSP = topOfStack;
Pokitto 5:ea7377f3d1af 655 }
Pokitto 5:ea7377f3d1af 656 #endif
Pokitto 5:ea7377f3d1af 657
Pokitto 5:ea7377f3d1af 658 /** \brief Get link register
Pokitto 5:ea7377f3d1af 659
Pokitto 5:ea7377f3d1af 660 This function returns the value of the link register
Pokitto 5:ea7377f3d1af 661
Pokitto 5:ea7377f3d1af 662 \return Value of link register
Pokitto 5:ea7377f3d1af 663 */
Pokitto 5:ea7377f3d1af 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
Pokitto 5:ea7377f3d1af 665 {
Pokitto 5:ea7377f3d1af 666 register uint32_t __reglr __ASM("lr");
Pokitto 5:ea7377f3d1af 667 return(__reglr);
Pokitto 5:ea7377f3d1af 668 }
Pokitto 5:ea7377f3d1af 669
Pokitto 5:ea7377f3d1af 670 #if 0
Pokitto 5:ea7377f3d1af 671 /** \brief Set link register
Pokitto 5:ea7377f3d1af 672
Pokitto 5:ea7377f3d1af 673 This function sets the value of the link register
Pokitto 5:ea7377f3d1af 674
Pokitto 5:ea7377f3d1af 675 \param [in] lr LR value to set
Pokitto 5:ea7377f3d1af 676 */
Pokitto 5:ea7377f3d1af 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
Pokitto 5:ea7377f3d1af 678 {
Pokitto 5:ea7377f3d1af 679 register uint32_t __reglr __ASM("lr");
Pokitto 5:ea7377f3d1af 680 __reglr = lr;
Pokitto 5:ea7377f3d1af 681 }
Pokitto 5:ea7377f3d1af 682 #endif
Pokitto 5:ea7377f3d1af 683
Pokitto 5:ea7377f3d1af 684 /** \brief Set Process Stack Pointer
Pokitto 5:ea7377f3d1af 685
Pokitto 5:ea7377f3d1af 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
Pokitto 5:ea7377f3d1af 687
Pokitto 5:ea7377f3d1af 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
Pokitto 5:ea7377f3d1af 689 */
Pokitto 5:ea7377f3d1af 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Pokitto 5:ea7377f3d1af 691 {
Pokitto 5:ea7377f3d1af 692 __asm__ volatile (
Pokitto 5:ea7377f3d1af 693 ".ARM;"
Pokitto 5:ea7377f3d1af 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
Pokitto 5:ea7377f3d1af 695
Pokitto 5:ea7377f3d1af 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
Pokitto 5:ea7377f3d1af 697 "MRS R1, CPSR;"
Pokitto 5:ea7377f3d1af 698 "CPS %0;" /* ;no effect in USR mode */
Pokitto 5:ea7377f3d1af 699 "MOV SP, R0;"
Pokitto 5:ea7377f3d1af 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
Pokitto 5:ea7377f3d1af 701 "ISB;"
Pokitto 5:ea7377f3d1af 702 //"BX LR;"
Pokitto 5:ea7377f3d1af 703 :
Pokitto 5:ea7377f3d1af 704 : "i"(MODE_SYS)
Pokitto 5:ea7377f3d1af 705 : "r0", "r1");
Pokitto 5:ea7377f3d1af 706 return;
Pokitto 5:ea7377f3d1af 707 }
Pokitto 5:ea7377f3d1af 708
Pokitto 5:ea7377f3d1af 709 /** \brief Set User Mode
Pokitto 5:ea7377f3d1af 710
Pokitto 5:ea7377f3d1af 711 This function changes the processor state to User Mode
Pokitto 5:ea7377f3d1af 712 */
Pokitto 5:ea7377f3d1af 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
Pokitto 5:ea7377f3d1af 714 {
Pokitto 5:ea7377f3d1af 715 __asm__ volatile (
Pokitto 5:ea7377f3d1af 716 ".ARM;"
Pokitto 5:ea7377f3d1af 717
Pokitto 5:ea7377f3d1af 718 "CPS %0;"
Pokitto 5:ea7377f3d1af 719 //"BX LR;"
Pokitto 5:ea7377f3d1af 720 :
Pokitto 5:ea7377f3d1af 721 : "i"(MODE_USR)
Pokitto 5:ea7377f3d1af 722 : );
Pokitto 5:ea7377f3d1af 723 return;
Pokitto 5:ea7377f3d1af 724 }
Pokitto 5:ea7377f3d1af 725
Pokitto 5:ea7377f3d1af 726
Pokitto 5:ea7377f3d1af 727 /** \brief Enable FIQ
Pokitto 5:ea7377f3d1af 728
Pokitto 5:ea7377f3d1af 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Pokitto 5:ea7377f3d1af 730 Can only be executed in Privileged modes.
Pokitto 5:ea7377f3d1af 731 */
Pokitto 5:ea7377f3d1af 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
Pokitto 5:ea7377f3d1af 733
Pokitto 5:ea7377f3d1af 734
Pokitto 5:ea7377f3d1af 735 /** \brief Disable FIQ
Pokitto 5:ea7377f3d1af 736
Pokitto 5:ea7377f3d1af 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Pokitto 5:ea7377f3d1af 738 Can only be executed in Privileged modes.
Pokitto 5:ea7377f3d1af 739 */
Pokitto 5:ea7377f3d1af 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
Pokitto 5:ea7377f3d1af 741
Pokitto 5:ea7377f3d1af 742
Pokitto 5:ea7377f3d1af 743 /** \brief Get FPSCR
Pokitto 5:ea7377f3d1af 744
Pokitto 5:ea7377f3d1af 745 This function returns the current value of the Floating Point Status/Control register.
Pokitto 5:ea7377f3d1af 746
Pokitto 5:ea7377f3d1af 747 \return Floating Point Status/Control register value
Pokitto 5:ea7377f3d1af 748 */
Pokitto 5:ea7377f3d1af 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Pokitto 5:ea7377f3d1af 750 {
Pokitto 5:ea7377f3d1af 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Pokitto 5:ea7377f3d1af 752 #if 1
Pokitto 5:ea7377f3d1af 753 uint32_t result;
Pokitto 5:ea7377f3d1af 754
Pokitto 5:ea7377f3d1af 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
Pokitto 5:ea7377f3d1af 756 return (result);
Pokitto 5:ea7377f3d1af 757 #else
Pokitto 5:ea7377f3d1af 758 register uint32_t __regfpscr __ASM("fpscr");
Pokitto 5:ea7377f3d1af 759 return(__regfpscr);
Pokitto 5:ea7377f3d1af 760 #endif
Pokitto 5:ea7377f3d1af 761 #else
Pokitto 5:ea7377f3d1af 762 return(0);
Pokitto 5:ea7377f3d1af 763 #endif
Pokitto 5:ea7377f3d1af 764 }
Pokitto 5:ea7377f3d1af 765
Pokitto 5:ea7377f3d1af 766
Pokitto 5:ea7377f3d1af 767 /** \brief Set FPSCR
Pokitto 5:ea7377f3d1af 768
Pokitto 5:ea7377f3d1af 769 This function assigns the given value to the Floating Point Status/Control register.
Pokitto 5:ea7377f3d1af 770
Pokitto 5:ea7377f3d1af 771 \param [in] fpscr Floating Point Status/Control value to set
Pokitto 5:ea7377f3d1af 772 */
Pokitto 5:ea7377f3d1af 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Pokitto 5:ea7377f3d1af 774 {
Pokitto 5:ea7377f3d1af 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Pokitto 5:ea7377f3d1af 776 #if 1
Pokitto 5:ea7377f3d1af 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
Pokitto 5:ea7377f3d1af 778 #else
Pokitto 5:ea7377f3d1af 779 register uint32_t __regfpscr __ASM("fpscr");
Pokitto 5:ea7377f3d1af 780 __regfpscr = (fpscr);
Pokitto 5:ea7377f3d1af 781 #endif
Pokitto 5:ea7377f3d1af 782 #endif
Pokitto 5:ea7377f3d1af 783 }
Pokitto 5:ea7377f3d1af 784
Pokitto 5:ea7377f3d1af 785 /** \brief Get FPEXC
Pokitto 5:ea7377f3d1af 786
Pokitto 5:ea7377f3d1af 787 This function returns the current value of the Floating Point Exception Control register.
Pokitto 5:ea7377f3d1af 788
Pokitto 5:ea7377f3d1af 789 \return Floating Point Exception Control register value
Pokitto 5:ea7377f3d1af 790 */
Pokitto 5:ea7377f3d1af 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
Pokitto 5:ea7377f3d1af 792 {
Pokitto 5:ea7377f3d1af 793 #if (__FPU_PRESENT == 1)
Pokitto 5:ea7377f3d1af 794 #if 1
Pokitto 5:ea7377f3d1af 795 uint32_t result;
Pokitto 5:ea7377f3d1af 796
Pokitto 5:ea7377f3d1af 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
Pokitto 5:ea7377f3d1af 798 return (result);
Pokitto 5:ea7377f3d1af 799 #else
Pokitto 5:ea7377f3d1af 800 register uint32_t __regfpexc __ASM("fpexc");
Pokitto 5:ea7377f3d1af 801 return(__regfpexc);
Pokitto 5:ea7377f3d1af 802 #endif
Pokitto 5:ea7377f3d1af 803 #else
Pokitto 5:ea7377f3d1af 804 return(0);
Pokitto 5:ea7377f3d1af 805 #endif
Pokitto 5:ea7377f3d1af 806 }
Pokitto 5:ea7377f3d1af 807
Pokitto 5:ea7377f3d1af 808
Pokitto 5:ea7377f3d1af 809 /** \brief Set FPEXC
Pokitto 5:ea7377f3d1af 810
Pokitto 5:ea7377f3d1af 811 This function assigns the given value to the Floating Point Exception Control register.
Pokitto 5:ea7377f3d1af 812
Pokitto 5:ea7377f3d1af 813 \param [in] fpscr Floating Point Exception Control value to set
Pokitto 5:ea7377f3d1af 814 */
Pokitto 5:ea7377f3d1af 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
Pokitto 5:ea7377f3d1af 816 {
Pokitto 5:ea7377f3d1af 817 #if (__FPU_PRESENT == 1)
Pokitto 5:ea7377f3d1af 818 #if 1
Pokitto 5:ea7377f3d1af 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
Pokitto 5:ea7377f3d1af 820 #else
Pokitto 5:ea7377f3d1af 821 register uint32_t __regfpexc __ASM("fpexc");
Pokitto 5:ea7377f3d1af 822 __regfpexc = (fpexc);
Pokitto 5:ea7377f3d1af 823 #endif
Pokitto 5:ea7377f3d1af 824 #endif
Pokitto 5:ea7377f3d1af 825 }
Pokitto 5:ea7377f3d1af 826
Pokitto 5:ea7377f3d1af 827 /** \brief Get CPACR
Pokitto 5:ea7377f3d1af 828
Pokitto 5:ea7377f3d1af 829 This function returns the current value of the Coprocessor Access Control register.
Pokitto 5:ea7377f3d1af 830
Pokitto 5:ea7377f3d1af 831 \return Coprocessor Access Control register value
Pokitto 5:ea7377f3d1af 832 */
Pokitto 5:ea7377f3d1af 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
Pokitto 5:ea7377f3d1af 834 {
Pokitto 5:ea7377f3d1af 835 #if 1
Pokitto 5:ea7377f3d1af 836 register uint32_t __regCPACR;
Pokitto 5:ea7377f3d1af 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
Pokitto 5:ea7377f3d1af 838 #else
Pokitto 5:ea7377f3d1af 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Pokitto 5:ea7377f3d1af 840 #endif
Pokitto 5:ea7377f3d1af 841 return __regCPACR;
Pokitto 5:ea7377f3d1af 842 }
Pokitto 5:ea7377f3d1af 843
Pokitto 5:ea7377f3d1af 844 /** \brief Set CPACR
Pokitto 5:ea7377f3d1af 845
Pokitto 5:ea7377f3d1af 846 This function assigns the given value to the Coprocessor Access Control register.
Pokitto 5:ea7377f3d1af 847
Pokitto 5:ea7377f3d1af 848 \param [in] cpacr Coprocessor Acccess Control value to set
Pokitto 5:ea7377f3d1af 849 */
Pokitto 5:ea7377f3d1af 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
Pokitto 5:ea7377f3d1af 851 {
Pokitto 5:ea7377f3d1af 852 #if 1
Pokitto 5:ea7377f3d1af 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
Pokitto 5:ea7377f3d1af 854 #else
Pokitto 5:ea7377f3d1af 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
Pokitto 5:ea7377f3d1af 856 __regCPACR = cpacr;
Pokitto 5:ea7377f3d1af 857 #endif
Pokitto 5:ea7377f3d1af 858 __ISB();
Pokitto 5:ea7377f3d1af 859 }
Pokitto 5:ea7377f3d1af 860
Pokitto 5:ea7377f3d1af 861 /** \brief Get CBAR
Pokitto 5:ea7377f3d1af 862
Pokitto 5:ea7377f3d1af 863 This function returns the value of the Configuration Base Address register.
Pokitto 5:ea7377f3d1af 864
Pokitto 5:ea7377f3d1af 865 \return Configuration Base Address register value
Pokitto 5:ea7377f3d1af 866 */
Pokitto 5:ea7377f3d1af 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
Pokitto 5:ea7377f3d1af 868 #if 1
Pokitto 5:ea7377f3d1af 869 register uint32_t __regCBAR;
Pokitto 5:ea7377f3d1af 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
Pokitto 5:ea7377f3d1af 871 #else
Pokitto 5:ea7377f3d1af 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
Pokitto 5:ea7377f3d1af 873 #endif
Pokitto 5:ea7377f3d1af 874 return(__regCBAR);
Pokitto 5:ea7377f3d1af 875 }
Pokitto 5:ea7377f3d1af 876
Pokitto 5:ea7377f3d1af 877 /** \brief Get TTBR0
Pokitto 5:ea7377f3d1af 878
Pokitto 5:ea7377f3d1af 879 This function returns the value of the Translation Table Base Register 0.
Pokitto 5:ea7377f3d1af 880
Pokitto 5:ea7377f3d1af 881 \return Translation Table Base Register 0 value
Pokitto 5:ea7377f3d1af 882 */
Pokitto 5:ea7377f3d1af 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
Pokitto 5:ea7377f3d1af 884 #if 1
Pokitto 5:ea7377f3d1af 885 register uint32_t __regTTBR0;
Pokitto 5:ea7377f3d1af 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
Pokitto 5:ea7377f3d1af 887 #else
Pokitto 5:ea7377f3d1af 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Pokitto 5:ea7377f3d1af 889 #endif
Pokitto 5:ea7377f3d1af 890 return(__regTTBR0);
Pokitto 5:ea7377f3d1af 891 }
Pokitto 5:ea7377f3d1af 892
Pokitto 5:ea7377f3d1af 893 /** \brief Set TTBR0
Pokitto 5:ea7377f3d1af 894
Pokitto 5:ea7377f3d1af 895 This function assigns the given value to the Translation Table Base Register 0.
Pokitto 5:ea7377f3d1af 896
Pokitto 5:ea7377f3d1af 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
Pokitto 5:ea7377f3d1af 898 */
Pokitto 5:ea7377f3d1af 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
Pokitto 5:ea7377f3d1af 900 #if 1
Pokitto 5:ea7377f3d1af 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
Pokitto 5:ea7377f3d1af 902 #else
Pokitto 5:ea7377f3d1af 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
Pokitto 5:ea7377f3d1af 904 __regTTBR0 = ttbr0;
Pokitto 5:ea7377f3d1af 905 #endif
Pokitto 5:ea7377f3d1af 906 __ISB();
Pokitto 5:ea7377f3d1af 907 }
Pokitto 5:ea7377f3d1af 908
Pokitto 5:ea7377f3d1af 909 /** \brief Get DACR
Pokitto 5:ea7377f3d1af 910
Pokitto 5:ea7377f3d1af 911 This function returns the value of the Domain Access Control Register.
Pokitto 5:ea7377f3d1af 912
Pokitto 5:ea7377f3d1af 913 \return Domain Access Control Register value
Pokitto 5:ea7377f3d1af 914 */
Pokitto 5:ea7377f3d1af 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
Pokitto 5:ea7377f3d1af 916 #if 1
Pokitto 5:ea7377f3d1af 917 register uint32_t __regDACR;
Pokitto 5:ea7377f3d1af 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
Pokitto 5:ea7377f3d1af 919 #else
Pokitto 5:ea7377f3d1af 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Pokitto 5:ea7377f3d1af 921 #endif
Pokitto 5:ea7377f3d1af 922 return(__regDACR);
Pokitto 5:ea7377f3d1af 923 }
Pokitto 5:ea7377f3d1af 924
Pokitto 5:ea7377f3d1af 925 /** \brief Set DACR
Pokitto 5:ea7377f3d1af 926
Pokitto 5:ea7377f3d1af 927 This function assigns the given value to the Domain Access Control Register.
Pokitto 5:ea7377f3d1af 928
Pokitto 5:ea7377f3d1af 929 \param [in] dacr Domain Access Control Register value to set
Pokitto 5:ea7377f3d1af 930 */
Pokitto 5:ea7377f3d1af 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
Pokitto 5:ea7377f3d1af 932 #if 1
Pokitto 5:ea7377f3d1af 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
Pokitto 5:ea7377f3d1af 934 #else
Pokitto 5:ea7377f3d1af 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
Pokitto 5:ea7377f3d1af 936 __regDACR = dacr;
Pokitto 5:ea7377f3d1af 937 #endif
Pokitto 5:ea7377f3d1af 938 __ISB();
Pokitto 5:ea7377f3d1af 939 }
Pokitto 5:ea7377f3d1af 940
Pokitto 5:ea7377f3d1af 941 /******************************** Cache and BTAC enable ****************************************************/
Pokitto 5:ea7377f3d1af 942
Pokitto 5:ea7377f3d1af 943 /** \brief Set SCTLR
Pokitto 5:ea7377f3d1af 944
Pokitto 5:ea7377f3d1af 945 This function assigns the given value to the System Control Register.
Pokitto 5:ea7377f3d1af 946
Pokitto 5:ea7377f3d1af 947 \param [in] sctlr System Control Register value to set
Pokitto 5:ea7377f3d1af 948 */
Pokitto 5:ea7377f3d1af 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
Pokitto 5:ea7377f3d1af 950 {
Pokitto 5:ea7377f3d1af 951 #if 1
Pokitto 5:ea7377f3d1af 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
Pokitto 5:ea7377f3d1af 953 #else
Pokitto 5:ea7377f3d1af 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Pokitto 5:ea7377f3d1af 955 __regSCTLR = sctlr;
Pokitto 5:ea7377f3d1af 956 #endif
Pokitto 5:ea7377f3d1af 957 }
Pokitto 5:ea7377f3d1af 958
Pokitto 5:ea7377f3d1af 959 /** \brief Get SCTLR
Pokitto 5:ea7377f3d1af 960
Pokitto 5:ea7377f3d1af 961 This function returns the value of the System Control Register.
Pokitto 5:ea7377f3d1af 962
Pokitto 5:ea7377f3d1af 963 \return System Control Register value
Pokitto 5:ea7377f3d1af 964 */
Pokitto 5:ea7377f3d1af 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
Pokitto 5:ea7377f3d1af 966 #if 1
Pokitto 5:ea7377f3d1af 967 register uint32_t __regSCTLR;
Pokitto 5:ea7377f3d1af 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
Pokitto 5:ea7377f3d1af 969 #else
Pokitto 5:ea7377f3d1af 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
Pokitto 5:ea7377f3d1af 971 #endif
Pokitto 5:ea7377f3d1af 972 return(__regSCTLR);
Pokitto 5:ea7377f3d1af 973 }
Pokitto 5:ea7377f3d1af 974
Pokitto 5:ea7377f3d1af 975 /** \brief Enable Caches
Pokitto 5:ea7377f3d1af 976
Pokitto 5:ea7377f3d1af 977 Enable Caches
Pokitto 5:ea7377f3d1af 978 */
Pokitto 5:ea7377f3d1af 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
Pokitto 5:ea7377f3d1af 980 // Set I bit 12 to enable I Cache
Pokitto 5:ea7377f3d1af 981 // Set C bit 2 to enable D Cache
Pokitto 5:ea7377f3d1af 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
Pokitto 5:ea7377f3d1af 983 }
Pokitto 5:ea7377f3d1af 984
Pokitto 5:ea7377f3d1af 985 /** \brief Disable Caches
Pokitto 5:ea7377f3d1af 986
Pokitto 5:ea7377f3d1af 987 Disable Caches
Pokitto 5:ea7377f3d1af 988 */
Pokitto 5:ea7377f3d1af 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
Pokitto 5:ea7377f3d1af 990 // Clear I bit 12 to disable I Cache
Pokitto 5:ea7377f3d1af 991 // Clear C bit 2 to disable D Cache
Pokitto 5:ea7377f3d1af 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
Pokitto 5:ea7377f3d1af 993 __ISB();
Pokitto 5:ea7377f3d1af 994 }
Pokitto 5:ea7377f3d1af 995
Pokitto 5:ea7377f3d1af 996 /** \brief Enable BTAC
Pokitto 5:ea7377f3d1af 997
Pokitto 5:ea7377f3d1af 998 Enable BTAC
Pokitto 5:ea7377f3d1af 999 */
Pokitto 5:ea7377f3d1af 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
Pokitto 5:ea7377f3d1af 1001 // Set Z bit 11 to enable branch prediction
Pokitto 5:ea7377f3d1af 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
Pokitto 5:ea7377f3d1af 1003 __ISB();
Pokitto 5:ea7377f3d1af 1004 }
Pokitto 5:ea7377f3d1af 1005
Pokitto 5:ea7377f3d1af 1006 /** \brief Disable BTAC
Pokitto 5:ea7377f3d1af 1007
Pokitto 5:ea7377f3d1af 1008 Disable BTAC
Pokitto 5:ea7377f3d1af 1009 */
Pokitto 5:ea7377f3d1af 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
Pokitto 5:ea7377f3d1af 1011 // Clear Z bit 11 to disable branch prediction
Pokitto 5:ea7377f3d1af 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
Pokitto 5:ea7377f3d1af 1013 }
Pokitto 5:ea7377f3d1af 1014
Pokitto 5:ea7377f3d1af 1015
Pokitto 5:ea7377f3d1af 1016 /** \brief Enable MMU
Pokitto 5:ea7377f3d1af 1017
Pokitto 5:ea7377f3d1af 1018 Enable MMU
Pokitto 5:ea7377f3d1af 1019 */
Pokitto 5:ea7377f3d1af 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
Pokitto 5:ea7377f3d1af 1021 // Set M bit 0 to enable the MMU
Pokitto 5:ea7377f3d1af 1022 // Set AFE bit to enable simplified access permissions model
Pokitto 5:ea7377f3d1af 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
Pokitto 5:ea7377f3d1af 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
Pokitto 5:ea7377f3d1af 1025 __ISB();
Pokitto 5:ea7377f3d1af 1026 }
Pokitto 5:ea7377f3d1af 1027
Pokitto 5:ea7377f3d1af 1028 /** \brief Disable MMU
Pokitto 5:ea7377f3d1af 1029
Pokitto 5:ea7377f3d1af 1030 Disable MMU
Pokitto 5:ea7377f3d1af 1031 */
Pokitto 5:ea7377f3d1af 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
Pokitto 5:ea7377f3d1af 1033 // Clear M bit 0 to disable the MMU
Pokitto 5:ea7377f3d1af 1034 __set_SCTLR( __get_SCTLR() & ~1);
Pokitto 5:ea7377f3d1af 1035 __ISB();
Pokitto 5:ea7377f3d1af 1036 }
Pokitto 5:ea7377f3d1af 1037
Pokitto 5:ea7377f3d1af 1038 /******************************** TLB maintenance operations ************************************************/
Pokitto 5:ea7377f3d1af 1039 /** \brief Invalidate the whole tlb
Pokitto 5:ea7377f3d1af 1040
Pokitto 5:ea7377f3d1af 1041 TLBIALL. Invalidate the whole tlb
Pokitto 5:ea7377f3d1af 1042 */
Pokitto 5:ea7377f3d1af 1043
Pokitto 5:ea7377f3d1af 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
Pokitto 5:ea7377f3d1af 1045 #if 1
Pokitto 5:ea7377f3d1af 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
Pokitto 5:ea7377f3d1af 1047 #else
Pokitto 5:ea7377f3d1af 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
Pokitto 5:ea7377f3d1af 1049 __TLBIALL = 0;
Pokitto 5:ea7377f3d1af 1050 #endif
Pokitto 5:ea7377f3d1af 1051 __DSB();
Pokitto 5:ea7377f3d1af 1052 __ISB();
Pokitto 5:ea7377f3d1af 1053 }
Pokitto 5:ea7377f3d1af 1054
Pokitto 5:ea7377f3d1af 1055 /******************************** BTB maintenance operations ************************************************/
Pokitto 5:ea7377f3d1af 1056 /** \brief Invalidate entire branch predictor array
Pokitto 5:ea7377f3d1af 1057
Pokitto 5:ea7377f3d1af 1058 BPIALL. Branch Predictor Invalidate All.
Pokitto 5:ea7377f3d1af 1059 */
Pokitto 5:ea7377f3d1af 1060
Pokitto 5:ea7377f3d1af 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
Pokitto 5:ea7377f3d1af 1062 #if 1
Pokitto 5:ea7377f3d1af 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
Pokitto 5:ea7377f3d1af 1064 #else
Pokitto 5:ea7377f3d1af 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
Pokitto 5:ea7377f3d1af 1066 __BPIALL = 0;
Pokitto 5:ea7377f3d1af 1067 #endif
Pokitto 5:ea7377f3d1af 1068 __DSB(); //ensure completion of the invalidation
Pokitto 5:ea7377f3d1af 1069 __ISB(); //ensure instruction fetch path sees new state
Pokitto 5:ea7377f3d1af 1070 }
Pokitto 5:ea7377f3d1af 1071
Pokitto 5:ea7377f3d1af 1072
Pokitto 5:ea7377f3d1af 1073 /******************************** L1 cache operations ******************************************************/
Pokitto 5:ea7377f3d1af 1074
Pokitto 5:ea7377f3d1af 1075 /** \brief Invalidate the whole I$
Pokitto 5:ea7377f3d1af 1076
Pokitto 5:ea7377f3d1af 1077 ICIALLU. Instruction Cache Invalidate All to PoU
Pokitto 5:ea7377f3d1af 1078 */
Pokitto 5:ea7377f3d1af 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
Pokitto 5:ea7377f3d1af 1080 #if 1
Pokitto 5:ea7377f3d1af 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
Pokitto 5:ea7377f3d1af 1082 #else
Pokitto 5:ea7377f3d1af 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
Pokitto 5:ea7377f3d1af 1084 __ICIALLU = 0;
Pokitto 5:ea7377f3d1af 1085 #endif
Pokitto 5:ea7377f3d1af 1086 __DSB(); //ensure completion of the invalidation
Pokitto 5:ea7377f3d1af 1087 __ISB(); //ensure instruction fetch path sees new I cache state
Pokitto 5:ea7377f3d1af 1088 }
Pokitto 5:ea7377f3d1af 1089
Pokitto 5:ea7377f3d1af 1090 /** \brief Clean D$ by MVA
Pokitto 5:ea7377f3d1af 1091
Pokitto 5:ea7377f3d1af 1092 DCCMVAC. Data cache clean by MVA to PoC
Pokitto 5:ea7377f3d1af 1093 */
Pokitto 5:ea7377f3d1af 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
Pokitto 5:ea7377f3d1af 1095 #if 1
Pokitto 5:ea7377f3d1af 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
Pokitto 5:ea7377f3d1af 1097 #else
Pokitto 5:ea7377f3d1af 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
Pokitto 5:ea7377f3d1af 1099 __DCCMVAC = (uint32_t)va;
Pokitto 5:ea7377f3d1af 1100 #endif
Pokitto 5:ea7377f3d1af 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:ea7377f3d1af 1102 }
Pokitto 5:ea7377f3d1af 1103
Pokitto 5:ea7377f3d1af 1104 /** \brief Invalidate D$ by MVA
Pokitto 5:ea7377f3d1af 1105
Pokitto 5:ea7377f3d1af 1106 DCIMVAC. Data cache invalidate by MVA to PoC
Pokitto 5:ea7377f3d1af 1107 */
Pokitto 5:ea7377f3d1af 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
Pokitto 5:ea7377f3d1af 1109 #if 1
Pokitto 5:ea7377f3d1af 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
Pokitto 5:ea7377f3d1af 1111 #else
Pokitto 5:ea7377f3d1af 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
Pokitto 5:ea7377f3d1af 1113 __DCIMVAC = (uint32_t)va;
Pokitto 5:ea7377f3d1af 1114 #endif
Pokitto 5:ea7377f3d1af 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:ea7377f3d1af 1116 }
Pokitto 5:ea7377f3d1af 1117
Pokitto 5:ea7377f3d1af 1118 /** \brief Clean and Invalidate D$ by MVA
Pokitto 5:ea7377f3d1af 1119
Pokitto 5:ea7377f3d1af 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
Pokitto 5:ea7377f3d1af 1121 */
Pokitto 5:ea7377f3d1af 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
Pokitto 5:ea7377f3d1af 1123 #if 1
Pokitto 5:ea7377f3d1af 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
Pokitto 5:ea7377f3d1af 1125 #else
Pokitto 5:ea7377f3d1af 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
Pokitto 5:ea7377f3d1af 1127 __DCCIMVAC = (uint32_t)va;
Pokitto 5:ea7377f3d1af 1128 #endif
Pokitto 5:ea7377f3d1af 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
Pokitto 5:ea7377f3d1af 1130 }
Pokitto 5:ea7377f3d1af 1131
Pokitto 5:ea7377f3d1af 1132 /** \brief Clean and Invalidate the entire data or unified cache
Pokitto 5:ea7377f3d1af 1133
Pokitto 5:ea7377f3d1af 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
Pokitto 5:ea7377f3d1af 1135 */
Pokitto 5:ea7377f3d1af 1136 extern void __v7_all_cache(uint32_t op);
Pokitto 5:ea7377f3d1af 1137
Pokitto 5:ea7377f3d1af 1138
Pokitto 5:ea7377f3d1af 1139 /** \brief Invalidate the whole D$
Pokitto 5:ea7377f3d1af 1140
Pokitto 5:ea7377f3d1af 1141 DCISW. Invalidate by Set/Way
Pokitto 5:ea7377f3d1af 1142 */
Pokitto 5:ea7377f3d1af 1143
Pokitto 5:ea7377f3d1af 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
Pokitto 5:ea7377f3d1af 1145 __v7_all_cache(0);
Pokitto 5:ea7377f3d1af 1146 }
Pokitto 5:ea7377f3d1af 1147
Pokitto 5:ea7377f3d1af 1148 /** \brief Clean the whole D$
Pokitto 5:ea7377f3d1af 1149
Pokitto 5:ea7377f3d1af 1150 DCCSW. Clean by Set/Way
Pokitto 5:ea7377f3d1af 1151 */
Pokitto 5:ea7377f3d1af 1152
Pokitto 5:ea7377f3d1af 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
Pokitto 5:ea7377f3d1af 1154 __v7_all_cache(1);
Pokitto 5:ea7377f3d1af 1155 }
Pokitto 5:ea7377f3d1af 1156
Pokitto 5:ea7377f3d1af 1157 /** \brief Clean and invalidate the whole D$
Pokitto 5:ea7377f3d1af 1158
Pokitto 5:ea7377f3d1af 1159 DCCISW. Clean and Invalidate by Set/Way
Pokitto 5:ea7377f3d1af 1160 */
Pokitto 5:ea7377f3d1af 1161
Pokitto 5:ea7377f3d1af 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
Pokitto 5:ea7377f3d1af 1163 __v7_all_cache(2);
Pokitto 5:ea7377f3d1af 1164 }
Pokitto 5:ea7377f3d1af 1165
Pokitto 5:ea7377f3d1af 1166 #include "core_ca_mmu.h"
Pokitto 5:ea7377f3d1af 1167
Pokitto 5:ea7377f3d1af 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
Pokitto 5:ea7377f3d1af 1169
Pokitto 5:ea7377f3d1af 1170 #error TASKING Compiler support not implemented for Cortex-A
Pokitto 5:ea7377f3d1af 1171
Pokitto 5:ea7377f3d1af 1172 #endif
Pokitto 5:ea7377f3d1af 1173
Pokitto 5:ea7377f3d1af 1174 /*@} end of CMSIS_Core_RegAccFunctions */
Pokitto 5:ea7377f3d1af 1175
Pokitto 5:ea7377f3d1af 1176
Pokitto 5:ea7377f3d1af 1177 #endif /* __CORE_CAFUNC_H__ */