Christian Agerer / SX1276_L072CZ-LRWAN1lib

Library SX1276 Pinout for DISCO_B_L072CZ-LRWAN1 Board

Fork of SX1276Lib by Semtech

sx1276/sx1276-hal.cpp@27:53d98539c28f, 2017-05-30 (annotated)

Committer:
Picard22
Date:
Tue May 30 23:37:42 2017 +0000
Revision:
27:53d98539c28f
Parent:
26:d09a8ef807e2 
corrected for DISCO-L072CZ Pinout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
mluis 22:7f3aab69cca9 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:e6ceb13d2d05 18
mluis 21:2e496deb7858 19 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
GregCr 0:e6ceb13d2d05 22 PinName antSwitch )
mluis 21:2e496deb7858 23 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
mluis 26:d09a8ef807e2 24 AntSwitch( antSwitch ),
GregCr 12:aa5b3bf7fdf4 25 #if( defined ( TARGET_NUCLEO_L152RE ) )
mluis 26:d09a8ef807e2 26 Fake( D8 )
GregCr 12:aa5b3bf7fdf4 27 #else
mluis 26:d09a8ef807e2 28 Fake( A3 )
GregCr 0:e6ceb13d2d05 29 #endif
GregCr 0:e6ceb13d2d05 30 {
mluis 21:2e496deb7858 31 this->RadioEvents = events;
mluis 21:2e496deb7858 32
GregCr 0:e6ceb13d2d05 33 Reset( );
mluis 26:d09a8ef807e2 34
GregCr 0:e6ceb13d2d05 35 RxChainCalibration( );
mluis 26:d09a8ef807e2 36
GregCr 0:e6ceb13d2d05 37 IoInit( );
mluis 26:d09a8ef807e2 38
GregCr 0:e6ceb13d2d05 39 SetOpMode( RF_OPMODE_SLEEP );
mluis 26:d09a8ef807e2 40
GregCr 0:e6ceb13d2d05 41 IoIrqInit( dioIrq );
mluis 26:d09a8ef807e2 42
GregCr 0:e6ceb13d2d05 43 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 44
GregCr 0:e6ceb13d2d05 45 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 46
mluis 21:2e496deb7858 47 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 48 }
GregCr 0:e6ceb13d2d05 49
mluis 26:d09a8ef807e2 50 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
GregCr 12:aa5b3bf7fdf4 51 #if defined ( TARGET_NUCLEO_L152RE )
mluis 21:2e496deb7858 52 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 26:d09a8ef807e2 53 AntSwitch( A4 ),
mluis 26:d09a8ef807e2 54 Fake( D8 )
mluis 20:e05596ba4166 55 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 56 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 26:d09a8ef807e2 57 AntSwitch( P0_23 ),
mluis 26:d09a8ef807e2 58 Fake( A3 )
Picard22 27:53d98539c28f 59
Picard22 27:53d98539c28f 60 #else( TARGET_DISCO_L072CZ )
Picard22 27:53d98539c28f 61 : SX1276( events, PA_7, PA_6, PB_3, PA_15, PC_0, PB_4, PB_1, PB_0, D6, PA_5, PA_4 ),
Picard22 27:53d98539c28f 62 AntSwitch( PA_1 ),
mluis 26:d09a8ef807e2 63 Fake( A3 )
GregCr 0:e6ceb13d2d05 64 #endif
GregCr 0:e6ceb13d2d05 65 {
mluis 21:2e496deb7858 66 this->RadioEvents = events;
mluis 21:2e496deb7858 67
GregCr 0:e6ceb13d2d05 68 Reset( );
mluis 26:d09a8ef807e2 69
GregCr 5:11ec8a6ba4f0 70 boardConnected = UNKNOWN;
mluis 26:d09a8ef807e2 71
GregCr 1:f979673946c0 72 DetectBoardType( );
mluis 26:d09a8ef807e2 73
GregCr 0:e6ceb13d2d05 74 RxChainCalibration( );
mluis 26:d09a8ef807e2 75
GregCr 0:e6ceb13d2d05 76 IoInit( );
mluis 26:d09a8ef807e2 77
GregCr 0:e6ceb13d2d05 78 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 79 IoIrqInit( dioIrq );
mluis 26:d09a8ef807e2 80
GregCr 0:e6ceb13d2d05 81 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 82
GregCr 0:e6ceb13d2d05 83 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 84
mluis 21:2e496deb7858 85 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 86 }
GregCr 0:e6ceb13d2d05 87
GregCr 0:e6ceb13d2d05 88 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 89 // Board relative functions
GregCr 0:e6ceb13d2d05 90 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 91 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 92 {
GregCr 5:11ec8a6ba4f0 93 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 94 {
mluis 26:d09a8ef807e2 95 this->AntSwitch.input( );
GregCr 5:11ec8a6ba4f0 96 wait_ms( 1 );
mluis 26:d09a8ef807e2 97 if( this->AntSwitch == 1 )
GregCr 5:11ec8a6ba4f0 98 {
GregCr 5:11ec8a6ba4f0 99 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 100 }
GregCr 5:11ec8a6ba4f0 101 else
GregCr 5:11ec8a6ba4f0 102 {
GregCr 5:11ec8a6ba4f0 103 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 104 }
mluis 26:d09a8ef807e2 105 this->AntSwitch.output( );
GregCr 5:11ec8a6ba4f0 106 wait_ms( 1 );
GregCr 1:f979673946c0 107 }
GregCr 2:5eb3066446dd 108 return ( boardConnected );
GregCr 1:f979673946c0 109 }
GregCr 0:e6ceb13d2d05 110
GregCr 0:e6ceb13d2d05 111 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 112 {
GregCr 0:e6ceb13d2d05 113 AntSwInit( );
GregCr 0:e6ceb13d2d05 114 SpiInit( );
GregCr 0:e6ceb13d2d05 115 }
GregCr 0:e6ceb13d2d05 116
mluis 22:7f3aab69cca9 117 void SX1276MB1xAS::RadioRegistersInit( )
mluis 22:7f3aab69cca9 118 {
GregCr 0:e6ceb13d2d05 119 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 120 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 121 {
GregCr 0:e6ceb13d2d05 122 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 123 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 124 }
GregCr 0:e6ceb13d2d05 125 }
GregCr 0:e6ceb13d2d05 126
GregCr 0:e6ceb13d2d05 127 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 128 {
GregCr 0:e6ceb13d2d05 129 nss = 1;
GregCr 0:e6ceb13d2d05 130 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 131 uint32_t frequencyToSet = 8000000;
mluis 26:d09a8ef807e2 132 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 133 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 134 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 135 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 136 #else
GregCr 0:e6ceb13d2d05 137 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 138 #endif
GregCr 0:e6ceb13d2d05 139 wait(0.1);
GregCr 0:e6ceb13d2d05 140 }
GregCr 0:e6ceb13d2d05 141
GregCr 0:e6ceb13d2d05 142 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 143 {
mluis 26:d09a8ef807e2 144 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
mluis 26:d09a8ef807e2 145 dio0.mode( PullDown );
mluis 26:d09a8ef807e2 146 dio1.mode( PullDown );
mluis 26:d09a8ef807e2 147 dio2.mode( PullDown );
mluis 26:d09a8ef807e2 148 dio3.mode( PullDown );
mluis 26:d09a8ef807e2 149 dio4.mode( PullDown );
mluis 22:7f3aab69cca9 150 #endif
mluis 26:d09a8ef807e2 151 dio0.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) ) );
mluis 26:d09a8ef807e2 152 dio1.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) ) );
mluis 26:d09a8ef807e2 153 dio2.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) ) );
mluis 26:d09a8ef807e2 154 dio3.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) ) );
mluis 26:d09a8ef807e2 155 dio4.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) ) );
GregCr 0:e6ceb13d2d05 156 }
GregCr 0:e6ceb13d2d05 157
GregCr 0:e6ceb13d2d05 158 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 159 {
GregCr 0:e6ceb13d2d05 160 //nothing
GregCr 0:e6ceb13d2d05 161 }
GregCr 0:e6ceb13d2d05 162
mluis 26:d09a8ef807e2 163 void SX1276MB1xAS::SetRfTxPower( int8_t power )
mluis 26:d09a8ef807e2 164 {
mluis 26:d09a8ef807e2 165 uint8_t paConfig = 0;
mluis 26:d09a8ef807e2 166 uint8_t paDac = 0;
mluis 26:d09a8ef807e2 167
mluis 26:d09a8ef807e2 168 paConfig = Read( REG_PACONFIG );
mluis 26:d09a8ef807e2 169 paDac = Read( REG_PADAC );
mluis 26:d09a8ef807e2 170
mluis 26:d09a8ef807e2 171 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
mluis 26:d09a8ef807e2 172 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
mluis 26:d09a8ef807e2 173
mluis 26:d09a8ef807e2 174 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 26:d09a8ef807e2 175 {
mluis 26:d09a8ef807e2 176 if( power > 17 )
mluis 26:d09a8ef807e2 177 {
mluis 26:d09a8ef807e2 178 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
mluis 26:d09a8ef807e2 179 }
mluis 26:d09a8ef807e2 180 else
mluis 26:d09a8ef807e2 181 {
mluis 26:d09a8ef807e2 182 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
mluis 26:d09a8ef807e2 183 }
mluis 26:d09a8ef807e2 184 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
mluis 26:d09a8ef807e2 185 {
mluis 26:d09a8ef807e2 186 if( power < 5 )
mluis 26:d09a8ef807e2 187 {
mluis 26:d09a8ef807e2 188 power = 5;
mluis 26:d09a8ef807e2 189 }
mluis 26:d09a8ef807e2 190 if( power > 20 )
mluis 26:d09a8ef807e2 191 {
mluis 26:d09a8ef807e2 192 power = 20;
mluis 26:d09a8ef807e2 193 }
mluis 26:d09a8ef807e2 194 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
mluis 26:d09a8ef807e2 195 }
mluis 26:d09a8ef807e2 196 else
mluis 26:d09a8ef807e2 197 {
mluis 26:d09a8ef807e2 198 if( power < 2 )
mluis 26:d09a8ef807e2 199 {
mluis 26:d09a8ef807e2 200 power = 2;
mluis 26:d09a8ef807e2 201 }
mluis 26:d09a8ef807e2 202 if( power > 17 )
mluis 26:d09a8ef807e2 203 {
mluis 26:d09a8ef807e2 204 power = 17;
mluis 26:d09a8ef807e2 205 }
mluis 26:d09a8ef807e2 206 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
mluis 26:d09a8ef807e2 207 }
mluis 26:d09a8ef807e2 208 }
mluis 26:d09a8ef807e2 209 else
mluis 26:d09a8ef807e2 210 {
mluis 26:d09a8ef807e2 211 if( power < -1 )
mluis 26:d09a8ef807e2 212 {
mluis 26:d09a8ef807e2 213 power = -1;
mluis 26:d09a8ef807e2 214 }
mluis 26:d09a8ef807e2 215 if( power > 14 )
mluis 26:d09a8ef807e2 216 {
mluis 26:d09a8ef807e2 217 power = 14;
mluis 26:d09a8ef807e2 218 }
mluis 26:d09a8ef807e2 219 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
mluis 26:d09a8ef807e2 220 }
mluis 26:d09a8ef807e2 221 Write( REG_PACONFIG, paConfig );
mluis 26:d09a8ef807e2 222 Write( REG_PADAC, paDac );
mluis 26:d09a8ef807e2 223 }
mluis 26:d09a8ef807e2 224
GregCr 0:e6ceb13d2d05 225 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 226 {
GregCr 0:e6ceb13d2d05 227 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 228 {
GregCr 3:ca84be1f3fac 229 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 230 {
GregCr 1:f979673946c0 231 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 232 }
GregCr 1:f979673946c0 233 else
GregCr 1:f979673946c0 234 {
GregCr 1:f979673946c0 235 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 236 }
GregCr 0:e6ceb13d2d05 237 }
GregCr 0:e6ceb13d2d05 238 else
GregCr 0:e6ceb13d2d05 239 {
GregCr 0:e6ceb13d2d05 240 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 241 }
GregCr 0:e6ceb13d2d05 242 }
GregCr 0:e6ceb13d2d05 243
GregCr 0:e6ceb13d2d05 244 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 245 {
GregCr 0:e6ceb13d2d05 246 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 247 {
GregCr 0:e6ceb13d2d05 248 isRadioActive = status;
GregCr 0:e6ceb13d2d05 249
GregCr 0:e6ceb13d2d05 250 if( status == false )
GregCr 0:e6ceb13d2d05 251 {
GregCr 0:e6ceb13d2d05 252 AntSwInit( );
GregCr 0:e6ceb13d2d05 253 }
GregCr 0:e6ceb13d2d05 254 else
GregCr 0:e6ceb13d2d05 255 {
GregCr 0:e6ceb13d2d05 256 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 257 }
GregCr 0:e6ceb13d2d05 258 }
GregCr 0:e6ceb13d2d05 259 }
GregCr 0:e6ceb13d2d05 260
GregCr 0:e6ceb13d2d05 261 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 262 {
mluis 26:d09a8ef807e2 263 this->AntSwitch = 0;
GregCr 0:e6ceb13d2d05 264 }
GregCr 0:e6ceb13d2d05 265
GregCr 0:e6ceb13d2d05 266 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 267 {
mluis 26:d09a8ef807e2 268 this->AntSwitch = 0;
GregCr 0:e6ceb13d2d05 269 }
GregCr 0:e6ceb13d2d05 270
mluis 26:d09a8ef807e2 271 void SX1276MB1xAS::SetAntSw( uint8_t opMode )
GregCr 0:e6ceb13d2d05 272 {
mluis 26:d09a8ef807e2 273 switch( opMode )
GregCr 0:e6ceb13d2d05 274 {
mluis 26:d09a8ef807e2 275 case RFLR_OPMODE_TRANSMITTER:
mluis 26:d09a8ef807e2 276 this->AntSwitch = 1;
mluis 26:d09a8ef807e2 277 break;
mluis 26:d09a8ef807e2 278 case RFLR_OPMODE_RECEIVER:
mluis 26:d09a8ef807e2 279 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 26:d09a8ef807e2 280 case RFLR_OPMODE_CAD:
mluis 26:d09a8ef807e2 281 this->AntSwitch = 0;
mluis 26:d09a8ef807e2 282 break;
mluis 26:d09a8ef807e2 283 default:
mluis 26:d09a8ef807e2 284 this->AntSwitch = 0;
mluis 26:d09a8ef807e2 285 break;
GregCr 0:e6ceb13d2d05 286 }
GregCr 0:e6ceb13d2d05 287 }
GregCr 0:e6ceb13d2d05 288
GregCr 0:e6ceb13d2d05 289 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 290 {
mluis 26:d09a8ef807e2 291 // Implement check. Currently all frequencies are supported
GregCr 0:e6ceb13d2d05 292 return true;
GregCr 0:e6ceb13d2d05 293 }
GregCr 0:e6ceb13d2d05 294
GregCr 0:e6ceb13d2d05 295 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 296 {
mluis 26:d09a8ef807e2 297 reset.output( );
GregCr 0:e6ceb13d2d05 298 reset = 0;
GregCr 0:e6ceb13d2d05 299 wait_ms( 1 );
mluis 26:d09a8ef807e2 300 reset.input( );
GregCr 0:e6ceb13d2d05 301 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 302 }
mluis 26:d09a8ef807e2 303
GregCr 0:e6ceb13d2d05 304 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 305 {
GregCr 0:e6ceb13d2d05 306 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 307 }
GregCr 0:e6ceb13d2d05 308
GregCr 0:e6ceb13d2d05 309 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 310 {
GregCr 0:e6ceb13d2d05 311 uint8_t data;
GregCr 0:e6ceb13d2d05 312 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 313 return data;
GregCr 0:e6ceb13d2d05 314 }
GregCr 0:e6ceb13d2d05 315
GregCr 0:e6ceb13d2d05 316 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 317 {
GregCr 0:e6ceb13d2d05 318 uint8_t i;
GregCr 0:e6ceb13d2d05 319
GregCr 0:e6ceb13d2d05 320 nss = 0;
GregCr 0:e6ceb13d2d05 321 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 322 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 323 {
GregCr 0:e6ceb13d2d05 324 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 325 }
GregCr 0:e6ceb13d2d05 326 nss = 1;
GregCr 0:e6ceb13d2d05 327 }
GregCr 0:e6ceb13d2d05 328
GregCr 0:e6ceb13d2d05 329 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 330 {
GregCr 0:e6ceb13d2d05 331 uint8_t i;
GregCr 0:e6ceb13d2d05 332
GregCr 0:e6ceb13d2d05 333 nss = 0;
GregCr 0:e6ceb13d2d05 334 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 335 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 336 {
GregCr 0:e6ceb13d2d05 337 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 338 }
GregCr 0:e6ceb13d2d05 339 nss = 1;
GregCr 0:e6ceb13d2d05 340 }
GregCr 0:e6ceb13d2d05 341
GregCr 0:e6ceb13d2d05 342 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 343 {
GregCr 0:e6ceb13d2d05 344 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 345 }
GregCr 0:e6ceb13d2d05 346
GregCr 0:e6ceb13d2d05 347 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 348 {
GregCr 0:e6ceb13d2d05 349 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 350 }