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MKL46Z4.h@6:090151fca074, 2016-02-27 (annotated)

Committer:: Piasiv1206
Date:: Sat Feb 27 07:16:16 2016 +0000
Revision:: 6:090151fca074
Parent:: 4:ec3f71ef8732

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User	Revision	Line number	New contents of line
Piasiv1206	4:ec3f71ef8732	1	/*
Piasiv1206	4:ec3f71ef8732	2	** ###################################################################
Piasiv1206	4:ec3f71ef8732	3	** Processors: MKL46Z256VLH4
Piasiv1206	4:ec3f71ef8732	4	** MKL46Z128VLH4
Piasiv1206	4:ec3f71ef8732	5	** MKL46Z256VLL4
Piasiv1206	4:ec3f71ef8732	6	** MKL46Z128VLL4
Piasiv1206	4:ec3f71ef8732	7	** MKL46Z256VMC4
Piasiv1206	4:ec3f71ef8732	8	** MKL46Z128VMC4
Piasiv1206	4:ec3f71ef8732	9	**
Piasiv1206	4:ec3f71ef8732	10	** Compilers: ARM Compiler
Piasiv1206	4:ec3f71ef8732	11	** Freescale C/C++ for Embedded ARM
Piasiv1206	4:ec3f71ef8732	12	** GNU C Compiler
Piasiv1206	4:ec3f71ef8732	13	** IAR ANSI C/C++ Compiler for ARM
Piasiv1206	4:ec3f71ef8732	14	**
Piasiv1206	4:ec3f71ef8732	15	** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
Piasiv1206	4:ec3f71ef8732	16	** Version: rev. 2.2, 2013-04-12
Piasiv1206	4:ec3f71ef8732	17	**
Piasiv1206	4:ec3f71ef8732	18	** Abstract:
Piasiv1206	4:ec3f71ef8732	19	** CMSIS Peripheral Access Layer for MKL46Z4
Piasiv1206	4:ec3f71ef8732	20	**
Piasiv1206	4:ec3f71ef8732	21	** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
Piasiv1206	4:ec3f71ef8732	22	**
Piasiv1206	4:ec3f71ef8732	23	** http: www.freescale.com
Piasiv1206	4:ec3f71ef8732	24	** mail: support@freescale.com
Piasiv1206	4:ec3f71ef8732	25	**
Piasiv1206	4:ec3f71ef8732	26	** Revisions:
Piasiv1206	4:ec3f71ef8732	27	** - rev. 1.0 (2012-10-16)
Piasiv1206	4:ec3f71ef8732	28	** Initial version.
Piasiv1206	4:ec3f71ef8732	29	** - rev. 2.0 (2012-12-12)
Piasiv1206	4:ec3f71ef8732	30	** Update to reference manual rev. 1.
Piasiv1206	4:ec3f71ef8732	31	** - rev. 2.1 (2013-04-05)
Piasiv1206	4:ec3f71ef8732	32	** Changed start of doxygen comment.
Piasiv1206	4:ec3f71ef8732	33	** - rev. 2.2 (2013-04-12)
Piasiv1206	4:ec3f71ef8732	34	** SystemInit function fixed for clock configuration 1.
Piasiv1206	4:ec3f71ef8732	35	** Name of the interrupt num. 31 updated to reflect proper function.
Piasiv1206	4:ec3f71ef8732	36	**
Piasiv1206	4:ec3f71ef8732	37	** ###################################################################
Piasiv1206	4:ec3f71ef8732	38	*/
Piasiv1206	4:ec3f71ef8732	39
Piasiv1206	4:ec3f71ef8732	40	/*!
Piasiv1206	4:ec3f71ef8732	41	* @file MKL46Z4.h
Piasiv1206	4:ec3f71ef8732	42	* @version 2.2
Piasiv1206	4:ec3f71ef8732	43	* @date 2013-04-12
Piasiv1206	4:ec3f71ef8732	44	* @brief CMSIS Peripheral Access Layer for MKL46Z4
Piasiv1206	4:ec3f71ef8732	45	*
Piasiv1206	4:ec3f71ef8732	46	* CMSIS Peripheral Access Layer for MKL46Z4
Piasiv1206	4:ec3f71ef8732	47	*/
Piasiv1206	4:ec3f71ef8732	48
Piasiv1206	4:ec3f71ef8732	49	#if !defined(MKL46Z4_H_)
Piasiv1206	4:ec3f71ef8732	50	#define MKL46Z4_H_ /*< Symbol preventing repeated inclusion /
Piasiv1206	4:ec3f71ef8732	51
Piasiv1206	4:ec3f71ef8732	52	/** Memory map major version (memory maps with equal major version number are
Piasiv1206	4:ec3f71ef8732	53	* compatible) */
Piasiv1206	4:ec3f71ef8732	54	#define MCU_MEM_MAP_VERSION 0x0200u
Piasiv1206	4:ec3f71ef8732	55	/** Memory map minor version */
Piasiv1206	4:ec3f71ef8732	56	#define MCU_MEM_MAP_VERSION_MINOR 0x0002u
Piasiv1206	4:ec3f71ef8732	57
Piasiv1206	4:ec3f71ef8732	58
Piasiv1206	4:ec3f71ef8732	59	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	60	-- Interrupt vector numbers
Piasiv1206	4:ec3f71ef8732	61	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	62
Piasiv1206	4:ec3f71ef8732	63	/*!
Piasiv1206	4:ec3f71ef8732	64	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
Piasiv1206	4:ec3f71ef8732	65	* @{
Piasiv1206	4:ec3f71ef8732	66	*/
Piasiv1206	4:ec3f71ef8732	67
Piasiv1206	4:ec3f71ef8732	68	/** Interrupt Number Definitions */
Piasiv1206	4:ec3f71ef8732	69	typedef enum IRQn {
Piasiv1206	4:ec3f71ef8732	70	/* Core interrupts */
Piasiv1206	4:ec3f71ef8732	71	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
Piasiv1206	4:ec3f71ef8732	72	HardFault_IRQn = -13, /*< Cortex-M0 SV Hard Fault Interrupt /
Piasiv1206	4:ec3f71ef8732	73	SVCall_IRQn = -5, /*< Cortex-M0 SV Call Interrupt /
Piasiv1206	4:ec3f71ef8732	74	PendSV_IRQn = -2, /*< Cortex-M0 Pend SV Interrupt /
Piasiv1206	4:ec3f71ef8732	75	SysTick_IRQn = -1, /*< Cortex-M0 System Tick Interrupt /
Piasiv1206	4:ec3f71ef8732	76
Piasiv1206	4:ec3f71ef8732	77	/* Device specific interrupts */
Piasiv1206	4:ec3f71ef8732	78	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete/error interrupt /
Piasiv1206	4:ec3f71ef8732	79	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete/error interrupt /
Piasiv1206	4:ec3f71ef8732	80	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete/error interrupt /
Piasiv1206	4:ec3f71ef8732	81	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete/error interrupt /
Piasiv1206	4:ec3f71ef8732	82	Reserved20_IRQn = 4, /*< Reserved interrupt 20 /
Piasiv1206	4:ec3f71ef8732	83	FTFA_IRQn = 5, /*< FTFA command complete/read collision interrupt /
Piasiv1206	4:ec3f71ef8732	84	LVD_LVW_IRQn = 6, /*< Low Voltage Detect, Low Voltage Warning /
Piasiv1206	4:ec3f71ef8732	85	LLW_IRQn = 7, /*< Low Leakage Wakeup /
Piasiv1206	4:ec3f71ef8732	86	I2C0_IRQn = 8, /*< I2C0 interrupt /
Piasiv1206	4:ec3f71ef8732	87	I2C1_IRQn = 9, /*< I2C0 interrupt 25 /
Piasiv1206	4:ec3f71ef8732	88	SPI0_IRQn = 10, /*< SPI0 interrupt /
Piasiv1206	4:ec3f71ef8732	89	SPI1_IRQn = 11, /*< SPI1 interrupt /
Piasiv1206	4:ec3f71ef8732	90	UART0_IRQn = 12, /*< UART0 status/error interrupt /
Piasiv1206	4:ec3f71ef8732	91	UART1_IRQn = 13, /*< UART1 status/error interrupt /
Piasiv1206	4:ec3f71ef8732	92	UART2_IRQn = 14, /*< UART2 status/error interrupt /
Piasiv1206	4:ec3f71ef8732	93	ADC0_IRQn = 15, /*< ADC0 interrupt /
Piasiv1206	4:ec3f71ef8732	94	CMP0_IRQn = 16, /*< CMP0 interrupt /
Piasiv1206	4:ec3f71ef8732	95	TPM0_IRQn = 17, /*< TPM0 fault, overflow and channels interrupt /
Piasiv1206	4:ec3f71ef8732	96	TPM1_IRQn = 18, /*< TPM1 fault, overflow and channels interrupt /
Piasiv1206	4:ec3f71ef8732	97	TPM2_IRQn = 19, /*< TPM2 fault, overflow and channels interrupt /
Piasiv1206	4:ec3f71ef8732	98	RTC_IRQn = 20, /*< RTC interrupt /
Piasiv1206	4:ec3f71ef8732	99	RTC_Seconds_IRQn = 21, /*< RTC seconds interrupt /
Piasiv1206	4:ec3f71ef8732	100	PIT_IRQn = 22, /*< PIT timer interrupt /
Piasiv1206	4:ec3f71ef8732	101	I2S0_IRQn = 23, /*< I2S0 transmit interrupt /
Piasiv1206	4:ec3f71ef8732	102	USB0_IRQn = 24, /*< USB0 interrupt /
Piasiv1206	4:ec3f71ef8732	103	DAC0_IRQn = 25, /*< DAC0 interrupt /
Piasiv1206	4:ec3f71ef8732	104	TSI0_IRQn = 26, /*< TSI0 interrupt /
Piasiv1206	4:ec3f71ef8732	105	MCG_IRQn = 27, /*< MCG interrupt /
Piasiv1206	4:ec3f71ef8732	106	LPTimer_IRQn = 28, /*< LPTimer interrupt /
Piasiv1206	4:ec3f71ef8732	107	LCD_IRQn = 29, /*< Segment LCD Interrupt /
Piasiv1206	4:ec3f71ef8732	108	PORTA_IRQn = 30, /*< Port A interrupt /
Piasiv1206	4:ec3f71ef8732	109	PORTC_PORTD_IRQn = 31 /*< Port C and port D interrupt /
Piasiv1206	4:ec3f71ef8732	110	} IRQn_Type;
Piasiv1206	4:ec3f71ef8732	111
Piasiv1206	4:ec3f71ef8732	112	/*!
Piasiv1206	4:ec3f71ef8732	113	* @}
Piasiv1206	4:ec3f71ef8732	114	/ / end of group Interrupt_vector_numbers */
Piasiv1206	4:ec3f71ef8732	115
Piasiv1206	4:ec3f71ef8732	116
Piasiv1206	4:ec3f71ef8732	117	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	118	-- Cortex M0 Core Configuration
Piasiv1206	4:ec3f71ef8732	119	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	120
Piasiv1206	4:ec3f71ef8732	121	/*!
Piasiv1206	4:ec3f71ef8732	122	* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
Piasiv1206	4:ec3f71ef8732	123	* @{
Piasiv1206	4:ec3f71ef8732	124	*/
Piasiv1206	4:ec3f71ef8732	125
Piasiv1206	4:ec3f71ef8732	126	#define __CM0PLUS_REV 0x0000 /*< Core revision r0p0 /
Piasiv1206	4:ec3f71ef8732	127	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
Piasiv1206	4:ec3f71ef8732	128	#define __VTOR_PRESENT 1 /*< Defines if an MPU is present or not /
Piasiv1206	4:ec3f71ef8732	129	#define __NVIC_PRIO_BITS 2 /*< Number of priority bits implemented in the NVIC /
Piasiv1206	4:ec3f71ef8732	130	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
Piasiv1206	4:ec3f71ef8732	131
Piasiv1206	4:ec3f71ef8732	132	#include "core_cm0plus.h" /* Core Peripheral Access Layer */
Piasiv1206	4:ec3f71ef8732	133	#include "system_MKL46Z4.h" /* Device specific configuration file */
Piasiv1206	4:ec3f71ef8732	134
Piasiv1206	4:ec3f71ef8732	135	/*!
Piasiv1206	4:ec3f71ef8732	136	* @}
Piasiv1206	4:ec3f71ef8732	137	/ / end of group Cortex_Core_Configuration */
Piasiv1206	4:ec3f71ef8732	138
Piasiv1206	4:ec3f71ef8732	139
Piasiv1206	4:ec3f71ef8732	140	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	141	-- Device Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	142	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	143
Piasiv1206	4:ec3f71ef8732	144	/*!
Piasiv1206	4:ec3f71ef8732	145	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	146	* @{
Piasiv1206	4:ec3f71ef8732	147	*/
Piasiv1206	4:ec3f71ef8732	148
Piasiv1206	4:ec3f71ef8732	149
Piasiv1206	4:ec3f71ef8732	150	/*
Piasiv1206	4:ec3f71ef8732	151	** Start of section using anonymous unions
Piasiv1206	4:ec3f71ef8732	152	*/
Piasiv1206	4:ec3f71ef8732	153
Piasiv1206	4:ec3f71ef8732	154	#if defined(__ARMCC_VERSION)
Piasiv1206	4:ec3f71ef8732	155	#pragma push
Piasiv1206	4:ec3f71ef8732	156	#pragma anon_unions
Piasiv1206	4:ec3f71ef8732	157	#elif defined(__CWCC__)
Piasiv1206	4:ec3f71ef8732	158	#pragma push
Piasiv1206	4:ec3f71ef8732	159	#pragma cpp_extensions on
Piasiv1206	4:ec3f71ef8732	160	#elif defined(__GNUC__)
Piasiv1206	4:ec3f71ef8732	161	/* anonymous unions are enabled by default */
Piasiv1206	4:ec3f71ef8732	162	#elif defined(__IAR_SYSTEMS_ICC__)
Piasiv1206	4:ec3f71ef8732	163	#pragma language=extended
Piasiv1206	4:ec3f71ef8732	164	#else
Piasiv1206	4:ec3f71ef8732	165	#error Not supported compiler type
Piasiv1206	4:ec3f71ef8732	166	#endif
Piasiv1206	4:ec3f71ef8732	167
Piasiv1206	4:ec3f71ef8732	168	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	169	-- ADC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	170	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	171
Piasiv1206	4:ec3f71ef8732	172	/*!
Piasiv1206	4:ec3f71ef8732	173	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	174	* @{
Piasiv1206	4:ec3f71ef8732	175	*/
Piasiv1206	4:ec3f71ef8732	176
Piasiv1206	4:ec3f71ef8732	177	/** ADC - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	178	typedef struct {
Piasiv1206	4:ec3f71ef8732	179	__IO uint32_t SC1[2]; /*< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	180	__IO uint32_t CFG1; /*< ADC Configuration Register 1, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	181	__IO uint32_t CFG2; /*< ADC Configuration Register 2, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	182	__I uint32_t R[2]; /*< ADC Data Result Register, array offset: 0x10, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	183	__IO uint32_t CV1; /*< Compare Value Registers, offset: 0x18 /
Piasiv1206	4:ec3f71ef8732	184	__IO uint32_t CV2; /*< Compare Value Registers, offset: 0x1C /
Piasiv1206	4:ec3f71ef8732	185	__IO uint32_t SC2; /*< Status and Control Register 2, offset: 0x20 /
Piasiv1206	4:ec3f71ef8732	186	__IO uint32_t SC3; /*< Status and Control Register 3, offset: 0x24 /
Piasiv1206	4:ec3f71ef8732	187	__IO uint32_t OFS; /*< ADC Offset Correction Register, offset: 0x28 /
Piasiv1206	4:ec3f71ef8732	188	__IO uint32_t PG; /*< ADC Plus-Side Gain Register, offset: 0x2C /
Piasiv1206	4:ec3f71ef8732	189	__IO uint32_t MG; /*< ADC Minus-Side Gain Register, offset: 0x30 /
Piasiv1206	4:ec3f71ef8732	190	__IO uint32_t CLPD; /*< ADC Plus-Side General Calibration Value Register, offset: 0x34 /
Piasiv1206	4:ec3f71ef8732	191	__IO uint32_t CLPS; /*< ADC Plus-Side General Calibration Value Register, offset: 0x38 /
Piasiv1206	4:ec3f71ef8732	192	__IO uint32_t CLP4; /*< ADC Plus-Side General Calibration Value Register, offset: 0x3C /
Piasiv1206	4:ec3f71ef8732	193	__IO uint32_t CLP3; /*< ADC Plus-Side General Calibration Value Register, offset: 0x40 /
Piasiv1206	4:ec3f71ef8732	194	__IO uint32_t CLP2; /*< ADC Plus-Side General Calibration Value Register, offset: 0x44 /
Piasiv1206	4:ec3f71ef8732	195	__IO uint32_t CLP1; /*< ADC Plus-Side General Calibration Value Register, offset: 0x48 /
Piasiv1206	4:ec3f71ef8732	196	__IO uint32_t CLP0; /*< ADC Plus-Side General Calibration Value Register, offset: 0x4C /
Piasiv1206	4:ec3f71ef8732	197	uint8_t RESERVED_0[4];
Piasiv1206	4:ec3f71ef8732	198	__IO uint32_t CLMD; /*< ADC Minus-Side General Calibration Value Register, offset: 0x54 /
Piasiv1206	4:ec3f71ef8732	199	__IO uint32_t CLMS; /*< ADC Minus-Side General Calibration Value Register, offset: 0x58 /
Piasiv1206	4:ec3f71ef8732	200	__IO uint32_t CLM4; /*< ADC Minus-Side General Calibration Value Register, offset: 0x5C /
Piasiv1206	4:ec3f71ef8732	201	__IO uint32_t CLM3; /*< ADC Minus-Side General Calibration Value Register, offset: 0x60 /
Piasiv1206	4:ec3f71ef8732	202	__IO uint32_t CLM2; /*< ADC Minus-Side General Calibration Value Register, offset: 0x64 /
Piasiv1206	4:ec3f71ef8732	203	__IO uint32_t CLM1; /*< ADC Minus-Side General Calibration Value Register, offset: 0x68 /
Piasiv1206	4:ec3f71ef8732	204	__IO uint32_t CLM0; /*< ADC Minus-Side General Calibration Value Register, offset: 0x6C /
Piasiv1206	4:ec3f71ef8732	205	} ADC_Type;
Piasiv1206	4:ec3f71ef8732	206
Piasiv1206	4:ec3f71ef8732	207	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	208	-- ADC Register Masks
Piasiv1206	4:ec3f71ef8732	209	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	210
Piasiv1206	4:ec3f71ef8732	211	/*!
Piasiv1206	4:ec3f71ef8732	212	* @addtogroup ADC_Register_Masks ADC Register Masks
Piasiv1206	4:ec3f71ef8732	213	* @{
Piasiv1206	4:ec3f71ef8732	214	*/
Piasiv1206	4:ec3f71ef8732	215
Piasiv1206	4:ec3f71ef8732	216	/* SC1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	217	#define ADC_SC1_ADCH_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	218	#define ADC_SC1_ADCH_SHIFT 0
Piasiv1206	4:ec3f71ef8732	219	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
Piasiv1206	4:ec3f71ef8732	220	#define ADC_SC1_DIFF_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	221	#define ADC_SC1_DIFF_SHIFT 5
Piasiv1206	4:ec3f71ef8732	222	#define ADC_SC1_AIEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	223	#define ADC_SC1_AIEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	224	#define ADC_SC1_COCO_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	225	#define ADC_SC1_COCO_SHIFT 7
Piasiv1206	4:ec3f71ef8732	226	/* CFG1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	227	#define ADC_CFG1_ADICLK_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	228	#define ADC_CFG1_ADICLK_SHIFT 0
Piasiv1206	4:ec3f71ef8732	229	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
Piasiv1206	4:ec3f71ef8732	230	#define ADC_CFG1_MODE_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	231	#define ADC_CFG1_MODE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	232	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
Piasiv1206	4:ec3f71ef8732	233	#define ADC_CFG1_ADLSMP_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	234	#define ADC_CFG1_ADLSMP_SHIFT 4
Piasiv1206	4:ec3f71ef8732	235	#define ADC_CFG1_ADIV_MASK 0x60u
Piasiv1206	4:ec3f71ef8732	236	#define ADC_CFG1_ADIV_SHIFT 5
Piasiv1206	4:ec3f71ef8732	237	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
Piasiv1206	4:ec3f71ef8732	238	#define ADC_CFG1_ADLPC_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	239	#define ADC_CFG1_ADLPC_SHIFT 7
Piasiv1206	4:ec3f71ef8732	240	/* CFG2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	241	#define ADC_CFG2_ADLSTS_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	242	#define ADC_CFG2_ADLSTS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	243	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
Piasiv1206	4:ec3f71ef8732	244	#define ADC_CFG2_ADHSC_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	245	#define ADC_CFG2_ADHSC_SHIFT 2
Piasiv1206	4:ec3f71ef8732	246	#define ADC_CFG2_ADACKEN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	247	#define ADC_CFG2_ADACKEN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	248	#define ADC_CFG2_MUXSEL_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	249	#define ADC_CFG2_MUXSEL_SHIFT 4
Piasiv1206	4:ec3f71ef8732	250	/* R Bit Fields */
Piasiv1206	4:ec3f71ef8732	251	#define ADC_R_D_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	252	#define ADC_R_D_SHIFT 0
Piasiv1206	4:ec3f71ef8732	253	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
Piasiv1206	4:ec3f71ef8732	254	/* CV1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	255	#define ADC_CV1_CV_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	256	#define ADC_CV1_CV_SHIFT 0
Piasiv1206	4:ec3f71ef8732	257	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
Piasiv1206	4:ec3f71ef8732	258	/* CV2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	259	#define ADC_CV2_CV_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	260	#define ADC_CV2_CV_SHIFT 0
Piasiv1206	4:ec3f71ef8732	261	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
Piasiv1206	4:ec3f71ef8732	262	/* SC2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	263	#define ADC_SC2_REFSEL_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	264	#define ADC_SC2_REFSEL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	265	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
Piasiv1206	4:ec3f71ef8732	266	#define ADC_SC2_DMAEN_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	267	#define ADC_SC2_DMAEN_SHIFT 2
Piasiv1206	4:ec3f71ef8732	268	#define ADC_SC2_ACREN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	269	#define ADC_SC2_ACREN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	270	#define ADC_SC2_ACFGT_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	271	#define ADC_SC2_ACFGT_SHIFT 4
Piasiv1206	4:ec3f71ef8732	272	#define ADC_SC2_ACFE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	273	#define ADC_SC2_ACFE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	274	#define ADC_SC2_ADTRG_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	275	#define ADC_SC2_ADTRG_SHIFT 6
Piasiv1206	4:ec3f71ef8732	276	#define ADC_SC2_ADACT_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	277	#define ADC_SC2_ADACT_SHIFT 7
Piasiv1206	4:ec3f71ef8732	278	/* SC3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	279	#define ADC_SC3_AVGS_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	280	#define ADC_SC3_AVGS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	281	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
Piasiv1206	4:ec3f71ef8732	282	#define ADC_SC3_AVGE_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	283	#define ADC_SC3_AVGE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	284	#define ADC_SC3_ADCO_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	285	#define ADC_SC3_ADCO_SHIFT 3
Piasiv1206	4:ec3f71ef8732	286	#define ADC_SC3_CALF_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	287	#define ADC_SC3_CALF_SHIFT 6
Piasiv1206	4:ec3f71ef8732	288	#define ADC_SC3_CAL_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	289	#define ADC_SC3_CAL_SHIFT 7
Piasiv1206	4:ec3f71ef8732	290	/* OFS Bit Fields */
Piasiv1206	4:ec3f71ef8732	291	#define ADC_OFS_OFS_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	292	#define ADC_OFS_OFS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	293	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
Piasiv1206	4:ec3f71ef8732	294	/* PG Bit Fields */
Piasiv1206	4:ec3f71ef8732	295	#define ADC_PG_PG_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	296	#define ADC_PG_PG_SHIFT 0
Piasiv1206	4:ec3f71ef8732	297	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
Piasiv1206	4:ec3f71ef8732	298	/* MG Bit Fields */
Piasiv1206	4:ec3f71ef8732	299	#define ADC_MG_MG_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	300	#define ADC_MG_MG_SHIFT 0
Piasiv1206	4:ec3f71ef8732	301	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
Piasiv1206	4:ec3f71ef8732	302	/* CLPD Bit Fields */
Piasiv1206	4:ec3f71ef8732	303	#define ADC_CLPD_CLPD_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	304	#define ADC_CLPD_CLPD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	305	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
Piasiv1206	4:ec3f71ef8732	306	/* CLPS Bit Fields */
Piasiv1206	4:ec3f71ef8732	307	#define ADC_CLPS_CLPS_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	308	#define ADC_CLPS_CLPS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	309	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
Piasiv1206	4:ec3f71ef8732	310	/* CLP4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	311	#define ADC_CLP4_CLP4_MASK 0x3FFu
Piasiv1206	4:ec3f71ef8732	312	#define ADC_CLP4_CLP4_SHIFT 0
Piasiv1206	4:ec3f71ef8732	313	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
Piasiv1206	4:ec3f71ef8732	314	/* CLP3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	315	#define ADC_CLP3_CLP3_MASK 0x1FFu
Piasiv1206	4:ec3f71ef8732	316	#define ADC_CLP3_CLP3_SHIFT 0
Piasiv1206	4:ec3f71ef8732	317	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
Piasiv1206	4:ec3f71ef8732	318	/* CLP2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	319	#define ADC_CLP2_CLP2_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	320	#define ADC_CLP2_CLP2_SHIFT 0
Piasiv1206	4:ec3f71ef8732	321	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
Piasiv1206	4:ec3f71ef8732	322	/* CLP1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	323	#define ADC_CLP1_CLP1_MASK 0x7Fu
Piasiv1206	4:ec3f71ef8732	324	#define ADC_CLP1_CLP1_SHIFT 0
Piasiv1206	4:ec3f71ef8732	325	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
Piasiv1206	4:ec3f71ef8732	326	/* CLP0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	327	#define ADC_CLP0_CLP0_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	328	#define ADC_CLP0_CLP0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	329	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
Piasiv1206	4:ec3f71ef8732	330	/* CLMD Bit Fields */
Piasiv1206	4:ec3f71ef8732	331	#define ADC_CLMD_CLMD_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	332	#define ADC_CLMD_CLMD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	333	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
Piasiv1206	4:ec3f71ef8732	334	/* CLMS Bit Fields */
Piasiv1206	4:ec3f71ef8732	335	#define ADC_CLMS_CLMS_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	336	#define ADC_CLMS_CLMS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	337	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
Piasiv1206	4:ec3f71ef8732	338	/* CLM4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	339	#define ADC_CLM4_CLM4_MASK 0x3FFu
Piasiv1206	4:ec3f71ef8732	340	#define ADC_CLM4_CLM4_SHIFT 0
Piasiv1206	4:ec3f71ef8732	341	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
Piasiv1206	4:ec3f71ef8732	342	/* CLM3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	343	#define ADC_CLM3_CLM3_MASK 0x1FFu
Piasiv1206	4:ec3f71ef8732	344	#define ADC_CLM3_CLM3_SHIFT 0
Piasiv1206	4:ec3f71ef8732	345	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
Piasiv1206	4:ec3f71ef8732	346	/* CLM2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	347	#define ADC_CLM2_CLM2_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	348	#define ADC_CLM2_CLM2_SHIFT 0
Piasiv1206	4:ec3f71ef8732	349	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
Piasiv1206	4:ec3f71ef8732	350	/* CLM1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	351	#define ADC_CLM1_CLM1_MASK 0x7Fu
Piasiv1206	4:ec3f71ef8732	352	#define ADC_CLM1_CLM1_SHIFT 0
Piasiv1206	4:ec3f71ef8732	353	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
Piasiv1206	4:ec3f71ef8732	354	/* CLM0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	355	#define ADC_CLM0_CLM0_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	356	#define ADC_CLM0_CLM0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	357	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
Piasiv1206	4:ec3f71ef8732	358
Piasiv1206	4:ec3f71ef8732	359	/*!
Piasiv1206	4:ec3f71ef8732	360	* @}
Piasiv1206	4:ec3f71ef8732	361	/ / end of group ADC_Register_Masks */
Piasiv1206	4:ec3f71ef8732	362
Piasiv1206	4:ec3f71ef8732	363
Piasiv1206	4:ec3f71ef8732	364	/* ADC - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	365	/** Peripheral ADC0 base address */
Piasiv1206	4:ec3f71ef8732	366	#define ADC0_BASE (0x4003B000u)
Piasiv1206	4:ec3f71ef8732	367	/** Peripheral ADC0 base pointer */
Piasiv1206	4:ec3f71ef8732	368	#define ADC0 ((ADC_Type *)ADC0_BASE)
Piasiv1206	4:ec3f71ef8732	369	/** Array initializer of ADC peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	370	#define ADC_BASES { ADC0 }
Piasiv1206	4:ec3f71ef8732	371
Piasiv1206	4:ec3f71ef8732	372	/*!
Piasiv1206	4:ec3f71ef8732	373	* @}
Piasiv1206	4:ec3f71ef8732	374	/ / end of group ADC_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	375
Piasiv1206	4:ec3f71ef8732	376
Piasiv1206	4:ec3f71ef8732	377	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	378	-- CMP Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	379	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	380
Piasiv1206	4:ec3f71ef8732	381	/*!
Piasiv1206	4:ec3f71ef8732	382	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	383	* @{
Piasiv1206	4:ec3f71ef8732	384	*/
Piasiv1206	4:ec3f71ef8732	385
Piasiv1206	4:ec3f71ef8732	386	/** CMP - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	387	typedef struct {
Piasiv1206	4:ec3f71ef8732	388	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	389	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	390	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	391	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	392	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	393	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	394	} CMP_Type;
Piasiv1206	4:ec3f71ef8732	395
Piasiv1206	4:ec3f71ef8732	396	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	397	-- CMP Register Masks
Piasiv1206	4:ec3f71ef8732	398	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	399
Piasiv1206	4:ec3f71ef8732	400	/*!
Piasiv1206	4:ec3f71ef8732	401	* @addtogroup CMP_Register_Masks CMP Register Masks
Piasiv1206	4:ec3f71ef8732	402	* @{
Piasiv1206	4:ec3f71ef8732	403	*/
Piasiv1206	4:ec3f71ef8732	404
Piasiv1206	4:ec3f71ef8732	405	/* CR0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	406	#define CMP_CR0_HYSTCTR_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	407	#define CMP_CR0_HYSTCTR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	408	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
Piasiv1206	4:ec3f71ef8732	409	#define CMP_CR0_FILTER_CNT_MASK 0x70u
Piasiv1206	4:ec3f71ef8732	410	#define CMP_CR0_FILTER_CNT_SHIFT 4
Piasiv1206	4:ec3f71ef8732	411	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
Piasiv1206	4:ec3f71ef8732	412	/* CR1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	413	#define CMP_CR1_EN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	414	#define CMP_CR1_EN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	415	#define CMP_CR1_OPE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	416	#define CMP_CR1_OPE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	417	#define CMP_CR1_COS_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	418	#define CMP_CR1_COS_SHIFT 2
Piasiv1206	4:ec3f71ef8732	419	#define CMP_CR1_INV_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	420	#define CMP_CR1_INV_SHIFT 3
Piasiv1206	4:ec3f71ef8732	421	#define CMP_CR1_PMODE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	422	#define CMP_CR1_PMODE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	423	#define CMP_CR1_TRIGM_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	424	#define CMP_CR1_TRIGM_SHIFT 5
Piasiv1206	4:ec3f71ef8732	425	#define CMP_CR1_WE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	426	#define CMP_CR1_WE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	427	#define CMP_CR1_SE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	428	#define CMP_CR1_SE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	429	/* FPR Bit Fields */
Piasiv1206	4:ec3f71ef8732	430	#define CMP_FPR_FILT_PER_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	431	#define CMP_FPR_FILT_PER_SHIFT 0
Piasiv1206	4:ec3f71ef8732	432	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
Piasiv1206	4:ec3f71ef8732	433	/* SCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	434	#define CMP_SCR_COUT_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	435	#define CMP_SCR_COUT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	436	#define CMP_SCR_CFF_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	437	#define CMP_SCR_CFF_SHIFT 1
Piasiv1206	4:ec3f71ef8732	438	#define CMP_SCR_CFR_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	439	#define CMP_SCR_CFR_SHIFT 2
Piasiv1206	4:ec3f71ef8732	440	#define CMP_SCR_IEF_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	441	#define CMP_SCR_IEF_SHIFT 3
Piasiv1206	4:ec3f71ef8732	442	#define CMP_SCR_IER_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	443	#define CMP_SCR_IER_SHIFT 4
Piasiv1206	4:ec3f71ef8732	444	#define CMP_SCR_DMAEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	445	#define CMP_SCR_DMAEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	446	/* DACCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	447	#define CMP_DACCR_VOSEL_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	448	#define CMP_DACCR_VOSEL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	449	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
Piasiv1206	4:ec3f71ef8732	450	#define CMP_DACCR_VRSEL_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	451	#define CMP_DACCR_VRSEL_SHIFT 6
Piasiv1206	4:ec3f71ef8732	452	#define CMP_DACCR_DACEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	453	#define CMP_DACCR_DACEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	454	/* MUXCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	455	#define CMP_MUXCR_MSEL_MASK 0x7u
Piasiv1206	4:ec3f71ef8732	456	#define CMP_MUXCR_MSEL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	457	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
Piasiv1206	4:ec3f71ef8732	458	#define CMP_MUXCR_PSEL_MASK 0x38u
Piasiv1206	4:ec3f71ef8732	459	#define CMP_MUXCR_PSEL_SHIFT 3
Piasiv1206	4:ec3f71ef8732	460	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
Piasiv1206	4:ec3f71ef8732	461	#define CMP_MUXCR_PSTM_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	462	#define CMP_MUXCR_PSTM_SHIFT 7
Piasiv1206	4:ec3f71ef8732	463
Piasiv1206	4:ec3f71ef8732	464	/*!
Piasiv1206	4:ec3f71ef8732	465	* @}
Piasiv1206	4:ec3f71ef8732	466	/ / end of group CMP_Register_Masks */
Piasiv1206	4:ec3f71ef8732	467
Piasiv1206	4:ec3f71ef8732	468
Piasiv1206	4:ec3f71ef8732	469	/* CMP - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	470	/** Peripheral CMP0 base address */
Piasiv1206	4:ec3f71ef8732	471	#define CMP0_BASE (0x40073000u)
Piasiv1206	4:ec3f71ef8732	472	/** Peripheral CMP0 base pointer */
Piasiv1206	4:ec3f71ef8732	473	#define CMP0 ((CMP_Type *)CMP0_BASE)
Piasiv1206	4:ec3f71ef8732	474	/** Array initializer of CMP peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	475	#define CMP_BASES { CMP0 }
Piasiv1206	4:ec3f71ef8732	476
Piasiv1206	4:ec3f71ef8732	477	/*!
Piasiv1206	4:ec3f71ef8732	478	* @}
Piasiv1206	4:ec3f71ef8732	479	/ / end of group CMP_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	480
Piasiv1206	4:ec3f71ef8732	481
Piasiv1206	4:ec3f71ef8732	482	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	483	-- DAC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	484	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	485
Piasiv1206	4:ec3f71ef8732	486	/*!
Piasiv1206	4:ec3f71ef8732	487	* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	488	* @{
Piasiv1206	4:ec3f71ef8732	489	*/
Piasiv1206	4:ec3f71ef8732	490
Piasiv1206	4:ec3f71ef8732	491	/** DAC - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	492	typedef struct {
Piasiv1206	4:ec3f71ef8732	493	struct { /* offset: 0x0, array step: 0x2 */
Piasiv1206	4:ec3f71ef8732	494	__IO uint8_t DATL; /*< DAC Data Low Register, array offset: 0x0, array step: 0x2 /
Piasiv1206	4:ec3f71ef8732	495	__IO uint8_t DATH; /*< DAC Data High Register, array offset: 0x1, array step: 0x2 /
Piasiv1206	4:ec3f71ef8732	496	} DAT[2];
Piasiv1206	4:ec3f71ef8732	497	uint8_t RESERVED_0[28];
Piasiv1206	4:ec3f71ef8732	498	__IO uint8_t SR; /*< DAC Status Register, offset: 0x20 /
Piasiv1206	4:ec3f71ef8732	499	__IO uint8_t C0; /*< DAC Control Register, offset: 0x21 /
Piasiv1206	4:ec3f71ef8732	500	__IO uint8_t C1; /*< DAC Control Register 1, offset: 0x22 /
Piasiv1206	4:ec3f71ef8732	501	__IO uint8_t C2; /*< DAC Control Register 2, offset: 0x23 /
Piasiv1206	4:ec3f71ef8732	502	} DAC_Type;
Piasiv1206	4:ec3f71ef8732	503
Piasiv1206	4:ec3f71ef8732	504	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	505	-- DAC Register Masks
Piasiv1206	4:ec3f71ef8732	506	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	507
Piasiv1206	4:ec3f71ef8732	508	/*!
Piasiv1206	4:ec3f71ef8732	509	* @addtogroup DAC_Register_Masks DAC Register Masks
Piasiv1206	4:ec3f71ef8732	510	* @{
Piasiv1206	4:ec3f71ef8732	511	*/
Piasiv1206	4:ec3f71ef8732	512
Piasiv1206	4:ec3f71ef8732	513	/* DATL Bit Fields */
Piasiv1206	4:ec3f71ef8732	514	#define DAC_DATL_DATA0_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	515	#define DAC_DATL_DATA0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	516	#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
Piasiv1206	4:ec3f71ef8732	517	/* DATH Bit Fields */
Piasiv1206	4:ec3f71ef8732	518	#define DAC_DATH_DATA1_MASK 0xFu
Piasiv1206	4:ec3f71ef8732	519	#define DAC_DATH_DATA1_SHIFT 0
Piasiv1206	4:ec3f71ef8732	520	#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
Piasiv1206	4:ec3f71ef8732	521	/* SR Bit Fields */
Piasiv1206	4:ec3f71ef8732	522	#define DAC_SR_DACBFRPBF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	523	#define DAC_SR_DACBFRPBF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	524	#define DAC_SR_DACBFRPTF_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	525	#define DAC_SR_DACBFRPTF_SHIFT 1
Piasiv1206	4:ec3f71ef8732	526	/* C0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	527	#define DAC_C0_DACBBIEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	528	#define DAC_C0_DACBBIEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	529	#define DAC_C0_DACBTIEN_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	530	#define DAC_C0_DACBTIEN_SHIFT 1
Piasiv1206	4:ec3f71ef8732	531	#define DAC_C0_LPEN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	532	#define DAC_C0_LPEN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	533	#define DAC_C0_DACSWTRG_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	534	#define DAC_C0_DACSWTRG_SHIFT 4
Piasiv1206	4:ec3f71ef8732	535	#define DAC_C0_DACTRGSEL_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	536	#define DAC_C0_DACTRGSEL_SHIFT 5
Piasiv1206	4:ec3f71ef8732	537	#define DAC_C0_DACRFS_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	538	#define DAC_C0_DACRFS_SHIFT 6
Piasiv1206	4:ec3f71ef8732	539	#define DAC_C0_DACEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	540	#define DAC_C0_DACEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	541	/* C1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	542	#define DAC_C1_DACBFEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	543	#define DAC_C1_DACBFEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	544	#define DAC_C1_DACBFMD_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	545	#define DAC_C1_DACBFMD_SHIFT 2
Piasiv1206	4:ec3f71ef8732	546	#define DAC_C1_DMAEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	547	#define DAC_C1_DMAEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	548	/* C2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	549	#define DAC_C2_DACBFUP_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	550	#define DAC_C2_DACBFUP_SHIFT 0
Piasiv1206	4:ec3f71ef8732	551	#define DAC_C2_DACBFRP_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	552	#define DAC_C2_DACBFRP_SHIFT 4
Piasiv1206	4:ec3f71ef8732	553
Piasiv1206	4:ec3f71ef8732	554	/*!
Piasiv1206	4:ec3f71ef8732	555	* @}
Piasiv1206	4:ec3f71ef8732	556	/ / end of group DAC_Register_Masks */
Piasiv1206	4:ec3f71ef8732	557
Piasiv1206	4:ec3f71ef8732	558
Piasiv1206	4:ec3f71ef8732	559	/* DAC - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	560	/** Peripheral DAC0 base address */
Piasiv1206	4:ec3f71ef8732	561	#define DAC0_BASE (0x4003F000u)
Piasiv1206	4:ec3f71ef8732	562	/** Peripheral DAC0 base pointer */
Piasiv1206	4:ec3f71ef8732	563	#define DAC0 ((DAC_Type *)DAC0_BASE)
Piasiv1206	4:ec3f71ef8732	564	/** Array initializer of DAC peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	565	#define DAC_BASES { DAC0 }
Piasiv1206	4:ec3f71ef8732	566
Piasiv1206	4:ec3f71ef8732	567	/*!
Piasiv1206	4:ec3f71ef8732	568	* @}
Piasiv1206	4:ec3f71ef8732	569	/ / end of group DAC_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	570
Piasiv1206	4:ec3f71ef8732	571
Piasiv1206	4:ec3f71ef8732	572	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	573	-- DMA Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	574	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	575
Piasiv1206	4:ec3f71ef8732	576	/*!
Piasiv1206	4:ec3f71ef8732	577	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	578	* @{
Piasiv1206	4:ec3f71ef8732	579	*/
Piasiv1206	4:ec3f71ef8732	580
Piasiv1206	4:ec3f71ef8732	581	/** DMA - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	582	typedef struct {
Piasiv1206	4:ec3f71ef8732	583	uint8_t RESERVED_0[256];
Piasiv1206	4:ec3f71ef8732	584	struct { /* offset: 0x100, array step: 0x10 */
Piasiv1206	4:ec3f71ef8732	585	__IO uint32_t SAR; /*< Source Address Register, array offset: 0x100, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	586	__IO uint32_t DAR; /*< Destination Address Register, array offset: 0x104, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	587	union { /* offset: 0x108, array step: 0x10 */
Piasiv1206	4:ec3f71ef8732	588	__IO uint32_t DSR_BCR; /*< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	589	struct { /* offset: 0x108, array step: 0x10 */
Piasiv1206	4:ec3f71ef8732	590	uint8_t RESERVED_0[3];
Piasiv1206	4:ec3f71ef8732	591	__IO uint8_t DSR; /*< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	592	} DMA_DSR_ACCESS8BIT;
Piasiv1206	4:ec3f71ef8732	593	};
Piasiv1206	4:ec3f71ef8732	594	__IO uint32_t DCR; /*< DMA Control Register, array offset: 0x10C, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	595	} DMA[4];
Piasiv1206	4:ec3f71ef8732	596	} DMA_Type;
Piasiv1206	4:ec3f71ef8732	597
Piasiv1206	4:ec3f71ef8732	598	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	599	-- DMA Register Masks
Piasiv1206	4:ec3f71ef8732	600	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	601
Piasiv1206	4:ec3f71ef8732	602	/*!
Piasiv1206	4:ec3f71ef8732	603	* @addtogroup DMA_Register_Masks DMA Register Masks
Piasiv1206	4:ec3f71ef8732	604	* @{
Piasiv1206	4:ec3f71ef8732	605	*/
Piasiv1206	4:ec3f71ef8732	606
Piasiv1206	4:ec3f71ef8732	607	/* SAR Bit Fields */
Piasiv1206	4:ec3f71ef8732	608	#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	609	#define DMA_SAR_SAR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	610	#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
Piasiv1206	4:ec3f71ef8732	611	/* DAR Bit Fields */
Piasiv1206	4:ec3f71ef8732	612	#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	613	#define DMA_DAR_DAR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	614	#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
Piasiv1206	4:ec3f71ef8732	615	/* DSR_BCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	616	#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
Piasiv1206	4:ec3f71ef8732	617	#define DMA_DSR_BCR_BCR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	618	#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
Piasiv1206	4:ec3f71ef8732	619	#define DMA_DSR_BCR_DONE_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	620	#define DMA_DSR_BCR_DONE_SHIFT 24
Piasiv1206	4:ec3f71ef8732	621	#define DMA_DSR_BCR_BSY_MASK 0x2000000u
Piasiv1206	4:ec3f71ef8732	622	#define DMA_DSR_BCR_BSY_SHIFT 25
Piasiv1206	4:ec3f71ef8732	623	#define DMA_DSR_BCR_REQ_MASK 0x4000000u
Piasiv1206	4:ec3f71ef8732	624	#define DMA_DSR_BCR_REQ_SHIFT 26
Piasiv1206	4:ec3f71ef8732	625	#define DMA_DSR_BCR_BED_MASK 0x10000000u
Piasiv1206	4:ec3f71ef8732	626	#define DMA_DSR_BCR_BED_SHIFT 28
Piasiv1206	4:ec3f71ef8732	627	#define DMA_DSR_BCR_BES_MASK 0x20000000u
Piasiv1206	4:ec3f71ef8732	628	#define DMA_DSR_BCR_BES_SHIFT 29
Piasiv1206	4:ec3f71ef8732	629	#define DMA_DSR_BCR_CE_MASK 0x40000000u
Piasiv1206	4:ec3f71ef8732	630	#define DMA_DSR_BCR_CE_SHIFT 30
Piasiv1206	4:ec3f71ef8732	631	/* DCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	632	#define DMA_DCR_LCH2_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	633	#define DMA_DCR_LCH2_SHIFT 0
Piasiv1206	4:ec3f71ef8732	634	#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
Piasiv1206	4:ec3f71ef8732	635	#define DMA_DCR_LCH1_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	636	#define DMA_DCR_LCH1_SHIFT 2
Piasiv1206	4:ec3f71ef8732	637	#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
Piasiv1206	4:ec3f71ef8732	638	#define DMA_DCR_LINKCC_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	639	#define DMA_DCR_LINKCC_SHIFT 4
Piasiv1206	4:ec3f71ef8732	640	#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
Piasiv1206	4:ec3f71ef8732	641	#define DMA_DCR_D_REQ_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	642	#define DMA_DCR_D_REQ_SHIFT 7
Piasiv1206	4:ec3f71ef8732	643	#define DMA_DCR_DMOD_MASK 0xF00u
Piasiv1206	4:ec3f71ef8732	644	#define DMA_DCR_DMOD_SHIFT 8
Piasiv1206	4:ec3f71ef8732	645	#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
Piasiv1206	4:ec3f71ef8732	646	#define DMA_DCR_SMOD_MASK 0xF000u
Piasiv1206	4:ec3f71ef8732	647	#define DMA_DCR_SMOD_SHIFT 12
Piasiv1206	4:ec3f71ef8732	648	#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
Piasiv1206	4:ec3f71ef8732	649	#define DMA_DCR_START_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	650	#define DMA_DCR_START_SHIFT 16
Piasiv1206	4:ec3f71ef8732	651	#define DMA_DCR_DSIZE_MASK 0x60000u
Piasiv1206	4:ec3f71ef8732	652	#define DMA_DCR_DSIZE_SHIFT 17
Piasiv1206	4:ec3f71ef8732	653	#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
Piasiv1206	4:ec3f71ef8732	654	#define DMA_DCR_DINC_MASK 0x80000u
Piasiv1206	4:ec3f71ef8732	655	#define DMA_DCR_DINC_SHIFT 19
Piasiv1206	4:ec3f71ef8732	656	#define DMA_DCR_SSIZE_MASK 0x300000u
Piasiv1206	4:ec3f71ef8732	657	#define DMA_DCR_SSIZE_SHIFT 20
Piasiv1206	4:ec3f71ef8732	658	#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
Piasiv1206	4:ec3f71ef8732	659	#define DMA_DCR_SINC_MASK 0x400000u
Piasiv1206	4:ec3f71ef8732	660	#define DMA_DCR_SINC_SHIFT 22
Piasiv1206	4:ec3f71ef8732	661	#define DMA_DCR_EADREQ_MASK 0x800000u
Piasiv1206	4:ec3f71ef8732	662	#define DMA_DCR_EADREQ_SHIFT 23
Piasiv1206	4:ec3f71ef8732	663	#define DMA_DCR_AA_MASK 0x10000000u
Piasiv1206	4:ec3f71ef8732	664	#define DMA_DCR_AA_SHIFT 28
Piasiv1206	4:ec3f71ef8732	665	#define DMA_DCR_CS_MASK 0x20000000u
Piasiv1206	4:ec3f71ef8732	666	#define DMA_DCR_CS_SHIFT 29
Piasiv1206	4:ec3f71ef8732	667	#define DMA_DCR_ERQ_MASK 0x40000000u
Piasiv1206	4:ec3f71ef8732	668	#define DMA_DCR_ERQ_SHIFT 30
Piasiv1206	4:ec3f71ef8732	669	#define DMA_DCR_EINT_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	670	#define DMA_DCR_EINT_SHIFT 31
Piasiv1206	4:ec3f71ef8732	671
Piasiv1206	4:ec3f71ef8732	672	/*!
Piasiv1206	4:ec3f71ef8732	673	* @}
Piasiv1206	4:ec3f71ef8732	674	/ / end of group DMA_Register_Masks */
Piasiv1206	4:ec3f71ef8732	675
Piasiv1206	4:ec3f71ef8732	676
Piasiv1206	4:ec3f71ef8732	677	/* DMA - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	678	/** Peripheral DMA base address */
Piasiv1206	4:ec3f71ef8732	679	#define DMA_BASE (0x40008000u)
Piasiv1206	4:ec3f71ef8732	680	/** Peripheral DMA base pointer */
Piasiv1206	4:ec3f71ef8732	681	#define DMA0 ((DMA_Type *)DMA_BASE)
Piasiv1206	4:ec3f71ef8732	682	/** Array initializer of DMA peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	683	#define DMA_BASES { DMA0 }
Piasiv1206	4:ec3f71ef8732	684
Piasiv1206	4:ec3f71ef8732	685	/*!
Piasiv1206	4:ec3f71ef8732	686	* @}
Piasiv1206	4:ec3f71ef8732	687	/ / end of group DMA_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	688
Piasiv1206	4:ec3f71ef8732	689
Piasiv1206	4:ec3f71ef8732	690	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	691	-- DMAMUX Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	692	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	693
Piasiv1206	4:ec3f71ef8732	694	/*!
Piasiv1206	4:ec3f71ef8732	695	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	696	* @{
Piasiv1206	4:ec3f71ef8732	697	*/
Piasiv1206	4:ec3f71ef8732	698
Piasiv1206	4:ec3f71ef8732	699	/** DMAMUX - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	700	typedef struct {
Piasiv1206	4:ec3f71ef8732	701	__IO uint8_t CHCFG[4]; /*< Channel Configuration register, array offset: 0x0, array step: 0x1 /
Piasiv1206	4:ec3f71ef8732	702	} DMAMUX_Type;
Piasiv1206	4:ec3f71ef8732	703
Piasiv1206	4:ec3f71ef8732	704	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	705	-- DMAMUX Register Masks
Piasiv1206	4:ec3f71ef8732	706	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	707
Piasiv1206	4:ec3f71ef8732	708	/*!
Piasiv1206	4:ec3f71ef8732	709	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
Piasiv1206	4:ec3f71ef8732	710	* @{
Piasiv1206	4:ec3f71ef8732	711	*/
Piasiv1206	4:ec3f71ef8732	712
Piasiv1206	4:ec3f71ef8732	713	/* CHCFG Bit Fields */
Piasiv1206	4:ec3f71ef8732	714	#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	715	#define DMAMUX_CHCFG_SOURCE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	716	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
Piasiv1206	4:ec3f71ef8732	717	#define DMAMUX_CHCFG_TRIG_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	718	#define DMAMUX_CHCFG_TRIG_SHIFT 6
Piasiv1206	4:ec3f71ef8732	719	#define DMAMUX_CHCFG_ENBL_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	720	#define DMAMUX_CHCFG_ENBL_SHIFT 7
Piasiv1206	4:ec3f71ef8732	721
Piasiv1206	4:ec3f71ef8732	722	/*!
Piasiv1206	4:ec3f71ef8732	723	* @}
Piasiv1206	4:ec3f71ef8732	724	/ / end of group DMAMUX_Register_Masks */
Piasiv1206	4:ec3f71ef8732	725
Piasiv1206	4:ec3f71ef8732	726
Piasiv1206	4:ec3f71ef8732	727	/* DMAMUX - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	728	/** Peripheral DMAMUX0 base address */
Piasiv1206	4:ec3f71ef8732	729	#define DMAMUX0_BASE (0x40021000u)
Piasiv1206	4:ec3f71ef8732	730	/** Peripheral DMAMUX0 base pointer */
Piasiv1206	4:ec3f71ef8732	731	#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
Piasiv1206	4:ec3f71ef8732	732	/** Array initializer of DMAMUX peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	733	#define DMAMUX_BASES { DMAMUX0 }
Piasiv1206	4:ec3f71ef8732	734
Piasiv1206	4:ec3f71ef8732	735	/*!
Piasiv1206	4:ec3f71ef8732	736	* @}
Piasiv1206	4:ec3f71ef8732	737	/ / end of group DMAMUX_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	738
Piasiv1206	4:ec3f71ef8732	739
Piasiv1206	4:ec3f71ef8732	740	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	741	-- FGPIO Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	742	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	743
Piasiv1206	4:ec3f71ef8732	744	/*!
Piasiv1206	4:ec3f71ef8732	745	* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	746	* @{
Piasiv1206	4:ec3f71ef8732	747	*/
Piasiv1206	4:ec3f71ef8732	748
Piasiv1206	4:ec3f71ef8732	749	/** FGPIO - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	750	typedef struct {
Piasiv1206	4:ec3f71ef8732	751	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	752	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	753	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	754	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	755	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
Piasiv1206	4:ec3f71ef8732	756	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
Piasiv1206	4:ec3f71ef8732	757	} FGPIO_Type;
Piasiv1206	4:ec3f71ef8732	758
Piasiv1206	4:ec3f71ef8732	759	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	760	-- FGPIO Register Masks
Piasiv1206	4:ec3f71ef8732	761	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	762
Piasiv1206	4:ec3f71ef8732	763	/*!
Piasiv1206	4:ec3f71ef8732	764	* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
Piasiv1206	4:ec3f71ef8732	765	* @{
Piasiv1206	4:ec3f71ef8732	766	*/
Piasiv1206	4:ec3f71ef8732	767
Piasiv1206	4:ec3f71ef8732	768	/* PDOR Bit Fields */
Piasiv1206	4:ec3f71ef8732	769	#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	770	#define FGPIO_PDOR_PDO_SHIFT 0
Piasiv1206	4:ec3f71ef8732	771	#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
Piasiv1206	4:ec3f71ef8732	772	/* PSOR Bit Fields */
Piasiv1206	4:ec3f71ef8732	773	#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	774	#define FGPIO_PSOR_PTSO_SHIFT 0
Piasiv1206	4:ec3f71ef8732	775	#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
Piasiv1206	4:ec3f71ef8732	776	/* PCOR Bit Fields */
Piasiv1206	4:ec3f71ef8732	777	#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	778	#define FGPIO_PCOR_PTCO_SHIFT 0
Piasiv1206	4:ec3f71ef8732	779	#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
Piasiv1206	4:ec3f71ef8732	780	/* PTOR Bit Fields */
Piasiv1206	4:ec3f71ef8732	781	#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	782	#define FGPIO_PTOR_PTTO_SHIFT 0
Piasiv1206	4:ec3f71ef8732	783	#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
Piasiv1206	4:ec3f71ef8732	784	/* PDIR Bit Fields */
Piasiv1206	4:ec3f71ef8732	785	#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	786	#define FGPIO_PDIR_PDI_SHIFT 0
Piasiv1206	4:ec3f71ef8732	787	#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
Piasiv1206	4:ec3f71ef8732	788	/* PDDR Bit Fields */
Piasiv1206	4:ec3f71ef8732	789	#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	790	#define FGPIO_PDDR_PDD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	791	#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
Piasiv1206	4:ec3f71ef8732	792
Piasiv1206	4:ec3f71ef8732	793	/*!
Piasiv1206	4:ec3f71ef8732	794	* @}
Piasiv1206	4:ec3f71ef8732	795	/ / end of group FGPIO_Register_Masks */
Piasiv1206	4:ec3f71ef8732	796
Piasiv1206	4:ec3f71ef8732	797
Piasiv1206	4:ec3f71ef8732	798	/* FGPIO - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	799	/** Peripheral FPTA base address */
Piasiv1206	4:ec3f71ef8732	800	#define FPTA_BASE (0xF80FF000u)
Piasiv1206	4:ec3f71ef8732	801	/** Peripheral FPTA base pointer */
Piasiv1206	4:ec3f71ef8732	802	#define FPTA ((FGPIO_Type *)FPTA_BASE)
Piasiv1206	4:ec3f71ef8732	803	/** Peripheral FPTB base address */
Piasiv1206	4:ec3f71ef8732	804	#define FPTB_BASE (0xF80FF040u)
Piasiv1206	4:ec3f71ef8732	805	/** Peripheral FPTB base pointer */
Piasiv1206	4:ec3f71ef8732	806	#define FPTB ((FGPIO_Type *)FPTB_BASE)
Piasiv1206	4:ec3f71ef8732	807	/** Peripheral FPTC base address */
Piasiv1206	4:ec3f71ef8732	808	#define FPTC_BASE (0xF80FF080u)
Piasiv1206	4:ec3f71ef8732	809	/** Peripheral FPTC base pointer */
Piasiv1206	4:ec3f71ef8732	810	#define FPTC ((FGPIO_Type *)FPTC_BASE)
Piasiv1206	4:ec3f71ef8732	811	/** Peripheral FPTD base address */
Piasiv1206	4:ec3f71ef8732	812	#define FPTD_BASE (0xF80FF0C0u)
Piasiv1206	4:ec3f71ef8732	813	/** Peripheral FPTD base pointer */
Piasiv1206	4:ec3f71ef8732	814	#define FPTD ((FGPIO_Type *)FPTD_BASE)
Piasiv1206	4:ec3f71ef8732	815	/** Peripheral FPTE base address */
Piasiv1206	4:ec3f71ef8732	816	#define FPTE_BASE (0xF80FF100u)
Piasiv1206	4:ec3f71ef8732	817	/** Peripheral FPTE base pointer */
Piasiv1206	4:ec3f71ef8732	818	#define FPTE ((FGPIO_Type *)FPTE_BASE)
Piasiv1206	4:ec3f71ef8732	819	/** Array initializer of FGPIO peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	820	#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
Piasiv1206	4:ec3f71ef8732	821
Piasiv1206	4:ec3f71ef8732	822	/*!
Piasiv1206	4:ec3f71ef8732	823	* @}
Piasiv1206	4:ec3f71ef8732	824	/ / end of group FGPIO_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	825
Piasiv1206	4:ec3f71ef8732	826
Piasiv1206	4:ec3f71ef8732	827	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	828	-- FTFA Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	829	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	830
Piasiv1206	4:ec3f71ef8732	831	/*!
Piasiv1206	4:ec3f71ef8732	832	* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	833	* @{
Piasiv1206	4:ec3f71ef8732	834	*/
Piasiv1206	4:ec3f71ef8732	835
Piasiv1206	4:ec3f71ef8732	836	/** FTFA - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	837	typedef struct {
Piasiv1206	4:ec3f71ef8732	838	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	839	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	840	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	841	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	842	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	843	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	844	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
Piasiv1206	4:ec3f71ef8732	845	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
Piasiv1206	4:ec3f71ef8732	846	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	847	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
Piasiv1206	4:ec3f71ef8732	848	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
Piasiv1206	4:ec3f71ef8732	849	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
Piasiv1206	4:ec3f71ef8732	850	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	851	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
Piasiv1206	4:ec3f71ef8732	852	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
Piasiv1206	4:ec3f71ef8732	853	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
Piasiv1206	4:ec3f71ef8732	854	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
Piasiv1206	4:ec3f71ef8732	855	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
Piasiv1206	4:ec3f71ef8732	856	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
Piasiv1206	4:ec3f71ef8732	857	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
Piasiv1206	4:ec3f71ef8732	858	} FTFA_Type;
Piasiv1206	4:ec3f71ef8732	859
Piasiv1206	4:ec3f71ef8732	860	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	861	-- FTFA Register Masks
Piasiv1206	4:ec3f71ef8732	862	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	863
Piasiv1206	4:ec3f71ef8732	864	/*!
Piasiv1206	4:ec3f71ef8732	865	* @addtogroup FTFA_Register_Masks FTFA Register Masks
Piasiv1206	4:ec3f71ef8732	866	* @{
Piasiv1206	4:ec3f71ef8732	867	*/
Piasiv1206	4:ec3f71ef8732	868
Piasiv1206	4:ec3f71ef8732	869	/* FSTAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	870	#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	871	#define FTFA_FSTAT_MGSTAT0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	872	#define FTFA_FSTAT_FPVIOL_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	873	#define FTFA_FSTAT_FPVIOL_SHIFT 4
Piasiv1206	4:ec3f71ef8732	874	#define FTFA_FSTAT_ACCERR_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	875	#define FTFA_FSTAT_ACCERR_SHIFT 5
Piasiv1206	4:ec3f71ef8732	876	#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	877	#define FTFA_FSTAT_RDCOLERR_SHIFT 6
Piasiv1206	4:ec3f71ef8732	878	#define FTFA_FSTAT_CCIF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	879	#define FTFA_FSTAT_CCIF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	880	/* FCNFG Bit Fields */
Piasiv1206	4:ec3f71ef8732	881	#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	882	#define FTFA_FCNFG_ERSSUSP_SHIFT 4
Piasiv1206	4:ec3f71ef8732	883	#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	884	#define FTFA_FCNFG_ERSAREQ_SHIFT 5
Piasiv1206	4:ec3f71ef8732	885	#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	886	#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	887	#define FTFA_FCNFG_CCIE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	888	#define FTFA_FCNFG_CCIE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	889	/* FSEC Bit Fields */
Piasiv1206	4:ec3f71ef8732	890	#define FTFA_FSEC_SEC_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	891	#define FTFA_FSEC_SEC_SHIFT 0
Piasiv1206	4:ec3f71ef8732	892	#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
Piasiv1206	4:ec3f71ef8732	893	#define FTFA_FSEC_FSLACC_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	894	#define FTFA_FSEC_FSLACC_SHIFT 2
Piasiv1206	4:ec3f71ef8732	895	#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
Piasiv1206	4:ec3f71ef8732	896	#define FTFA_FSEC_MEEN_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	897	#define FTFA_FSEC_MEEN_SHIFT 4
Piasiv1206	4:ec3f71ef8732	898	#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
Piasiv1206	4:ec3f71ef8732	899	#define FTFA_FSEC_KEYEN_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	900	#define FTFA_FSEC_KEYEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	901	#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
Piasiv1206	4:ec3f71ef8732	902	/* FOPT Bit Fields */
Piasiv1206	4:ec3f71ef8732	903	#define FTFA_FOPT_OPT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	904	#define FTFA_FOPT_OPT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	905	#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
Piasiv1206	4:ec3f71ef8732	906	/* FCCOB3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	907	#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	908	#define FTFA_FCCOB3_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	909	#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	910	/* FCCOB2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	911	#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	912	#define FTFA_FCCOB2_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	913	#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	914	/* FCCOB1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	915	#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	916	#define FTFA_FCCOB1_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	917	#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	918	/* FCCOB0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	919	#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	920	#define FTFA_FCCOB0_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	921	#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	922	/* FCCOB7 Bit Fields */
Piasiv1206	4:ec3f71ef8732	923	#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	924	#define FTFA_FCCOB7_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	925	#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	926	/* FCCOB6 Bit Fields */
Piasiv1206	4:ec3f71ef8732	927	#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	928	#define FTFA_FCCOB6_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	929	#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	930	/* FCCOB5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	931	#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	932	#define FTFA_FCCOB5_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	933	#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	934	/* FCCOB4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	935	#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	936	#define FTFA_FCCOB4_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	937	#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	938	/* FCCOBB Bit Fields */
Piasiv1206	4:ec3f71ef8732	939	#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	940	#define FTFA_FCCOBB_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	941	#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	942	/* FCCOBA Bit Fields */
Piasiv1206	4:ec3f71ef8732	943	#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	944	#define FTFA_FCCOBA_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	945	#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	946	/* FCCOB9 Bit Fields */
Piasiv1206	4:ec3f71ef8732	947	#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	948	#define FTFA_FCCOB9_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	949	#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	950	/* FCCOB8 Bit Fields */
Piasiv1206	4:ec3f71ef8732	951	#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	952	#define FTFA_FCCOB8_CCOBn_SHIFT 0
Piasiv1206	4:ec3f71ef8732	953	#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
Piasiv1206	4:ec3f71ef8732	954	/* FPROT3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	955	#define FTFA_FPROT3_PROT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	956	#define FTFA_FPROT3_PROT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	957	#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
Piasiv1206	4:ec3f71ef8732	958	/* FPROT2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	959	#define FTFA_FPROT2_PROT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	960	#define FTFA_FPROT2_PROT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	961	#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
Piasiv1206	4:ec3f71ef8732	962	/* FPROT1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	963	#define FTFA_FPROT1_PROT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	964	#define FTFA_FPROT1_PROT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	965	#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
Piasiv1206	4:ec3f71ef8732	966	/* FPROT0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	967	#define FTFA_FPROT0_PROT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	968	#define FTFA_FPROT0_PROT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	969	#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
Piasiv1206	4:ec3f71ef8732	970
Piasiv1206	4:ec3f71ef8732	971	/*!
Piasiv1206	4:ec3f71ef8732	972	* @}
Piasiv1206	4:ec3f71ef8732	973	/ / end of group FTFA_Register_Masks */
Piasiv1206	4:ec3f71ef8732	974
Piasiv1206	4:ec3f71ef8732	975
Piasiv1206	4:ec3f71ef8732	976	/* FTFA - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	977	/** Peripheral FTFA base address */
Piasiv1206	4:ec3f71ef8732	978	#define FTFA_BASE (0x40020000u)
Piasiv1206	4:ec3f71ef8732	979	/** Peripheral FTFA base pointer */
Piasiv1206	4:ec3f71ef8732	980	#define FTFA ((FTFA_Type *)FTFA_BASE)
Piasiv1206	4:ec3f71ef8732	981	/** Array initializer of FTFA peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	982	#define FTFA_BASES { FTFA }
Piasiv1206	4:ec3f71ef8732	983
Piasiv1206	4:ec3f71ef8732	984	/*!
Piasiv1206	4:ec3f71ef8732	985	* @}
Piasiv1206	4:ec3f71ef8732	986	/ / end of group FTFA_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	987
Piasiv1206	4:ec3f71ef8732	988
Piasiv1206	4:ec3f71ef8732	989	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	990	-- GPIO Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	991	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	992
Piasiv1206	4:ec3f71ef8732	993	/*!
Piasiv1206	4:ec3f71ef8732	994	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	995	* @{
Piasiv1206	4:ec3f71ef8732	996	*/
Piasiv1206	4:ec3f71ef8732	997
Piasiv1206	4:ec3f71ef8732	998	/** GPIO - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	999	typedef struct {
Piasiv1206	4:ec3f71ef8732	1000	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	1001	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	1002	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	1003	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	1004	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
Piasiv1206	4:ec3f71ef8732	1005	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
Piasiv1206	4:ec3f71ef8732	1006	} GPIO_Type;
Piasiv1206	4:ec3f71ef8732	1007
Piasiv1206	4:ec3f71ef8732	1008	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	1009	-- GPIO Register Masks
Piasiv1206	4:ec3f71ef8732	1010	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	1011
Piasiv1206	4:ec3f71ef8732	1012	/*!
Piasiv1206	4:ec3f71ef8732	1013	* @addtogroup GPIO_Register_Masks GPIO Register Masks
Piasiv1206	4:ec3f71ef8732	1014	* @{
Piasiv1206	4:ec3f71ef8732	1015	*/
Piasiv1206	4:ec3f71ef8732	1016
Piasiv1206	4:ec3f71ef8732	1017	/* PDOR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1018	#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1019	#define GPIO_PDOR_PDO_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1020	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
Piasiv1206	4:ec3f71ef8732	1021	/* PSOR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1022	#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1023	#define GPIO_PSOR_PTSO_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1024	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
Piasiv1206	4:ec3f71ef8732	1025	/* PCOR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1026	#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1027	#define GPIO_PCOR_PTCO_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1028	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
Piasiv1206	4:ec3f71ef8732	1029	/* PTOR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1030	#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1031	#define GPIO_PTOR_PTTO_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1032	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
Piasiv1206	4:ec3f71ef8732	1033	/* PDIR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1034	#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1035	#define GPIO_PDIR_PDI_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1036	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
Piasiv1206	4:ec3f71ef8732	1037	/* PDDR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1038	#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1039	#define GPIO_PDDR_PDD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1040	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
Piasiv1206	4:ec3f71ef8732	1041
Piasiv1206	4:ec3f71ef8732	1042	/*!
Piasiv1206	4:ec3f71ef8732	1043	* @}
Piasiv1206	4:ec3f71ef8732	1044	/ / end of group GPIO_Register_Masks */
Piasiv1206	4:ec3f71ef8732	1045
Piasiv1206	4:ec3f71ef8732	1046
Piasiv1206	4:ec3f71ef8732	1047	/* GPIO - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	1048	/** Peripheral PTA base address */
Piasiv1206	4:ec3f71ef8732	1049	#define PTA_BASE (0x400FF000u)
Piasiv1206	4:ec3f71ef8732	1050	/** Peripheral PTA base pointer */
Piasiv1206	4:ec3f71ef8732	1051	#define PTA ((GPIO_Type *)PTA_BASE)
Piasiv1206	4:ec3f71ef8732	1052	/** Peripheral PTB base address */
Piasiv1206	4:ec3f71ef8732	1053	#define PTB_BASE (0x400FF040u)
Piasiv1206	4:ec3f71ef8732	1054	/** Peripheral PTB base pointer */
Piasiv1206	4:ec3f71ef8732	1055	#define PTB ((GPIO_Type *)PTB_BASE)
Piasiv1206	4:ec3f71ef8732	1056	/** Peripheral PTC base address */
Piasiv1206	4:ec3f71ef8732	1057	#define PTC_BASE (0x400FF080u)
Piasiv1206	4:ec3f71ef8732	1058	/** Peripheral PTC base pointer */
Piasiv1206	4:ec3f71ef8732	1059	#define PTC ((GPIO_Type *)PTC_BASE)
Piasiv1206	4:ec3f71ef8732	1060	/** Peripheral PTD base address */
Piasiv1206	4:ec3f71ef8732	1061	#define PTD_BASE (0x400FF0C0u)
Piasiv1206	4:ec3f71ef8732	1062	/** Peripheral PTD base pointer */
Piasiv1206	4:ec3f71ef8732	1063	#define PTD ((GPIO_Type *)PTD_BASE)
Piasiv1206	4:ec3f71ef8732	1064	/** Peripheral PTE base address */
Piasiv1206	4:ec3f71ef8732	1065	#define PTE_BASE (0x400FF100u)
Piasiv1206	4:ec3f71ef8732	1066	/** Peripheral PTE base pointer */
Piasiv1206	4:ec3f71ef8732	1067	#define PTE ((GPIO_Type *)PTE_BASE)
Piasiv1206	4:ec3f71ef8732	1068	/** Array initializer of GPIO peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	1069	#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
Piasiv1206	4:ec3f71ef8732	1070
Piasiv1206	4:ec3f71ef8732	1071	/*!
Piasiv1206	4:ec3f71ef8732	1072	* @}
Piasiv1206	4:ec3f71ef8732	1073	/ / end of group GPIO_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	1074
Piasiv1206	4:ec3f71ef8732	1075
Piasiv1206	4:ec3f71ef8732	1076	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	1077	-- I2C Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	1078	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	1079
Piasiv1206	4:ec3f71ef8732	1080	/*!
Piasiv1206	4:ec3f71ef8732	1081	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	1082	* @{
Piasiv1206	4:ec3f71ef8732	1083	*/
Piasiv1206	4:ec3f71ef8732	1084
Piasiv1206	4:ec3f71ef8732	1085	/** I2C - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	1086	typedef struct {
Piasiv1206	4:ec3f71ef8732	1087	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	1088	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	1089	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	1090	__IO uint8_t S; /*< I2C Status register, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	1091	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	1092	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	1093	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
Piasiv1206	4:ec3f71ef8732	1094	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
Piasiv1206	4:ec3f71ef8732	1095	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	1096	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
Piasiv1206	4:ec3f71ef8732	1097	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
Piasiv1206	4:ec3f71ef8732	1098	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
Piasiv1206	4:ec3f71ef8732	1099	} I2C_Type;
Piasiv1206	4:ec3f71ef8732	1100
Piasiv1206	4:ec3f71ef8732	1101	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	1102	-- I2C Register Masks
Piasiv1206	4:ec3f71ef8732	1103	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	1104
Piasiv1206	4:ec3f71ef8732	1105	/*!
Piasiv1206	4:ec3f71ef8732	1106	* @addtogroup I2C_Register_Masks I2C Register Masks
Piasiv1206	4:ec3f71ef8732	1107	* @{
Piasiv1206	4:ec3f71ef8732	1108	*/
Piasiv1206	4:ec3f71ef8732	1109
Piasiv1206	4:ec3f71ef8732	1110	/* A1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1111	#define I2C_A1_AD_MASK 0xFEu
Piasiv1206	4:ec3f71ef8732	1112	#define I2C_A1_AD_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1113	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
Piasiv1206	4:ec3f71ef8732	1114	/* F Bit Fields */
Piasiv1206	4:ec3f71ef8732	1115	#define I2C_F_ICR_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	1116	#define I2C_F_ICR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1117	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
Piasiv1206	4:ec3f71ef8732	1118	#define I2C_F_MULT_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	1119	#define I2C_F_MULT_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1120	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
Piasiv1206	4:ec3f71ef8732	1121	/* C1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1122	#define I2C_C1_DMAEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1123	#define I2C_C1_DMAEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1124	#define I2C_C1_WUEN_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1125	#define I2C_C1_WUEN_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1126	#define I2C_C1_RSTA_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	1127	#define I2C_C1_RSTA_SHIFT 2
Piasiv1206	4:ec3f71ef8732	1128	#define I2C_C1_TXAK_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	1129	#define I2C_C1_TXAK_SHIFT 3
Piasiv1206	4:ec3f71ef8732	1130	#define I2C_C1_TX_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	1131	#define I2C_C1_TX_SHIFT 4
Piasiv1206	4:ec3f71ef8732	1132	#define I2C_C1_MST_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	1133	#define I2C_C1_MST_SHIFT 5
Piasiv1206	4:ec3f71ef8732	1134	#define I2C_C1_IICIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	1135	#define I2C_C1_IICIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1136	#define I2C_C1_IICEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	1137	#define I2C_C1_IICEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	1138	/* S Bit Fields */
Piasiv1206	4:ec3f71ef8732	1139	#define I2C_S_RXAK_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1140	#define I2C_S_RXAK_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1141	#define I2C_S_IICIF_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1142	#define I2C_S_IICIF_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1143	#define I2C_S_SRW_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	1144	#define I2C_S_SRW_SHIFT 2
Piasiv1206	4:ec3f71ef8732	1145	#define I2C_S_RAM_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	1146	#define I2C_S_RAM_SHIFT 3
Piasiv1206	4:ec3f71ef8732	1147	#define I2C_S_ARBL_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	1148	#define I2C_S_ARBL_SHIFT 4
Piasiv1206	4:ec3f71ef8732	1149	#define I2C_S_BUSY_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	1150	#define I2C_S_BUSY_SHIFT 5
Piasiv1206	4:ec3f71ef8732	1151	#define I2C_S_IAAS_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	1152	#define I2C_S_IAAS_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1153	#define I2C_S_TCF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	1154	#define I2C_S_TCF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	1155	/* D Bit Fields */
Piasiv1206	4:ec3f71ef8732	1156	#define I2C_D_DATA_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1157	#define I2C_D_DATA_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1158	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
Piasiv1206	4:ec3f71ef8732	1159	/* C2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1160	#define I2C_C2_AD_MASK 0x7u
Piasiv1206	4:ec3f71ef8732	1161	#define I2C_C2_AD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1162	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
Piasiv1206	4:ec3f71ef8732	1163	#define I2C_C2_RMEN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	1164	#define I2C_C2_RMEN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	1165	#define I2C_C2_SBRC_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	1166	#define I2C_C2_SBRC_SHIFT 4
Piasiv1206	4:ec3f71ef8732	1167	#define I2C_C2_HDRS_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	1168	#define I2C_C2_HDRS_SHIFT 5
Piasiv1206	4:ec3f71ef8732	1169	#define I2C_C2_ADEXT_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	1170	#define I2C_C2_ADEXT_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1171	#define I2C_C2_GCAEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	1172	#define I2C_C2_GCAEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	1173	/* FLT Bit Fields */
Piasiv1206	4:ec3f71ef8732	1174	#define I2C_FLT_FLT_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	1175	#define I2C_FLT_FLT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1176	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
Piasiv1206	4:ec3f71ef8732	1177	#define I2C_FLT_STOPIE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	1178	#define I2C_FLT_STOPIE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	1179	#define I2C_FLT_STOPF_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	1180	#define I2C_FLT_STOPF_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1181	#define I2C_FLT_SHEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	1182	#define I2C_FLT_SHEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	1183	/* RA Bit Fields */
Piasiv1206	4:ec3f71ef8732	1184	#define I2C_RA_RAD_MASK 0xFEu
Piasiv1206	4:ec3f71ef8732	1185	#define I2C_RA_RAD_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1186	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
Piasiv1206	4:ec3f71ef8732	1187	/* SMB Bit Fields */
Piasiv1206	4:ec3f71ef8732	1188	#define I2C_SMB_SHTF2IE_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1189	#define I2C_SMB_SHTF2IE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1190	#define I2C_SMB_SHTF2_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1191	#define I2C_SMB_SHTF2_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1192	#define I2C_SMB_SHTF1_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	1193	#define I2C_SMB_SHTF1_SHIFT 2
Piasiv1206	4:ec3f71ef8732	1194	#define I2C_SMB_SLTF_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	1195	#define I2C_SMB_SLTF_SHIFT 3
Piasiv1206	4:ec3f71ef8732	1196	#define I2C_SMB_TCKSEL_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	1197	#define I2C_SMB_TCKSEL_SHIFT 4
Piasiv1206	4:ec3f71ef8732	1198	#define I2C_SMB_SIICAEN_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	1199	#define I2C_SMB_SIICAEN_SHIFT 5
Piasiv1206	4:ec3f71ef8732	1200	#define I2C_SMB_ALERTEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	1201	#define I2C_SMB_ALERTEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1202	#define I2C_SMB_FACK_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	1203	#define I2C_SMB_FACK_SHIFT 7
Piasiv1206	4:ec3f71ef8732	1204	/* A2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1205	#define I2C_A2_SAD_MASK 0xFEu
Piasiv1206	4:ec3f71ef8732	1206	#define I2C_A2_SAD_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1207	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
Piasiv1206	4:ec3f71ef8732	1208	/* SLTH Bit Fields */
Piasiv1206	4:ec3f71ef8732	1209	#define I2C_SLTH_SSLT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1210	#define I2C_SLTH_SSLT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1211	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
Piasiv1206	4:ec3f71ef8732	1212	/* SLTL Bit Fields */
Piasiv1206	4:ec3f71ef8732	1213	#define I2C_SLTL_SSLT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1214	#define I2C_SLTL_SSLT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1215	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
Piasiv1206	4:ec3f71ef8732	1216
Piasiv1206	4:ec3f71ef8732	1217	/*!
Piasiv1206	4:ec3f71ef8732	1218	* @}
Piasiv1206	4:ec3f71ef8732	1219	/ / end of group I2C_Register_Masks */
Piasiv1206	4:ec3f71ef8732	1220
Piasiv1206	4:ec3f71ef8732	1221
Piasiv1206	4:ec3f71ef8732	1222	/* I2C - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	1223	/** Peripheral I2C0 base address */
Piasiv1206	4:ec3f71ef8732	1224	#define I2C0_BASE (0x40066000u)
Piasiv1206	4:ec3f71ef8732	1225	/** Peripheral I2C0 base pointer */
Piasiv1206	4:ec3f71ef8732	1226	#define I2C0 ((I2C_Type *)I2C0_BASE)
Piasiv1206	4:ec3f71ef8732	1227	/** Peripheral I2C1 base address */
Piasiv1206	4:ec3f71ef8732	1228	#define I2C1_BASE (0x40067000u)
Piasiv1206	4:ec3f71ef8732	1229	/** Peripheral I2C1 base pointer */
Piasiv1206	4:ec3f71ef8732	1230	#define I2C1 ((I2C_Type *)I2C1_BASE)
Piasiv1206	4:ec3f71ef8732	1231	/** Array initializer of I2C peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	1232	#define I2C_BASES { I2C0, I2C1 }
Piasiv1206	4:ec3f71ef8732	1233
Piasiv1206	4:ec3f71ef8732	1234	/*!
Piasiv1206	4:ec3f71ef8732	1235	* @}
Piasiv1206	4:ec3f71ef8732	1236	/ / end of group I2C_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	1237
Piasiv1206	4:ec3f71ef8732	1238
Piasiv1206	4:ec3f71ef8732	1239	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	1240	-- I2S Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	1241	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	1242
Piasiv1206	4:ec3f71ef8732	1243	/*!
Piasiv1206	4:ec3f71ef8732	1244	* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	1245	* @{
Piasiv1206	4:ec3f71ef8732	1246	*/
Piasiv1206	4:ec3f71ef8732	1247
Piasiv1206	4:ec3f71ef8732	1248	/** I2S - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	1249	typedef struct {
Piasiv1206	4:ec3f71ef8732	1250	__IO uint32_t TCSR; /*< SAI Transmit Control Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	1251	uint8_t RESERVED_0[4];
Piasiv1206	4:ec3f71ef8732	1252	__IO uint32_t TCR2; /*< SAI Transmit Configuration 2 Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	1253	__IO uint32_t TCR3; /*< SAI Transmit Configuration 3 Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	1254	__IO uint32_t TCR4; /*< SAI Transmit Configuration 4 Register, offset: 0x10 /
Piasiv1206	4:ec3f71ef8732	1255	__IO uint32_t TCR5; /*< SAI Transmit Configuration 5 Register, offset: 0x14 /
Piasiv1206	4:ec3f71ef8732	1256	uint8_t RESERVED_1[8];
Piasiv1206	4:ec3f71ef8732	1257	__O uint32_t TDR[1]; /*< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	1258	uint8_t RESERVED_2[60];
Piasiv1206	4:ec3f71ef8732	1259	__IO uint32_t TMR; /*< SAI Transmit Mask Register, offset: 0x60 /
Piasiv1206	4:ec3f71ef8732	1260	uint8_t RESERVED_3[28];
Piasiv1206	4:ec3f71ef8732	1261	__IO uint32_t RCSR; /*< SAI Receive Control Register, offset: 0x80 /
Piasiv1206	4:ec3f71ef8732	1262	uint8_t RESERVED_4[4];
Piasiv1206	4:ec3f71ef8732	1263	__IO uint32_t RCR2; /*< SAI Receive Configuration 2 Register, offset: 0x88 /
Piasiv1206	4:ec3f71ef8732	1264	__IO uint32_t RCR3; /*< SAI Receive Configuration 3 Register, offset: 0x8C /
Piasiv1206	4:ec3f71ef8732	1265	__IO uint32_t RCR4; /*< SAI Receive Configuration 4 Register, offset: 0x90 /
Piasiv1206	4:ec3f71ef8732	1266	__IO uint32_t RCR5; /*< SAI Receive Configuration 5 Register, offset: 0x94 /
Piasiv1206	4:ec3f71ef8732	1267	uint8_t RESERVED_5[8];
Piasiv1206	4:ec3f71ef8732	1268	__I uint32_t RDR[1]; /*< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	1269	uint8_t RESERVED_6[60];
Piasiv1206	4:ec3f71ef8732	1270	__IO uint32_t RMR; /*< SAI Receive Mask Register, offset: 0xE0 /
Piasiv1206	4:ec3f71ef8732	1271	uint8_t RESERVED_7[28];
Piasiv1206	4:ec3f71ef8732	1272	__IO uint32_t MCR; /*< SAI MCLK Control Register, offset: 0x100 /
Piasiv1206	4:ec3f71ef8732	1273	__IO uint32_t MDR; /*< SAI MCLK Divide Register, offset: 0x104 /
Piasiv1206	4:ec3f71ef8732	1274	} I2S_Type;
Piasiv1206	4:ec3f71ef8732	1275
Piasiv1206	4:ec3f71ef8732	1276	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	1277	-- I2S Register Masks
Piasiv1206	4:ec3f71ef8732	1278	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	1279
Piasiv1206	4:ec3f71ef8732	1280	/*!
Piasiv1206	4:ec3f71ef8732	1281	* @addtogroup I2S_Register_Masks I2S Register Masks
Piasiv1206	4:ec3f71ef8732	1282	* @{
Piasiv1206	4:ec3f71ef8732	1283	*/
Piasiv1206	4:ec3f71ef8732	1284
Piasiv1206	4:ec3f71ef8732	1285	/* TCSR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1286	#define I2S_TCSR_FWDE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1287	#define I2S_TCSR_FWDE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1288	#define I2S_TCSR_FWIE_MASK 0x200u
Piasiv1206	4:ec3f71ef8732	1289	#define I2S_TCSR_FWIE_SHIFT 9
Piasiv1206	4:ec3f71ef8732	1290	#define I2S_TCSR_FEIE_MASK 0x400u
Piasiv1206	4:ec3f71ef8732	1291	#define I2S_TCSR_FEIE_SHIFT 10
Piasiv1206	4:ec3f71ef8732	1292	#define I2S_TCSR_SEIE_MASK 0x800u
Piasiv1206	4:ec3f71ef8732	1293	#define I2S_TCSR_SEIE_SHIFT 11
Piasiv1206	4:ec3f71ef8732	1294	#define I2S_TCSR_WSIE_MASK 0x1000u
Piasiv1206	4:ec3f71ef8732	1295	#define I2S_TCSR_WSIE_SHIFT 12
Piasiv1206	4:ec3f71ef8732	1296	#define I2S_TCSR_FWF_MASK 0x20000u
Piasiv1206	4:ec3f71ef8732	1297	#define I2S_TCSR_FWF_SHIFT 17
Piasiv1206	4:ec3f71ef8732	1298	#define I2S_TCSR_FEF_MASK 0x40000u
Piasiv1206	4:ec3f71ef8732	1299	#define I2S_TCSR_FEF_SHIFT 18
Piasiv1206	4:ec3f71ef8732	1300	#define I2S_TCSR_SEF_MASK 0x80000u
Piasiv1206	4:ec3f71ef8732	1301	#define I2S_TCSR_SEF_SHIFT 19
Piasiv1206	4:ec3f71ef8732	1302	#define I2S_TCSR_WSF_MASK 0x100000u
Piasiv1206	4:ec3f71ef8732	1303	#define I2S_TCSR_WSF_SHIFT 20
Piasiv1206	4:ec3f71ef8732	1304	#define I2S_TCSR_SR_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	1305	#define I2S_TCSR_SR_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1306	#define I2S_TCSR_FR_MASK 0x2000000u
Piasiv1206	4:ec3f71ef8732	1307	#define I2S_TCSR_FR_SHIFT 25
Piasiv1206	4:ec3f71ef8732	1308	#define I2S_TCSR_BCE_MASK 0x10000000u
Piasiv1206	4:ec3f71ef8732	1309	#define I2S_TCSR_BCE_SHIFT 28
Piasiv1206	4:ec3f71ef8732	1310	#define I2S_TCSR_DBGE_MASK 0x20000000u
Piasiv1206	4:ec3f71ef8732	1311	#define I2S_TCSR_DBGE_SHIFT 29
Piasiv1206	4:ec3f71ef8732	1312	#define I2S_TCSR_STOPE_MASK 0x40000000u
Piasiv1206	4:ec3f71ef8732	1313	#define I2S_TCSR_STOPE_SHIFT 30
Piasiv1206	4:ec3f71ef8732	1314	#define I2S_TCSR_TE_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	1315	#define I2S_TCSR_TE_SHIFT 31
Piasiv1206	4:ec3f71ef8732	1316	/* TCR2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1317	#define I2S_TCR2_DIV_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1318	#define I2S_TCR2_DIV_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1319	#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
Piasiv1206	4:ec3f71ef8732	1320	#define I2S_TCR2_BCD_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	1321	#define I2S_TCR2_BCD_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1322	#define I2S_TCR2_BCP_MASK 0x2000000u
Piasiv1206	4:ec3f71ef8732	1323	#define I2S_TCR2_BCP_SHIFT 25
Piasiv1206	4:ec3f71ef8732	1324	#define I2S_TCR2_CLKMODE_MASK 0xC000000u
Piasiv1206	4:ec3f71ef8732	1325	#define I2S_TCR2_CLKMODE_SHIFT 26
Piasiv1206	4:ec3f71ef8732	1326	#define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
Piasiv1206	4:ec3f71ef8732	1327	/* TCR3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1328	#define I2S_TCR3_WDFL_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1329	#define I2S_TCR3_WDFL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1330	#define I2S_TCR3_TCE_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	1331	#define I2S_TCR3_TCE_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1332	/* TCR4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1333	#define I2S_TCR4_FSD_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1334	#define I2S_TCR4_FSD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1335	#define I2S_TCR4_FSP_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1336	#define I2S_TCR4_FSP_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1337	#define I2S_TCR4_FSE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	1338	#define I2S_TCR4_FSE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	1339	#define I2S_TCR4_MF_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	1340	#define I2S_TCR4_MF_SHIFT 4
Piasiv1206	4:ec3f71ef8732	1341	#define I2S_TCR4_SYWD_MASK 0x1F00u
Piasiv1206	4:ec3f71ef8732	1342	#define I2S_TCR4_SYWD_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1343	#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
Piasiv1206	4:ec3f71ef8732	1344	#define I2S_TCR4_FRSZ_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	1345	#define I2S_TCR4_FRSZ_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1346	/* TCR5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1347	#define I2S_TCR5_FBT_MASK 0x1F00u
Piasiv1206	4:ec3f71ef8732	1348	#define I2S_TCR5_FBT_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1349	#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
Piasiv1206	4:ec3f71ef8732	1350	#define I2S_TCR5_W0W_MASK 0x1F0000u
Piasiv1206	4:ec3f71ef8732	1351	#define I2S_TCR5_W0W_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1352	#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
Piasiv1206	4:ec3f71ef8732	1353	#define I2S_TCR5_WNW_MASK 0x1F000000u
Piasiv1206	4:ec3f71ef8732	1354	#define I2S_TCR5_WNW_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1355	#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
Piasiv1206	4:ec3f71ef8732	1356	/* TDR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1357	#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1358	#define I2S_TDR_TDR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1359	#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
Piasiv1206	4:ec3f71ef8732	1360	/* TMR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1361	#define I2S_TMR_TWM_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	1362	#define I2S_TMR_TWM_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1363	#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
Piasiv1206	4:ec3f71ef8732	1364	/* RCSR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1365	#define I2S_RCSR_FWDE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1366	#define I2S_RCSR_FWDE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1367	#define I2S_RCSR_FWIE_MASK 0x200u
Piasiv1206	4:ec3f71ef8732	1368	#define I2S_RCSR_FWIE_SHIFT 9
Piasiv1206	4:ec3f71ef8732	1369	#define I2S_RCSR_FEIE_MASK 0x400u
Piasiv1206	4:ec3f71ef8732	1370	#define I2S_RCSR_FEIE_SHIFT 10
Piasiv1206	4:ec3f71ef8732	1371	#define I2S_RCSR_SEIE_MASK 0x800u
Piasiv1206	4:ec3f71ef8732	1372	#define I2S_RCSR_SEIE_SHIFT 11
Piasiv1206	4:ec3f71ef8732	1373	#define I2S_RCSR_WSIE_MASK 0x1000u
Piasiv1206	4:ec3f71ef8732	1374	#define I2S_RCSR_WSIE_SHIFT 12
Piasiv1206	4:ec3f71ef8732	1375	#define I2S_RCSR_FWF_MASK 0x20000u
Piasiv1206	4:ec3f71ef8732	1376	#define I2S_RCSR_FWF_SHIFT 17
Piasiv1206	4:ec3f71ef8732	1377	#define I2S_RCSR_FEF_MASK 0x40000u
Piasiv1206	4:ec3f71ef8732	1378	#define I2S_RCSR_FEF_SHIFT 18
Piasiv1206	4:ec3f71ef8732	1379	#define I2S_RCSR_SEF_MASK 0x80000u
Piasiv1206	4:ec3f71ef8732	1380	#define I2S_RCSR_SEF_SHIFT 19
Piasiv1206	4:ec3f71ef8732	1381	#define I2S_RCSR_WSF_MASK 0x100000u
Piasiv1206	4:ec3f71ef8732	1382	#define I2S_RCSR_WSF_SHIFT 20
Piasiv1206	4:ec3f71ef8732	1383	#define I2S_RCSR_SR_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	1384	#define I2S_RCSR_SR_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1385	#define I2S_RCSR_FR_MASK 0x2000000u
Piasiv1206	4:ec3f71ef8732	1386	#define I2S_RCSR_FR_SHIFT 25
Piasiv1206	4:ec3f71ef8732	1387	#define I2S_RCSR_BCE_MASK 0x10000000u
Piasiv1206	4:ec3f71ef8732	1388	#define I2S_RCSR_BCE_SHIFT 28
Piasiv1206	4:ec3f71ef8732	1389	#define I2S_RCSR_DBGE_MASK 0x20000000u
Piasiv1206	4:ec3f71ef8732	1390	#define I2S_RCSR_DBGE_SHIFT 29
Piasiv1206	4:ec3f71ef8732	1391	#define I2S_RCSR_STOPE_MASK 0x40000000u
Piasiv1206	4:ec3f71ef8732	1392	#define I2S_RCSR_STOPE_SHIFT 30
Piasiv1206	4:ec3f71ef8732	1393	#define I2S_RCSR_RE_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	1394	#define I2S_RCSR_RE_SHIFT 31
Piasiv1206	4:ec3f71ef8732	1395	/* RCR2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1396	#define I2S_RCR2_DIV_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1397	#define I2S_RCR2_DIV_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1398	#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
Piasiv1206	4:ec3f71ef8732	1399	#define I2S_RCR2_BCD_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	1400	#define I2S_RCR2_BCD_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1401	#define I2S_RCR2_BCP_MASK 0x2000000u
Piasiv1206	4:ec3f71ef8732	1402	#define I2S_RCR2_BCP_SHIFT 25
Piasiv1206	4:ec3f71ef8732	1403	#define I2S_RCR2_CLKMODE_MASK 0xC000000u
Piasiv1206	4:ec3f71ef8732	1404	#define I2S_RCR2_CLKMODE_SHIFT 26
Piasiv1206	4:ec3f71ef8732	1405	#define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
Piasiv1206	4:ec3f71ef8732	1406	/* RCR3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1407	#define I2S_RCR3_WDFL_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1408	#define I2S_RCR3_WDFL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1409	#define I2S_RCR3_RCE_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	1410	#define I2S_RCR3_RCE_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1411	/* RCR4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1412	#define I2S_RCR4_FSD_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1413	#define I2S_RCR4_FSD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1414	#define I2S_RCR4_FSP_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1415	#define I2S_RCR4_FSP_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1416	#define I2S_RCR4_FSE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	1417	#define I2S_RCR4_FSE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	1418	#define I2S_RCR4_MF_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	1419	#define I2S_RCR4_MF_SHIFT 4
Piasiv1206	4:ec3f71ef8732	1420	#define I2S_RCR4_SYWD_MASK 0x1F00u
Piasiv1206	4:ec3f71ef8732	1421	#define I2S_RCR4_SYWD_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1422	#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
Piasiv1206	4:ec3f71ef8732	1423	#define I2S_RCR4_FRSZ_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	1424	#define I2S_RCR4_FRSZ_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1425	/* RCR5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	1426	#define I2S_RCR5_FBT_MASK 0x1F00u
Piasiv1206	4:ec3f71ef8732	1427	#define I2S_RCR5_FBT_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1428	#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
Piasiv1206	4:ec3f71ef8732	1429	#define I2S_RCR5_W0W_MASK 0x1F0000u
Piasiv1206	4:ec3f71ef8732	1430	#define I2S_RCR5_W0W_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1431	#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
Piasiv1206	4:ec3f71ef8732	1432	#define I2S_RCR5_WNW_MASK 0x1F000000u
Piasiv1206	4:ec3f71ef8732	1433	#define I2S_RCR5_WNW_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1434	#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
Piasiv1206	4:ec3f71ef8732	1435	/* RDR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1436	#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1437	#define I2S_RDR_RDR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1438	#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
Piasiv1206	4:ec3f71ef8732	1439	/* RMR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1440	#define I2S_RMR_RWM_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	1441	#define I2S_RMR_RWM_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1442	#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
Piasiv1206	4:ec3f71ef8732	1443	/* MCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1444	#define I2S_MCR_MICS_MASK 0x3000000u
Piasiv1206	4:ec3f71ef8732	1445	#define I2S_MCR_MICS_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1446	#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
Piasiv1206	4:ec3f71ef8732	1447	#define I2S_MCR_MOE_MASK 0x40000000u
Piasiv1206	4:ec3f71ef8732	1448	#define I2S_MCR_MOE_SHIFT 30
Piasiv1206	4:ec3f71ef8732	1449	#define I2S_MCR_DUF_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	1450	#define I2S_MCR_DUF_SHIFT 31
Piasiv1206	4:ec3f71ef8732	1451	/* MDR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1452	#define I2S_MDR_DIVIDE_MASK 0xFFFu
Piasiv1206	4:ec3f71ef8732	1453	#define I2S_MDR_DIVIDE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1454	#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
Piasiv1206	4:ec3f71ef8732	1455	#define I2S_MDR_FRACT_MASK 0xFF000u
Piasiv1206	4:ec3f71ef8732	1456	#define I2S_MDR_FRACT_SHIFT 12
Piasiv1206	4:ec3f71ef8732	1457	#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
Piasiv1206	4:ec3f71ef8732	1458
Piasiv1206	4:ec3f71ef8732	1459	/*!
Piasiv1206	4:ec3f71ef8732	1460	* @}
Piasiv1206	4:ec3f71ef8732	1461	/ / end of group I2S_Register_Masks */
Piasiv1206	4:ec3f71ef8732	1462
Piasiv1206	4:ec3f71ef8732	1463
Piasiv1206	4:ec3f71ef8732	1464	/* I2S - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	1465	/** Peripheral I2S0 base address */
Piasiv1206	4:ec3f71ef8732	1466	#define I2S0_BASE (0x4002F000u)
Piasiv1206	4:ec3f71ef8732	1467	/** Peripheral I2S0 base pointer */
Piasiv1206	4:ec3f71ef8732	1468	#define I2S0 ((I2S_Type *)I2S0_BASE)
Piasiv1206	4:ec3f71ef8732	1469	/** Array initializer of I2S peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	1470	#define I2S_BASES { I2S0 }
Piasiv1206	4:ec3f71ef8732	1471
Piasiv1206	4:ec3f71ef8732	1472	/*!
Piasiv1206	4:ec3f71ef8732	1473	* @}
Piasiv1206	4:ec3f71ef8732	1474	/ / end of group I2S_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	1475
Piasiv1206	4:ec3f71ef8732	1476
Piasiv1206	4:ec3f71ef8732	1477	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	1478	-- LCD Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	1479	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	1480
Piasiv1206	4:ec3f71ef8732	1481	/*!
Piasiv1206	4:ec3f71ef8732	1482	* @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	1483	* @{
Piasiv1206	4:ec3f71ef8732	1484	*/
Piasiv1206	4:ec3f71ef8732	1485
Piasiv1206	4:ec3f71ef8732	1486	/** LCD - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	1487	typedef struct {
Piasiv1206	4:ec3f71ef8732	1488	__IO uint32_t GCR; /*< LCD General Control Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	1489	__IO uint32_t AR; /*< LCD Auxiliary Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	1490	__IO uint32_t FDCR; /*< LCD Fault Detect Control Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	1491	__IO uint32_t FDSR; /*< LCD Fault Detect Status Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	1492	__IO uint32_t PEN[2]; /*< LCD Pin Enable register, array offset: 0x10, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	1493	__IO uint32_t BPEN[2]; /*< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	1494	union { /* offset: 0x20 */
Piasiv1206	4:ec3f71ef8732	1495	__IO uint32_t WF[16]; /*< LCD Waveform register, array offset: 0x20, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	1496	__IO uint8_t WF8B[64]; /*< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 /
Piasiv1206	4:ec3f71ef8732	1497	};
Piasiv1206	4:ec3f71ef8732	1498	} LCD_Type;
Piasiv1206	4:ec3f71ef8732	1499
Piasiv1206	4:ec3f71ef8732	1500	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	1501	-- LCD Register Masks
Piasiv1206	4:ec3f71ef8732	1502	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	1503
Piasiv1206	4:ec3f71ef8732	1504	/*!
Piasiv1206	4:ec3f71ef8732	1505	* @addtogroup LCD_Register_Masks LCD Register Masks
Piasiv1206	4:ec3f71ef8732	1506	* @{
Piasiv1206	4:ec3f71ef8732	1507	*/
Piasiv1206	4:ec3f71ef8732	1508
Piasiv1206	4:ec3f71ef8732	1509	/* GCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1510	#define LCD_GCR_DUTY_MASK 0x7u
Piasiv1206	4:ec3f71ef8732	1511	#define LCD_GCR_DUTY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1512	#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
Piasiv1206	4:ec3f71ef8732	1513	#define LCD_GCR_LCLK_MASK 0x38u
Piasiv1206	4:ec3f71ef8732	1514	#define LCD_GCR_LCLK_SHIFT 3
Piasiv1206	4:ec3f71ef8732	1515	#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
Piasiv1206	4:ec3f71ef8732	1516	#define LCD_GCR_SOURCE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	1517	#define LCD_GCR_SOURCE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1518	#define LCD_GCR_LCDEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	1519	#define LCD_GCR_LCDEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	1520	#define LCD_GCR_LCDSTP_MASK 0x100u
Piasiv1206	4:ec3f71ef8732	1521	#define LCD_GCR_LCDSTP_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1522	#define LCD_GCR_LCDDOZE_MASK 0x200u
Piasiv1206	4:ec3f71ef8732	1523	#define LCD_GCR_LCDDOZE_SHIFT 9
Piasiv1206	4:ec3f71ef8732	1524	#define LCD_GCR_FFR_MASK 0x400u
Piasiv1206	4:ec3f71ef8732	1525	#define LCD_GCR_FFR_SHIFT 10
Piasiv1206	4:ec3f71ef8732	1526	#define LCD_GCR_ALTSOURCE_MASK 0x800u
Piasiv1206	4:ec3f71ef8732	1527	#define LCD_GCR_ALTSOURCE_SHIFT 11
Piasiv1206	4:ec3f71ef8732	1528	#define LCD_GCR_ALTDIV_MASK 0x3000u
Piasiv1206	4:ec3f71ef8732	1529	#define LCD_GCR_ALTDIV_SHIFT 12
Piasiv1206	4:ec3f71ef8732	1530	#define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
Piasiv1206	4:ec3f71ef8732	1531	#define LCD_GCR_FDCIEN_MASK 0x4000u
Piasiv1206	4:ec3f71ef8732	1532	#define LCD_GCR_FDCIEN_SHIFT 14
Piasiv1206	4:ec3f71ef8732	1533	#define LCD_GCR_PADSAFE_MASK 0x8000u
Piasiv1206	4:ec3f71ef8732	1534	#define LCD_GCR_PADSAFE_SHIFT 15
Piasiv1206	4:ec3f71ef8732	1535	#define LCD_GCR_VSUPPLY_MASK 0x20000u
Piasiv1206	4:ec3f71ef8732	1536	#define LCD_GCR_VSUPPLY_SHIFT 17
Piasiv1206	4:ec3f71ef8732	1537	#define LCD_GCR_LADJ_MASK 0x300000u
Piasiv1206	4:ec3f71ef8732	1538	#define LCD_GCR_LADJ_SHIFT 20
Piasiv1206	4:ec3f71ef8732	1539	#define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
Piasiv1206	4:ec3f71ef8732	1540	#define LCD_GCR_CPSEL_MASK 0x800000u
Piasiv1206	4:ec3f71ef8732	1541	#define LCD_GCR_CPSEL_SHIFT 23
Piasiv1206	4:ec3f71ef8732	1542	#define LCD_GCR_RVTRIM_MASK 0xF000000u
Piasiv1206	4:ec3f71ef8732	1543	#define LCD_GCR_RVTRIM_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1544	#define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
Piasiv1206	4:ec3f71ef8732	1545	#define LCD_GCR_RVEN_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	1546	#define LCD_GCR_RVEN_SHIFT 31
Piasiv1206	4:ec3f71ef8732	1547	/* AR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1548	#define LCD_AR_BRATE_MASK 0x7u
Piasiv1206	4:ec3f71ef8732	1549	#define LCD_AR_BRATE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1550	#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
Piasiv1206	4:ec3f71ef8732	1551	#define LCD_AR_BMODE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	1552	#define LCD_AR_BMODE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	1553	#define LCD_AR_BLANK_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	1554	#define LCD_AR_BLANK_SHIFT 5
Piasiv1206	4:ec3f71ef8732	1555	#define LCD_AR_ALT_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	1556	#define LCD_AR_ALT_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1557	#define LCD_AR_BLINK_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	1558	#define LCD_AR_BLINK_SHIFT 7
Piasiv1206	4:ec3f71ef8732	1559	/* FDCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1560	#define LCD_FDCR_FDPINID_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	1561	#define LCD_FDCR_FDPINID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1562	#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
Piasiv1206	4:ec3f71ef8732	1563	#define LCD_FDCR_FDBPEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	1564	#define LCD_FDCR_FDBPEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	1565	#define LCD_FDCR_FDEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	1566	#define LCD_FDCR_FDEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	1567	#define LCD_FDCR_FDSWW_MASK 0xE00u
Piasiv1206	4:ec3f71ef8732	1568	#define LCD_FDCR_FDSWW_SHIFT 9
Piasiv1206	4:ec3f71ef8732	1569	#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
Piasiv1206	4:ec3f71ef8732	1570	#define LCD_FDCR_FDPRS_MASK 0x7000u
Piasiv1206	4:ec3f71ef8732	1571	#define LCD_FDCR_FDPRS_SHIFT 12
Piasiv1206	4:ec3f71ef8732	1572	#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
Piasiv1206	4:ec3f71ef8732	1573	/* FDSR Bit Fields */
Piasiv1206	4:ec3f71ef8732	1574	#define LCD_FDSR_FDCNT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1575	#define LCD_FDSR_FDCNT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1576	#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
Piasiv1206	4:ec3f71ef8732	1577	#define LCD_FDSR_FDCF_MASK 0x8000u
Piasiv1206	4:ec3f71ef8732	1578	#define LCD_FDSR_FDCF_SHIFT 15
Piasiv1206	4:ec3f71ef8732	1579	/* PEN Bit Fields */
Piasiv1206	4:ec3f71ef8732	1580	#define LCD_PEN_PEN_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1581	#define LCD_PEN_PEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1582	#define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
Piasiv1206	4:ec3f71ef8732	1583	/* BPEN Bit Fields */
Piasiv1206	4:ec3f71ef8732	1584	#define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	1585	#define LCD_BPEN_BPEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1586	#define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
Piasiv1206	4:ec3f71ef8732	1587	/* WF Bit Fields */
Piasiv1206	4:ec3f71ef8732	1588	#define LCD_WF_WF0_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1589	#define LCD_WF_WF0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1590	#define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
Piasiv1206	4:ec3f71ef8732	1591	#define LCD_WF_WF60_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1592	#define LCD_WF_WF60_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1593	#define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
Piasiv1206	4:ec3f71ef8732	1594	#define LCD_WF_WF56_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1595	#define LCD_WF_WF56_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1596	#define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
Piasiv1206	4:ec3f71ef8732	1597	#define LCD_WF_WF52_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1598	#define LCD_WF_WF52_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1599	#define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
Piasiv1206	4:ec3f71ef8732	1600	#define LCD_WF_WF4_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1601	#define LCD_WF_WF4_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1602	#define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
Piasiv1206	4:ec3f71ef8732	1603	#define LCD_WF_WF48_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1604	#define LCD_WF_WF48_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1605	#define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
Piasiv1206	4:ec3f71ef8732	1606	#define LCD_WF_WF44_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1607	#define LCD_WF_WF44_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1608	#define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
Piasiv1206	4:ec3f71ef8732	1609	#define LCD_WF_WF40_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1610	#define LCD_WF_WF40_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1611	#define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
Piasiv1206	4:ec3f71ef8732	1612	#define LCD_WF_WF8_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1613	#define LCD_WF_WF8_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1614	#define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
Piasiv1206	4:ec3f71ef8732	1615	#define LCD_WF_WF36_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1616	#define LCD_WF_WF36_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1617	#define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
Piasiv1206	4:ec3f71ef8732	1618	#define LCD_WF_WF32_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1619	#define LCD_WF_WF32_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1620	#define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
Piasiv1206	4:ec3f71ef8732	1621	#define LCD_WF_WF28_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1622	#define LCD_WF_WF28_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1623	#define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
Piasiv1206	4:ec3f71ef8732	1624	#define LCD_WF_WF12_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1625	#define LCD_WF_WF12_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1626	#define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
Piasiv1206	4:ec3f71ef8732	1627	#define LCD_WF_WF24_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1628	#define LCD_WF_WF24_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1629	#define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
Piasiv1206	4:ec3f71ef8732	1630	#define LCD_WF_WF20_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1631	#define LCD_WF_WF20_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1632	#define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
Piasiv1206	4:ec3f71ef8732	1633	#define LCD_WF_WF16_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	1634	#define LCD_WF_WF16_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1635	#define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
Piasiv1206	4:ec3f71ef8732	1636	#define LCD_WF_WF5_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1637	#define LCD_WF_WF5_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1638	#define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
Piasiv1206	4:ec3f71ef8732	1639	#define LCD_WF_WF49_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1640	#define LCD_WF_WF49_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1641	#define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
Piasiv1206	4:ec3f71ef8732	1642	#define LCD_WF_WF45_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1643	#define LCD_WF_WF45_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1644	#define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
Piasiv1206	4:ec3f71ef8732	1645	#define LCD_WF_WF61_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1646	#define LCD_WF_WF61_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1647	#define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
Piasiv1206	4:ec3f71ef8732	1648	#define LCD_WF_WF25_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1649	#define LCD_WF_WF25_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1650	#define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
Piasiv1206	4:ec3f71ef8732	1651	#define LCD_WF_WF17_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1652	#define LCD_WF_WF17_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1653	#define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
Piasiv1206	4:ec3f71ef8732	1654	#define LCD_WF_WF41_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1655	#define LCD_WF_WF41_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1656	#define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
Piasiv1206	4:ec3f71ef8732	1657	#define LCD_WF_WF13_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1658	#define LCD_WF_WF13_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1659	#define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
Piasiv1206	4:ec3f71ef8732	1660	#define LCD_WF_WF57_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1661	#define LCD_WF_WF57_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1662	#define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
Piasiv1206	4:ec3f71ef8732	1663	#define LCD_WF_WF53_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1664	#define LCD_WF_WF53_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1665	#define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
Piasiv1206	4:ec3f71ef8732	1666	#define LCD_WF_WF37_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1667	#define LCD_WF_WF37_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1668	#define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
Piasiv1206	4:ec3f71ef8732	1669	#define LCD_WF_WF9_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1670	#define LCD_WF_WF9_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1671	#define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
Piasiv1206	4:ec3f71ef8732	1672	#define LCD_WF_WF1_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1673	#define LCD_WF_WF1_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1674	#define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
Piasiv1206	4:ec3f71ef8732	1675	#define LCD_WF_WF29_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1676	#define LCD_WF_WF29_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1677	#define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
Piasiv1206	4:ec3f71ef8732	1678	#define LCD_WF_WF33_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1679	#define LCD_WF_WF33_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1680	#define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
Piasiv1206	4:ec3f71ef8732	1681	#define LCD_WF_WF21_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	1682	#define LCD_WF_WF21_SHIFT 8
Piasiv1206	4:ec3f71ef8732	1683	#define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
Piasiv1206	4:ec3f71ef8732	1684	#define LCD_WF_WF26_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1685	#define LCD_WF_WF26_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1686	#define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
Piasiv1206	4:ec3f71ef8732	1687	#define LCD_WF_WF46_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1688	#define LCD_WF_WF46_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1689	#define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
Piasiv1206	4:ec3f71ef8732	1690	#define LCD_WF_WF6_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1691	#define LCD_WF_WF6_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1692	#define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
Piasiv1206	4:ec3f71ef8732	1693	#define LCD_WF_WF42_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1694	#define LCD_WF_WF42_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1695	#define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
Piasiv1206	4:ec3f71ef8732	1696	#define LCD_WF_WF18_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1697	#define LCD_WF_WF18_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1698	#define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
Piasiv1206	4:ec3f71ef8732	1699	#define LCD_WF_WF38_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1700	#define LCD_WF_WF38_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1701	#define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
Piasiv1206	4:ec3f71ef8732	1702	#define LCD_WF_WF22_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1703	#define LCD_WF_WF22_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1704	#define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
Piasiv1206	4:ec3f71ef8732	1705	#define LCD_WF_WF34_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1706	#define LCD_WF_WF34_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1707	#define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
Piasiv1206	4:ec3f71ef8732	1708	#define LCD_WF_WF50_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1709	#define LCD_WF_WF50_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1710	#define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
Piasiv1206	4:ec3f71ef8732	1711	#define LCD_WF_WF14_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1712	#define LCD_WF_WF14_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1713	#define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
Piasiv1206	4:ec3f71ef8732	1714	#define LCD_WF_WF54_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1715	#define LCD_WF_WF54_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1716	#define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
Piasiv1206	4:ec3f71ef8732	1717	#define LCD_WF_WF2_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1718	#define LCD_WF_WF2_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1719	#define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
Piasiv1206	4:ec3f71ef8732	1720	#define LCD_WF_WF58_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1721	#define LCD_WF_WF58_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1722	#define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
Piasiv1206	4:ec3f71ef8732	1723	#define LCD_WF_WF30_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1724	#define LCD_WF_WF30_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1725	#define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
Piasiv1206	4:ec3f71ef8732	1726	#define LCD_WF_WF62_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1727	#define LCD_WF_WF62_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1728	#define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
Piasiv1206	4:ec3f71ef8732	1729	#define LCD_WF_WF10_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	1730	#define LCD_WF_WF10_SHIFT 16
Piasiv1206	4:ec3f71ef8732	1731	#define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
Piasiv1206	4:ec3f71ef8732	1732	#define LCD_WF_WF63_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1733	#define LCD_WF_WF63_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1734	#define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
Piasiv1206	4:ec3f71ef8732	1735	#define LCD_WF_WF59_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1736	#define LCD_WF_WF59_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1737	#define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
Piasiv1206	4:ec3f71ef8732	1738	#define LCD_WF_WF55_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1739	#define LCD_WF_WF55_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1740	#define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
Piasiv1206	4:ec3f71ef8732	1741	#define LCD_WF_WF3_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1742	#define LCD_WF_WF3_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1743	#define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
Piasiv1206	4:ec3f71ef8732	1744	#define LCD_WF_WF51_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1745	#define LCD_WF_WF51_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1746	#define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
Piasiv1206	4:ec3f71ef8732	1747	#define LCD_WF_WF47_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1748	#define LCD_WF_WF47_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1749	#define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
Piasiv1206	4:ec3f71ef8732	1750	#define LCD_WF_WF43_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1751	#define LCD_WF_WF43_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1752	#define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
Piasiv1206	4:ec3f71ef8732	1753	#define LCD_WF_WF7_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1754	#define LCD_WF_WF7_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1755	#define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
Piasiv1206	4:ec3f71ef8732	1756	#define LCD_WF_WF39_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1757	#define LCD_WF_WF39_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1758	#define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
Piasiv1206	4:ec3f71ef8732	1759	#define LCD_WF_WF35_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1760	#define LCD_WF_WF35_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1761	#define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
Piasiv1206	4:ec3f71ef8732	1762	#define LCD_WF_WF31_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1763	#define LCD_WF_WF31_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1764	#define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
Piasiv1206	4:ec3f71ef8732	1765	#define LCD_WF_WF11_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1766	#define LCD_WF_WF11_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1767	#define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
Piasiv1206	4:ec3f71ef8732	1768	#define LCD_WF_WF27_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1769	#define LCD_WF_WF27_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1770	#define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
Piasiv1206	4:ec3f71ef8732	1771	#define LCD_WF_WF23_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1772	#define LCD_WF_WF23_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1773	#define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
Piasiv1206	4:ec3f71ef8732	1774	#define LCD_WF_WF19_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1775	#define LCD_WF_WF19_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1776	#define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
Piasiv1206	4:ec3f71ef8732	1777	#define LCD_WF_WF15_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	1778	#define LCD_WF_WF15_SHIFT 24
Piasiv1206	4:ec3f71ef8732	1779	#define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
Piasiv1206	4:ec3f71ef8732	1780	/* WF8B Bit Fields */
Piasiv1206	4:ec3f71ef8732	1781	#define LCD_WF8B_BPALCD0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1782	#define LCD_WF8B_BPALCD0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1783	#define LCD_WF8B_BPALCD63_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1784	#define LCD_WF8B_BPALCD63_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1785	#define LCD_WF8B_BPALCD62_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1786	#define LCD_WF8B_BPALCD62_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1787	#define LCD_WF8B_BPALCD61_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1788	#define LCD_WF8B_BPALCD61_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1789	#define LCD_WF8B_BPALCD60_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1790	#define LCD_WF8B_BPALCD60_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1791	#define LCD_WF8B_BPALCD59_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1792	#define LCD_WF8B_BPALCD59_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1793	#define LCD_WF8B_BPALCD58_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1794	#define LCD_WF8B_BPALCD58_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1795	#define LCD_WF8B_BPALCD57_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1796	#define LCD_WF8B_BPALCD57_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1797	#define LCD_WF8B_BPALCD1_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1798	#define LCD_WF8B_BPALCD1_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1799	#define LCD_WF8B_BPALCD56_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1800	#define LCD_WF8B_BPALCD56_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1801	#define LCD_WF8B_BPALCD55_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1802	#define LCD_WF8B_BPALCD55_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1803	#define LCD_WF8B_BPALCD54_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1804	#define LCD_WF8B_BPALCD54_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1805	#define LCD_WF8B_BPALCD53_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1806	#define LCD_WF8B_BPALCD53_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1807	#define LCD_WF8B_BPALCD52_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1808	#define LCD_WF8B_BPALCD52_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1809	#define LCD_WF8B_BPALCD51_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1810	#define LCD_WF8B_BPALCD51_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1811	#define LCD_WF8B_BPALCD50_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1812	#define LCD_WF8B_BPALCD50_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1813	#define LCD_WF8B_BPALCD2_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1814	#define LCD_WF8B_BPALCD2_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1815	#define LCD_WF8B_BPALCD49_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1816	#define LCD_WF8B_BPALCD49_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1817	#define LCD_WF8B_BPALCD48_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1818	#define LCD_WF8B_BPALCD48_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1819	#define LCD_WF8B_BPALCD47_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1820	#define LCD_WF8B_BPALCD47_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1821	#define LCD_WF8B_BPALCD46_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1822	#define LCD_WF8B_BPALCD46_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1823	#define LCD_WF8B_BPALCD45_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1824	#define LCD_WF8B_BPALCD45_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1825	#define LCD_WF8B_BPALCD44_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1826	#define LCD_WF8B_BPALCD44_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1827	#define LCD_WF8B_BPALCD43_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1828	#define LCD_WF8B_BPALCD43_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1829	#define LCD_WF8B_BPALCD3_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1830	#define LCD_WF8B_BPALCD3_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1831	#define LCD_WF8B_BPALCD42_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1832	#define LCD_WF8B_BPALCD42_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1833	#define LCD_WF8B_BPALCD41_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1834	#define LCD_WF8B_BPALCD41_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1835	#define LCD_WF8B_BPALCD40_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1836	#define LCD_WF8B_BPALCD40_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1837	#define LCD_WF8B_BPALCD39_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1838	#define LCD_WF8B_BPALCD39_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1839	#define LCD_WF8B_BPALCD38_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1840	#define LCD_WF8B_BPALCD38_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1841	#define LCD_WF8B_BPALCD37_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1842	#define LCD_WF8B_BPALCD37_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1843	#define LCD_WF8B_BPALCD36_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1844	#define LCD_WF8B_BPALCD36_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1845	#define LCD_WF8B_BPALCD4_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1846	#define LCD_WF8B_BPALCD4_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1847	#define LCD_WF8B_BPALCD35_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1848	#define LCD_WF8B_BPALCD35_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1849	#define LCD_WF8B_BPALCD34_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1850	#define LCD_WF8B_BPALCD34_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1851	#define LCD_WF8B_BPALCD33_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1852	#define LCD_WF8B_BPALCD33_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1853	#define LCD_WF8B_BPALCD32_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1854	#define LCD_WF8B_BPALCD32_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1855	#define LCD_WF8B_BPALCD31_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1856	#define LCD_WF8B_BPALCD31_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1857	#define LCD_WF8B_BPALCD30_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1858	#define LCD_WF8B_BPALCD30_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1859	#define LCD_WF8B_BPALCD29_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1860	#define LCD_WF8B_BPALCD29_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1861	#define LCD_WF8B_BPALCD5_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1862	#define LCD_WF8B_BPALCD5_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1863	#define LCD_WF8B_BPALCD28_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1864	#define LCD_WF8B_BPALCD28_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1865	#define LCD_WF8B_BPALCD27_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1866	#define LCD_WF8B_BPALCD27_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1867	#define LCD_WF8B_BPALCD26_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1868	#define LCD_WF8B_BPALCD26_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1869	#define LCD_WF8B_BPALCD25_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1870	#define LCD_WF8B_BPALCD25_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1871	#define LCD_WF8B_BPALCD24_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1872	#define LCD_WF8B_BPALCD24_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1873	#define LCD_WF8B_BPALCD23_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1874	#define LCD_WF8B_BPALCD23_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1875	#define LCD_WF8B_BPALCD22_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1876	#define LCD_WF8B_BPALCD22_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1877	#define LCD_WF8B_BPALCD6_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1878	#define LCD_WF8B_BPALCD6_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1879	#define LCD_WF8B_BPALCD21_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1880	#define LCD_WF8B_BPALCD21_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1881	#define LCD_WF8B_BPALCD20_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1882	#define LCD_WF8B_BPALCD20_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1883	#define LCD_WF8B_BPALCD19_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1884	#define LCD_WF8B_BPALCD19_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1885	#define LCD_WF8B_BPALCD18_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1886	#define LCD_WF8B_BPALCD18_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1887	#define LCD_WF8B_BPALCD17_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1888	#define LCD_WF8B_BPALCD17_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1889	#define LCD_WF8B_BPALCD16_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1890	#define LCD_WF8B_BPALCD16_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1891	#define LCD_WF8B_BPALCD15_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1892	#define LCD_WF8B_BPALCD15_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1893	#define LCD_WF8B_BPALCD7_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1894	#define LCD_WF8B_BPALCD7_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1895	#define LCD_WF8B_BPALCD14_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1896	#define LCD_WF8B_BPALCD14_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1897	#define LCD_WF8B_BPALCD13_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1898	#define LCD_WF8B_BPALCD13_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1899	#define LCD_WF8B_BPALCD12_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1900	#define LCD_WF8B_BPALCD12_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1901	#define LCD_WF8B_BPALCD11_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1902	#define LCD_WF8B_BPALCD11_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1903	#define LCD_WF8B_BPALCD10_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1904	#define LCD_WF8B_BPALCD10_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1905	#define LCD_WF8B_BPALCD9_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1906	#define LCD_WF8B_BPALCD9_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1907	#define LCD_WF8B_BPALCD8_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	1908	#define LCD_WF8B_BPALCD8_SHIFT 0
Piasiv1206	4:ec3f71ef8732	1909	#define LCD_WF8B_BPBLCD1_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1910	#define LCD_WF8B_BPBLCD1_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1911	#define LCD_WF8B_BPBLCD32_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1912	#define LCD_WF8B_BPBLCD32_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1913	#define LCD_WF8B_BPBLCD30_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1914	#define LCD_WF8B_BPBLCD30_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1915	#define LCD_WF8B_BPBLCD60_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1916	#define LCD_WF8B_BPBLCD60_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1917	#define LCD_WF8B_BPBLCD24_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1918	#define LCD_WF8B_BPBLCD24_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1919	#define LCD_WF8B_BPBLCD28_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1920	#define LCD_WF8B_BPBLCD28_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1921	#define LCD_WF8B_BPBLCD23_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1922	#define LCD_WF8B_BPBLCD23_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1923	#define LCD_WF8B_BPBLCD48_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1924	#define LCD_WF8B_BPBLCD48_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1925	#define LCD_WF8B_BPBLCD10_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1926	#define LCD_WF8B_BPBLCD10_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1927	#define LCD_WF8B_BPBLCD15_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1928	#define LCD_WF8B_BPBLCD15_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1929	#define LCD_WF8B_BPBLCD36_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1930	#define LCD_WF8B_BPBLCD36_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1931	#define LCD_WF8B_BPBLCD44_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1932	#define LCD_WF8B_BPBLCD44_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1933	#define LCD_WF8B_BPBLCD62_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1934	#define LCD_WF8B_BPBLCD62_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1935	#define LCD_WF8B_BPBLCD53_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1936	#define LCD_WF8B_BPBLCD53_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1937	#define LCD_WF8B_BPBLCD22_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1938	#define LCD_WF8B_BPBLCD22_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1939	#define LCD_WF8B_BPBLCD47_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1940	#define LCD_WF8B_BPBLCD47_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1941	#define LCD_WF8B_BPBLCD33_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1942	#define LCD_WF8B_BPBLCD33_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1943	#define LCD_WF8B_BPBLCD2_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1944	#define LCD_WF8B_BPBLCD2_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1945	#define LCD_WF8B_BPBLCD49_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1946	#define LCD_WF8B_BPBLCD49_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1947	#define LCD_WF8B_BPBLCD0_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1948	#define LCD_WF8B_BPBLCD0_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1949	#define LCD_WF8B_BPBLCD55_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1950	#define LCD_WF8B_BPBLCD55_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1951	#define LCD_WF8B_BPBLCD56_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1952	#define LCD_WF8B_BPBLCD56_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1953	#define LCD_WF8B_BPBLCD21_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1954	#define LCD_WF8B_BPBLCD21_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1955	#define LCD_WF8B_BPBLCD6_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1956	#define LCD_WF8B_BPBLCD6_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1957	#define LCD_WF8B_BPBLCD29_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1958	#define LCD_WF8B_BPBLCD29_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1959	#define LCD_WF8B_BPBLCD25_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1960	#define LCD_WF8B_BPBLCD25_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1961	#define LCD_WF8B_BPBLCD8_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1962	#define LCD_WF8B_BPBLCD8_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1963	#define LCD_WF8B_BPBLCD54_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1964	#define LCD_WF8B_BPBLCD54_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1965	#define LCD_WF8B_BPBLCD38_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1966	#define LCD_WF8B_BPBLCD38_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1967	#define LCD_WF8B_BPBLCD43_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1968	#define LCD_WF8B_BPBLCD43_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1969	#define LCD_WF8B_BPBLCD20_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1970	#define LCD_WF8B_BPBLCD20_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1971	#define LCD_WF8B_BPBLCD9_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1972	#define LCD_WF8B_BPBLCD9_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1973	#define LCD_WF8B_BPBLCD7_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1974	#define LCD_WF8B_BPBLCD7_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1975	#define LCD_WF8B_BPBLCD50_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1976	#define LCD_WF8B_BPBLCD50_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1977	#define LCD_WF8B_BPBLCD40_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1978	#define LCD_WF8B_BPBLCD40_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1979	#define LCD_WF8B_BPBLCD63_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1980	#define LCD_WF8B_BPBLCD63_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1981	#define LCD_WF8B_BPBLCD26_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1982	#define LCD_WF8B_BPBLCD26_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1983	#define LCD_WF8B_BPBLCD12_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1984	#define LCD_WF8B_BPBLCD12_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1985	#define LCD_WF8B_BPBLCD19_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1986	#define LCD_WF8B_BPBLCD19_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1987	#define LCD_WF8B_BPBLCD34_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1988	#define LCD_WF8B_BPBLCD34_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1989	#define LCD_WF8B_BPBLCD39_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1990	#define LCD_WF8B_BPBLCD39_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1991	#define LCD_WF8B_BPBLCD59_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1992	#define LCD_WF8B_BPBLCD59_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1993	#define LCD_WF8B_BPBLCD61_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1994	#define LCD_WF8B_BPBLCD61_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1995	#define LCD_WF8B_BPBLCD37_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1996	#define LCD_WF8B_BPBLCD37_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1997	#define LCD_WF8B_BPBLCD31_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	1998	#define LCD_WF8B_BPBLCD31_SHIFT 1
Piasiv1206	4:ec3f71ef8732	1999	#define LCD_WF8B_BPBLCD58_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2000	#define LCD_WF8B_BPBLCD58_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2001	#define LCD_WF8B_BPBLCD18_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2002	#define LCD_WF8B_BPBLCD18_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2003	#define LCD_WF8B_BPBLCD45_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2004	#define LCD_WF8B_BPBLCD45_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2005	#define LCD_WF8B_BPBLCD27_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2006	#define LCD_WF8B_BPBLCD27_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2007	#define LCD_WF8B_BPBLCD14_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2008	#define LCD_WF8B_BPBLCD14_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2009	#define LCD_WF8B_BPBLCD51_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2010	#define LCD_WF8B_BPBLCD51_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2011	#define LCD_WF8B_BPBLCD52_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2012	#define LCD_WF8B_BPBLCD52_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2013	#define LCD_WF8B_BPBLCD4_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2014	#define LCD_WF8B_BPBLCD4_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2015	#define LCD_WF8B_BPBLCD35_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2016	#define LCD_WF8B_BPBLCD35_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2017	#define LCD_WF8B_BPBLCD17_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2018	#define LCD_WF8B_BPBLCD17_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2019	#define LCD_WF8B_BPBLCD41_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2020	#define LCD_WF8B_BPBLCD41_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2021	#define LCD_WF8B_BPBLCD11_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2022	#define LCD_WF8B_BPBLCD11_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2023	#define LCD_WF8B_BPBLCD46_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2024	#define LCD_WF8B_BPBLCD46_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2025	#define LCD_WF8B_BPBLCD57_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2026	#define LCD_WF8B_BPBLCD57_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2027	#define LCD_WF8B_BPBLCD42_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2028	#define LCD_WF8B_BPBLCD42_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2029	#define LCD_WF8B_BPBLCD5_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2030	#define LCD_WF8B_BPBLCD5_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2031	#define LCD_WF8B_BPBLCD3_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2032	#define LCD_WF8B_BPBLCD3_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2033	#define LCD_WF8B_BPBLCD16_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2034	#define LCD_WF8B_BPBLCD16_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2035	#define LCD_WF8B_BPBLCD13_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2036	#define LCD_WF8B_BPBLCD13_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2037	#define LCD_WF8B_BPCLCD10_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2038	#define LCD_WF8B_BPCLCD10_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2039	#define LCD_WF8B_BPCLCD55_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2040	#define LCD_WF8B_BPCLCD55_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2041	#define LCD_WF8B_BPCLCD2_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2042	#define LCD_WF8B_BPCLCD2_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2043	#define LCD_WF8B_BPCLCD23_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2044	#define LCD_WF8B_BPCLCD23_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2045	#define LCD_WF8B_BPCLCD48_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2046	#define LCD_WF8B_BPCLCD48_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2047	#define LCD_WF8B_BPCLCD24_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2048	#define LCD_WF8B_BPCLCD24_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2049	#define LCD_WF8B_BPCLCD60_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2050	#define LCD_WF8B_BPCLCD60_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2051	#define LCD_WF8B_BPCLCD47_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2052	#define LCD_WF8B_BPCLCD47_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2053	#define LCD_WF8B_BPCLCD22_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2054	#define LCD_WF8B_BPCLCD22_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2055	#define LCD_WF8B_BPCLCD8_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2056	#define LCD_WF8B_BPCLCD8_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2057	#define LCD_WF8B_BPCLCD21_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2058	#define LCD_WF8B_BPCLCD21_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2059	#define LCD_WF8B_BPCLCD49_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2060	#define LCD_WF8B_BPCLCD49_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2061	#define LCD_WF8B_BPCLCD25_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2062	#define LCD_WF8B_BPCLCD25_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2063	#define LCD_WF8B_BPCLCD1_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2064	#define LCD_WF8B_BPCLCD1_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2065	#define LCD_WF8B_BPCLCD20_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2066	#define LCD_WF8B_BPCLCD20_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2067	#define LCD_WF8B_BPCLCD50_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2068	#define LCD_WF8B_BPCLCD50_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2069	#define LCD_WF8B_BPCLCD19_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2070	#define LCD_WF8B_BPCLCD19_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2071	#define LCD_WF8B_BPCLCD26_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2072	#define LCD_WF8B_BPCLCD26_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2073	#define LCD_WF8B_BPCLCD59_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2074	#define LCD_WF8B_BPCLCD59_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2075	#define LCD_WF8B_BPCLCD61_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2076	#define LCD_WF8B_BPCLCD61_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2077	#define LCD_WF8B_BPCLCD46_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2078	#define LCD_WF8B_BPCLCD46_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2079	#define LCD_WF8B_BPCLCD18_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2080	#define LCD_WF8B_BPCLCD18_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2081	#define LCD_WF8B_BPCLCD5_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2082	#define LCD_WF8B_BPCLCD5_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2083	#define LCD_WF8B_BPCLCD63_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2084	#define LCD_WF8B_BPCLCD63_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2085	#define LCD_WF8B_BPCLCD27_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2086	#define LCD_WF8B_BPCLCD27_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2087	#define LCD_WF8B_BPCLCD17_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2088	#define LCD_WF8B_BPCLCD17_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2089	#define LCD_WF8B_BPCLCD51_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2090	#define LCD_WF8B_BPCLCD51_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2091	#define LCD_WF8B_BPCLCD9_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2092	#define LCD_WF8B_BPCLCD9_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2093	#define LCD_WF8B_BPCLCD54_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2094	#define LCD_WF8B_BPCLCD54_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2095	#define LCD_WF8B_BPCLCD15_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2096	#define LCD_WF8B_BPCLCD15_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2097	#define LCD_WF8B_BPCLCD16_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2098	#define LCD_WF8B_BPCLCD16_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2099	#define LCD_WF8B_BPCLCD14_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2100	#define LCD_WF8B_BPCLCD14_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2101	#define LCD_WF8B_BPCLCD32_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2102	#define LCD_WF8B_BPCLCD32_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2103	#define LCD_WF8B_BPCLCD28_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2104	#define LCD_WF8B_BPCLCD28_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2105	#define LCD_WF8B_BPCLCD53_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2106	#define LCD_WF8B_BPCLCD53_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2107	#define LCD_WF8B_BPCLCD33_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2108	#define LCD_WF8B_BPCLCD33_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2109	#define LCD_WF8B_BPCLCD0_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2110	#define LCD_WF8B_BPCLCD0_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2111	#define LCD_WF8B_BPCLCD43_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2112	#define LCD_WF8B_BPCLCD43_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2113	#define LCD_WF8B_BPCLCD7_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2114	#define LCD_WF8B_BPCLCD7_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2115	#define LCD_WF8B_BPCLCD4_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2116	#define LCD_WF8B_BPCLCD4_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2117	#define LCD_WF8B_BPCLCD34_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2118	#define LCD_WF8B_BPCLCD34_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2119	#define LCD_WF8B_BPCLCD29_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2120	#define LCD_WF8B_BPCLCD29_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2121	#define LCD_WF8B_BPCLCD45_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2122	#define LCD_WF8B_BPCLCD45_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2123	#define LCD_WF8B_BPCLCD57_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2124	#define LCD_WF8B_BPCLCD57_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2125	#define LCD_WF8B_BPCLCD42_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2126	#define LCD_WF8B_BPCLCD42_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2127	#define LCD_WF8B_BPCLCD35_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2128	#define LCD_WF8B_BPCLCD35_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2129	#define LCD_WF8B_BPCLCD13_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2130	#define LCD_WF8B_BPCLCD13_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2131	#define LCD_WF8B_BPCLCD36_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2132	#define LCD_WF8B_BPCLCD36_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2133	#define LCD_WF8B_BPCLCD30_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2134	#define LCD_WF8B_BPCLCD30_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2135	#define LCD_WF8B_BPCLCD52_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2136	#define LCD_WF8B_BPCLCD52_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2137	#define LCD_WF8B_BPCLCD58_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2138	#define LCD_WF8B_BPCLCD58_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2139	#define LCD_WF8B_BPCLCD41_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2140	#define LCD_WF8B_BPCLCD41_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2141	#define LCD_WF8B_BPCLCD37_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2142	#define LCD_WF8B_BPCLCD37_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2143	#define LCD_WF8B_BPCLCD3_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2144	#define LCD_WF8B_BPCLCD3_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2145	#define LCD_WF8B_BPCLCD12_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2146	#define LCD_WF8B_BPCLCD12_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2147	#define LCD_WF8B_BPCLCD11_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2148	#define LCD_WF8B_BPCLCD11_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2149	#define LCD_WF8B_BPCLCD38_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2150	#define LCD_WF8B_BPCLCD38_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2151	#define LCD_WF8B_BPCLCD44_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2152	#define LCD_WF8B_BPCLCD44_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2153	#define LCD_WF8B_BPCLCD31_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2154	#define LCD_WF8B_BPCLCD31_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2155	#define LCD_WF8B_BPCLCD40_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2156	#define LCD_WF8B_BPCLCD40_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2157	#define LCD_WF8B_BPCLCD62_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2158	#define LCD_WF8B_BPCLCD62_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2159	#define LCD_WF8B_BPCLCD56_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2160	#define LCD_WF8B_BPCLCD56_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2161	#define LCD_WF8B_BPCLCD39_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2162	#define LCD_WF8B_BPCLCD39_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2163	#define LCD_WF8B_BPCLCD6_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2164	#define LCD_WF8B_BPCLCD6_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2165	#define LCD_WF8B_BPDLCD47_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2166	#define LCD_WF8B_BPDLCD47_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2167	#define LCD_WF8B_BPDLCD23_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2168	#define LCD_WF8B_BPDLCD23_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2169	#define LCD_WF8B_BPDLCD48_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2170	#define LCD_WF8B_BPDLCD48_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2171	#define LCD_WF8B_BPDLCD24_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2172	#define LCD_WF8B_BPDLCD24_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2173	#define LCD_WF8B_BPDLCD15_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2174	#define LCD_WF8B_BPDLCD15_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2175	#define LCD_WF8B_BPDLCD22_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2176	#define LCD_WF8B_BPDLCD22_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2177	#define LCD_WF8B_BPDLCD60_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2178	#define LCD_WF8B_BPDLCD60_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2179	#define LCD_WF8B_BPDLCD10_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2180	#define LCD_WF8B_BPDLCD10_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2181	#define LCD_WF8B_BPDLCD21_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2182	#define LCD_WF8B_BPDLCD21_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2183	#define LCD_WF8B_BPDLCD49_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2184	#define LCD_WF8B_BPDLCD49_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2185	#define LCD_WF8B_BPDLCD1_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2186	#define LCD_WF8B_BPDLCD1_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2187	#define LCD_WF8B_BPDLCD25_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2188	#define LCD_WF8B_BPDLCD25_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2189	#define LCD_WF8B_BPDLCD20_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2190	#define LCD_WF8B_BPDLCD20_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2191	#define LCD_WF8B_BPDLCD2_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2192	#define LCD_WF8B_BPDLCD2_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2193	#define LCD_WF8B_BPDLCD55_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2194	#define LCD_WF8B_BPDLCD55_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2195	#define LCD_WF8B_BPDLCD59_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2196	#define LCD_WF8B_BPDLCD59_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2197	#define LCD_WF8B_BPDLCD5_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2198	#define LCD_WF8B_BPDLCD5_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2199	#define LCD_WF8B_BPDLCD19_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2200	#define LCD_WF8B_BPDLCD19_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2201	#define LCD_WF8B_BPDLCD6_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2202	#define LCD_WF8B_BPDLCD6_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2203	#define LCD_WF8B_BPDLCD26_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2204	#define LCD_WF8B_BPDLCD26_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2205	#define LCD_WF8B_BPDLCD0_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2206	#define LCD_WF8B_BPDLCD0_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2207	#define LCD_WF8B_BPDLCD50_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2208	#define LCD_WF8B_BPDLCD50_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2209	#define LCD_WF8B_BPDLCD46_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2210	#define LCD_WF8B_BPDLCD46_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2211	#define LCD_WF8B_BPDLCD18_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2212	#define LCD_WF8B_BPDLCD18_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2213	#define LCD_WF8B_BPDLCD61_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2214	#define LCD_WF8B_BPDLCD61_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2215	#define LCD_WF8B_BPDLCD9_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2216	#define LCD_WF8B_BPDLCD9_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2217	#define LCD_WF8B_BPDLCD17_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2218	#define LCD_WF8B_BPDLCD17_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2219	#define LCD_WF8B_BPDLCD27_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2220	#define LCD_WF8B_BPDLCD27_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2221	#define LCD_WF8B_BPDLCD53_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2222	#define LCD_WF8B_BPDLCD53_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2223	#define LCD_WF8B_BPDLCD51_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2224	#define LCD_WF8B_BPDLCD51_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2225	#define LCD_WF8B_BPDLCD54_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2226	#define LCD_WF8B_BPDLCD54_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2227	#define LCD_WF8B_BPDLCD13_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2228	#define LCD_WF8B_BPDLCD13_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2229	#define LCD_WF8B_BPDLCD16_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2230	#define LCD_WF8B_BPDLCD16_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2231	#define LCD_WF8B_BPDLCD32_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2232	#define LCD_WF8B_BPDLCD32_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2233	#define LCD_WF8B_BPDLCD14_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2234	#define LCD_WF8B_BPDLCD14_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2235	#define LCD_WF8B_BPDLCD28_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2236	#define LCD_WF8B_BPDLCD28_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2237	#define LCD_WF8B_BPDLCD43_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2238	#define LCD_WF8B_BPDLCD43_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2239	#define LCD_WF8B_BPDLCD4_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2240	#define LCD_WF8B_BPDLCD4_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2241	#define LCD_WF8B_BPDLCD45_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2242	#define LCD_WF8B_BPDLCD45_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2243	#define LCD_WF8B_BPDLCD8_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2244	#define LCD_WF8B_BPDLCD8_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2245	#define LCD_WF8B_BPDLCD62_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2246	#define LCD_WF8B_BPDLCD62_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2247	#define LCD_WF8B_BPDLCD33_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2248	#define LCD_WF8B_BPDLCD33_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2249	#define LCD_WF8B_BPDLCD34_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2250	#define LCD_WF8B_BPDLCD34_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2251	#define LCD_WF8B_BPDLCD29_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2252	#define LCD_WF8B_BPDLCD29_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2253	#define LCD_WF8B_BPDLCD58_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2254	#define LCD_WF8B_BPDLCD58_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2255	#define LCD_WF8B_BPDLCD57_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2256	#define LCD_WF8B_BPDLCD57_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2257	#define LCD_WF8B_BPDLCD42_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2258	#define LCD_WF8B_BPDLCD42_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2259	#define LCD_WF8B_BPDLCD35_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2260	#define LCD_WF8B_BPDLCD35_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2261	#define LCD_WF8B_BPDLCD52_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2262	#define LCD_WF8B_BPDLCD52_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2263	#define LCD_WF8B_BPDLCD7_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2264	#define LCD_WF8B_BPDLCD7_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2265	#define LCD_WF8B_BPDLCD36_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2266	#define LCD_WF8B_BPDLCD36_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2267	#define LCD_WF8B_BPDLCD30_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2268	#define LCD_WF8B_BPDLCD30_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2269	#define LCD_WF8B_BPDLCD41_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2270	#define LCD_WF8B_BPDLCD41_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2271	#define LCD_WF8B_BPDLCD37_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2272	#define LCD_WF8B_BPDLCD37_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2273	#define LCD_WF8B_BPDLCD44_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2274	#define LCD_WF8B_BPDLCD44_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2275	#define LCD_WF8B_BPDLCD63_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2276	#define LCD_WF8B_BPDLCD63_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2277	#define LCD_WF8B_BPDLCD38_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2278	#define LCD_WF8B_BPDLCD38_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2279	#define LCD_WF8B_BPDLCD56_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2280	#define LCD_WF8B_BPDLCD56_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2281	#define LCD_WF8B_BPDLCD40_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2282	#define LCD_WF8B_BPDLCD40_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2283	#define LCD_WF8B_BPDLCD31_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2284	#define LCD_WF8B_BPDLCD31_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2285	#define LCD_WF8B_BPDLCD12_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2286	#define LCD_WF8B_BPDLCD12_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2287	#define LCD_WF8B_BPDLCD39_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2288	#define LCD_WF8B_BPDLCD39_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2289	#define LCD_WF8B_BPDLCD3_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2290	#define LCD_WF8B_BPDLCD3_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2291	#define LCD_WF8B_BPDLCD11_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2292	#define LCD_WF8B_BPDLCD11_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2293	#define LCD_WF8B_BPELCD12_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2294	#define LCD_WF8B_BPELCD12_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2295	#define LCD_WF8B_BPELCD39_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2296	#define LCD_WF8B_BPELCD39_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2297	#define LCD_WF8B_BPELCD3_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2298	#define LCD_WF8B_BPELCD3_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2299	#define LCD_WF8B_BPELCD38_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2300	#define LCD_WF8B_BPELCD38_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2301	#define LCD_WF8B_BPELCD40_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2302	#define LCD_WF8B_BPELCD40_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2303	#define LCD_WF8B_BPELCD37_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2304	#define LCD_WF8B_BPELCD37_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2305	#define LCD_WF8B_BPELCD41_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2306	#define LCD_WF8B_BPELCD41_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2307	#define LCD_WF8B_BPELCD36_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2308	#define LCD_WF8B_BPELCD36_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2309	#define LCD_WF8B_BPELCD8_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2310	#define LCD_WF8B_BPELCD8_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2311	#define LCD_WF8B_BPELCD35_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2312	#define LCD_WF8B_BPELCD35_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2313	#define LCD_WF8B_BPELCD42_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2314	#define LCD_WF8B_BPELCD42_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2315	#define LCD_WF8B_BPELCD34_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2316	#define LCD_WF8B_BPELCD34_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2317	#define LCD_WF8B_BPELCD33_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2318	#define LCD_WF8B_BPELCD33_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2319	#define LCD_WF8B_BPELCD11_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2320	#define LCD_WF8B_BPELCD11_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2321	#define LCD_WF8B_BPELCD43_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2322	#define LCD_WF8B_BPELCD43_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2323	#define LCD_WF8B_BPELCD32_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2324	#define LCD_WF8B_BPELCD32_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2325	#define LCD_WF8B_BPELCD31_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2326	#define LCD_WF8B_BPELCD31_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2327	#define LCD_WF8B_BPELCD44_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2328	#define LCD_WF8B_BPELCD44_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2329	#define LCD_WF8B_BPELCD30_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2330	#define LCD_WF8B_BPELCD30_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2331	#define LCD_WF8B_BPELCD29_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2332	#define LCD_WF8B_BPELCD29_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2333	#define LCD_WF8B_BPELCD7_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2334	#define LCD_WF8B_BPELCD7_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2335	#define LCD_WF8B_BPELCD45_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2336	#define LCD_WF8B_BPELCD45_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2337	#define LCD_WF8B_BPELCD28_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2338	#define LCD_WF8B_BPELCD28_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2339	#define LCD_WF8B_BPELCD2_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2340	#define LCD_WF8B_BPELCD2_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2341	#define LCD_WF8B_BPELCD27_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2342	#define LCD_WF8B_BPELCD27_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2343	#define LCD_WF8B_BPELCD46_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2344	#define LCD_WF8B_BPELCD46_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2345	#define LCD_WF8B_BPELCD26_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2346	#define LCD_WF8B_BPELCD26_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2347	#define LCD_WF8B_BPELCD10_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2348	#define LCD_WF8B_BPELCD10_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2349	#define LCD_WF8B_BPELCD13_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2350	#define LCD_WF8B_BPELCD13_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2351	#define LCD_WF8B_BPELCD25_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2352	#define LCD_WF8B_BPELCD25_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2353	#define LCD_WF8B_BPELCD5_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2354	#define LCD_WF8B_BPELCD5_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2355	#define LCD_WF8B_BPELCD24_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2356	#define LCD_WF8B_BPELCD24_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2357	#define LCD_WF8B_BPELCD47_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2358	#define LCD_WF8B_BPELCD47_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2359	#define LCD_WF8B_BPELCD23_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2360	#define LCD_WF8B_BPELCD23_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2361	#define LCD_WF8B_BPELCD22_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2362	#define LCD_WF8B_BPELCD22_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2363	#define LCD_WF8B_BPELCD48_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2364	#define LCD_WF8B_BPELCD48_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2365	#define LCD_WF8B_BPELCD21_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2366	#define LCD_WF8B_BPELCD21_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2367	#define LCD_WF8B_BPELCD49_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2368	#define LCD_WF8B_BPELCD49_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2369	#define LCD_WF8B_BPELCD20_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2370	#define LCD_WF8B_BPELCD20_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2371	#define LCD_WF8B_BPELCD19_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2372	#define LCD_WF8B_BPELCD19_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2373	#define LCD_WF8B_BPELCD9_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2374	#define LCD_WF8B_BPELCD9_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2375	#define LCD_WF8B_BPELCD50_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2376	#define LCD_WF8B_BPELCD50_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2377	#define LCD_WF8B_BPELCD18_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2378	#define LCD_WF8B_BPELCD18_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2379	#define LCD_WF8B_BPELCD6_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2380	#define LCD_WF8B_BPELCD6_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2381	#define LCD_WF8B_BPELCD17_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2382	#define LCD_WF8B_BPELCD17_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2383	#define LCD_WF8B_BPELCD51_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2384	#define LCD_WF8B_BPELCD51_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2385	#define LCD_WF8B_BPELCD16_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2386	#define LCD_WF8B_BPELCD16_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2387	#define LCD_WF8B_BPELCD56_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2388	#define LCD_WF8B_BPELCD56_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2389	#define LCD_WF8B_BPELCD57_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2390	#define LCD_WF8B_BPELCD57_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2391	#define LCD_WF8B_BPELCD52_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2392	#define LCD_WF8B_BPELCD52_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2393	#define LCD_WF8B_BPELCD1_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2394	#define LCD_WF8B_BPELCD1_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2395	#define LCD_WF8B_BPELCD58_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2396	#define LCD_WF8B_BPELCD58_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2397	#define LCD_WF8B_BPELCD59_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2398	#define LCD_WF8B_BPELCD59_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2399	#define LCD_WF8B_BPELCD53_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2400	#define LCD_WF8B_BPELCD53_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2401	#define LCD_WF8B_BPELCD14_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2402	#define LCD_WF8B_BPELCD14_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2403	#define LCD_WF8B_BPELCD0_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2404	#define LCD_WF8B_BPELCD0_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2405	#define LCD_WF8B_BPELCD60_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2406	#define LCD_WF8B_BPELCD60_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2407	#define LCD_WF8B_BPELCD15_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2408	#define LCD_WF8B_BPELCD15_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2409	#define LCD_WF8B_BPELCD61_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2410	#define LCD_WF8B_BPELCD61_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2411	#define LCD_WF8B_BPELCD54_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2412	#define LCD_WF8B_BPELCD54_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2413	#define LCD_WF8B_BPELCD62_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2414	#define LCD_WF8B_BPELCD62_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2415	#define LCD_WF8B_BPELCD63_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2416	#define LCD_WF8B_BPELCD63_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2417	#define LCD_WF8B_BPELCD55_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2418	#define LCD_WF8B_BPELCD55_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2419	#define LCD_WF8B_BPELCD4_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2420	#define LCD_WF8B_BPELCD4_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2421	#define LCD_WF8B_BPFLCD13_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2422	#define LCD_WF8B_BPFLCD13_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2423	#define LCD_WF8B_BPFLCD39_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2424	#define LCD_WF8B_BPFLCD39_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2425	#define LCD_WF8B_BPFLCD55_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2426	#define LCD_WF8B_BPFLCD55_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2427	#define LCD_WF8B_BPFLCD47_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2428	#define LCD_WF8B_BPFLCD47_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2429	#define LCD_WF8B_BPFLCD63_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2430	#define LCD_WF8B_BPFLCD63_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2431	#define LCD_WF8B_BPFLCD43_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2432	#define LCD_WF8B_BPFLCD43_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2433	#define LCD_WF8B_BPFLCD5_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2434	#define LCD_WF8B_BPFLCD5_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2435	#define LCD_WF8B_BPFLCD62_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2436	#define LCD_WF8B_BPFLCD62_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2437	#define LCD_WF8B_BPFLCD14_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2438	#define LCD_WF8B_BPFLCD14_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2439	#define LCD_WF8B_BPFLCD24_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2440	#define LCD_WF8B_BPFLCD24_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2441	#define LCD_WF8B_BPFLCD54_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2442	#define LCD_WF8B_BPFLCD54_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2443	#define LCD_WF8B_BPFLCD15_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2444	#define LCD_WF8B_BPFLCD15_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2445	#define LCD_WF8B_BPFLCD32_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2446	#define LCD_WF8B_BPFLCD32_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2447	#define LCD_WF8B_BPFLCD61_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2448	#define LCD_WF8B_BPFLCD61_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2449	#define LCD_WF8B_BPFLCD25_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2450	#define LCD_WF8B_BPFLCD25_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2451	#define LCD_WF8B_BPFLCD60_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2452	#define LCD_WF8B_BPFLCD60_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2453	#define LCD_WF8B_BPFLCD41_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2454	#define LCD_WF8B_BPFLCD41_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2455	#define LCD_WF8B_BPFLCD33_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2456	#define LCD_WF8B_BPFLCD33_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2457	#define LCD_WF8B_BPFLCD53_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2458	#define LCD_WF8B_BPFLCD53_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2459	#define LCD_WF8B_BPFLCD59_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2460	#define LCD_WF8B_BPFLCD59_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2461	#define LCD_WF8B_BPFLCD0_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2462	#define LCD_WF8B_BPFLCD0_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2463	#define LCD_WF8B_BPFLCD46_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2464	#define LCD_WF8B_BPFLCD46_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2465	#define LCD_WF8B_BPFLCD58_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2466	#define LCD_WF8B_BPFLCD58_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2467	#define LCD_WF8B_BPFLCD26_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2468	#define LCD_WF8B_BPFLCD26_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2469	#define LCD_WF8B_BPFLCD36_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2470	#define LCD_WF8B_BPFLCD36_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2471	#define LCD_WF8B_BPFLCD10_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2472	#define LCD_WF8B_BPFLCD10_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2473	#define LCD_WF8B_BPFLCD52_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2474	#define LCD_WF8B_BPFLCD52_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2475	#define LCD_WF8B_BPFLCD57_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2476	#define LCD_WF8B_BPFLCD57_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2477	#define LCD_WF8B_BPFLCD27_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2478	#define LCD_WF8B_BPFLCD27_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2479	#define LCD_WF8B_BPFLCD11_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2480	#define LCD_WF8B_BPFLCD11_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2481	#define LCD_WF8B_BPFLCD56_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2482	#define LCD_WF8B_BPFLCD56_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2483	#define LCD_WF8B_BPFLCD1_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2484	#define LCD_WF8B_BPFLCD1_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2485	#define LCD_WF8B_BPFLCD8_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2486	#define LCD_WF8B_BPFLCD8_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2487	#define LCD_WF8B_BPFLCD40_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2488	#define LCD_WF8B_BPFLCD40_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2489	#define LCD_WF8B_BPFLCD51_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2490	#define LCD_WF8B_BPFLCD51_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2491	#define LCD_WF8B_BPFLCD16_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2492	#define LCD_WF8B_BPFLCD16_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2493	#define LCD_WF8B_BPFLCD45_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2494	#define LCD_WF8B_BPFLCD45_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2495	#define LCD_WF8B_BPFLCD6_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2496	#define LCD_WF8B_BPFLCD6_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2497	#define LCD_WF8B_BPFLCD17_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2498	#define LCD_WF8B_BPFLCD17_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2499	#define LCD_WF8B_BPFLCD28_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2500	#define LCD_WF8B_BPFLCD28_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2501	#define LCD_WF8B_BPFLCD42_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2502	#define LCD_WF8B_BPFLCD42_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2503	#define LCD_WF8B_BPFLCD29_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2504	#define LCD_WF8B_BPFLCD29_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2505	#define LCD_WF8B_BPFLCD50_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2506	#define LCD_WF8B_BPFLCD50_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2507	#define LCD_WF8B_BPFLCD18_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2508	#define LCD_WF8B_BPFLCD18_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2509	#define LCD_WF8B_BPFLCD34_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2510	#define LCD_WF8B_BPFLCD34_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2511	#define LCD_WF8B_BPFLCD19_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2512	#define LCD_WF8B_BPFLCD19_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2513	#define LCD_WF8B_BPFLCD2_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2514	#define LCD_WF8B_BPFLCD2_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2515	#define LCD_WF8B_BPFLCD9_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2516	#define LCD_WF8B_BPFLCD9_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2517	#define LCD_WF8B_BPFLCD3_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2518	#define LCD_WF8B_BPFLCD3_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2519	#define LCD_WF8B_BPFLCD37_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2520	#define LCD_WF8B_BPFLCD37_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2521	#define LCD_WF8B_BPFLCD49_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2522	#define LCD_WF8B_BPFLCD49_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2523	#define LCD_WF8B_BPFLCD20_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2524	#define LCD_WF8B_BPFLCD20_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2525	#define LCD_WF8B_BPFLCD44_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2526	#define LCD_WF8B_BPFLCD44_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2527	#define LCD_WF8B_BPFLCD30_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2528	#define LCD_WF8B_BPFLCD30_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2529	#define LCD_WF8B_BPFLCD21_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2530	#define LCD_WF8B_BPFLCD21_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2531	#define LCD_WF8B_BPFLCD35_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2532	#define LCD_WF8B_BPFLCD35_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2533	#define LCD_WF8B_BPFLCD4_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2534	#define LCD_WF8B_BPFLCD4_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2535	#define LCD_WF8B_BPFLCD31_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2536	#define LCD_WF8B_BPFLCD31_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2537	#define LCD_WF8B_BPFLCD48_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2538	#define LCD_WF8B_BPFLCD48_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2539	#define LCD_WF8B_BPFLCD7_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2540	#define LCD_WF8B_BPFLCD7_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2541	#define LCD_WF8B_BPFLCD22_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2542	#define LCD_WF8B_BPFLCD22_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2543	#define LCD_WF8B_BPFLCD38_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2544	#define LCD_WF8B_BPFLCD38_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2545	#define LCD_WF8B_BPFLCD12_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2546	#define LCD_WF8B_BPFLCD12_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2547	#define LCD_WF8B_BPFLCD23_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2548	#define LCD_WF8B_BPFLCD23_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2549	#define LCD_WF8B_BPGLCD14_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2550	#define LCD_WF8B_BPGLCD14_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2551	#define LCD_WF8B_BPGLCD55_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2552	#define LCD_WF8B_BPGLCD55_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2553	#define LCD_WF8B_BPGLCD63_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2554	#define LCD_WF8B_BPGLCD63_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2555	#define LCD_WF8B_BPGLCD15_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2556	#define LCD_WF8B_BPGLCD15_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2557	#define LCD_WF8B_BPGLCD62_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2558	#define LCD_WF8B_BPGLCD62_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2559	#define LCD_WF8B_BPGLCD54_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2560	#define LCD_WF8B_BPGLCD54_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2561	#define LCD_WF8B_BPGLCD61_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2562	#define LCD_WF8B_BPGLCD61_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2563	#define LCD_WF8B_BPGLCD60_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2564	#define LCD_WF8B_BPGLCD60_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2565	#define LCD_WF8B_BPGLCD59_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2566	#define LCD_WF8B_BPGLCD59_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2567	#define LCD_WF8B_BPGLCD53_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2568	#define LCD_WF8B_BPGLCD53_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2569	#define LCD_WF8B_BPGLCD58_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2570	#define LCD_WF8B_BPGLCD58_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2571	#define LCD_WF8B_BPGLCD0_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2572	#define LCD_WF8B_BPGLCD0_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2573	#define LCD_WF8B_BPGLCD57_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2574	#define LCD_WF8B_BPGLCD57_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2575	#define LCD_WF8B_BPGLCD52_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2576	#define LCD_WF8B_BPGLCD52_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2577	#define LCD_WF8B_BPGLCD7_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2578	#define LCD_WF8B_BPGLCD7_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2579	#define LCD_WF8B_BPGLCD56_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2580	#define LCD_WF8B_BPGLCD56_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2581	#define LCD_WF8B_BPGLCD6_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2582	#define LCD_WF8B_BPGLCD6_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2583	#define LCD_WF8B_BPGLCD51_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2584	#define LCD_WF8B_BPGLCD51_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2585	#define LCD_WF8B_BPGLCD16_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2586	#define LCD_WF8B_BPGLCD16_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2587	#define LCD_WF8B_BPGLCD1_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2588	#define LCD_WF8B_BPGLCD1_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2589	#define LCD_WF8B_BPGLCD17_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2590	#define LCD_WF8B_BPGLCD17_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2591	#define LCD_WF8B_BPGLCD50_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2592	#define LCD_WF8B_BPGLCD50_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2593	#define LCD_WF8B_BPGLCD18_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2594	#define LCD_WF8B_BPGLCD18_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2595	#define LCD_WF8B_BPGLCD19_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2596	#define LCD_WF8B_BPGLCD19_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2597	#define LCD_WF8B_BPGLCD8_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2598	#define LCD_WF8B_BPGLCD8_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2599	#define LCD_WF8B_BPGLCD49_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2600	#define LCD_WF8B_BPGLCD49_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2601	#define LCD_WF8B_BPGLCD20_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2602	#define LCD_WF8B_BPGLCD20_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2603	#define LCD_WF8B_BPGLCD9_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2604	#define LCD_WF8B_BPGLCD9_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2605	#define LCD_WF8B_BPGLCD21_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2606	#define LCD_WF8B_BPGLCD21_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2607	#define LCD_WF8B_BPGLCD13_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2608	#define LCD_WF8B_BPGLCD13_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2609	#define LCD_WF8B_BPGLCD48_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2610	#define LCD_WF8B_BPGLCD48_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2611	#define LCD_WF8B_BPGLCD22_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2612	#define LCD_WF8B_BPGLCD22_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2613	#define LCD_WF8B_BPGLCD5_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2614	#define LCD_WF8B_BPGLCD5_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2615	#define LCD_WF8B_BPGLCD47_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2616	#define LCD_WF8B_BPGLCD47_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2617	#define LCD_WF8B_BPGLCD23_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2618	#define LCD_WF8B_BPGLCD23_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2619	#define LCD_WF8B_BPGLCD24_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2620	#define LCD_WF8B_BPGLCD24_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2621	#define LCD_WF8B_BPGLCD25_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2622	#define LCD_WF8B_BPGLCD25_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2623	#define LCD_WF8B_BPGLCD46_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2624	#define LCD_WF8B_BPGLCD46_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2625	#define LCD_WF8B_BPGLCD26_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2626	#define LCD_WF8B_BPGLCD26_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2627	#define LCD_WF8B_BPGLCD27_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2628	#define LCD_WF8B_BPGLCD27_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2629	#define LCD_WF8B_BPGLCD10_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2630	#define LCD_WF8B_BPGLCD10_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2631	#define LCD_WF8B_BPGLCD45_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2632	#define LCD_WF8B_BPGLCD45_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2633	#define LCD_WF8B_BPGLCD28_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2634	#define LCD_WF8B_BPGLCD28_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2635	#define LCD_WF8B_BPGLCD29_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2636	#define LCD_WF8B_BPGLCD29_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2637	#define LCD_WF8B_BPGLCD4_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2638	#define LCD_WF8B_BPGLCD4_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2639	#define LCD_WF8B_BPGLCD44_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2640	#define LCD_WF8B_BPGLCD44_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2641	#define LCD_WF8B_BPGLCD30_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2642	#define LCD_WF8B_BPGLCD30_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2643	#define LCD_WF8B_BPGLCD2_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2644	#define LCD_WF8B_BPGLCD2_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2645	#define LCD_WF8B_BPGLCD31_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2646	#define LCD_WF8B_BPGLCD31_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2647	#define LCD_WF8B_BPGLCD43_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2648	#define LCD_WF8B_BPGLCD43_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2649	#define LCD_WF8B_BPGLCD32_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2650	#define LCD_WF8B_BPGLCD32_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2651	#define LCD_WF8B_BPGLCD33_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2652	#define LCD_WF8B_BPGLCD33_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2653	#define LCD_WF8B_BPGLCD42_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2654	#define LCD_WF8B_BPGLCD42_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2655	#define LCD_WF8B_BPGLCD34_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2656	#define LCD_WF8B_BPGLCD34_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2657	#define LCD_WF8B_BPGLCD11_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2658	#define LCD_WF8B_BPGLCD11_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2659	#define LCD_WF8B_BPGLCD35_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2660	#define LCD_WF8B_BPGLCD35_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2661	#define LCD_WF8B_BPGLCD12_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2662	#define LCD_WF8B_BPGLCD12_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2663	#define LCD_WF8B_BPGLCD41_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2664	#define LCD_WF8B_BPGLCD41_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2665	#define LCD_WF8B_BPGLCD36_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2666	#define LCD_WF8B_BPGLCD36_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2667	#define LCD_WF8B_BPGLCD3_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2668	#define LCD_WF8B_BPGLCD3_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2669	#define LCD_WF8B_BPGLCD37_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2670	#define LCD_WF8B_BPGLCD37_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2671	#define LCD_WF8B_BPGLCD40_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2672	#define LCD_WF8B_BPGLCD40_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2673	#define LCD_WF8B_BPGLCD38_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2674	#define LCD_WF8B_BPGLCD38_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2675	#define LCD_WF8B_BPGLCD39_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2676	#define LCD_WF8B_BPGLCD39_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2677	#define LCD_WF8B_BPHLCD63_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2678	#define LCD_WF8B_BPHLCD63_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2679	#define LCD_WF8B_BPHLCD62_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2680	#define LCD_WF8B_BPHLCD62_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2681	#define LCD_WF8B_BPHLCD61_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2682	#define LCD_WF8B_BPHLCD61_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2683	#define LCD_WF8B_BPHLCD60_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2684	#define LCD_WF8B_BPHLCD60_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2685	#define LCD_WF8B_BPHLCD59_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2686	#define LCD_WF8B_BPHLCD59_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2687	#define LCD_WF8B_BPHLCD58_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2688	#define LCD_WF8B_BPHLCD58_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2689	#define LCD_WF8B_BPHLCD57_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2690	#define LCD_WF8B_BPHLCD57_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2691	#define LCD_WF8B_BPHLCD0_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2692	#define LCD_WF8B_BPHLCD0_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2693	#define LCD_WF8B_BPHLCD56_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2694	#define LCD_WF8B_BPHLCD56_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2695	#define LCD_WF8B_BPHLCD55_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2696	#define LCD_WF8B_BPHLCD55_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2697	#define LCD_WF8B_BPHLCD54_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2698	#define LCD_WF8B_BPHLCD54_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2699	#define LCD_WF8B_BPHLCD53_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2700	#define LCD_WF8B_BPHLCD53_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2701	#define LCD_WF8B_BPHLCD52_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2702	#define LCD_WF8B_BPHLCD52_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2703	#define LCD_WF8B_BPHLCD51_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2704	#define LCD_WF8B_BPHLCD51_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2705	#define LCD_WF8B_BPHLCD50_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2706	#define LCD_WF8B_BPHLCD50_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2707	#define LCD_WF8B_BPHLCD1_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2708	#define LCD_WF8B_BPHLCD1_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2709	#define LCD_WF8B_BPHLCD49_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2710	#define LCD_WF8B_BPHLCD49_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2711	#define LCD_WF8B_BPHLCD48_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2712	#define LCD_WF8B_BPHLCD48_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2713	#define LCD_WF8B_BPHLCD47_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2714	#define LCD_WF8B_BPHLCD47_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2715	#define LCD_WF8B_BPHLCD46_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2716	#define LCD_WF8B_BPHLCD46_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2717	#define LCD_WF8B_BPHLCD45_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2718	#define LCD_WF8B_BPHLCD45_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2719	#define LCD_WF8B_BPHLCD44_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2720	#define LCD_WF8B_BPHLCD44_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2721	#define LCD_WF8B_BPHLCD43_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2722	#define LCD_WF8B_BPHLCD43_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2723	#define LCD_WF8B_BPHLCD2_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2724	#define LCD_WF8B_BPHLCD2_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2725	#define LCD_WF8B_BPHLCD42_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2726	#define LCD_WF8B_BPHLCD42_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2727	#define LCD_WF8B_BPHLCD41_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2728	#define LCD_WF8B_BPHLCD41_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2729	#define LCD_WF8B_BPHLCD40_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2730	#define LCD_WF8B_BPHLCD40_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2731	#define LCD_WF8B_BPHLCD39_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2732	#define LCD_WF8B_BPHLCD39_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2733	#define LCD_WF8B_BPHLCD38_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2734	#define LCD_WF8B_BPHLCD38_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2735	#define LCD_WF8B_BPHLCD37_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2736	#define LCD_WF8B_BPHLCD37_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2737	#define LCD_WF8B_BPHLCD36_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2738	#define LCD_WF8B_BPHLCD36_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2739	#define LCD_WF8B_BPHLCD3_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2740	#define LCD_WF8B_BPHLCD3_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2741	#define LCD_WF8B_BPHLCD35_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2742	#define LCD_WF8B_BPHLCD35_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2743	#define LCD_WF8B_BPHLCD34_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2744	#define LCD_WF8B_BPHLCD34_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2745	#define LCD_WF8B_BPHLCD33_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2746	#define LCD_WF8B_BPHLCD33_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2747	#define LCD_WF8B_BPHLCD32_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2748	#define LCD_WF8B_BPHLCD32_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2749	#define LCD_WF8B_BPHLCD31_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2750	#define LCD_WF8B_BPHLCD31_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2751	#define LCD_WF8B_BPHLCD30_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2752	#define LCD_WF8B_BPHLCD30_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2753	#define LCD_WF8B_BPHLCD29_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2754	#define LCD_WF8B_BPHLCD29_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2755	#define LCD_WF8B_BPHLCD4_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2756	#define LCD_WF8B_BPHLCD4_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2757	#define LCD_WF8B_BPHLCD28_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2758	#define LCD_WF8B_BPHLCD28_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2759	#define LCD_WF8B_BPHLCD27_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2760	#define LCD_WF8B_BPHLCD27_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2761	#define LCD_WF8B_BPHLCD26_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2762	#define LCD_WF8B_BPHLCD26_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2763	#define LCD_WF8B_BPHLCD25_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2764	#define LCD_WF8B_BPHLCD25_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2765	#define LCD_WF8B_BPHLCD24_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2766	#define LCD_WF8B_BPHLCD24_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2767	#define LCD_WF8B_BPHLCD23_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2768	#define LCD_WF8B_BPHLCD23_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2769	#define LCD_WF8B_BPHLCD22_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2770	#define LCD_WF8B_BPHLCD22_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2771	#define LCD_WF8B_BPHLCD5_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2772	#define LCD_WF8B_BPHLCD5_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2773	#define LCD_WF8B_BPHLCD21_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2774	#define LCD_WF8B_BPHLCD21_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2775	#define LCD_WF8B_BPHLCD20_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2776	#define LCD_WF8B_BPHLCD20_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2777	#define LCD_WF8B_BPHLCD19_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2778	#define LCD_WF8B_BPHLCD19_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2779	#define LCD_WF8B_BPHLCD18_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2780	#define LCD_WF8B_BPHLCD18_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2781	#define LCD_WF8B_BPHLCD17_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2782	#define LCD_WF8B_BPHLCD17_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2783	#define LCD_WF8B_BPHLCD16_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2784	#define LCD_WF8B_BPHLCD16_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2785	#define LCD_WF8B_BPHLCD15_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2786	#define LCD_WF8B_BPHLCD15_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2787	#define LCD_WF8B_BPHLCD6_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2788	#define LCD_WF8B_BPHLCD6_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2789	#define LCD_WF8B_BPHLCD14_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2790	#define LCD_WF8B_BPHLCD14_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2791	#define LCD_WF8B_BPHLCD13_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2792	#define LCD_WF8B_BPHLCD13_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2793	#define LCD_WF8B_BPHLCD12_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2794	#define LCD_WF8B_BPHLCD12_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2795	#define LCD_WF8B_BPHLCD11_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2796	#define LCD_WF8B_BPHLCD11_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2797	#define LCD_WF8B_BPHLCD10_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2798	#define LCD_WF8B_BPHLCD10_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2799	#define LCD_WF8B_BPHLCD9_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2800	#define LCD_WF8B_BPHLCD9_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2801	#define LCD_WF8B_BPHLCD8_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2802	#define LCD_WF8B_BPHLCD8_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2803	#define LCD_WF8B_BPHLCD7_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2804	#define LCD_WF8B_BPHLCD7_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2805
Piasiv1206	4:ec3f71ef8732	2806	/*!
Piasiv1206	4:ec3f71ef8732	2807	* @}
Piasiv1206	4:ec3f71ef8732	2808	/ / end of group LCD_Register_Masks */
Piasiv1206	4:ec3f71ef8732	2809
Piasiv1206	4:ec3f71ef8732	2810
Piasiv1206	4:ec3f71ef8732	2811	/* LCD - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	2812	/** Peripheral LCD base address */
Piasiv1206	4:ec3f71ef8732	2813	#define LCD_BASE (0x40053000u)
Piasiv1206	4:ec3f71ef8732	2814	/** Peripheral LCD base pointer */
Piasiv1206	4:ec3f71ef8732	2815	#define LCD ((LCD_Type *)LCD_BASE)
Piasiv1206	4:ec3f71ef8732	2816	/** Array initializer of LCD peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	2817	#define LCD_BASES { LCD }
Piasiv1206	4:ec3f71ef8732	2818
Piasiv1206	4:ec3f71ef8732	2819	/*!
Piasiv1206	4:ec3f71ef8732	2820	* @}
Piasiv1206	4:ec3f71ef8732	2821	/ / end of group LCD_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	2822
Piasiv1206	4:ec3f71ef8732	2823
Piasiv1206	4:ec3f71ef8732	2824	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	2825	-- LLWU Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	2826	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	2827
Piasiv1206	4:ec3f71ef8732	2828	/*!
Piasiv1206	4:ec3f71ef8732	2829	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	2830	* @{
Piasiv1206	4:ec3f71ef8732	2831	*/
Piasiv1206	4:ec3f71ef8732	2832
Piasiv1206	4:ec3f71ef8732	2833	/** LLWU - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	2834	typedef struct {
Piasiv1206	4:ec3f71ef8732	2835	__IO uint8_t PE1; /*< LLWU Pin Enable 1 register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	2836	__IO uint8_t PE2; /*< LLWU Pin Enable 2 register, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	2837	__IO uint8_t PE3; /*< LLWU Pin Enable 3 register, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	2838	__IO uint8_t PE4; /*< LLWU Pin Enable 4 register, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	2839	__IO uint8_t ME; /*< LLWU Module Enable register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	2840	__IO uint8_t F1; /*< LLWU Flag 1 register, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	2841	__IO uint8_t F2; /*< LLWU Flag 2 register, offset: 0x6 /
Piasiv1206	4:ec3f71ef8732	2842	__I uint8_t F3; /*< LLWU Flag 3 register, offset: 0x7 /
Piasiv1206	4:ec3f71ef8732	2843	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	2844	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 register, offset: 0x9 /
Piasiv1206	4:ec3f71ef8732	2845	} LLWU_Type;
Piasiv1206	4:ec3f71ef8732	2846
Piasiv1206	4:ec3f71ef8732	2847	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	2848	-- LLWU Register Masks
Piasiv1206	4:ec3f71ef8732	2849	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	2850
Piasiv1206	4:ec3f71ef8732	2851	/*!
Piasiv1206	4:ec3f71ef8732	2852	* @addtogroup LLWU_Register_Masks LLWU Register Masks
Piasiv1206	4:ec3f71ef8732	2853	* @{
Piasiv1206	4:ec3f71ef8732	2854	*/
Piasiv1206	4:ec3f71ef8732	2855
Piasiv1206	4:ec3f71ef8732	2856	/* PE1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2857	#define LLWU_PE1_WUPE0_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	2858	#define LLWU_PE1_WUPE0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2859	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
Piasiv1206	4:ec3f71ef8732	2860	#define LLWU_PE1_WUPE1_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	2861	#define LLWU_PE1_WUPE1_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2862	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
Piasiv1206	4:ec3f71ef8732	2863	#define LLWU_PE1_WUPE2_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	2864	#define LLWU_PE1_WUPE2_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2865	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
Piasiv1206	4:ec3f71ef8732	2866	#define LLWU_PE1_WUPE3_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	2867	#define LLWU_PE1_WUPE3_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2868	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
Piasiv1206	4:ec3f71ef8732	2869	/* PE2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2870	#define LLWU_PE2_WUPE4_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	2871	#define LLWU_PE2_WUPE4_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2872	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
Piasiv1206	4:ec3f71ef8732	2873	#define LLWU_PE2_WUPE5_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	2874	#define LLWU_PE2_WUPE5_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2875	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
Piasiv1206	4:ec3f71ef8732	2876	#define LLWU_PE2_WUPE6_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	2877	#define LLWU_PE2_WUPE6_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2878	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
Piasiv1206	4:ec3f71ef8732	2879	#define LLWU_PE2_WUPE7_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	2880	#define LLWU_PE2_WUPE7_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2881	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
Piasiv1206	4:ec3f71ef8732	2882	/* PE3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2883	#define LLWU_PE3_WUPE8_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	2884	#define LLWU_PE3_WUPE8_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2885	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
Piasiv1206	4:ec3f71ef8732	2886	#define LLWU_PE3_WUPE9_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	2887	#define LLWU_PE3_WUPE9_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2888	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
Piasiv1206	4:ec3f71ef8732	2889	#define LLWU_PE3_WUPE10_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	2890	#define LLWU_PE3_WUPE10_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2891	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
Piasiv1206	4:ec3f71ef8732	2892	#define LLWU_PE3_WUPE11_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	2893	#define LLWU_PE3_WUPE11_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2894	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
Piasiv1206	4:ec3f71ef8732	2895	/* PE4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2896	#define LLWU_PE4_WUPE12_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	2897	#define LLWU_PE4_WUPE12_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2898	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
Piasiv1206	4:ec3f71ef8732	2899	#define LLWU_PE4_WUPE13_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	2900	#define LLWU_PE4_WUPE13_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2901	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
Piasiv1206	4:ec3f71ef8732	2902	#define LLWU_PE4_WUPE14_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	2903	#define LLWU_PE4_WUPE14_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2904	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
Piasiv1206	4:ec3f71ef8732	2905	#define LLWU_PE4_WUPE15_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	2906	#define LLWU_PE4_WUPE15_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2907	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
Piasiv1206	4:ec3f71ef8732	2908	/* ME Bit Fields */
Piasiv1206	4:ec3f71ef8732	2909	#define LLWU_ME_WUME0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	2910	#define LLWU_ME_WUME0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2911	#define LLWU_ME_WUME1_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2912	#define LLWU_ME_WUME1_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2913	#define LLWU_ME_WUME2_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2914	#define LLWU_ME_WUME2_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2915	#define LLWU_ME_WUME3_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2916	#define LLWU_ME_WUME3_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2917	#define LLWU_ME_WUME4_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2918	#define LLWU_ME_WUME4_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2919	#define LLWU_ME_WUME5_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2920	#define LLWU_ME_WUME5_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2921	#define LLWU_ME_WUME6_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2922	#define LLWU_ME_WUME6_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2923	#define LLWU_ME_WUME7_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2924	#define LLWU_ME_WUME7_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2925	/* F1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2926	#define LLWU_F1_WUF0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	2927	#define LLWU_F1_WUF0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2928	#define LLWU_F1_WUF1_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2929	#define LLWU_F1_WUF1_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2930	#define LLWU_F1_WUF2_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2931	#define LLWU_F1_WUF2_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2932	#define LLWU_F1_WUF3_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2933	#define LLWU_F1_WUF3_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2934	#define LLWU_F1_WUF4_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2935	#define LLWU_F1_WUF4_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2936	#define LLWU_F1_WUF5_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2937	#define LLWU_F1_WUF5_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2938	#define LLWU_F1_WUF6_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2939	#define LLWU_F1_WUF6_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2940	#define LLWU_F1_WUF7_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2941	#define LLWU_F1_WUF7_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2942	/* F2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2943	#define LLWU_F2_WUF8_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	2944	#define LLWU_F2_WUF8_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2945	#define LLWU_F2_WUF9_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2946	#define LLWU_F2_WUF9_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2947	#define LLWU_F2_WUF10_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2948	#define LLWU_F2_WUF10_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2949	#define LLWU_F2_WUF11_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2950	#define LLWU_F2_WUF11_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2951	#define LLWU_F2_WUF12_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2952	#define LLWU_F2_WUF12_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2953	#define LLWU_F2_WUF13_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2954	#define LLWU_F2_WUF13_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2955	#define LLWU_F2_WUF14_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2956	#define LLWU_F2_WUF14_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2957	#define LLWU_F2_WUF15_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2958	#define LLWU_F2_WUF15_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2959	/* F3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2960	#define LLWU_F3_MWUF0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	2961	#define LLWU_F3_MWUF0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2962	#define LLWU_F3_MWUF1_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	2963	#define LLWU_F3_MWUF1_SHIFT 1
Piasiv1206	4:ec3f71ef8732	2964	#define LLWU_F3_MWUF2_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	2965	#define LLWU_F3_MWUF2_SHIFT 2
Piasiv1206	4:ec3f71ef8732	2966	#define LLWU_F3_MWUF3_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	2967	#define LLWU_F3_MWUF3_SHIFT 3
Piasiv1206	4:ec3f71ef8732	2968	#define LLWU_F3_MWUF4_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	2969	#define LLWU_F3_MWUF4_SHIFT 4
Piasiv1206	4:ec3f71ef8732	2970	#define LLWU_F3_MWUF5_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	2971	#define LLWU_F3_MWUF5_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2972	#define LLWU_F3_MWUF6_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	2973	#define LLWU_F3_MWUF6_SHIFT 6
Piasiv1206	4:ec3f71ef8732	2974	#define LLWU_F3_MWUF7_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2975	#define LLWU_F3_MWUF7_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2976	/* FILT1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2977	#define LLWU_FILT1_FILTSEL_MASK 0xFu
Piasiv1206	4:ec3f71ef8732	2978	#define LLWU_FILT1_FILTSEL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2979	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
Piasiv1206	4:ec3f71ef8732	2980	#define LLWU_FILT1_FILTE_MASK 0x60u
Piasiv1206	4:ec3f71ef8732	2981	#define LLWU_FILT1_FILTE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2982	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
Piasiv1206	4:ec3f71ef8732	2983	#define LLWU_FILT1_FILTF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2984	#define LLWU_FILT1_FILTF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2985	/* FILT2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	2986	#define LLWU_FILT2_FILTSEL_MASK 0xFu
Piasiv1206	4:ec3f71ef8732	2987	#define LLWU_FILT2_FILTSEL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	2988	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
Piasiv1206	4:ec3f71ef8732	2989	#define LLWU_FILT2_FILTE_MASK 0x60u
Piasiv1206	4:ec3f71ef8732	2990	#define LLWU_FILT2_FILTE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	2991	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
Piasiv1206	4:ec3f71ef8732	2992	#define LLWU_FILT2_FILTF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	2993	#define LLWU_FILT2_FILTF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	2994
Piasiv1206	4:ec3f71ef8732	2995	/*!
Piasiv1206	4:ec3f71ef8732	2996	* @}
Piasiv1206	4:ec3f71ef8732	2997	/ / end of group LLWU_Register_Masks */
Piasiv1206	4:ec3f71ef8732	2998
Piasiv1206	4:ec3f71ef8732	2999
Piasiv1206	4:ec3f71ef8732	3000	/* LLWU - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3001	/** Peripheral LLWU base address */
Piasiv1206	4:ec3f71ef8732	3002	#define LLWU_BASE (0x4007C000u)
Piasiv1206	4:ec3f71ef8732	3003	/** Peripheral LLWU base pointer */
Piasiv1206	4:ec3f71ef8732	3004	#define LLWU ((LLWU_Type *)LLWU_BASE)
Piasiv1206	4:ec3f71ef8732	3005	/** Array initializer of LLWU peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3006	#define LLWU_BASES { LLWU }
Piasiv1206	4:ec3f71ef8732	3007
Piasiv1206	4:ec3f71ef8732	3008	/*!
Piasiv1206	4:ec3f71ef8732	3009	* @}
Piasiv1206	4:ec3f71ef8732	3010	/ / end of group LLWU_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3011
Piasiv1206	4:ec3f71ef8732	3012
Piasiv1206	4:ec3f71ef8732	3013	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3014	-- LPTMR Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3015	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3016
Piasiv1206	4:ec3f71ef8732	3017	/*!
Piasiv1206	4:ec3f71ef8732	3018	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3019	* @{
Piasiv1206	4:ec3f71ef8732	3020	*/
Piasiv1206	4:ec3f71ef8732	3021
Piasiv1206	4:ec3f71ef8732	3022	/** LPTMR - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3023	typedef struct {
Piasiv1206	4:ec3f71ef8732	3024	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	3025	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	3026	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	3027	__I uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	3028	} LPTMR_Type;
Piasiv1206	4:ec3f71ef8732	3029
Piasiv1206	4:ec3f71ef8732	3030	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3031	-- LPTMR Register Masks
Piasiv1206	4:ec3f71ef8732	3032	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3033
Piasiv1206	4:ec3f71ef8732	3034	/*!
Piasiv1206	4:ec3f71ef8732	3035	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
Piasiv1206	4:ec3f71ef8732	3036	* @{
Piasiv1206	4:ec3f71ef8732	3037	*/
Piasiv1206	4:ec3f71ef8732	3038
Piasiv1206	4:ec3f71ef8732	3039	/* CSR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3040	#define LPTMR_CSR_TEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3041	#define LPTMR_CSR_TEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3042	#define LPTMR_CSR_TMS_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3043	#define LPTMR_CSR_TMS_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3044	#define LPTMR_CSR_TFC_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3045	#define LPTMR_CSR_TFC_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3046	#define LPTMR_CSR_TPP_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	3047	#define LPTMR_CSR_TPP_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3048	#define LPTMR_CSR_TPS_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	3049	#define LPTMR_CSR_TPS_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3050	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
Piasiv1206	4:ec3f71ef8732	3051	#define LPTMR_CSR_TIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3052	#define LPTMR_CSR_TIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3053	#define LPTMR_CSR_TCF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3054	#define LPTMR_CSR_TCF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3055	/* PSR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3056	#define LPTMR_PSR_PCS_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	3057	#define LPTMR_PSR_PCS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3058	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
Piasiv1206	4:ec3f71ef8732	3059	#define LPTMR_PSR_PBYP_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3060	#define LPTMR_PSR_PBYP_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3061	#define LPTMR_PSR_PRESCALE_MASK 0x78u
Piasiv1206	4:ec3f71ef8732	3062	#define LPTMR_PSR_PRESCALE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3063	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
Piasiv1206	4:ec3f71ef8732	3064	/* CMR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3065	#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	3066	#define LPTMR_CMR_COMPARE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3067	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
Piasiv1206	4:ec3f71ef8732	3068	/* CNR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3069	#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	3070	#define LPTMR_CNR_COUNTER_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3071	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
Piasiv1206	4:ec3f71ef8732	3072
Piasiv1206	4:ec3f71ef8732	3073	/*!
Piasiv1206	4:ec3f71ef8732	3074	* @}
Piasiv1206	4:ec3f71ef8732	3075	/ / end of group LPTMR_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3076
Piasiv1206	4:ec3f71ef8732	3077
Piasiv1206	4:ec3f71ef8732	3078	/* LPTMR - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3079	/** Peripheral LPTMR0 base address */
Piasiv1206	4:ec3f71ef8732	3080	#define LPTMR0_BASE (0x40040000u)
Piasiv1206	4:ec3f71ef8732	3081	/** Peripheral LPTMR0 base pointer */
Piasiv1206	4:ec3f71ef8732	3082	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
Piasiv1206	4:ec3f71ef8732	3083	/** Array initializer of LPTMR peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3084	#define LPTMR_BASES { LPTMR0 }
Piasiv1206	4:ec3f71ef8732	3085
Piasiv1206	4:ec3f71ef8732	3086	/*!
Piasiv1206	4:ec3f71ef8732	3087	* @}
Piasiv1206	4:ec3f71ef8732	3088	/ / end of group LPTMR_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3089
Piasiv1206	4:ec3f71ef8732	3090
Piasiv1206	4:ec3f71ef8732	3091	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3092	-- MCG Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3093	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3094
Piasiv1206	4:ec3f71ef8732	3095	/*!
Piasiv1206	4:ec3f71ef8732	3096	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3097	* @{
Piasiv1206	4:ec3f71ef8732	3098	*/
Piasiv1206	4:ec3f71ef8732	3099
Piasiv1206	4:ec3f71ef8732	3100	/** MCG - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3101	typedef struct {
Piasiv1206	4:ec3f71ef8732	3102	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	3103	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	3104	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	3105	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	3106	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	3107	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	3108	__I uint8_t S; /*< MCG Status Register, offset: 0x6 /
Piasiv1206	4:ec3f71ef8732	3109	uint8_t RESERVED_0[1];
Piasiv1206	4:ec3f71ef8732	3110	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	3111	uint8_t RESERVED_1[1];
Piasiv1206	4:ec3f71ef8732	3112	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
Piasiv1206	4:ec3f71ef8732	3113	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
Piasiv1206	4:ec3f71ef8732	3114	__I uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	3115	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
Piasiv1206	4:ec3f71ef8732	3116	__I uint8_t C9; /*< MCG Control 9 Register, offset: 0xE /
Piasiv1206	4:ec3f71ef8732	3117	__I uint8_t C10; /*< MCG Control 10 Register, offset: 0xF /
Piasiv1206	4:ec3f71ef8732	3118	} MCG_Type;
Piasiv1206	4:ec3f71ef8732	3119
Piasiv1206	4:ec3f71ef8732	3120	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3121	-- MCG Register Masks
Piasiv1206	4:ec3f71ef8732	3122	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3123
Piasiv1206	4:ec3f71ef8732	3124	/*!
Piasiv1206	4:ec3f71ef8732	3125	* @addtogroup MCG_Register_Masks MCG Register Masks
Piasiv1206	4:ec3f71ef8732	3126	* @{
Piasiv1206	4:ec3f71ef8732	3127	*/
Piasiv1206	4:ec3f71ef8732	3128
Piasiv1206	4:ec3f71ef8732	3129	/* C1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3130	#define MCG_C1_IREFSTEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3131	#define MCG_C1_IREFSTEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3132	#define MCG_C1_IRCLKEN_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3133	#define MCG_C1_IRCLKEN_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3134	#define MCG_C1_IREFS_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3135	#define MCG_C1_IREFS_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3136	#define MCG_C1_FRDIV_MASK 0x38u
Piasiv1206	4:ec3f71ef8732	3137	#define MCG_C1_FRDIV_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3138	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
Piasiv1206	4:ec3f71ef8732	3139	#define MCG_C1_CLKS_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	3140	#define MCG_C1_CLKS_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3141	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
Piasiv1206	4:ec3f71ef8732	3142	/* C2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3143	#define MCG_C2_IRCS_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3144	#define MCG_C2_IRCS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3145	#define MCG_C2_LP_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3146	#define MCG_C2_LP_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3147	#define MCG_C2_EREFS0_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3148	#define MCG_C2_EREFS0_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3149	#define MCG_C2_HGO0_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	3150	#define MCG_C2_HGO0_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3151	#define MCG_C2_RANGE0_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	3152	#define MCG_C2_RANGE0_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3153	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
Piasiv1206	4:ec3f71ef8732	3154	#define MCG_C2_FCFTRIM_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3155	#define MCG_C2_FCFTRIM_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3156	#define MCG_C2_LOCRE0_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3157	#define MCG_C2_LOCRE0_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3158	/* C3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3159	#define MCG_C3_SCTRIM_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3160	#define MCG_C3_SCTRIM_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3161	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
Piasiv1206	4:ec3f71ef8732	3162	/* C4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3163	#define MCG_C4_SCFTRIM_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3164	#define MCG_C4_SCFTRIM_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3165	#define MCG_C4_FCTRIM_MASK 0x1Eu
Piasiv1206	4:ec3f71ef8732	3166	#define MCG_C4_FCTRIM_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3167	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
Piasiv1206	4:ec3f71ef8732	3168	#define MCG_C4_DRST_DRS_MASK 0x60u
Piasiv1206	4:ec3f71ef8732	3169	#define MCG_C4_DRST_DRS_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3170	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
Piasiv1206	4:ec3f71ef8732	3171	#define MCG_C4_DMX32_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3172	#define MCG_C4_DMX32_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3173	/* C5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3174	#define MCG_C5_PRDIV0_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	3175	#define MCG_C5_PRDIV0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3176	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
Piasiv1206	4:ec3f71ef8732	3177	#define MCG_C5_PLLSTEN0_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3178	#define MCG_C5_PLLSTEN0_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3179	#define MCG_C5_PLLCLKEN0_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3180	#define MCG_C5_PLLCLKEN0_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3181	/* C6 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3182	#define MCG_C6_VDIV0_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	3183	#define MCG_C6_VDIV0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3184	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
Piasiv1206	4:ec3f71ef8732	3185	#define MCG_C6_CME0_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3186	#define MCG_C6_CME0_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3187	#define MCG_C6_PLLS_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3188	#define MCG_C6_PLLS_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3189	#define MCG_C6_LOLIE0_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3190	#define MCG_C6_LOLIE0_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3191	/* S Bit Fields */
Piasiv1206	4:ec3f71ef8732	3192	#define MCG_S_IRCST_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3193	#define MCG_S_IRCST_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3194	#define MCG_S_OSCINIT0_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3195	#define MCG_S_OSCINIT0_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3196	#define MCG_S_CLKST_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	3197	#define MCG_S_CLKST_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3198	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
Piasiv1206	4:ec3f71ef8732	3199	#define MCG_S_IREFST_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	3200	#define MCG_S_IREFST_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3201	#define MCG_S_PLLST_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3202	#define MCG_S_PLLST_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3203	#define MCG_S_LOCK0_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3204	#define MCG_S_LOCK0_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3205	#define MCG_S_LOLS_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3206	#define MCG_S_LOLS_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3207	/* SC Bit Fields */
Piasiv1206	4:ec3f71ef8732	3208	#define MCG_SC_LOCS0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3209	#define MCG_SC_LOCS0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3210	#define MCG_SC_FCRDIV_MASK 0xEu
Piasiv1206	4:ec3f71ef8732	3211	#define MCG_SC_FCRDIV_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3212	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
Piasiv1206	4:ec3f71ef8732	3213	#define MCG_SC_FLTPRSRV_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	3214	#define MCG_SC_FLTPRSRV_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3215	#define MCG_SC_ATMF_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3216	#define MCG_SC_ATMF_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3217	#define MCG_SC_ATMS_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3218	#define MCG_SC_ATMS_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3219	#define MCG_SC_ATME_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3220	#define MCG_SC_ATME_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3221	/* ATCVH Bit Fields */
Piasiv1206	4:ec3f71ef8732	3222	#define MCG_ATCVH_ATCVH_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3223	#define MCG_ATCVH_ATCVH_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3224	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
Piasiv1206	4:ec3f71ef8732	3225	/* ATCVL Bit Fields */
Piasiv1206	4:ec3f71ef8732	3226	#define MCG_ATCVL_ATCVL_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3227	#define MCG_ATCVL_ATCVL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3228	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
Piasiv1206	4:ec3f71ef8732	3229	/* C8 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3230	#define MCG_C8_LOLRE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3231	#define MCG_C8_LOLRE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3232
Piasiv1206	4:ec3f71ef8732	3233	/*!
Piasiv1206	4:ec3f71ef8732	3234	* @}
Piasiv1206	4:ec3f71ef8732	3235	/ / end of group MCG_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3236
Piasiv1206	4:ec3f71ef8732	3237
Piasiv1206	4:ec3f71ef8732	3238	/* MCG - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3239	/** Peripheral MCG base address */
Piasiv1206	4:ec3f71ef8732	3240	#define MCG_BASE (0x40064000u)
Piasiv1206	4:ec3f71ef8732	3241	/** Peripheral MCG base pointer */
Piasiv1206	4:ec3f71ef8732	3242	#define MCG ((MCG_Type *)MCG_BASE)
Piasiv1206	4:ec3f71ef8732	3243	/** Array initializer of MCG peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3244	#define MCG_BASES { MCG }
Piasiv1206	4:ec3f71ef8732	3245
Piasiv1206	4:ec3f71ef8732	3246	/*!
Piasiv1206	4:ec3f71ef8732	3247	* @}
Piasiv1206	4:ec3f71ef8732	3248	/ / end of group MCG_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3249
Piasiv1206	4:ec3f71ef8732	3250
Piasiv1206	4:ec3f71ef8732	3251	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3252	-- MCM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3253	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3254
Piasiv1206	4:ec3f71ef8732	3255	/*!
Piasiv1206	4:ec3f71ef8732	3256	* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3257	* @{
Piasiv1206	4:ec3f71ef8732	3258	*/
Piasiv1206	4:ec3f71ef8732	3259
Piasiv1206	4:ec3f71ef8732	3260	/** MCM - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3261	typedef struct {
Piasiv1206	4:ec3f71ef8732	3262	uint8_t RESERVED_0[8];
Piasiv1206	4:ec3f71ef8732	3263	__I uint16_t PLASC; /*< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	3264	__I uint16_t PLAMC; /*< Crossbar Switch (AXBS) Master Configuration, offset: 0xA /
Piasiv1206	4:ec3f71ef8732	3265	__IO uint32_t PLACR; /*< Platform Control Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	3266	uint8_t RESERVED_1[48];
Piasiv1206	4:ec3f71ef8732	3267	__IO uint32_t CPO; /*< Compute Operation Control Register, offset: 0x40 /
Piasiv1206	4:ec3f71ef8732	3268	} MCM_Type;
Piasiv1206	4:ec3f71ef8732	3269
Piasiv1206	4:ec3f71ef8732	3270	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3271	-- MCM Register Masks
Piasiv1206	4:ec3f71ef8732	3272	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3273
Piasiv1206	4:ec3f71ef8732	3274	/*!
Piasiv1206	4:ec3f71ef8732	3275	* @addtogroup MCM_Register_Masks MCM Register Masks
Piasiv1206	4:ec3f71ef8732	3276	* @{
Piasiv1206	4:ec3f71ef8732	3277	*/
Piasiv1206	4:ec3f71ef8732	3278
Piasiv1206	4:ec3f71ef8732	3279	/* PLASC Bit Fields */
Piasiv1206	4:ec3f71ef8732	3280	#define MCM_PLASC_ASC_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3281	#define MCM_PLASC_ASC_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3282	#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
Piasiv1206	4:ec3f71ef8732	3283	/* PLAMC Bit Fields */
Piasiv1206	4:ec3f71ef8732	3284	#define MCM_PLAMC_AMC_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3285	#define MCM_PLAMC_AMC_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3286	#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
Piasiv1206	4:ec3f71ef8732	3287	/* PLACR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3288	#define MCM_PLACR_ARB_MASK 0x200u
Piasiv1206	4:ec3f71ef8732	3289	#define MCM_PLACR_ARB_SHIFT 9
Piasiv1206	4:ec3f71ef8732	3290	#define MCM_PLACR_CFCC_MASK 0x400u
Piasiv1206	4:ec3f71ef8732	3291	#define MCM_PLACR_CFCC_SHIFT 10
Piasiv1206	4:ec3f71ef8732	3292	#define MCM_PLACR_DFCDA_MASK 0x800u
Piasiv1206	4:ec3f71ef8732	3293	#define MCM_PLACR_DFCDA_SHIFT 11
Piasiv1206	4:ec3f71ef8732	3294	#define MCM_PLACR_DFCIC_MASK 0x1000u
Piasiv1206	4:ec3f71ef8732	3295	#define MCM_PLACR_DFCIC_SHIFT 12
Piasiv1206	4:ec3f71ef8732	3296	#define MCM_PLACR_DFCC_MASK 0x2000u
Piasiv1206	4:ec3f71ef8732	3297	#define MCM_PLACR_DFCC_SHIFT 13
Piasiv1206	4:ec3f71ef8732	3298	#define MCM_PLACR_EFDS_MASK 0x4000u
Piasiv1206	4:ec3f71ef8732	3299	#define MCM_PLACR_EFDS_SHIFT 14
Piasiv1206	4:ec3f71ef8732	3300	#define MCM_PLACR_DFCS_MASK 0x8000u
Piasiv1206	4:ec3f71ef8732	3301	#define MCM_PLACR_DFCS_SHIFT 15
Piasiv1206	4:ec3f71ef8732	3302	#define MCM_PLACR_ESFC_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	3303	#define MCM_PLACR_ESFC_SHIFT 16
Piasiv1206	4:ec3f71ef8732	3304	/* CPO Bit Fields */
Piasiv1206	4:ec3f71ef8732	3305	#define MCM_CPO_CPOREQ_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3306	#define MCM_CPO_CPOREQ_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3307	#define MCM_CPO_CPOACK_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3308	#define MCM_CPO_CPOACK_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3309	#define MCM_CPO_CPOWOI_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3310	#define MCM_CPO_CPOWOI_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3311
Piasiv1206	4:ec3f71ef8732	3312	/*!
Piasiv1206	4:ec3f71ef8732	3313	* @}
Piasiv1206	4:ec3f71ef8732	3314	/ / end of group MCM_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3315
Piasiv1206	4:ec3f71ef8732	3316
Piasiv1206	4:ec3f71ef8732	3317	/* MCM - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3318	/** Peripheral MCM base address */
Piasiv1206	4:ec3f71ef8732	3319	#define MCM_BASE (0xF0003000u)
Piasiv1206	4:ec3f71ef8732	3320	/** Peripheral MCM base pointer */
Piasiv1206	4:ec3f71ef8732	3321	#define MCM ((MCM_Type *)MCM_BASE)
Piasiv1206	4:ec3f71ef8732	3322	/** Array initializer of MCM peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3323	#define MCM_BASES { MCM }
Piasiv1206	4:ec3f71ef8732	3324
Piasiv1206	4:ec3f71ef8732	3325	/*!
Piasiv1206	4:ec3f71ef8732	3326	* @}
Piasiv1206	4:ec3f71ef8732	3327	/ / end of group MCM_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3328
Piasiv1206	4:ec3f71ef8732	3329
Piasiv1206	4:ec3f71ef8732	3330	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3331	-- MTB Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3332	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3333
Piasiv1206	4:ec3f71ef8732	3334	/*!
Piasiv1206	4:ec3f71ef8732	3335	* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3336	* @{
Piasiv1206	4:ec3f71ef8732	3337	*/
Piasiv1206	4:ec3f71ef8732	3338
Piasiv1206	4:ec3f71ef8732	3339	/** MTB - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3340	typedef struct {
Piasiv1206	4:ec3f71ef8732	3341	__IO uint32_t POSITION; /*< MTB Position Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	3342	__IO uint32_t MASTER; /*< MTB Master Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	3343	__IO uint32_t FLOW; /*< MTB Flow Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	3344	__I uint32_t BASE; /*< MTB Base Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	3345	uint8_t RESERVED_0[3824];
Piasiv1206	4:ec3f71ef8732	3346	__I uint32_t MODECTRL; /*< Integration Mode Control Register, offset: 0xF00 /
Piasiv1206	4:ec3f71ef8732	3347	uint8_t RESERVED_1[156];
Piasiv1206	4:ec3f71ef8732	3348	__I uint32_t TAGSET; /*< Claim TAG Set Register, offset: 0xFA0 /
Piasiv1206	4:ec3f71ef8732	3349	__I uint32_t TAGCLEAR; /*< Claim TAG Clear Register, offset: 0xFA4 /
Piasiv1206	4:ec3f71ef8732	3350	uint8_t RESERVED_2[8];
Piasiv1206	4:ec3f71ef8732	3351	__I uint32_t LOCKACCESS; /*< Lock Access Register, offset: 0xFB0 /
Piasiv1206	4:ec3f71ef8732	3352	__I uint32_t LOCKSTAT; /*< Lock Status Register, offset: 0xFB4 /
Piasiv1206	4:ec3f71ef8732	3353	__I uint32_t AUTHSTAT; /*< Authentication Status Register, offset: 0xFB8 /
Piasiv1206	4:ec3f71ef8732	3354	__I uint32_t DEVICEARCH; /*< Device Architecture Register, offset: 0xFBC /
Piasiv1206	4:ec3f71ef8732	3355	uint8_t RESERVED_3[8];
Piasiv1206	4:ec3f71ef8732	3356	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
Piasiv1206	4:ec3f71ef8732	3357	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
Piasiv1206	4:ec3f71ef8732	3358	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	3359	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	3360	} MTB_Type;
Piasiv1206	4:ec3f71ef8732	3361
Piasiv1206	4:ec3f71ef8732	3362	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3363	-- MTB Register Masks
Piasiv1206	4:ec3f71ef8732	3364	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3365
Piasiv1206	4:ec3f71ef8732	3366	/*!
Piasiv1206	4:ec3f71ef8732	3367	* @addtogroup MTB_Register_Masks MTB Register Masks
Piasiv1206	4:ec3f71ef8732	3368	* @{
Piasiv1206	4:ec3f71ef8732	3369	*/
Piasiv1206	4:ec3f71ef8732	3370
Piasiv1206	4:ec3f71ef8732	3371	/* POSITION Bit Fields */
Piasiv1206	4:ec3f71ef8732	3372	#define MTB_POSITION_WRAP_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3373	#define MTB_POSITION_WRAP_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3374	#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
Piasiv1206	4:ec3f71ef8732	3375	#define MTB_POSITION_POINTER_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3376	#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
Piasiv1206	4:ec3f71ef8732	3377	/* MASTER Bit Fields */
Piasiv1206	4:ec3f71ef8732	3378	#define MTB_MASTER_MASK_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	3379	#define MTB_MASTER_MASK_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3380	#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
Piasiv1206	4:ec3f71ef8732	3381	#define MTB_MASTER_TSTARTEN_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3382	#define MTB_MASTER_TSTARTEN_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3383	#define MTB_MASTER_TSTOPEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3384	#define MTB_MASTER_TSTOPEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3385	#define MTB_MASTER_SFRWPRIV_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3386	#define MTB_MASTER_SFRWPRIV_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3387	#define MTB_MASTER_RAMPRIV_MASK 0x100u
Piasiv1206	4:ec3f71ef8732	3388	#define MTB_MASTER_RAMPRIV_SHIFT 8
Piasiv1206	4:ec3f71ef8732	3389	#define MTB_MASTER_HALTREQ_MASK 0x200u
Piasiv1206	4:ec3f71ef8732	3390	#define MTB_MASTER_HALTREQ_SHIFT 9
Piasiv1206	4:ec3f71ef8732	3391	#define MTB_MASTER_EN_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	3392	#define MTB_MASTER_EN_SHIFT 31
Piasiv1206	4:ec3f71ef8732	3393	/* FLOW Bit Fields */
Piasiv1206	4:ec3f71ef8732	3394	#define MTB_FLOW_AUTOSTOP_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3395	#define MTB_FLOW_AUTOSTOP_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3396	#define MTB_FLOW_AUTOHALT_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3397	#define MTB_FLOW_AUTOHALT_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3398	#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
Piasiv1206	4:ec3f71ef8732	3399	#define MTB_FLOW_WATERMARK_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3400	#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
Piasiv1206	4:ec3f71ef8732	3401	/* BASE Bit Fields */
Piasiv1206	4:ec3f71ef8732	3402	#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3403	#define MTB_BASE_BASEADDR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3404	#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
Piasiv1206	4:ec3f71ef8732	3405	/* MODECTRL Bit Fields */
Piasiv1206	4:ec3f71ef8732	3406	#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3407	#define MTB_MODECTRL_MODECTRL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3408	#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
Piasiv1206	4:ec3f71ef8732	3409	/* TAGSET Bit Fields */
Piasiv1206	4:ec3f71ef8732	3410	#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3411	#define MTB_TAGSET_TAGSET_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3412	#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
Piasiv1206	4:ec3f71ef8732	3413	/* TAGCLEAR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3414	#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3415	#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3416	#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
Piasiv1206	4:ec3f71ef8732	3417	/* LOCKACCESS Bit Fields */
Piasiv1206	4:ec3f71ef8732	3418	#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3419	#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3420	#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
Piasiv1206	4:ec3f71ef8732	3421	/* LOCKSTAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	3422	#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3423	#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3424	#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
Piasiv1206	4:ec3f71ef8732	3425	/* AUTHSTAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	3426	#define MTB_AUTHSTAT_BIT0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3427	#define MTB_AUTHSTAT_BIT0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3428	#define MTB_AUTHSTAT_BIT1_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3429	#define MTB_AUTHSTAT_BIT1_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3430	#define MTB_AUTHSTAT_BIT2_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3431	#define MTB_AUTHSTAT_BIT2_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3432	#define MTB_AUTHSTAT_BIT3_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	3433	#define MTB_AUTHSTAT_BIT3_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3434	/* DEVICEARCH Bit Fields */
Piasiv1206	4:ec3f71ef8732	3435	#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3436	#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3437	#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
Piasiv1206	4:ec3f71ef8732	3438	/* DEVICECFG Bit Fields */
Piasiv1206	4:ec3f71ef8732	3439	#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3440	#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3441	#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
Piasiv1206	4:ec3f71ef8732	3442	/* DEVICETYPID Bit Fields */
Piasiv1206	4:ec3f71ef8732	3443	#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3444	#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3445	#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
Piasiv1206	4:ec3f71ef8732	3446	/* PERIPHID Bit Fields */
Piasiv1206	4:ec3f71ef8732	3447	#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3448	#define MTB_PERIPHID_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3449	#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	3450	/* COMPID Bit Fields */
Piasiv1206	4:ec3f71ef8732	3451	#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3452	#define MTB_COMPID_COMPID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3453	#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
Piasiv1206	4:ec3f71ef8732	3454
Piasiv1206	4:ec3f71ef8732	3455	/*!
Piasiv1206	4:ec3f71ef8732	3456	* @}
Piasiv1206	4:ec3f71ef8732	3457	/ / end of group MTB_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3458
Piasiv1206	4:ec3f71ef8732	3459
Piasiv1206	4:ec3f71ef8732	3460	/* MTB - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3461	/** Peripheral MTB base address */
Piasiv1206	4:ec3f71ef8732	3462	#define MTB_BASE (0xF0000000u)
Piasiv1206	4:ec3f71ef8732	3463	/** Peripheral MTB base pointer */
Piasiv1206	4:ec3f71ef8732	3464	#define MTB ((MTB_Type *)MTB_BASE)
Piasiv1206	4:ec3f71ef8732	3465	/** Array initializer of MTB peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3466	#define MTB_BASES { MTB }
Piasiv1206	4:ec3f71ef8732	3467
Piasiv1206	4:ec3f71ef8732	3468	/*!
Piasiv1206	4:ec3f71ef8732	3469	* @}
Piasiv1206	4:ec3f71ef8732	3470	/ / end of group MTB_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3471
Piasiv1206	4:ec3f71ef8732	3472
Piasiv1206	4:ec3f71ef8732	3473	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3474	-- MTBDWT Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3475	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3476
Piasiv1206	4:ec3f71ef8732	3477	/*!
Piasiv1206	4:ec3f71ef8732	3478	* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3479	* @{
Piasiv1206	4:ec3f71ef8732	3480	*/
Piasiv1206	4:ec3f71ef8732	3481
Piasiv1206	4:ec3f71ef8732	3482	/** MTBDWT - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3483	typedef struct {
Piasiv1206	4:ec3f71ef8732	3484	__I uint32_t CTRL; /*< MTB DWT Control Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	3485	uint8_t RESERVED_0[28];
Piasiv1206	4:ec3f71ef8732	3486	struct { /* offset: 0x20, array step: 0x10 */
Piasiv1206	4:ec3f71ef8732	3487	__IO uint32_t COMP; /*< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	3488	__IO uint32_t MASK; /*< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	3489	__IO uint32_t FCT; /*< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	3490	uint8_t RESERVED_0[4];
Piasiv1206	4:ec3f71ef8732	3491	} COMPARATOR[2];
Piasiv1206	4:ec3f71ef8732	3492	uint8_t RESERVED_1[448];
Piasiv1206	4:ec3f71ef8732	3493	__IO uint32_t TBCTRL; /*< MTB_DWT Trace Buffer Control Register, offset: 0x200 /
Piasiv1206	4:ec3f71ef8732	3494	uint8_t RESERVED_2[3524];
Piasiv1206	4:ec3f71ef8732	3495	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
Piasiv1206	4:ec3f71ef8732	3496	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
Piasiv1206	4:ec3f71ef8732	3497	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	3498	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	3499	} MTBDWT_Type;
Piasiv1206	4:ec3f71ef8732	3500
Piasiv1206	4:ec3f71ef8732	3501	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3502	-- MTBDWT Register Masks
Piasiv1206	4:ec3f71ef8732	3503	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3504
Piasiv1206	4:ec3f71ef8732	3505	/*!
Piasiv1206	4:ec3f71ef8732	3506	* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
Piasiv1206	4:ec3f71ef8732	3507	* @{
Piasiv1206	4:ec3f71ef8732	3508	*/
Piasiv1206	4:ec3f71ef8732	3509
Piasiv1206	4:ec3f71ef8732	3510	/* CTRL Bit Fields */
Piasiv1206	4:ec3f71ef8732	3511	#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3512	#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3513	#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
Piasiv1206	4:ec3f71ef8732	3514	#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
Piasiv1206	4:ec3f71ef8732	3515	#define MTBDWT_CTRL_NUMCMP_SHIFT 28
Piasiv1206	4:ec3f71ef8732	3516	#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
Piasiv1206	4:ec3f71ef8732	3517	/* COMP Bit Fields */
Piasiv1206	4:ec3f71ef8732	3518	#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3519	#define MTBDWT_COMP_COMP_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3520	#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
Piasiv1206	4:ec3f71ef8732	3521	/* MASK Bit Fields */
Piasiv1206	4:ec3f71ef8732	3522	#define MTBDWT_MASK_MASK_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	3523	#define MTBDWT_MASK_MASK_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3524	#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
Piasiv1206	4:ec3f71ef8732	3525	/* FCT Bit Fields */
Piasiv1206	4:ec3f71ef8732	3526	#define MTBDWT_FCT_FUNCTION_MASK 0xFu
Piasiv1206	4:ec3f71ef8732	3527	#define MTBDWT_FCT_FUNCTION_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3528	#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
Piasiv1206	4:ec3f71ef8732	3529	#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
Piasiv1206	4:ec3f71ef8732	3530	#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
Piasiv1206	4:ec3f71ef8732	3531	#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
Piasiv1206	4:ec3f71ef8732	3532	#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
Piasiv1206	4:ec3f71ef8732	3533	#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
Piasiv1206	4:ec3f71ef8732	3534	#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
Piasiv1206	4:ec3f71ef8732	3535	#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
Piasiv1206	4:ec3f71ef8732	3536	#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
Piasiv1206	4:ec3f71ef8732	3537	#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	3538	#define MTBDWT_FCT_MATCHED_SHIFT 24
Piasiv1206	4:ec3f71ef8732	3539	/* TBCTRL Bit Fields */
Piasiv1206	4:ec3f71ef8732	3540	#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3541	#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3542	#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3543	#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3544	#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
Piasiv1206	4:ec3f71ef8732	3545	#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
Piasiv1206	4:ec3f71ef8732	3546	#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
Piasiv1206	4:ec3f71ef8732	3547	/* DEVICECFG Bit Fields */
Piasiv1206	4:ec3f71ef8732	3548	#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3549	#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3550	#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
Piasiv1206	4:ec3f71ef8732	3551	/* DEVICETYPID Bit Fields */
Piasiv1206	4:ec3f71ef8732	3552	#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3553	#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3554	#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
Piasiv1206	4:ec3f71ef8732	3555	/* PERIPHID Bit Fields */
Piasiv1206	4:ec3f71ef8732	3556	#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3557	#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3558	#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	3559	/* COMPID Bit Fields */
Piasiv1206	4:ec3f71ef8732	3560	#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3561	#define MTBDWT_COMPID_COMPID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3562	#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
Piasiv1206	4:ec3f71ef8732	3563
Piasiv1206	4:ec3f71ef8732	3564	/*!
Piasiv1206	4:ec3f71ef8732	3565	* @}
Piasiv1206	4:ec3f71ef8732	3566	/ / end of group MTBDWT_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3567
Piasiv1206	4:ec3f71ef8732	3568
Piasiv1206	4:ec3f71ef8732	3569	/* MTBDWT - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3570	/** Peripheral MTBDWT base address */
Piasiv1206	4:ec3f71ef8732	3571	#define MTBDWT_BASE (0xF0001000u)
Piasiv1206	4:ec3f71ef8732	3572	/** Peripheral MTBDWT base pointer */
Piasiv1206	4:ec3f71ef8732	3573	#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
Piasiv1206	4:ec3f71ef8732	3574	/** Array initializer of MTBDWT peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3575	#define MTBDWT_BASES { MTBDWT }
Piasiv1206	4:ec3f71ef8732	3576
Piasiv1206	4:ec3f71ef8732	3577	/*!
Piasiv1206	4:ec3f71ef8732	3578	* @}
Piasiv1206	4:ec3f71ef8732	3579	/ / end of group MTBDWT_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3580
Piasiv1206	4:ec3f71ef8732	3581
Piasiv1206	4:ec3f71ef8732	3582	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3583	-- NV Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3584	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3585
Piasiv1206	4:ec3f71ef8732	3586	/*!
Piasiv1206	4:ec3f71ef8732	3587	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3588	* @{
Piasiv1206	4:ec3f71ef8732	3589	*/
Piasiv1206	4:ec3f71ef8732	3590
Piasiv1206	4:ec3f71ef8732	3591	/** NV - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3592	typedef struct {
Piasiv1206	4:ec3f71ef8732	3593	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	3594	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	3595	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	3596	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	3597	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	3598	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	3599	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
Piasiv1206	4:ec3f71ef8732	3600	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
Piasiv1206	4:ec3f71ef8732	3601	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	3602	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
Piasiv1206	4:ec3f71ef8732	3603	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
Piasiv1206	4:ec3f71ef8732	3604	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
Piasiv1206	4:ec3f71ef8732	3605	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	3606	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
Piasiv1206	4:ec3f71ef8732	3607	} NV_Type;
Piasiv1206	4:ec3f71ef8732	3608
Piasiv1206	4:ec3f71ef8732	3609	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3610	-- NV Register Masks
Piasiv1206	4:ec3f71ef8732	3611	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3612
Piasiv1206	4:ec3f71ef8732	3613	/*!
Piasiv1206	4:ec3f71ef8732	3614	* @addtogroup NV_Register_Masks NV Register Masks
Piasiv1206	4:ec3f71ef8732	3615	* @{
Piasiv1206	4:ec3f71ef8732	3616	*/
Piasiv1206	4:ec3f71ef8732	3617
Piasiv1206	4:ec3f71ef8732	3618	/* BACKKEY3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3619	#define NV_BACKKEY3_KEY_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3620	#define NV_BACKKEY3_KEY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3621	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
Piasiv1206	4:ec3f71ef8732	3622	/* BACKKEY2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3623	#define NV_BACKKEY2_KEY_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3624	#define NV_BACKKEY2_KEY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3625	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
Piasiv1206	4:ec3f71ef8732	3626	/* BACKKEY1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3627	#define NV_BACKKEY1_KEY_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3628	#define NV_BACKKEY1_KEY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3629	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
Piasiv1206	4:ec3f71ef8732	3630	/* BACKKEY0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3631	#define NV_BACKKEY0_KEY_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3632	#define NV_BACKKEY0_KEY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3633	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
Piasiv1206	4:ec3f71ef8732	3634	/* BACKKEY7 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3635	#define NV_BACKKEY7_KEY_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3636	#define NV_BACKKEY7_KEY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3637	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
Piasiv1206	4:ec3f71ef8732	3638	/* BACKKEY6 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3639	#define NV_BACKKEY6_KEY_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3640	#define NV_BACKKEY6_KEY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3641	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
Piasiv1206	4:ec3f71ef8732	3642	/* BACKKEY5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3643	#define NV_BACKKEY5_KEY_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3644	#define NV_BACKKEY5_KEY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3645	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
Piasiv1206	4:ec3f71ef8732	3646	/* BACKKEY4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3647	#define NV_BACKKEY4_KEY_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3648	#define NV_BACKKEY4_KEY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3649	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
Piasiv1206	4:ec3f71ef8732	3650	/* FPROT3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3651	#define NV_FPROT3_PROT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3652	#define NV_FPROT3_PROT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3653	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
Piasiv1206	4:ec3f71ef8732	3654	/* FPROT2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3655	#define NV_FPROT2_PROT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3656	#define NV_FPROT2_PROT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3657	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
Piasiv1206	4:ec3f71ef8732	3658	/* FPROT1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3659	#define NV_FPROT1_PROT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3660	#define NV_FPROT1_PROT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3661	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
Piasiv1206	4:ec3f71ef8732	3662	/* FPROT0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3663	#define NV_FPROT0_PROT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	3664	#define NV_FPROT0_PROT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3665	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
Piasiv1206	4:ec3f71ef8732	3666	/* FSEC Bit Fields */
Piasiv1206	4:ec3f71ef8732	3667	#define NV_FSEC_SEC_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	3668	#define NV_FSEC_SEC_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3669	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
Piasiv1206	4:ec3f71ef8732	3670	#define NV_FSEC_FSLACC_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	3671	#define NV_FSEC_FSLACC_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3672	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
Piasiv1206	4:ec3f71ef8732	3673	#define NV_FSEC_MEEN_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	3674	#define NV_FSEC_MEEN_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3675	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
Piasiv1206	4:ec3f71ef8732	3676	#define NV_FSEC_KEYEN_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	3677	#define NV_FSEC_KEYEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3678	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
Piasiv1206	4:ec3f71ef8732	3679	/* FOPT Bit Fields */
Piasiv1206	4:ec3f71ef8732	3680	#define NV_FOPT_LPBOOT0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3681	#define NV_FOPT_LPBOOT0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3682	#define NV_FOPT_NMI_DIS_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3683	#define NV_FOPT_NMI_DIS_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3684	#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	3685	#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3686	#define NV_FOPT_LPBOOT1_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	3687	#define NV_FOPT_LPBOOT1_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3688	#define NV_FOPT_FAST_INIT_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3689	#define NV_FOPT_FAST_INIT_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3690
Piasiv1206	4:ec3f71ef8732	3691	/*!
Piasiv1206	4:ec3f71ef8732	3692	* @}
Piasiv1206	4:ec3f71ef8732	3693	/ / end of group NV_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3694
Piasiv1206	4:ec3f71ef8732	3695
Piasiv1206	4:ec3f71ef8732	3696	/* NV - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3697	/** Peripheral FTFA_FlashConfig base address */
Piasiv1206	4:ec3f71ef8732	3698	#define FTFA_FlashConfig_BASE (0x400u)
Piasiv1206	4:ec3f71ef8732	3699	/** Peripheral FTFA_FlashConfig base pointer */
Piasiv1206	4:ec3f71ef8732	3700	#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
Piasiv1206	4:ec3f71ef8732	3701	/** Array initializer of NV peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3702	#define NV_BASES { FTFA_FlashConfig }
Piasiv1206	4:ec3f71ef8732	3703
Piasiv1206	4:ec3f71ef8732	3704	/*!
Piasiv1206	4:ec3f71ef8732	3705	* @}
Piasiv1206	4:ec3f71ef8732	3706	/ / end of group NV_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3707
Piasiv1206	4:ec3f71ef8732	3708
Piasiv1206	4:ec3f71ef8732	3709	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3710	-- OSC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3711	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3712
Piasiv1206	4:ec3f71ef8732	3713	/*!
Piasiv1206	4:ec3f71ef8732	3714	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3715	* @{
Piasiv1206	4:ec3f71ef8732	3716	*/
Piasiv1206	4:ec3f71ef8732	3717
Piasiv1206	4:ec3f71ef8732	3718	/** OSC - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3719	typedef struct {
Piasiv1206	4:ec3f71ef8732	3720	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	3721	} OSC_Type;
Piasiv1206	4:ec3f71ef8732	3722
Piasiv1206	4:ec3f71ef8732	3723	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3724	-- OSC Register Masks
Piasiv1206	4:ec3f71ef8732	3725	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3726
Piasiv1206	4:ec3f71ef8732	3727	/*!
Piasiv1206	4:ec3f71ef8732	3728	* @addtogroup OSC_Register_Masks OSC Register Masks
Piasiv1206	4:ec3f71ef8732	3729	* @{
Piasiv1206	4:ec3f71ef8732	3730	*/
Piasiv1206	4:ec3f71ef8732	3731
Piasiv1206	4:ec3f71ef8732	3732	/* CR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3733	#define OSC_CR_SC16P_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3734	#define OSC_CR_SC16P_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3735	#define OSC_CR_SC8P_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3736	#define OSC_CR_SC8P_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3737	#define OSC_CR_SC4P_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3738	#define OSC_CR_SC4P_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3739	#define OSC_CR_SC2P_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	3740	#define OSC_CR_SC2P_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3741	#define OSC_CR_EREFSTEN_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3742	#define OSC_CR_EREFSTEN_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3743	#define OSC_CR_ERCLKEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3744	#define OSC_CR_ERCLKEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3745
Piasiv1206	4:ec3f71ef8732	3746	/*!
Piasiv1206	4:ec3f71ef8732	3747	* @}
Piasiv1206	4:ec3f71ef8732	3748	/ / end of group OSC_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3749
Piasiv1206	4:ec3f71ef8732	3750
Piasiv1206	4:ec3f71ef8732	3751	/* OSC - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3752	/** Peripheral OSC0 base address */
Piasiv1206	4:ec3f71ef8732	3753	#define OSC0_BASE (0x40065000u)
Piasiv1206	4:ec3f71ef8732	3754	/** Peripheral OSC0 base pointer */
Piasiv1206	4:ec3f71ef8732	3755	#define OSC0 ((OSC_Type *)OSC0_BASE)
Piasiv1206	4:ec3f71ef8732	3756	/** Array initializer of OSC peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3757	#define OSC_BASES { OSC0 }
Piasiv1206	4:ec3f71ef8732	3758
Piasiv1206	4:ec3f71ef8732	3759	/*!
Piasiv1206	4:ec3f71ef8732	3760	* @}
Piasiv1206	4:ec3f71ef8732	3761	/ / end of group OSC_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3762
Piasiv1206	4:ec3f71ef8732	3763
Piasiv1206	4:ec3f71ef8732	3764	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3765	-- PIT Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3766	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3767
Piasiv1206	4:ec3f71ef8732	3768	/*!
Piasiv1206	4:ec3f71ef8732	3769	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3770	* @{
Piasiv1206	4:ec3f71ef8732	3771	*/
Piasiv1206	4:ec3f71ef8732	3772
Piasiv1206	4:ec3f71ef8732	3773	/** PIT - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3774	typedef struct {
Piasiv1206	4:ec3f71ef8732	3775	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	3776	uint8_t RESERVED_0[220];
Piasiv1206	4:ec3f71ef8732	3777	__I uint32_t LTMR64H; /*< PIT Upper Lifetime Timer Register, offset: 0xE0 /
Piasiv1206	4:ec3f71ef8732	3778	__I uint32_t LTMR64L; /*< PIT Lower Lifetime Timer Register, offset: 0xE4 /
Piasiv1206	4:ec3f71ef8732	3779	uint8_t RESERVED_1[24];
Piasiv1206	4:ec3f71ef8732	3780	struct { /* offset: 0x100, array step: 0x10 */
Piasiv1206	4:ec3f71ef8732	3781	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	3782	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	3783	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	3784	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
Piasiv1206	4:ec3f71ef8732	3785	} CHANNEL[2];
Piasiv1206	4:ec3f71ef8732	3786	} PIT_Type;
Piasiv1206	4:ec3f71ef8732	3787
Piasiv1206	4:ec3f71ef8732	3788	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3789	-- PIT Register Masks
Piasiv1206	4:ec3f71ef8732	3790	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3791
Piasiv1206	4:ec3f71ef8732	3792	/*!
Piasiv1206	4:ec3f71ef8732	3793	* @addtogroup PIT_Register_Masks PIT Register Masks
Piasiv1206	4:ec3f71ef8732	3794	* @{
Piasiv1206	4:ec3f71ef8732	3795	*/
Piasiv1206	4:ec3f71ef8732	3796
Piasiv1206	4:ec3f71ef8732	3797	/* MCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3798	#define PIT_MCR_FRZ_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3799	#define PIT_MCR_FRZ_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3800	#define PIT_MCR_MDIS_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3801	#define PIT_MCR_MDIS_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3802	/* LTMR64H Bit Fields */
Piasiv1206	4:ec3f71ef8732	3803	#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3804	#define PIT_LTMR64H_LTH_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3805	#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
Piasiv1206	4:ec3f71ef8732	3806	/* LTMR64L Bit Fields */
Piasiv1206	4:ec3f71ef8732	3807	#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3808	#define PIT_LTMR64L_LTL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3809	#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
Piasiv1206	4:ec3f71ef8732	3810	/* LDVAL Bit Fields */
Piasiv1206	4:ec3f71ef8732	3811	#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3812	#define PIT_LDVAL_TSV_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3813	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
Piasiv1206	4:ec3f71ef8732	3814	/* CVAL Bit Fields */
Piasiv1206	4:ec3f71ef8732	3815	#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3816	#define PIT_CVAL_TVL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3817	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
Piasiv1206	4:ec3f71ef8732	3818	/* TCTRL Bit Fields */
Piasiv1206	4:ec3f71ef8732	3819	#define PIT_TCTRL_TEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3820	#define PIT_TCTRL_TEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3821	#define PIT_TCTRL_TIE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3822	#define PIT_TCTRL_TIE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3823	#define PIT_TCTRL_CHN_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3824	#define PIT_TCTRL_CHN_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3825	/* TFLG Bit Fields */
Piasiv1206	4:ec3f71ef8732	3826	#define PIT_TFLG_TIF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3827	#define PIT_TFLG_TIF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3828
Piasiv1206	4:ec3f71ef8732	3829	/*!
Piasiv1206	4:ec3f71ef8732	3830	* @}
Piasiv1206	4:ec3f71ef8732	3831	/ / end of group PIT_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3832
Piasiv1206	4:ec3f71ef8732	3833
Piasiv1206	4:ec3f71ef8732	3834	/* PIT - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3835	/** Peripheral PIT base address */
Piasiv1206	4:ec3f71ef8732	3836	#define PIT_BASE (0x40037000u)
Piasiv1206	4:ec3f71ef8732	3837	/** Peripheral PIT base pointer */
Piasiv1206	4:ec3f71ef8732	3838	#define PIT ((PIT_Type *)PIT_BASE)
Piasiv1206	4:ec3f71ef8732	3839	/** Array initializer of PIT peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3840	#define PIT_BASES { PIT }
Piasiv1206	4:ec3f71ef8732	3841
Piasiv1206	4:ec3f71ef8732	3842	/*!
Piasiv1206	4:ec3f71ef8732	3843	* @}
Piasiv1206	4:ec3f71ef8732	3844	/ / end of group PIT_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3845
Piasiv1206	4:ec3f71ef8732	3846
Piasiv1206	4:ec3f71ef8732	3847	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3848	-- PMC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3849	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3850
Piasiv1206	4:ec3f71ef8732	3851	/*!
Piasiv1206	4:ec3f71ef8732	3852	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3853	* @{
Piasiv1206	4:ec3f71ef8732	3854	*/
Piasiv1206	4:ec3f71ef8732	3855
Piasiv1206	4:ec3f71ef8732	3856	/** PMC - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3857	typedef struct {
Piasiv1206	4:ec3f71ef8732	3858	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status And Control 1 register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	3859	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status And Control 2 register, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	3860	__IO uint8_t REGSC; /*< Regulator Status And Control register, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	3861	} PMC_Type;
Piasiv1206	4:ec3f71ef8732	3862
Piasiv1206	4:ec3f71ef8732	3863	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3864	-- PMC Register Masks
Piasiv1206	4:ec3f71ef8732	3865	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3866
Piasiv1206	4:ec3f71ef8732	3867	/*!
Piasiv1206	4:ec3f71ef8732	3868	* @addtogroup PMC_Register_Masks PMC Register Masks
Piasiv1206	4:ec3f71ef8732	3869	* @{
Piasiv1206	4:ec3f71ef8732	3870	*/
Piasiv1206	4:ec3f71ef8732	3871
Piasiv1206	4:ec3f71ef8732	3872	/* LVDSC1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3873	#define PMC_LVDSC1_LVDV_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	3874	#define PMC_LVDSC1_LVDV_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3875	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
Piasiv1206	4:ec3f71ef8732	3876	#define PMC_LVDSC1_LVDRE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	3877	#define PMC_LVDSC1_LVDRE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3878	#define PMC_LVDSC1_LVDIE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3879	#define PMC_LVDSC1_LVDIE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3880	#define PMC_LVDSC1_LVDACK_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3881	#define PMC_LVDSC1_LVDACK_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3882	#define PMC_LVDSC1_LVDF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3883	#define PMC_LVDSC1_LVDF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3884	/* LVDSC2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	3885	#define PMC_LVDSC2_LVWV_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	3886	#define PMC_LVDSC2_LVWV_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3887	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
Piasiv1206	4:ec3f71ef8732	3888	#define PMC_LVDSC2_LVWIE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	3889	#define PMC_LVDSC2_LVWIE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	3890	#define PMC_LVDSC2_LVWACK_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3891	#define PMC_LVDSC2_LVWACK_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3892	#define PMC_LVDSC2_LVWF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	3893	#define PMC_LVDSC2_LVWF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	3894	/* REGSC Bit Fields */
Piasiv1206	4:ec3f71ef8732	3895	#define PMC_REGSC_BGBE_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3896	#define PMC_REGSC_BGBE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3897	#define PMC_REGSC_REGONS_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3898	#define PMC_REGSC_REGONS_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3899	#define PMC_REGSC_ACKISO_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	3900	#define PMC_REGSC_ACKISO_SHIFT 3
Piasiv1206	4:ec3f71ef8732	3901	#define PMC_REGSC_BGEN_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	3902	#define PMC_REGSC_BGEN_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3903
Piasiv1206	4:ec3f71ef8732	3904	/*!
Piasiv1206	4:ec3f71ef8732	3905	* @}
Piasiv1206	4:ec3f71ef8732	3906	/ / end of group PMC_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3907
Piasiv1206	4:ec3f71ef8732	3908
Piasiv1206	4:ec3f71ef8732	3909	/* PMC - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3910	/** Peripheral PMC base address */
Piasiv1206	4:ec3f71ef8732	3911	#define PMC_BASE (0x4007D000u)
Piasiv1206	4:ec3f71ef8732	3912	/** Peripheral PMC base pointer */
Piasiv1206	4:ec3f71ef8732	3913	#define PMC ((PMC_Type *)PMC_BASE)
Piasiv1206	4:ec3f71ef8732	3914	/** Array initializer of PMC peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	3915	#define PMC_BASES { PMC }
Piasiv1206	4:ec3f71ef8732	3916
Piasiv1206	4:ec3f71ef8732	3917	/*!
Piasiv1206	4:ec3f71ef8732	3918	* @}
Piasiv1206	4:ec3f71ef8732	3919	/ / end of group PMC_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	3920
Piasiv1206	4:ec3f71ef8732	3921
Piasiv1206	4:ec3f71ef8732	3922	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3923	-- PORT Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3924	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3925
Piasiv1206	4:ec3f71ef8732	3926	/*!
Piasiv1206	4:ec3f71ef8732	3927	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	3928	* @{
Piasiv1206	4:ec3f71ef8732	3929	*/
Piasiv1206	4:ec3f71ef8732	3930
Piasiv1206	4:ec3f71ef8732	3931	/** PORT - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	3932	typedef struct {
Piasiv1206	4:ec3f71ef8732	3933	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	3934	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
Piasiv1206	4:ec3f71ef8732	3935	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
Piasiv1206	4:ec3f71ef8732	3936	uint8_t RESERVED_0[24];
Piasiv1206	4:ec3f71ef8732	3937	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
Piasiv1206	4:ec3f71ef8732	3938	} PORT_Type;
Piasiv1206	4:ec3f71ef8732	3939
Piasiv1206	4:ec3f71ef8732	3940	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	3941	-- PORT Register Masks
Piasiv1206	4:ec3f71ef8732	3942	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	3943
Piasiv1206	4:ec3f71ef8732	3944	/*!
Piasiv1206	4:ec3f71ef8732	3945	* @addtogroup PORT_Register_Masks PORT Register Masks
Piasiv1206	4:ec3f71ef8732	3946	* @{
Piasiv1206	4:ec3f71ef8732	3947	*/
Piasiv1206	4:ec3f71ef8732	3948
Piasiv1206	4:ec3f71ef8732	3949	/* PCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3950	#define PORT_PCR_PS_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	3951	#define PORT_PCR_PS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3952	#define PORT_PCR_PE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	3953	#define PORT_PCR_PE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	3954	#define PORT_PCR_SRE_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	3955	#define PORT_PCR_SRE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	3956	#define PORT_PCR_PFE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	3957	#define PORT_PCR_PFE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	3958	#define PORT_PCR_DSE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	3959	#define PORT_PCR_DSE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	3960	#define PORT_PCR_MUX_MASK 0x700u
Piasiv1206	4:ec3f71ef8732	3961	#define PORT_PCR_MUX_SHIFT 8
Piasiv1206	4:ec3f71ef8732	3962	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
Piasiv1206	4:ec3f71ef8732	3963	#define PORT_PCR_IRQC_MASK 0xF0000u
Piasiv1206	4:ec3f71ef8732	3964	#define PORT_PCR_IRQC_SHIFT 16
Piasiv1206	4:ec3f71ef8732	3965	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
Piasiv1206	4:ec3f71ef8732	3966	#define PORT_PCR_ISF_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	3967	#define PORT_PCR_ISF_SHIFT 24
Piasiv1206	4:ec3f71ef8732	3968	/* GPCLR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3969	#define PORT_GPCLR_GPWD_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	3970	#define PORT_GPCLR_GPWD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3971	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
Piasiv1206	4:ec3f71ef8732	3972	#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
Piasiv1206	4:ec3f71ef8732	3973	#define PORT_GPCLR_GPWE_SHIFT 16
Piasiv1206	4:ec3f71ef8732	3974	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
Piasiv1206	4:ec3f71ef8732	3975	/* GPCHR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3976	#define PORT_GPCHR_GPWD_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	3977	#define PORT_GPCHR_GPWD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3978	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
Piasiv1206	4:ec3f71ef8732	3979	#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
Piasiv1206	4:ec3f71ef8732	3980	#define PORT_GPCHR_GPWE_SHIFT 16
Piasiv1206	4:ec3f71ef8732	3981	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
Piasiv1206	4:ec3f71ef8732	3982	/* ISFR Bit Fields */
Piasiv1206	4:ec3f71ef8732	3983	#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	3984	#define PORT_ISFR_ISF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	3985	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
Piasiv1206	4:ec3f71ef8732	3986
Piasiv1206	4:ec3f71ef8732	3987	/*!
Piasiv1206	4:ec3f71ef8732	3988	* @}
Piasiv1206	4:ec3f71ef8732	3989	/ / end of group PORT_Register_Masks */
Piasiv1206	4:ec3f71ef8732	3990
Piasiv1206	4:ec3f71ef8732	3991
Piasiv1206	4:ec3f71ef8732	3992	/* PORT - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	3993	/** Peripheral PORTA base address */
Piasiv1206	4:ec3f71ef8732	3994	#define PORTA_BASE (0x40049000u)
Piasiv1206	4:ec3f71ef8732	3995	/** Peripheral PORTA base pointer */
Piasiv1206	4:ec3f71ef8732	3996	#define PORTA ((PORT_Type *)PORTA_BASE)
Piasiv1206	4:ec3f71ef8732	3997	/** Peripheral PORTB base address */
Piasiv1206	4:ec3f71ef8732	3998	#define PORTB_BASE (0x4004A000u)
Piasiv1206	4:ec3f71ef8732	3999	/** Peripheral PORTB base pointer */
Piasiv1206	4:ec3f71ef8732	4000	#define PORTB ((PORT_Type *)PORTB_BASE)
Piasiv1206	4:ec3f71ef8732	4001	/** Peripheral PORTC base address */
Piasiv1206	4:ec3f71ef8732	4002	#define PORTC_BASE (0x4004B000u)
Piasiv1206	4:ec3f71ef8732	4003	/** Peripheral PORTC base pointer */
Piasiv1206	4:ec3f71ef8732	4004	#define PORTC ((PORT_Type *)PORTC_BASE)
Piasiv1206	4:ec3f71ef8732	4005	/** Peripheral PORTD base address */
Piasiv1206	4:ec3f71ef8732	4006	#define PORTD_BASE (0x4004C000u)
Piasiv1206	4:ec3f71ef8732	4007	/** Peripheral PORTD base pointer */
Piasiv1206	4:ec3f71ef8732	4008	#define PORTD ((PORT_Type *)PORTD_BASE)
Piasiv1206	4:ec3f71ef8732	4009	/** Peripheral PORTE base address */
Piasiv1206	4:ec3f71ef8732	4010	#define PORTE_BASE (0x4004D000u)
Piasiv1206	4:ec3f71ef8732	4011	/** Peripheral PORTE base pointer */
Piasiv1206	4:ec3f71ef8732	4012	#define PORTE ((PORT_Type *)PORTE_BASE)
Piasiv1206	4:ec3f71ef8732	4013	/** Array initializer of PORT peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	4014	#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
Piasiv1206	4:ec3f71ef8732	4015
Piasiv1206	4:ec3f71ef8732	4016	/*!
Piasiv1206	4:ec3f71ef8732	4017	* @}
Piasiv1206	4:ec3f71ef8732	4018	/ / end of group PORT_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	4019
Piasiv1206	4:ec3f71ef8732	4020
Piasiv1206	4:ec3f71ef8732	4021	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4022	-- RCM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4023	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4024
Piasiv1206	4:ec3f71ef8732	4025	/*!
Piasiv1206	4:ec3f71ef8732	4026	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4027	* @{
Piasiv1206	4:ec3f71ef8732	4028	*/
Piasiv1206	4:ec3f71ef8732	4029
Piasiv1206	4:ec3f71ef8732	4030	/** RCM - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	4031	typedef struct {
Piasiv1206	4:ec3f71ef8732	4032	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	4033	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	4034	uint8_t RESERVED_0[2];
Piasiv1206	4:ec3f71ef8732	4035	__IO uint8_t RPFC; /*< Reset Pin Filter Control register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	4036	__IO uint8_t RPFW; /*< Reset Pin Filter Width register, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	4037	} RCM_Type;
Piasiv1206	4:ec3f71ef8732	4038
Piasiv1206	4:ec3f71ef8732	4039	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4040	-- RCM Register Masks
Piasiv1206	4:ec3f71ef8732	4041	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4042
Piasiv1206	4:ec3f71ef8732	4043	/*!
Piasiv1206	4:ec3f71ef8732	4044	* @addtogroup RCM_Register_Masks RCM Register Masks
Piasiv1206	4:ec3f71ef8732	4045	* @{
Piasiv1206	4:ec3f71ef8732	4046	*/
Piasiv1206	4:ec3f71ef8732	4047
Piasiv1206	4:ec3f71ef8732	4048	/* SRS0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4049	#define RCM_SRS0_WAKEUP_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4050	#define RCM_SRS0_WAKEUP_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4051	#define RCM_SRS0_LVD_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4052	#define RCM_SRS0_LVD_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4053	#define RCM_SRS0_LOC_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4054	#define RCM_SRS0_LOC_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4055	#define RCM_SRS0_LOL_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4056	#define RCM_SRS0_LOL_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4057	#define RCM_SRS0_WDOG_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4058	#define RCM_SRS0_WDOG_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4059	#define RCM_SRS0_PIN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4060	#define RCM_SRS0_PIN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4061	#define RCM_SRS0_POR_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4062	#define RCM_SRS0_POR_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4063	/* SRS1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4064	#define RCM_SRS1_LOCKUP_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4065	#define RCM_SRS1_LOCKUP_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4066	#define RCM_SRS1_SW_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4067	#define RCM_SRS1_SW_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4068	#define RCM_SRS1_MDM_AP_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4069	#define RCM_SRS1_MDM_AP_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4070	#define RCM_SRS1_SACKERR_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4071	#define RCM_SRS1_SACKERR_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4072	/* RPFC Bit Fields */
Piasiv1206	4:ec3f71ef8732	4073	#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	4074	#define RCM_RPFC_RSTFLTSRW_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4075	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
Piasiv1206	4:ec3f71ef8732	4076	#define RCM_RPFC_RSTFLTSS_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4077	#define RCM_RPFC_RSTFLTSS_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4078	/* RPFW Bit Fields */
Piasiv1206	4:ec3f71ef8732	4079	#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	4080	#define RCM_RPFW_RSTFLTSEL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4081	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
Piasiv1206	4:ec3f71ef8732	4082
Piasiv1206	4:ec3f71ef8732	4083	/*!
Piasiv1206	4:ec3f71ef8732	4084	* @}
Piasiv1206	4:ec3f71ef8732	4085	/ / end of group RCM_Register_Masks */
Piasiv1206	4:ec3f71ef8732	4086
Piasiv1206	4:ec3f71ef8732	4087
Piasiv1206	4:ec3f71ef8732	4088	/* RCM - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	4089	/** Peripheral RCM base address */
Piasiv1206	4:ec3f71ef8732	4090	#define RCM_BASE (0x4007F000u)
Piasiv1206	4:ec3f71ef8732	4091	/** Peripheral RCM base pointer */
Piasiv1206	4:ec3f71ef8732	4092	#define RCM ((RCM_Type *)RCM_BASE)
Piasiv1206	4:ec3f71ef8732	4093	/** Array initializer of RCM peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	4094	#define RCM_BASES { RCM }
Piasiv1206	4:ec3f71ef8732	4095
Piasiv1206	4:ec3f71ef8732	4096	/*!
Piasiv1206	4:ec3f71ef8732	4097	* @}
Piasiv1206	4:ec3f71ef8732	4098	/ / end of group RCM_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	4099
Piasiv1206	4:ec3f71ef8732	4100
Piasiv1206	4:ec3f71ef8732	4101	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4102	-- ROM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4103	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4104
Piasiv1206	4:ec3f71ef8732	4105	/*!
Piasiv1206	4:ec3f71ef8732	4106	* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4107	* @{
Piasiv1206	4:ec3f71ef8732	4108	*/
Piasiv1206	4:ec3f71ef8732	4109
Piasiv1206	4:ec3f71ef8732	4110	/** ROM - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	4111	typedef struct {
Piasiv1206	4:ec3f71ef8732	4112	__I uint32_t ENTRY[3]; /*< Entry, array offset: 0x0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	4113	__I uint32_t TABLEMARK; /*< End of Table Marker Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	4114	uint8_t RESERVED_0[4028];
Piasiv1206	4:ec3f71ef8732	4115	__I uint32_t SYSACCESS; /*< System Access Register, offset: 0xFCC /
Piasiv1206	4:ec3f71ef8732	4116	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
Piasiv1206	4:ec3f71ef8732	4117	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
Piasiv1206	4:ec3f71ef8732	4118	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
Piasiv1206	4:ec3f71ef8732	4119	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
Piasiv1206	4:ec3f71ef8732	4120	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
Piasiv1206	4:ec3f71ef8732	4121	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
Piasiv1206	4:ec3f71ef8732	4122	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
Piasiv1206	4:ec3f71ef8732	4123	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
Piasiv1206	4:ec3f71ef8732	4124	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	4125	} ROM_Type;
Piasiv1206	4:ec3f71ef8732	4126
Piasiv1206	4:ec3f71ef8732	4127	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4128	-- ROM Register Masks
Piasiv1206	4:ec3f71ef8732	4129	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4130
Piasiv1206	4:ec3f71ef8732	4131	/*!
Piasiv1206	4:ec3f71ef8732	4132	* @addtogroup ROM_Register_Masks ROM Register Masks
Piasiv1206	4:ec3f71ef8732	4133	* @{
Piasiv1206	4:ec3f71ef8732	4134	*/
Piasiv1206	4:ec3f71ef8732	4135
Piasiv1206	4:ec3f71ef8732	4136	/* ENTRY Bit Fields */
Piasiv1206	4:ec3f71ef8732	4137	#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4138	#define ROM_ENTRY_ENTRY_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4139	#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
Piasiv1206	4:ec3f71ef8732	4140	/* TABLEMARK Bit Fields */
Piasiv1206	4:ec3f71ef8732	4141	#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4142	#define ROM_TABLEMARK_MARK_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4143	#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
Piasiv1206	4:ec3f71ef8732	4144	/* SYSACCESS Bit Fields */
Piasiv1206	4:ec3f71ef8732	4145	#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4146	#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4147	#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
Piasiv1206	4:ec3f71ef8732	4148	/* PERIPHID4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4149	#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4150	#define ROM_PERIPHID4_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4151	#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	4152	/* PERIPHID5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4153	#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4154	#define ROM_PERIPHID5_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4155	#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	4156	/* PERIPHID6 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4157	#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4158	#define ROM_PERIPHID6_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4159	#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	4160	/* PERIPHID7 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4161	#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4162	#define ROM_PERIPHID7_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4163	#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	4164	/* PERIPHID0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4165	#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4166	#define ROM_PERIPHID0_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4167	#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	4168	/* PERIPHID1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4169	#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4170	#define ROM_PERIPHID1_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4171	#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	4172	/* PERIPHID2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4173	#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4174	#define ROM_PERIPHID2_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4175	#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	4176	/* PERIPHID3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4177	#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4178	#define ROM_PERIPHID3_PERIPHID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4179	#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
Piasiv1206	4:ec3f71ef8732	4180	/* COMPID Bit Fields */
Piasiv1206	4:ec3f71ef8732	4181	#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4182	#define ROM_COMPID_COMPID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4183	#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
Piasiv1206	4:ec3f71ef8732	4184
Piasiv1206	4:ec3f71ef8732	4185	/*!
Piasiv1206	4:ec3f71ef8732	4186	* @}
Piasiv1206	4:ec3f71ef8732	4187	/ / end of group ROM_Register_Masks */
Piasiv1206	4:ec3f71ef8732	4188
Piasiv1206	4:ec3f71ef8732	4189
Piasiv1206	4:ec3f71ef8732	4190	/* ROM - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	4191	/** Peripheral ROM base address */
Piasiv1206	4:ec3f71ef8732	4192	#define ROM_BASE (0xF0002000u)
Piasiv1206	4:ec3f71ef8732	4193	/** Peripheral ROM base pointer */
Piasiv1206	4:ec3f71ef8732	4194	#define ROM ((ROM_Type *)ROM_BASE)
Piasiv1206	4:ec3f71ef8732	4195	/** Array initializer of ROM peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	4196	#define ROM_BASES { ROM }
Piasiv1206	4:ec3f71ef8732	4197
Piasiv1206	4:ec3f71ef8732	4198	/*!
Piasiv1206	4:ec3f71ef8732	4199	* @}
Piasiv1206	4:ec3f71ef8732	4200	/ / end of group ROM_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	4201
Piasiv1206	4:ec3f71ef8732	4202
Piasiv1206	4:ec3f71ef8732	4203	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4204	-- RTC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4205	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4206
Piasiv1206	4:ec3f71ef8732	4207	/*!
Piasiv1206	4:ec3f71ef8732	4208	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4209	* @{
Piasiv1206	4:ec3f71ef8732	4210	*/
Piasiv1206	4:ec3f71ef8732	4211
Piasiv1206	4:ec3f71ef8732	4212	/** RTC - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	4213	typedef struct {
Piasiv1206	4:ec3f71ef8732	4214	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	4215	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	4216	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	4217	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	4218	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
Piasiv1206	4:ec3f71ef8732	4219	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
Piasiv1206	4:ec3f71ef8732	4220	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
Piasiv1206	4:ec3f71ef8732	4221	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
Piasiv1206	4:ec3f71ef8732	4222	} RTC_Type;
Piasiv1206	4:ec3f71ef8732	4223
Piasiv1206	4:ec3f71ef8732	4224	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4225	-- RTC Register Masks
Piasiv1206	4:ec3f71ef8732	4226	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4227
Piasiv1206	4:ec3f71ef8732	4228	/*!
Piasiv1206	4:ec3f71ef8732	4229	* @addtogroup RTC_Register_Masks RTC Register Masks
Piasiv1206	4:ec3f71ef8732	4230	* @{
Piasiv1206	4:ec3f71ef8732	4231	*/
Piasiv1206	4:ec3f71ef8732	4232
Piasiv1206	4:ec3f71ef8732	4233	/* TSR Bit Fields */
Piasiv1206	4:ec3f71ef8732	4234	#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4235	#define RTC_TSR_TSR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4236	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
Piasiv1206	4:ec3f71ef8732	4237	/* TPR Bit Fields */
Piasiv1206	4:ec3f71ef8732	4238	#define RTC_TPR_TPR_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	4239	#define RTC_TPR_TPR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4240	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
Piasiv1206	4:ec3f71ef8732	4241	/* TAR Bit Fields */
Piasiv1206	4:ec3f71ef8732	4242	#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4243	#define RTC_TAR_TAR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4244	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
Piasiv1206	4:ec3f71ef8732	4245	/* TCR Bit Fields */
Piasiv1206	4:ec3f71ef8732	4246	#define RTC_TCR_TCR_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	4247	#define RTC_TCR_TCR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4248	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
Piasiv1206	4:ec3f71ef8732	4249	#define RTC_TCR_CIR_MASK 0xFF00u
Piasiv1206	4:ec3f71ef8732	4250	#define RTC_TCR_CIR_SHIFT 8
Piasiv1206	4:ec3f71ef8732	4251	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
Piasiv1206	4:ec3f71ef8732	4252	#define RTC_TCR_TCV_MASK 0xFF0000u
Piasiv1206	4:ec3f71ef8732	4253	#define RTC_TCR_TCV_SHIFT 16
Piasiv1206	4:ec3f71ef8732	4254	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
Piasiv1206	4:ec3f71ef8732	4255	#define RTC_TCR_CIC_MASK 0xFF000000u
Piasiv1206	4:ec3f71ef8732	4256	#define RTC_TCR_CIC_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4257	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
Piasiv1206	4:ec3f71ef8732	4258	/* CR Bit Fields */
Piasiv1206	4:ec3f71ef8732	4259	#define RTC_CR_SWR_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4260	#define RTC_CR_SWR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4261	#define RTC_CR_WPE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4262	#define RTC_CR_WPE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4263	#define RTC_CR_SUP_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4264	#define RTC_CR_SUP_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4265	#define RTC_CR_UM_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4266	#define RTC_CR_UM_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4267	#define RTC_CR_OSCE_MASK 0x100u
Piasiv1206	4:ec3f71ef8732	4268	#define RTC_CR_OSCE_SHIFT 8
Piasiv1206	4:ec3f71ef8732	4269	#define RTC_CR_CLKO_MASK 0x200u
Piasiv1206	4:ec3f71ef8732	4270	#define RTC_CR_CLKO_SHIFT 9
Piasiv1206	4:ec3f71ef8732	4271	#define RTC_CR_SC16P_MASK 0x400u
Piasiv1206	4:ec3f71ef8732	4272	#define RTC_CR_SC16P_SHIFT 10
Piasiv1206	4:ec3f71ef8732	4273	#define RTC_CR_SC8P_MASK 0x800u
Piasiv1206	4:ec3f71ef8732	4274	#define RTC_CR_SC8P_SHIFT 11
Piasiv1206	4:ec3f71ef8732	4275	#define RTC_CR_SC4P_MASK 0x1000u
Piasiv1206	4:ec3f71ef8732	4276	#define RTC_CR_SC4P_SHIFT 12
Piasiv1206	4:ec3f71ef8732	4277	#define RTC_CR_SC2P_MASK 0x2000u
Piasiv1206	4:ec3f71ef8732	4278	#define RTC_CR_SC2P_SHIFT 13
Piasiv1206	4:ec3f71ef8732	4279	/* SR Bit Fields */
Piasiv1206	4:ec3f71ef8732	4280	#define RTC_SR_TIF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4281	#define RTC_SR_TIF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4282	#define RTC_SR_TOF_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4283	#define RTC_SR_TOF_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4284	#define RTC_SR_TAF_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4285	#define RTC_SR_TAF_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4286	#define RTC_SR_TCE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4287	#define RTC_SR_TCE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4288	/* LR Bit Fields */
Piasiv1206	4:ec3f71ef8732	4289	#define RTC_LR_TCL_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4290	#define RTC_LR_TCL_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4291	#define RTC_LR_CRL_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4292	#define RTC_LR_CRL_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4293	#define RTC_LR_SRL_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4294	#define RTC_LR_SRL_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4295	#define RTC_LR_LRL_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4296	#define RTC_LR_LRL_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4297	/* IER Bit Fields */
Piasiv1206	4:ec3f71ef8732	4298	#define RTC_IER_TIIE_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4299	#define RTC_IER_TIIE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4300	#define RTC_IER_TOIE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4301	#define RTC_IER_TOIE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4302	#define RTC_IER_TAIE_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4303	#define RTC_IER_TAIE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4304	#define RTC_IER_TSIE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4305	#define RTC_IER_TSIE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4306	#define RTC_IER_WPON_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4307	#define RTC_IER_WPON_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4308
Piasiv1206	4:ec3f71ef8732	4309	/*!
Piasiv1206	4:ec3f71ef8732	4310	* @}
Piasiv1206	4:ec3f71ef8732	4311	/ / end of group RTC_Register_Masks */
Piasiv1206	4:ec3f71ef8732	4312
Piasiv1206	4:ec3f71ef8732	4313
Piasiv1206	4:ec3f71ef8732	4314	/* RTC - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	4315	/** Peripheral RTC base address */
Piasiv1206	4:ec3f71ef8732	4316	#define RTC_BASE (0x4003D000u)
Piasiv1206	4:ec3f71ef8732	4317	/** Peripheral RTC base pointer */
Piasiv1206	4:ec3f71ef8732	4318	#define RTC ((RTC_Type *)RTC_BASE)
Piasiv1206	4:ec3f71ef8732	4319	/** Array initializer of RTC peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	4320	#define RTC_BASES { RTC }
Piasiv1206	4:ec3f71ef8732	4321
Piasiv1206	4:ec3f71ef8732	4322	/*!
Piasiv1206	4:ec3f71ef8732	4323	* @}
Piasiv1206	4:ec3f71ef8732	4324	/ / end of group RTC_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	4325
Piasiv1206	4:ec3f71ef8732	4326
Piasiv1206	4:ec3f71ef8732	4327	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4328	-- SIM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4329	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4330
Piasiv1206	4:ec3f71ef8732	4331	/*!
Piasiv1206	4:ec3f71ef8732	4332	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4333	* @{
Piasiv1206	4:ec3f71ef8732	4334	*/
Piasiv1206	4:ec3f71ef8732	4335
Piasiv1206	4:ec3f71ef8732	4336	/** SIM - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	4337	typedef struct {
Piasiv1206	4:ec3f71ef8732	4338	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	4339	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	4340	uint8_t RESERVED_0[4092];
Piasiv1206	4:ec3f71ef8732	4341	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
Piasiv1206	4:ec3f71ef8732	4342	uint8_t RESERVED_1[4];
Piasiv1206	4:ec3f71ef8732	4343	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
Piasiv1206	4:ec3f71ef8732	4344	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
Piasiv1206	4:ec3f71ef8732	4345	uint8_t RESERVED_2[4];
Piasiv1206	4:ec3f71ef8732	4346	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
Piasiv1206	4:ec3f71ef8732	4347	uint8_t RESERVED_3[8];
Piasiv1206	4:ec3f71ef8732	4348	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
Piasiv1206	4:ec3f71ef8732	4349	uint8_t RESERVED_4[12];
Piasiv1206	4:ec3f71ef8732	4350	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
Piasiv1206	4:ec3f71ef8732	4351	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
Piasiv1206	4:ec3f71ef8732	4352	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
Piasiv1206	4:ec3f71ef8732	4353	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
Piasiv1206	4:ec3f71ef8732	4354	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
Piasiv1206	4:ec3f71ef8732	4355	uint8_t RESERVED_5[4];
Piasiv1206	4:ec3f71ef8732	4356	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
Piasiv1206	4:ec3f71ef8732	4357	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
Piasiv1206	4:ec3f71ef8732	4358	uint8_t RESERVED_6[4];
Piasiv1206	4:ec3f71ef8732	4359	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
Piasiv1206	4:ec3f71ef8732	4360	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
Piasiv1206	4:ec3f71ef8732	4361	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
Piasiv1206	4:ec3f71ef8732	4362	uint8_t RESERVED_7[156];
Piasiv1206	4:ec3f71ef8732	4363	__IO uint32_t COPC; /*< COP Control Register, offset: 0x1100 /
Piasiv1206	4:ec3f71ef8732	4364	__O uint32_t SRVCOP; /*< Service COP Register, offset: 0x1104 /
Piasiv1206	4:ec3f71ef8732	4365	} SIM_Type;
Piasiv1206	4:ec3f71ef8732	4366
Piasiv1206	4:ec3f71ef8732	4367	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4368	-- SIM Register Masks
Piasiv1206	4:ec3f71ef8732	4369	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4370
Piasiv1206	4:ec3f71ef8732	4371	/*!
Piasiv1206	4:ec3f71ef8732	4372	* @addtogroup SIM_Register_Masks SIM Register Masks
Piasiv1206	4:ec3f71ef8732	4373	* @{
Piasiv1206	4:ec3f71ef8732	4374	*/
Piasiv1206	4:ec3f71ef8732	4375
Piasiv1206	4:ec3f71ef8732	4376	/* SOPT1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4377	#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
Piasiv1206	4:ec3f71ef8732	4378	#define SIM_SOPT1_OSC32KSEL_SHIFT 18
Piasiv1206	4:ec3f71ef8732	4379	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
Piasiv1206	4:ec3f71ef8732	4380	#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
Piasiv1206	4:ec3f71ef8732	4381	#define SIM_SOPT1_USBVSTBY_SHIFT 29
Piasiv1206	4:ec3f71ef8732	4382	#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
Piasiv1206	4:ec3f71ef8732	4383	#define SIM_SOPT1_USBSSTBY_SHIFT 30
Piasiv1206	4:ec3f71ef8732	4384	#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	4385	#define SIM_SOPT1_USBREGEN_SHIFT 31
Piasiv1206	4:ec3f71ef8732	4386	/* SOPT1CFG Bit Fields */
Piasiv1206	4:ec3f71ef8732	4387	#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	4388	#define SIM_SOPT1CFG_URWE_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4389	#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
Piasiv1206	4:ec3f71ef8732	4390	#define SIM_SOPT1CFG_UVSWE_SHIFT 25
Piasiv1206	4:ec3f71ef8732	4391	#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
Piasiv1206	4:ec3f71ef8732	4392	#define SIM_SOPT1CFG_USSWE_SHIFT 26
Piasiv1206	4:ec3f71ef8732	4393	/* SOPT2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4394	#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4395	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4396	#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
Piasiv1206	4:ec3f71ef8732	4397	#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4398	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
Piasiv1206	4:ec3f71ef8732	4399	#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	4400	#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
Piasiv1206	4:ec3f71ef8732	4401	#define SIM_SOPT2_USBSRC_MASK 0x40000u
Piasiv1206	4:ec3f71ef8732	4402	#define SIM_SOPT2_USBSRC_SHIFT 18
Piasiv1206	4:ec3f71ef8732	4403	#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
Piasiv1206	4:ec3f71ef8732	4404	#define SIM_SOPT2_TPMSRC_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4405	#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
Piasiv1206	4:ec3f71ef8732	4406	#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
Piasiv1206	4:ec3f71ef8732	4407	#define SIM_SOPT2_UART0SRC_SHIFT 26
Piasiv1206	4:ec3f71ef8732	4408	#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
Piasiv1206	4:ec3f71ef8732	4409	/* SOPT4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4410	#define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
Piasiv1206	4:ec3f71ef8732	4411	#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
Piasiv1206	4:ec3f71ef8732	4412	#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
Piasiv1206	4:ec3f71ef8732	4413	#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
Piasiv1206	4:ec3f71ef8732	4414	#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
Piasiv1206	4:ec3f71ef8732	4415	#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	4416	#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4417	#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
Piasiv1206	4:ec3f71ef8732	4418	#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
Piasiv1206	4:ec3f71ef8732	4419	#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
Piasiv1206	4:ec3f71ef8732	4420	#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
Piasiv1206	4:ec3f71ef8732	4421	/* SOPT5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4422	#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
Piasiv1206	4:ec3f71ef8732	4423	#define SIM_SOPT5_UART0TXSRC_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4424	#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
Piasiv1206	4:ec3f71ef8732	4425	#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4426	#define SIM_SOPT5_UART0RXSRC_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4427	#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
Piasiv1206	4:ec3f71ef8732	4428	#define SIM_SOPT5_UART1TXSRC_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4429	#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
Piasiv1206	4:ec3f71ef8732	4430	#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4431	#define SIM_SOPT5_UART1RXSRC_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4432	#define SIM_SOPT5_UART0ODE_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	4433	#define SIM_SOPT5_UART0ODE_SHIFT 16
Piasiv1206	4:ec3f71ef8732	4434	#define SIM_SOPT5_UART1ODE_MASK 0x20000u
Piasiv1206	4:ec3f71ef8732	4435	#define SIM_SOPT5_UART1ODE_SHIFT 17
Piasiv1206	4:ec3f71ef8732	4436	#define SIM_SOPT5_UART2ODE_MASK 0x40000u
Piasiv1206	4:ec3f71ef8732	4437	#define SIM_SOPT5_UART2ODE_SHIFT 18
Piasiv1206	4:ec3f71ef8732	4438	/* SOPT7 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4439	#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
Piasiv1206	4:ec3f71ef8732	4440	#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4441	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
Piasiv1206	4:ec3f71ef8732	4442	#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4443	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4444	#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4445	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4446	/* SDID Bit Fields */
Piasiv1206	4:ec3f71ef8732	4447	#define SIM_SDID_PINID_MASK 0xFu
Piasiv1206	4:ec3f71ef8732	4448	#define SIM_SDID_PINID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4449	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
Piasiv1206	4:ec3f71ef8732	4450	#define SIM_SDID_DIEID_MASK 0xF80u
Piasiv1206	4:ec3f71ef8732	4451	#define SIM_SDID_DIEID_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4452	#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
Piasiv1206	4:ec3f71ef8732	4453	#define SIM_SDID_REVID_MASK 0xF000u
Piasiv1206	4:ec3f71ef8732	4454	#define SIM_SDID_REVID_SHIFT 12
Piasiv1206	4:ec3f71ef8732	4455	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
Piasiv1206	4:ec3f71ef8732	4456	#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
Piasiv1206	4:ec3f71ef8732	4457	#define SIM_SDID_SRAMSIZE_SHIFT 16
Piasiv1206	4:ec3f71ef8732	4458	#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
Piasiv1206	4:ec3f71ef8732	4459	#define SIM_SDID_SERIESID_MASK 0xF00000u
Piasiv1206	4:ec3f71ef8732	4460	#define SIM_SDID_SERIESID_SHIFT 20
Piasiv1206	4:ec3f71ef8732	4461	#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
Piasiv1206	4:ec3f71ef8732	4462	#define SIM_SDID_SUBFAMID_MASK 0xF000000u
Piasiv1206	4:ec3f71ef8732	4463	#define SIM_SDID_SUBFAMID_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4464	#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
Piasiv1206	4:ec3f71ef8732	4465	#define SIM_SDID_FAMID_MASK 0xF0000000u
Piasiv1206	4:ec3f71ef8732	4466	#define SIM_SDID_FAMID_SHIFT 28
Piasiv1206	4:ec3f71ef8732	4467	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
Piasiv1206	4:ec3f71ef8732	4468	/* SCGC4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4469	#define SIM_SCGC4_I2C0_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4470	#define SIM_SCGC4_I2C0_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4471	#define SIM_SCGC4_I2C1_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4472	#define SIM_SCGC4_I2C1_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4473	#define SIM_SCGC4_UART0_MASK 0x400u
Piasiv1206	4:ec3f71ef8732	4474	#define SIM_SCGC4_UART0_SHIFT 10
Piasiv1206	4:ec3f71ef8732	4475	#define SIM_SCGC4_UART1_MASK 0x800u
Piasiv1206	4:ec3f71ef8732	4476	#define SIM_SCGC4_UART1_SHIFT 11
Piasiv1206	4:ec3f71ef8732	4477	#define SIM_SCGC4_UART2_MASK 0x1000u
Piasiv1206	4:ec3f71ef8732	4478	#define SIM_SCGC4_UART2_SHIFT 12
Piasiv1206	4:ec3f71ef8732	4479	#define SIM_SCGC4_USBOTG_MASK 0x40000u
Piasiv1206	4:ec3f71ef8732	4480	#define SIM_SCGC4_USBOTG_SHIFT 18
Piasiv1206	4:ec3f71ef8732	4481	#define SIM_SCGC4_CMP_MASK 0x80000u
Piasiv1206	4:ec3f71ef8732	4482	#define SIM_SCGC4_CMP_SHIFT 19
Piasiv1206	4:ec3f71ef8732	4483	#define SIM_SCGC4_SPI0_MASK 0x400000u
Piasiv1206	4:ec3f71ef8732	4484	#define SIM_SCGC4_SPI0_SHIFT 22
Piasiv1206	4:ec3f71ef8732	4485	#define SIM_SCGC4_SPI1_MASK 0x800000u
Piasiv1206	4:ec3f71ef8732	4486	#define SIM_SCGC4_SPI1_SHIFT 23
Piasiv1206	4:ec3f71ef8732	4487	/* SCGC5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4488	#define SIM_SCGC5_LPTMR_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4489	#define SIM_SCGC5_LPTMR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4490	#define SIM_SCGC5_TSI_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4491	#define SIM_SCGC5_TSI_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4492	#define SIM_SCGC5_PORTA_MASK 0x200u
Piasiv1206	4:ec3f71ef8732	4493	#define SIM_SCGC5_PORTA_SHIFT 9
Piasiv1206	4:ec3f71ef8732	4494	#define SIM_SCGC5_PORTB_MASK 0x400u
Piasiv1206	4:ec3f71ef8732	4495	#define SIM_SCGC5_PORTB_SHIFT 10
Piasiv1206	4:ec3f71ef8732	4496	#define SIM_SCGC5_PORTC_MASK 0x800u
Piasiv1206	4:ec3f71ef8732	4497	#define SIM_SCGC5_PORTC_SHIFT 11
Piasiv1206	4:ec3f71ef8732	4498	#define SIM_SCGC5_PORTD_MASK 0x1000u
Piasiv1206	4:ec3f71ef8732	4499	#define SIM_SCGC5_PORTD_SHIFT 12
Piasiv1206	4:ec3f71ef8732	4500	#define SIM_SCGC5_PORTE_MASK 0x2000u
Piasiv1206	4:ec3f71ef8732	4501	#define SIM_SCGC5_PORTE_SHIFT 13
Piasiv1206	4:ec3f71ef8732	4502	#define SIM_SCGC5_SLCD_MASK 0x80000u
Piasiv1206	4:ec3f71ef8732	4503	#define SIM_SCGC5_SLCD_SHIFT 19
Piasiv1206	4:ec3f71ef8732	4504	/* SCGC6 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4505	#define SIM_SCGC6_FTF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4506	#define SIM_SCGC6_FTF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4507	#define SIM_SCGC6_DMAMUX_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4508	#define SIM_SCGC6_DMAMUX_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4509	#define SIM_SCGC6_I2S_MASK 0x8000u
Piasiv1206	4:ec3f71ef8732	4510	#define SIM_SCGC6_I2S_SHIFT 15
Piasiv1206	4:ec3f71ef8732	4511	#define SIM_SCGC6_PIT_MASK 0x800000u
Piasiv1206	4:ec3f71ef8732	4512	#define SIM_SCGC6_PIT_SHIFT 23
Piasiv1206	4:ec3f71ef8732	4513	#define SIM_SCGC6_TPM0_MASK 0x1000000u
Piasiv1206	4:ec3f71ef8732	4514	#define SIM_SCGC6_TPM0_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4515	#define SIM_SCGC6_TPM1_MASK 0x2000000u
Piasiv1206	4:ec3f71ef8732	4516	#define SIM_SCGC6_TPM1_SHIFT 25
Piasiv1206	4:ec3f71ef8732	4517	#define SIM_SCGC6_TPM2_MASK 0x4000000u
Piasiv1206	4:ec3f71ef8732	4518	#define SIM_SCGC6_TPM2_SHIFT 26
Piasiv1206	4:ec3f71ef8732	4519	#define SIM_SCGC6_ADC0_MASK 0x8000000u
Piasiv1206	4:ec3f71ef8732	4520	#define SIM_SCGC6_ADC0_SHIFT 27
Piasiv1206	4:ec3f71ef8732	4521	#define SIM_SCGC6_RTC_MASK 0x20000000u
Piasiv1206	4:ec3f71ef8732	4522	#define SIM_SCGC6_RTC_SHIFT 29
Piasiv1206	4:ec3f71ef8732	4523	#define SIM_SCGC6_DAC0_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	4524	#define SIM_SCGC6_DAC0_SHIFT 31
Piasiv1206	4:ec3f71ef8732	4525	/* SCGC7 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4526	#define SIM_SCGC7_DMA_MASK 0x100u
Piasiv1206	4:ec3f71ef8732	4527	#define SIM_SCGC7_DMA_SHIFT 8
Piasiv1206	4:ec3f71ef8732	4528	/* CLKDIV1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4529	#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
Piasiv1206	4:ec3f71ef8732	4530	#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
Piasiv1206	4:ec3f71ef8732	4531	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
Piasiv1206	4:ec3f71ef8732	4532	#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
Piasiv1206	4:ec3f71ef8732	4533	#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
Piasiv1206	4:ec3f71ef8732	4534	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
Piasiv1206	4:ec3f71ef8732	4535	/* FCFG1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4536	#define SIM_FCFG1_FLASHDIS_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4537	#define SIM_FCFG1_FLASHDIS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4538	#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4539	#define SIM_FCFG1_FLASHDOZE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4540	#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
Piasiv1206	4:ec3f71ef8732	4541	#define SIM_FCFG1_PFSIZE_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4542	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
Piasiv1206	4:ec3f71ef8732	4543	/* FCFG2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4544	#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
Piasiv1206	4:ec3f71ef8732	4545	#define SIM_FCFG2_MAXADDR1_SHIFT 16
Piasiv1206	4:ec3f71ef8732	4546	#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
Piasiv1206	4:ec3f71ef8732	4547	#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
Piasiv1206	4:ec3f71ef8732	4548	#define SIM_FCFG2_MAXADDR0_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4549	#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
Piasiv1206	4:ec3f71ef8732	4550	/* UIDMH Bit Fields */
Piasiv1206	4:ec3f71ef8732	4551	#define SIM_UIDMH_UID_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	4552	#define SIM_UIDMH_UID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4553	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
Piasiv1206	4:ec3f71ef8732	4554	/* UIDML Bit Fields */
Piasiv1206	4:ec3f71ef8732	4555	#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4556	#define SIM_UIDML_UID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4557	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
Piasiv1206	4:ec3f71ef8732	4558	/* UIDL Bit Fields */
Piasiv1206	4:ec3f71ef8732	4559	#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
Piasiv1206	4:ec3f71ef8732	4560	#define SIM_UIDL_UID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4561	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
Piasiv1206	4:ec3f71ef8732	4562	/* COPC Bit Fields */
Piasiv1206	4:ec3f71ef8732	4563	#define SIM_COPC_COPW_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4564	#define SIM_COPC_COPW_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4565	#define SIM_COPC_COPCLKS_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4566	#define SIM_COPC_COPCLKS_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4567	#define SIM_COPC_COPT_MASK 0xCu
Piasiv1206	4:ec3f71ef8732	4568	#define SIM_COPC_COPT_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4569	#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
Piasiv1206	4:ec3f71ef8732	4570	/* SRVCOP Bit Fields */
Piasiv1206	4:ec3f71ef8732	4571	#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	4572	#define SIM_SRVCOP_SRVCOP_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4573	#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
Piasiv1206	4:ec3f71ef8732	4574
Piasiv1206	4:ec3f71ef8732	4575	/*!
Piasiv1206	4:ec3f71ef8732	4576	* @}
Piasiv1206	4:ec3f71ef8732	4577	/ / end of group SIM_Register_Masks */
Piasiv1206	4:ec3f71ef8732	4578
Piasiv1206	4:ec3f71ef8732	4579
Piasiv1206	4:ec3f71ef8732	4580	/* SIM - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	4581	/** Peripheral SIM base address */
Piasiv1206	4:ec3f71ef8732	4582	#define SIM_BASE (0x40047000u)
Piasiv1206	4:ec3f71ef8732	4583	/** Peripheral SIM base pointer */
Piasiv1206	4:ec3f71ef8732	4584	#define SIM ((SIM_Type *)SIM_BASE)
Piasiv1206	4:ec3f71ef8732	4585	/** Array initializer of SIM peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	4586	#define SIM_BASES { SIM }
Piasiv1206	4:ec3f71ef8732	4587
Piasiv1206	4:ec3f71ef8732	4588	/*!
Piasiv1206	4:ec3f71ef8732	4589	* @}
Piasiv1206	4:ec3f71ef8732	4590	/ / end of group SIM_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	4591
Piasiv1206	4:ec3f71ef8732	4592
Piasiv1206	4:ec3f71ef8732	4593	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4594	-- SMC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4595	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4596
Piasiv1206	4:ec3f71ef8732	4597	/*!
Piasiv1206	4:ec3f71ef8732	4598	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4599	* @{
Piasiv1206	4:ec3f71ef8732	4600	*/
Piasiv1206	4:ec3f71ef8732	4601
Piasiv1206	4:ec3f71ef8732	4602	/** SMC - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	4603	typedef struct {
Piasiv1206	4:ec3f71ef8732	4604	__IO uint8_t PMPROT; /*< Power Mode Protection register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	4605	__IO uint8_t PMCTRL; /*< Power Mode Control register, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	4606	__IO uint8_t STOPCTRL; /*< Stop Control Register, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	4607	__I uint8_t PMSTAT; /*< Power Mode Status register, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	4608	} SMC_Type;
Piasiv1206	4:ec3f71ef8732	4609
Piasiv1206	4:ec3f71ef8732	4610	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4611	-- SMC Register Masks
Piasiv1206	4:ec3f71ef8732	4612	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4613
Piasiv1206	4:ec3f71ef8732	4614	/*!
Piasiv1206	4:ec3f71ef8732	4615	* @addtogroup SMC_Register_Masks SMC Register Masks
Piasiv1206	4:ec3f71ef8732	4616	* @{
Piasiv1206	4:ec3f71ef8732	4617	*/
Piasiv1206	4:ec3f71ef8732	4618
Piasiv1206	4:ec3f71ef8732	4619	/* PMPROT Bit Fields */
Piasiv1206	4:ec3f71ef8732	4620	#define SMC_PMPROT_AVLLS_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4621	#define SMC_PMPROT_AVLLS_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4622	#define SMC_PMPROT_ALLS_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4623	#define SMC_PMPROT_ALLS_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4624	#define SMC_PMPROT_AVLP_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4625	#define SMC_PMPROT_AVLP_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4626	/* PMCTRL Bit Fields */
Piasiv1206	4:ec3f71ef8732	4627	#define SMC_PMCTRL_STOPM_MASK 0x7u
Piasiv1206	4:ec3f71ef8732	4628	#define SMC_PMCTRL_STOPM_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4629	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
Piasiv1206	4:ec3f71ef8732	4630	#define SMC_PMCTRL_STOPA_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4631	#define SMC_PMCTRL_STOPA_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4632	#define SMC_PMCTRL_RUNM_MASK 0x60u
Piasiv1206	4:ec3f71ef8732	4633	#define SMC_PMCTRL_RUNM_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4634	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
Piasiv1206	4:ec3f71ef8732	4635	/* STOPCTRL Bit Fields */
Piasiv1206	4:ec3f71ef8732	4636	#define SMC_STOPCTRL_VLLSM_MASK 0x7u
Piasiv1206	4:ec3f71ef8732	4637	#define SMC_STOPCTRL_VLLSM_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4638	#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
Piasiv1206	4:ec3f71ef8732	4639	#define SMC_STOPCTRL_PORPO_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4640	#define SMC_STOPCTRL_PORPO_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4641	#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	4642	#define SMC_STOPCTRL_PSTOPO_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4643	#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
Piasiv1206	4:ec3f71ef8732	4644	/* PMSTAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	4645	#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
Piasiv1206	4:ec3f71ef8732	4646	#define SMC_PMSTAT_PMSTAT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4647	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
Piasiv1206	4:ec3f71ef8732	4648
Piasiv1206	4:ec3f71ef8732	4649	/*!
Piasiv1206	4:ec3f71ef8732	4650	* @}
Piasiv1206	4:ec3f71ef8732	4651	/ / end of group SMC_Register_Masks */
Piasiv1206	4:ec3f71ef8732	4652
Piasiv1206	4:ec3f71ef8732	4653
Piasiv1206	4:ec3f71ef8732	4654	/* SMC - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	4655	/** Peripheral SMC base address */
Piasiv1206	4:ec3f71ef8732	4656	#define SMC_BASE (0x4007E000u)
Piasiv1206	4:ec3f71ef8732	4657	/** Peripheral SMC base pointer */
Piasiv1206	4:ec3f71ef8732	4658	#define SMC ((SMC_Type *)SMC_BASE)
Piasiv1206	4:ec3f71ef8732	4659	/** Array initializer of SMC peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	4660	#define SMC_BASES { SMC }
Piasiv1206	4:ec3f71ef8732	4661
Piasiv1206	4:ec3f71ef8732	4662	/*!
Piasiv1206	4:ec3f71ef8732	4663	* @}
Piasiv1206	4:ec3f71ef8732	4664	/ / end of group SMC_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	4665
Piasiv1206	4:ec3f71ef8732	4666
Piasiv1206	4:ec3f71ef8732	4667	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4668	-- SPI Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4669	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4670
Piasiv1206	4:ec3f71ef8732	4671	/*!
Piasiv1206	4:ec3f71ef8732	4672	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4673	* @{
Piasiv1206	4:ec3f71ef8732	4674	*/
Piasiv1206	4:ec3f71ef8732	4675
Piasiv1206	4:ec3f71ef8732	4676	/** SPI - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	4677	typedef struct {
Piasiv1206	4:ec3f71ef8732	4678	__I uint8_t S; /*< SPI status register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	4679	__IO uint8_t BR; /*< SPI baud rate register, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	4680	__IO uint8_t C2; /*< SPI control register 2, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	4681	__IO uint8_t C1; /*< SPI control register 1, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	4682	__IO uint8_t ML; /*< SPI match register low, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	4683	__IO uint8_t MH; /*< SPI match register high, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	4684	__IO uint8_t DL; /*< SPI data register low, offset: 0x6 /
Piasiv1206	4:ec3f71ef8732	4685	__IO uint8_t DH; /*< SPI data register high, offset: 0x7 /
Piasiv1206	4:ec3f71ef8732	4686	uint8_t RESERVED_0[2];
Piasiv1206	4:ec3f71ef8732	4687	__IO uint8_t CI; /*< SPI clear interrupt register, offset: 0xA /
Piasiv1206	4:ec3f71ef8732	4688	__IO uint8_t C3; /*< SPI control register 3, offset: 0xB /
Piasiv1206	4:ec3f71ef8732	4689	} SPI_Type;
Piasiv1206	4:ec3f71ef8732	4690
Piasiv1206	4:ec3f71ef8732	4691	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4692	-- SPI Register Masks
Piasiv1206	4:ec3f71ef8732	4693	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4694
Piasiv1206	4:ec3f71ef8732	4695	/*!
Piasiv1206	4:ec3f71ef8732	4696	* @addtogroup SPI_Register_Masks SPI Register Masks
Piasiv1206	4:ec3f71ef8732	4697	* @{
Piasiv1206	4:ec3f71ef8732	4698	*/
Piasiv1206	4:ec3f71ef8732	4699
Piasiv1206	4:ec3f71ef8732	4700	/* S Bit Fields */
Piasiv1206	4:ec3f71ef8732	4701	#define SPI_S_RFIFOEF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4702	#define SPI_S_RFIFOEF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4703	#define SPI_S_TXFULLF_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4704	#define SPI_S_TXFULLF_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4705	#define SPI_S_TNEAREF_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4706	#define SPI_S_TNEAREF_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4707	#define SPI_S_RNFULLF_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4708	#define SPI_S_RNFULLF_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4709	#define SPI_S_MODF_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4710	#define SPI_S_MODF_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4711	#define SPI_S_SPTEF_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4712	#define SPI_S_SPTEF_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4713	#define SPI_S_SPMF_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4714	#define SPI_S_SPMF_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4715	#define SPI_S_SPRF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4716	#define SPI_S_SPRF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4717	/* BR Bit Fields */
Piasiv1206	4:ec3f71ef8732	4718	#define SPI_BR_SPR_MASK 0xFu
Piasiv1206	4:ec3f71ef8732	4719	#define SPI_BR_SPR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4720	#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
Piasiv1206	4:ec3f71ef8732	4721	#define SPI_BR_SPPR_MASK 0x70u
Piasiv1206	4:ec3f71ef8732	4722	#define SPI_BR_SPPR_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4723	#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
Piasiv1206	4:ec3f71ef8732	4724	/* C2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4725	#define SPI_C2_SPC0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4726	#define SPI_C2_SPC0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4727	#define SPI_C2_SPISWAI_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4728	#define SPI_C2_SPISWAI_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4729	#define SPI_C2_RXDMAE_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4730	#define SPI_C2_RXDMAE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4731	#define SPI_C2_BIDIROE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4732	#define SPI_C2_BIDIROE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4733	#define SPI_C2_MODFEN_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4734	#define SPI_C2_MODFEN_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4735	#define SPI_C2_TXDMAE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4736	#define SPI_C2_TXDMAE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4737	#define SPI_C2_SPIMODE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4738	#define SPI_C2_SPIMODE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4739	#define SPI_C2_SPMIE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4740	#define SPI_C2_SPMIE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4741	/* C1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4742	#define SPI_C1_LSBFE_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4743	#define SPI_C1_LSBFE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4744	#define SPI_C1_SSOE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4745	#define SPI_C1_SSOE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4746	#define SPI_C1_CPHA_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4747	#define SPI_C1_CPHA_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4748	#define SPI_C1_CPOL_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4749	#define SPI_C1_CPOL_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4750	#define SPI_C1_MSTR_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4751	#define SPI_C1_MSTR_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4752	#define SPI_C1_SPTIE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4753	#define SPI_C1_SPTIE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4754	#define SPI_C1_SPE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4755	#define SPI_C1_SPE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4756	#define SPI_C1_SPIE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4757	#define SPI_C1_SPIE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4758	/* ML Bit Fields */
Piasiv1206	4:ec3f71ef8732	4759	#define SPI_ML_Bits_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	4760	#define SPI_ML_Bits_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4761	#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
Piasiv1206	4:ec3f71ef8732	4762	/* MH Bit Fields */
Piasiv1206	4:ec3f71ef8732	4763	#define SPI_MH_Bits_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	4764	#define SPI_MH_Bits_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4765	#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
Piasiv1206	4:ec3f71ef8732	4766	/* DL Bit Fields */
Piasiv1206	4:ec3f71ef8732	4767	#define SPI_DL_Bits_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	4768	#define SPI_DL_Bits_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4769	#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
Piasiv1206	4:ec3f71ef8732	4770	/* DH Bit Fields */
Piasiv1206	4:ec3f71ef8732	4771	#define SPI_DH_Bits_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	4772	#define SPI_DH_Bits_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4773	#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
Piasiv1206	4:ec3f71ef8732	4774	/* CI Bit Fields */
Piasiv1206	4:ec3f71ef8732	4775	#define SPI_CI_SPRFCI_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4776	#define SPI_CI_SPRFCI_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4777	#define SPI_CI_SPTEFCI_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4778	#define SPI_CI_SPTEFCI_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4779	#define SPI_CI_RNFULLFCI_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4780	#define SPI_CI_RNFULLFCI_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4781	#define SPI_CI_TNEAREFCI_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4782	#define SPI_CI_TNEAREFCI_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4783	#define SPI_CI_RXFOF_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4784	#define SPI_CI_RXFOF_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4785	#define SPI_CI_TXFOF_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4786	#define SPI_CI_TXFOF_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4787	#define SPI_CI_RXFERR_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4788	#define SPI_CI_RXFERR_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4789	#define SPI_CI_TXFERR_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4790	#define SPI_CI_TXFERR_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4791	/* C3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	4792	#define SPI_C3_FIFOMODE_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4793	#define SPI_C3_FIFOMODE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4794	#define SPI_C3_RNFULLIEN_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4795	#define SPI_C3_RNFULLIEN_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4796	#define SPI_C3_TNEARIEN_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4797	#define SPI_C3_TNEARIEN_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4798	#define SPI_C3_INTCLR_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4799	#define SPI_C3_INTCLR_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4800	#define SPI_C3_RNFULLF_MARK_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4801	#define SPI_C3_RNFULLF_MARK_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4802	#define SPI_C3_TNEAREF_MARK_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4803	#define SPI_C3_TNEAREF_MARK_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4804
Piasiv1206	4:ec3f71ef8732	4805	/*!
Piasiv1206	4:ec3f71ef8732	4806	* @}
Piasiv1206	4:ec3f71ef8732	4807	/ / end of group SPI_Register_Masks */
Piasiv1206	4:ec3f71ef8732	4808
Piasiv1206	4:ec3f71ef8732	4809
Piasiv1206	4:ec3f71ef8732	4810	/* SPI - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	4811	/** Peripheral SPI0 base address */
Piasiv1206	4:ec3f71ef8732	4812	#define SPI0_BASE (0x40076000u)
Piasiv1206	4:ec3f71ef8732	4813	/** Peripheral SPI0 base pointer */
Piasiv1206	4:ec3f71ef8732	4814	#define SPI0 ((SPI_Type *)SPI0_BASE)
Piasiv1206	4:ec3f71ef8732	4815	/** Peripheral SPI1 base address */
Piasiv1206	4:ec3f71ef8732	4816	#define SPI1_BASE (0x40077000u)
Piasiv1206	4:ec3f71ef8732	4817	/** Peripheral SPI1 base pointer */
Piasiv1206	4:ec3f71ef8732	4818	#define SPI1 ((SPI_Type *)SPI1_BASE)
Piasiv1206	4:ec3f71ef8732	4819	/** Array initializer of SPI peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	4820	#define SPI_BASES { SPI0, SPI1 }
Piasiv1206	4:ec3f71ef8732	4821
Piasiv1206	4:ec3f71ef8732	4822	/*!
Piasiv1206	4:ec3f71ef8732	4823	* @}
Piasiv1206	4:ec3f71ef8732	4824	/ / end of group SPI_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	4825
Piasiv1206	4:ec3f71ef8732	4826
Piasiv1206	4:ec3f71ef8732	4827	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4828	-- TPM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4829	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4830
Piasiv1206	4:ec3f71ef8732	4831	/*!
Piasiv1206	4:ec3f71ef8732	4832	* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4833	* @{
Piasiv1206	4:ec3f71ef8732	4834	*/
Piasiv1206	4:ec3f71ef8732	4835
Piasiv1206	4:ec3f71ef8732	4836	/** TPM - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	4837	typedef struct {
Piasiv1206	4:ec3f71ef8732	4838	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	4839	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	4840	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	4841	struct { /* offset: 0xC, array step: 0x8 */
Piasiv1206	4:ec3f71ef8732	4842	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
Piasiv1206	4:ec3f71ef8732	4843	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
Piasiv1206	4:ec3f71ef8732	4844	} CONTROLS[6];
Piasiv1206	4:ec3f71ef8732	4845	uint8_t RESERVED_0[20];
Piasiv1206	4:ec3f71ef8732	4846	__IO uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
Piasiv1206	4:ec3f71ef8732	4847	uint8_t RESERVED_1[48];
Piasiv1206	4:ec3f71ef8732	4848	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
Piasiv1206	4:ec3f71ef8732	4849	} TPM_Type;
Piasiv1206	4:ec3f71ef8732	4850
Piasiv1206	4:ec3f71ef8732	4851	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4852	-- TPM Register Masks
Piasiv1206	4:ec3f71ef8732	4853	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4854
Piasiv1206	4:ec3f71ef8732	4855	/*!
Piasiv1206	4:ec3f71ef8732	4856	* @addtogroup TPM_Register_Masks TPM Register Masks
Piasiv1206	4:ec3f71ef8732	4857	* @{
Piasiv1206	4:ec3f71ef8732	4858	*/
Piasiv1206	4:ec3f71ef8732	4859
Piasiv1206	4:ec3f71ef8732	4860	/* SC Bit Fields */
Piasiv1206	4:ec3f71ef8732	4861	#define TPM_SC_PS_MASK 0x7u
Piasiv1206	4:ec3f71ef8732	4862	#define TPM_SC_PS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4863	#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
Piasiv1206	4:ec3f71ef8732	4864	#define TPM_SC_CMOD_MASK 0x18u
Piasiv1206	4:ec3f71ef8732	4865	#define TPM_SC_CMOD_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4866	#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
Piasiv1206	4:ec3f71ef8732	4867	#define TPM_SC_CPWMS_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4868	#define TPM_SC_CPWMS_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4869	#define TPM_SC_TOIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4870	#define TPM_SC_TOIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4871	#define TPM_SC_TOF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4872	#define TPM_SC_TOF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4873	#define TPM_SC_DMA_MASK 0x100u
Piasiv1206	4:ec3f71ef8732	4874	#define TPM_SC_DMA_SHIFT 8
Piasiv1206	4:ec3f71ef8732	4875	/* CNT Bit Fields */
Piasiv1206	4:ec3f71ef8732	4876	#define TPM_CNT_COUNT_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	4877	#define TPM_CNT_COUNT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4878	#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
Piasiv1206	4:ec3f71ef8732	4879	/* MOD Bit Fields */
Piasiv1206	4:ec3f71ef8732	4880	#define TPM_MOD_MOD_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	4881	#define TPM_MOD_MOD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4882	#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
Piasiv1206	4:ec3f71ef8732	4883	/* CnSC Bit Fields */
Piasiv1206	4:ec3f71ef8732	4884	#define TPM_CnSC_DMA_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4885	#define TPM_CnSC_DMA_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4886	#define TPM_CnSC_ELSA_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4887	#define TPM_CnSC_ELSA_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4888	#define TPM_CnSC_ELSB_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4889	#define TPM_CnSC_ELSB_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4890	#define TPM_CnSC_MSA_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4891	#define TPM_CnSC_MSA_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4892	#define TPM_CnSC_MSB_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4893	#define TPM_CnSC_MSB_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4894	#define TPM_CnSC_CHIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4895	#define TPM_CnSC_CHIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4896	#define TPM_CnSC_CHF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	4897	#define TPM_CnSC_CHF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	4898	/* CnV Bit Fields */
Piasiv1206	4:ec3f71ef8732	4899	#define TPM_CnV_VAL_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	4900	#define TPM_CnV_VAL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4901	#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
Piasiv1206	4:ec3f71ef8732	4902	/* STATUS Bit Fields */
Piasiv1206	4:ec3f71ef8732	4903	#define TPM_STATUS_CH0F_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	4904	#define TPM_STATUS_CH0F_SHIFT 0
Piasiv1206	4:ec3f71ef8732	4905	#define TPM_STATUS_CH1F_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4906	#define TPM_STATUS_CH1F_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4907	#define TPM_STATUS_CH2F_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4908	#define TPM_STATUS_CH2F_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4909	#define TPM_STATUS_CH3F_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4910	#define TPM_STATUS_CH3F_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4911	#define TPM_STATUS_CH4F_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4912	#define TPM_STATUS_CH4F_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4913	#define TPM_STATUS_CH5F_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4914	#define TPM_STATUS_CH5F_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4915	#define TPM_STATUS_TOF_MASK 0x100u
Piasiv1206	4:ec3f71ef8732	4916	#define TPM_STATUS_TOF_SHIFT 8
Piasiv1206	4:ec3f71ef8732	4917	/* CONF Bit Fields */
Piasiv1206	4:ec3f71ef8732	4918	#define TPM_CONF_DOZEEN_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4919	#define TPM_CONF_DOZEEN_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4920	#define TPM_CONF_DBGMODE_MASK 0xC0u
Piasiv1206	4:ec3f71ef8732	4921	#define TPM_CONF_DBGMODE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4922	#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
Piasiv1206	4:ec3f71ef8732	4923	#define TPM_CONF_GTBEEN_MASK 0x200u
Piasiv1206	4:ec3f71ef8732	4924	#define TPM_CONF_GTBEEN_SHIFT 9
Piasiv1206	4:ec3f71ef8732	4925	#define TPM_CONF_CSOT_MASK 0x10000u
Piasiv1206	4:ec3f71ef8732	4926	#define TPM_CONF_CSOT_SHIFT 16
Piasiv1206	4:ec3f71ef8732	4927	#define TPM_CONF_CSOO_MASK 0x20000u
Piasiv1206	4:ec3f71ef8732	4928	#define TPM_CONF_CSOO_SHIFT 17
Piasiv1206	4:ec3f71ef8732	4929	#define TPM_CONF_CROT_MASK 0x40000u
Piasiv1206	4:ec3f71ef8732	4930	#define TPM_CONF_CROT_SHIFT 18
Piasiv1206	4:ec3f71ef8732	4931	#define TPM_CONF_TRGSEL_MASK 0xF000000u
Piasiv1206	4:ec3f71ef8732	4932	#define TPM_CONF_TRGSEL_SHIFT 24
Piasiv1206	4:ec3f71ef8732	4933	#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
Piasiv1206	4:ec3f71ef8732	4934
Piasiv1206	4:ec3f71ef8732	4935	/*!
Piasiv1206	4:ec3f71ef8732	4936	* @}
Piasiv1206	4:ec3f71ef8732	4937	/ / end of group TPM_Register_Masks */
Piasiv1206	4:ec3f71ef8732	4938
Piasiv1206	4:ec3f71ef8732	4939
Piasiv1206	4:ec3f71ef8732	4940	/* TPM - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	4941	/** Peripheral TPM0 base address */
Piasiv1206	4:ec3f71ef8732	4942	#define TPM0_BASE (0x40038000u)
Piasiv1206	4:ec3f71ef8732	4943	/** Peripheral TPM0 base pointer */
Piasiv1206	4:ec3f71ef8732	4944	#define TPM0 ((TPM_Type *)TPM0_BASE)
Piasiv1206	4:ec3f71ef8732	4945	/** Peripheral TPM1 base address */
Piasiv1206	4:ec3f71ef8732	4946	#define TPM1_BASE (0x40039000u)
Piasiv1206	4:ec3f71ef8732	4947	/** Peripheral TPM1 base pointer */
Piasiv1206	4:ec3f71ef8732	4948	#define TPM1 ((TPM_Type *)TPM1_BASE)
Piasiv1206	4:ec3f71ef8732	4949	/** Peripheral TPM2 base address */
Piasiv1206	4:ec3f71ef8732	4950	#define TPM2_BASE (0x4003A000u)
Piasiv1206	4:ec3f71ef8732	4951	/** Peripheral TPM2 base pointer */
Piasiv1206	4:ec3f71ef8732	4952	#define TPM2 ((TPM_Type *)TPM2_BASE)
Piasiv1206	4:ec3f71ef8732	4953	/** Array initializer of TPM peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	4954	#define TPM_BASES { TPM0, TPM1, TPM2 }
Piasiv1206	4:ec3f71ef8732	4955
Piasiv1206	4:ec3f71ef8732	4956	/*!
Piasiv1206	4:ec3f71ef8732	4957	* @}
Piasiv1206	4:ec3f71ef8732	4958	/ / end of group TPM_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	4959
Piasiv1206	4:ec3f71ef8732	4960
Piasiv1206	4:ec3f71ef8732	4961	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4962	-- TSI Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4963	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4964
Piasiv1206	4:ec3f71ef8732	4965	/*!
Piasiv1206	4:ec3f71ef8732	4966	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	4967	* @{
Piasiv1206	4:ec3f71ef8732	4968	*/
Piasiv1206	4:ec3f71ef8732	4969
Piasiv1206	4:ec3f71ef8732	4970	/** TSI - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	4971	typedef struct {
Piasiv1206	4:ec3f71ef8732	4972	__IO uint32_t GENCS; /*< TSI General Control and Status Register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	4973	__IO uint32_t DATA; /*< TSI DATA Register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	4974	__IO uint32_t TSHD; /*< TSI Threshold Register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	4975	} TSI_Type;
Piasiv1206	4:ec3f71ef8732	4976
Piasiv1206	4:ec3f71ef8732	4977	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	4978	-- TSI Register Masks
Piasiv1206	4:ec3f71ef8732	4979	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	4980
Piasiv1206	4:ec3f71ef8732	4981	/*!
Piasiv1206	4:ec3f71ef8732	4982	* @addtogroup TSI_Register_Masks TSI Register Masks
Piasiv1206	4:ec3f71ef8732	4983	* @{
Piasiv1206	4:ec3f71ef8732	4984	*/
Piasiv1206	4:ec3f71ef8732	4985
Piasiv1206	4:ec3f71ef8732	4986	/* GENCS Bit Fields */
Piasiv1206	4:ec3f71ef8732	4987	#define TSI_GENCS_CURSW_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	4988	#define TSI_GENCS_CURSW_SHIFT 1
Piasiv1206	4:ec3f71ef8732	4989	#define TSI_GENCS_EOSF_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	4990	#define TSI_GENCS_EOSF_SHIFT 2
Piasiv1206	4:ec3f71ef8732	4991	#define TSI_GENCS_SCNIP_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	4992	#define TSI_GENCS_SCNIP_SHIFT 3
Piasiv1206	4:ec3f71ef8732	4993	#define TSI_GENCS_STM_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	4994	#define TSI_GENCS_STM_SHIFT 4
Piasiv1206	4:ec3f71ef8732	4995	#define TSI_GENCS_STPE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	4996	#define TSI_GENCS_STPE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	4997	#define TSI_GENCS_TSIIEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	4998	#define TSI_GENCS_TSIIEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	4999	#define TSI_GENCS_TSIEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5000	#define TSI_GENCS_TSIEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5001	#define TSI_GENCS_NSCN_MASK 0x1F00u
Piasiv1206	4:ec3f71ef8732	5002	#define TSI_GENCS_NSCN_SHIFT 8
Piasiv1206	4:ec3f71ef8732	5003	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
Piasiv1206	4:ec3f71ef8732	5004	#define TSI_GENCS_PS_MASK 0xE000u
Piasiv1206	4:ec3f71ef8732	5005	#define TSI_GENCS_PS_SHIFT 13
Piasiv1206	4:ec3f71ef8732	5006	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
Piasiv1206	4:ec3f71ef8732	5007	#define TSI_GENCS_EXTCHRG_MASK 0x70000u
Piasiv1206	4:ec3f71ef8732	5008	#define TSI_GENCS_EXTCHRG_SHIFT 16
Piasiv1206	4:ec3f71ef8732	5009	#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
Piasiv1206	4:ec3f71ef8732	5010	#define TSI_GENCS_DVOLT_MASK 0x180000u
Piasiv1206	4:ec3f71ef8732	5011	#define TSI_GENCS_DVOLT_SHIFT 19
Piasiv1206	4:ec3f71ef8732	5012	#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
Piasiv1206	4:ec3f71ef8732	5013	#define TSI_GENCS_REFCHRG_MASK 0xE00000u
Piasiv1206	4:ec3f71ef8732	5014	#define TSI_GENCS_REFCHRG_SHIFT 21
Piasiv1206	4:ec3f71ef8732	5015	#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
Piasiv1206	4:ec3f71ef8732	5016	#define TSI_GENCS_MODE_MASK 0xF000000u
Piasiv1206	4:ec3f71ef8732	5017	#define TSI_GENCS_MODE_SHIFT 24
Piasiv1206	4:ec3f71ef8732	5018	#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
Piasiv1206	4:ec3f71ef8732	5019	#define TSI_GENCS_ESOR_MASK 0x10000000u
Piasiv1206	4:ec3f71ef8732	5020	#define TSI_GENCS_ESOR_SHIFT 28
Piasiv1206	4:ec3f71ef8732	5021	#define TSI_GENCS_OUTRGF_MASK 0x80000000u
Piasiv1206	4:ec3f71ef8732	5022	#define TSI_GENCS_OUTRGF_SHIFT 31
Piasiv1206	4:ec3f71ef8732	5023	/* DATA Bit Fields */
Piasiv1206	4:ec3f71ef8732	5024	#define TSI_DATA_TSICNT_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	5025	#define TSI_DATA_TSICNT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5026	#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
Piasiv1206	4:ec3f71ef8732	5027	#define TSI_DATA_SWTS_MASK 0x400000u
Piasiv1206	4:ec3f71ef8732	5028	#define TSI_DATA_SWTS_SHIFT 22
Piasiv1206	4:ec3f71ef8732	5029	#define TSI_DATA_DMAEN_MASK 0x800000u
Piasiv1206	4:ec3f71ef8732	5030	#define TSI_DATA_DMAEN_SHIFT 23
Piasiv1206	4:ec3f71ef8732	5031	#define TSI_DATA_TSICH_MASK 0xF0000000u
Piasiv1206	4:ec3f71ef8732	5032	#define TSI_DATA_TSICH_SHIFT 28
Piasiv1206	4:ec3f71ef8732	5033	#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
Piasiv1206	4:ec3f71ef8732	5034	/* TSHD Bit Fields */
Piasiv1206	4:ec3f71ef8732	5035	#define TSI_TSHD_THRESL_MASK 0xFFFFu
Piasiv1206	4:ec3f71ef8732	5036	#define TSI_TSHD_THRESL_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5037	#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
Piasiv1206	4:ec3f71ef8732	5038	#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
Piasiv1206	4:ec3f71ef8732	5039	#define TSI_TSHD_THRESH_SHIFT 16
Piasiv1206	4:ec3f71ef8732	5040	#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
Piasiv1206	4:ec3f71ef8732	5041
Piasiv1206	4:ec3f71ef8732	5042	/*!
Piasiv1206	4:ec3f71ef8732	5043	* @}
Piasiv1206	4:ec3f71ef8732	5044	/ / end of group TSI_Register_Masks */
Piasiv1206	4:ec3f71ef8732	5045
Piasiv1206	4:ec3f71ef8732	5046
Piasiv1206	4:ec3f71ef8732	5047	/* TSI - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	5048	/** Peripheral TSI0 base address */
Piasiv1206	4:ec3f71ef8732	5049	#define TSI0_BASE (0x40045000u)
Piasiv1206	4:ec3f71ef8732	5050	/** Peripheral TSI0 base pointer */
Piasiv1206	4:ec3f71ef8732	5051	#define TSI0 ((TSI_Type *)TSI0_BASE)
Piasiv1206	4:ec3f71ef8732	5052	/** Array initializer of TSI peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	5053	#define TSI_BASES { TSI0 }
Piasiv1206	4:ec3f71ef8732	5054
Piasiv1206	4:ec3f71ef8732	5055	/*!
Piasiv1206	4:ec3f71ef8732	5056	* @}
Piasiv1206	4:ec3f71ef8732	5057	/ / end of group TSI_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	5058
Piasiv1206	4:ec3f71ef8732	5059
Piasiv1206	4:ec3f71ef8732	5060	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	5061	-- UART Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	5062	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	5063
Piasiv1206	4:ec3f71ef8732	5064	/*!
Piasiv1206	4:ec3f71ef8732	5065	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	5066	* @{
Piasiv1206	4:ec3f71ef8732	5067	*/
Piasiv1206	4:ec3f71ef8732	5068
Piasiv1206	4:ec3f71ef8732	5069	/** UART - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	5070	typedef struct {
Piasiv1206	4:ec3f71ef8732	5071	__IO uint8_t BDH; /*< UART Baud Rate Register: High, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	5072	__IO uint8_t BDL; /*< UART Baud Rate Register: Low, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	5073	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	5074	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	5075	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	5076	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	5077	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
Piasiv1206	4:ec3f71ef8732	5078	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
Piasiv1206	4:ec3f71ef8732	5079	__IO uint8_t C4; /*< UART Control Register 4, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	5080	} UART_Type;
Piasiv1206	4:ec3f71ef8732	5081
Piasiv1206	4:ec3f71ef8732	5082	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	5083	-- UART Register Masks
Piasiv1206	4:ec3f71ef8732	5084	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	5085
Piasiv1206	4:ec3f71ef8732	5086	/*!
Piasiv1206	4:ec3f71ef8732	5087	* @addtogroup UART_Register_Masks UART Register Masks
Piasiv1206	4:ec3f71ef8732	5088	* @{
Piasiv1206	4:ec3f71ef8732	5089	*/
Piasiv1206	4:ec3f71ef8732	5090
Piasiv1206	4:ec3f71ef8732	5091	/* BDH Bit Fields */
Piasiv1206	4:ec3f71ef8732	5092	#define UART_BDH_SBR_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	5093	#define UART_BDH_SBR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5094	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
Piasiv1206	4:ec3f71ef8732	5095	#define UART_BDH_SBNS_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5096	#define UART_BDH_SBNS_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5097	#define UART_BDH_RXEDGIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5098	#define UART_BDH_RXEDGIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5099	#define UART_BDH_LBKDIE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5100	#define UART_BDH_LBKDIE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5101	/* BDL Bit Fields */
Piasiv1206	4:ec3f71ef8732	5102	#define UART_BDL_SBR_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5103	#define UART_BDL_SBR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5104	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
Piasiv1206	4:ec3f71ef8732	5105	/* C1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5106	#define UART_C1_PT_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5107	#define UART_C1_PT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5108	#define UART_C1_PE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5109	#define UART_C1_PE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5110	#define UART_C1_ILT_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5111	#define UART_C1_ILT_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5112	#define UART_C1_WAKE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5113	#define UART_C1_WAKE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5114	#define UART_C1_M_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5115	#define UART_C1_M_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5116	#define UART_C1_RSRC_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5117	#define UART_C1_RSRC_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5118	#define UART_C1_UARTSWAI_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5119	#define UART_C1_UARTSWAI_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5120	#define UART_C1_LOOPS_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5121	#define UART_C1_LOOPS_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5122	/* C2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5123	#define UART_C2_SBK_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5124	#define UART_C2_SBK_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5125	#define UART_C2_RWU_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5126	#define UART_C2_RWU_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5127	#define UART_C2_RE_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5128	#define UART_C2_RE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5129	#define UART_C2_TE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5130	#define UART_C2_TE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5131	#define UART_C2_ILIE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5132	#define UART_C2_ILIE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5133	#define UART_C2_RIE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5134	#define UART_C2_RIE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5135	#define UART_C2_TCIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5136	#define UART_C2_TCIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5137	#define UART_C2_TIE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5138	#define UART_C2_TIE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5139	/* S1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5140	#define UART_S1_PF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5141	#define UART_S1_PF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5142	#define UART_S1_FE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5143	#define UART_S1_FE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5144	#define UART_S1_NF_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5145	#define UART_S1_NF_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5146	#define UART_S1_OR_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5147	#define UART_S1_OR_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5148	#define UART_S1_IDLE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5149	#define UART_S1_IDLE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5150	#define UART_S1_RDRF_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5151	#define UART_S1_RDRF_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5152	#define UART_S1_TC_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5153	#define UART_S1_TC_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5154	#define UART_S1_TDRE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5155	#define UART_S1_TDRE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5156	/* S2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5157	#define UART_S2_RAF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5158	#define UART_S2_RAF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5159	#define UART_S2_LBKDE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5160	#define UART_S2_LBKDE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5161	#define UART_S2_BRK13_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5162	#define UART_S2_BRK13_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5163	#define UART_S2_RWUID_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5164	#define UART_S2_RWUID_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5165	#define UART_S2_RXINV_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5166	#define UART_S2_RXINV_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5167	#define UART_S2_RXEDGIF_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5168	#define UART_S2_RXEDGIF_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5169	#define UART_S2_LBKDIF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5170	#define UART_S2_LBKDIF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5171	/* C3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5172	#define UART_C3_PEIE_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5173	#define UART_C3_PEIE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5174	#define UART_C3_FEIE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5175	#define UART_C3_FEIE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5176	#define UART_C3_NEIE_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5177	#define UART_C3_NEIE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5178	#define UART_C3_ORIE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5179	#define UART_C3_ORIE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5180	#define UART_C3_TXINV_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5181	#define UART_C3_TXINV_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5182	#define UART_C3_TXDIR_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5183	#define UART_C3_TXDIR_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5184	#define UART_C3_T8_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5185	#define UART_C3_T8_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5186	#define UART_C3_R8_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5187	#define UART_C3_R8_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5188	/* D Bit Fields */
Piasiv1206	4:ec3f71ef8732	5189	#define UART_D_R0T0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5190	#define UART_D_R0T0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5191	#define UART_D_R1T1_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5192	#define UART_D_R1T1_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5193	#define UART_D_R2T2_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5194	#define UART_D_R2T2_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5195	#define UART_D_R3T3_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5196	#define UART_D_R3T3_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5197	#define UART_D_R4T4_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5198	#define UART_D_R4T4_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5199	#define UART_D_R5T5_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5200	#define UART_D_R5T5_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5201	#define UART_D_R6T6_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5202	#define UART_D_R6T6_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5203	#define UART_D_R7T7_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5204	#define UART_D_R7T7_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5205	/* C4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5206	#define UART_C4_RDMAS_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5207	#define UART_C4_RDMAS_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5208	#define UART_C4_TDMAS_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5209	#define UART_C4_TDMAS_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5210
Piasiv1206	4:ec3f71ef8732	5211	/*!
Piasiv1206	4:ec3f71ef8732	5212	* @}
Piasiv1206	4:ec3f71ef8732	5213	/ / end of group UART_Register_Masks */
Piasiv1206	4:ec3f71ef8732	5214
Piasiv1206	4:ec3f71ef8732	5215
Piasiv1206	4:ec3f71ef8732	5216	/* UART - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	5217	/** Peripheral UART1 base address */
Piasiv1206	4:ec3f71ef8732	5218	#define UART1_BASE (0x4006B000u)
Piasiv1206	4:ec3f71ef8732	5219	/** Peripheral UART1 base pointer */
Piasiv1206	4:ec3f71ef8732	5220	#define UART1 ((UART_Type *)UART1_BASE)
Piasiv1206	4:ec3f71ef8732	5221	/** Peripheral UART2 base address */
Piasiv1206	4:ec3f71ef8732	5222	#define UART2_BASE (0x4006C000u)
Piasiv1206	4:ec3f71ef8732	5223	/** Peripheral UART2 base pointer */
Piasiv1206	4:ec3f71ef8732	5224	#define UART2 ((UART_Type *)UART2_BASE)
Piasiv1206	4:ec3f71ef8732	5225	/** Array initializer of UART peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	5226	#define UART_BASES { UART1, UART2 }
Piasiv1206	4:ec3f71ef8732	5227
Piasiv1206	4:ec3f71ef8732	5228	/*!
Piasiv1206	4:ec3f71ef8732	5229	* @}
Piasiv1206	4:ec3f71ef8732	5230	/ / end of group UART_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	5231
Piasiv1206	4:ec3f71ef8732	5232
Piasiv1206	4:ec3f71ef8732	5233	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	5234	-- UART0 Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	5235	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	5236
Piasiv1206	4:ec3f71ef8732	5237	/*!
Piasiv1206	4:ec3f71ef8732	5238	* @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	5239	* @{
Piasiv1206	4:ec3f71ef8732	5240	*/
Piasiv1206	4:ec3f71ef8732	5241
Piasiv1206	4:ec3f71ef8732	5242	/** UART0 - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	5243	typedef struct {
Piasiv1206	4:ec3f71ef8732	5244	__IO uint8_t BDH; /*< UART Baud Rate Register High, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	5245	__IO uint8_t BDL; /*< UART Baud Rate Register Low, offset: 0x1 /
Piasiv1206	4:ec3f71ef8732	5246	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
Piasiv1206	4:ec3f71ef8732	5247	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
Piasiv1206	4:ec3f71ef8732	5248	__IO uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	5249	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
Piasiv1206	4:ec3f71ef8732	5250	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
Piasiv1206	4:ec3f71ef8732	5251	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
Piasiv1206	4:ec3f71ef8732	5252	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	5253	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
Piasiv1206	4:ec3f71ef8732	5254	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
Piasiv1206	4:ec3f71ef8732	5255	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
Piasiv1206	4:ec3f71ef8732	5256	} UART0_Type;
Piasiv1206	4:ec3f71ef8732	5257
Piasiv1206	4:ec3f71ef8732	5258	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	5259	-- UART0 Register Masks
Piasiv1206	4:ec3f71ef8732	5260	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	5261
Piasiv1206	4:ec3f71ef8732	5262	/*!
Piasiv1206	4:ec3f71ef8732	5263	* @addtogroup UART0_Register_Masks UART0 Register Masks
Piasiv1206	4:ec3f71ef8732	5264	* @{
Piasiv1206	4:ec3f71ef8732	5265	*/
Piasiv1206	4:ec3f71ef8732	5266
Piasiv1206	4:ec3f71ef8732	5267	/* BDH Bit Fields */
Piasiv1206	4:ec3f71ef8732	5268	#define UART0_BDH_SBR_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	5269	#define UART0_BDH_SBR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5270	#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
Piasiv1206	4:ec3f71ef8732	5271	#define UART0_BDH_SBNS_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5272	#define UART0_BDH_SBNS_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5273	#define UART0_BDH_RXEDGIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5274	#define UART0_BDH_RXEDGIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5275	#define UART0_BDH_LBKDIE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5276	#define UART0_BDH_LBKDIE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5277	/* BDL Bit Fields */
Piasiv1206	4:ec3f71ef8732	5278	#define UART0_BDL_SBR_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5279	#define UART0_BDL_SBR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5280	#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
Piasiv1206	4:ec3f71ef8732	5281	/* C1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5282	#define UART0_C1_PT_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5283	#define UART0_C1_PT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5284	#define UART0_C1_PE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5285	#define UART0_C1_PE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5286	#define UART0_C1_ILT_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5287	#define UART0_C1_ILT_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5288	#define UART0_C1_WAKE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5289	#define UART0_C1_WAKE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5290	#define UART0_C1_M_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5291	#define UART0_C1_M_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5292	#define UART0_C1_RSRC_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5293	#define UART0_C1_RSRC_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5294	#define UART0_C1_DOZEEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5295	#define UART0_C1_DOZEEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5296	#define UART0_C1_LOOPS_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5297	#define UART0_C1_LOOPS_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5298	/* C2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5299	#define UART0_C2_SBK_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5300	#define UART0_C2_SBK_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5301	#define UART0_C2_RWU_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5302	#define UART0_C2_RWU_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5303	#define UART0_C2_RE_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5304	#define UART0_C2_RE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5305	#define UART0_C2_TE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5306	#define UART0_C2_TE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5307	#define UART0_C2_ILIE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5308	#define UART0_C2_ILIE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5309	#define UART0_C2_RIE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5310	#define UART0_C2_RIE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5311	#define UART0_C2_TCIE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5312	#define UART0_C2_TCIE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5313	#define UART0_C2_TIE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5314	#define UART0_C2_TIE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5315	/* S1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5316	#define UART0_S1_PF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5317	#define UART0_S1_PF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5318	#define UART0_S1_FE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5319	#define UART0_S1_FE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5320	#define UART0_S1_NF_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5321	#define UART0_S1_NF_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5322	#define UART0_S1_OR_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5323	#define UART0_S1_OR_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5324	#define UART0_S1_IDLE_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5325	#define UART0_S1_IDLE_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5326	#define UART0_S1_RDRF_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5327	#define UART0_S1_RDRF_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5328	#define UART0_S1_TC_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5329	#define UART0_S1_TC_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5330	#define UART0_S1_TDRE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5331	#define UART0_S1_TDRE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5332	/* S2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5333	#define UART0_S2_RAF_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5334	#define UART0_S2_RAF_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5335	#define UART0_S2_LBKDE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5336	#define UART0_S2_LBKDE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5337	#define UART0_S2_BRK13_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5338	#define UART0_S2_BRK13_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5339	#define UART0_S2_RWUID_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5340	#define UART0_S2_RWUID_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5341	#define UART0_S2_RXINV_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5342	#define UART0_S2_RXINV_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5343	#define UART0_S2_MSBF_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5344	#define UART0_S2_MSBF_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5345	#define UART0_S2_RXEDGIF_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5346	#define UART0_S2_RXEDGIF_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5347	#define UART0_S2_LBKDIF_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5348	#define UART0_S2_LBKDIF_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5349	/* C3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5350	#define UART0_C3_PEIE_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5351	#define UART0_C3_PEIE_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5352	#define UART0_C3_FEIE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5353	#define UART0_C3_FEIE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5354	#define UART0_C3_NEIE_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5355	#define UART0_C3_NEIE_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5356	#define UART0_C3_ORIE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5357	#define UART0_C3_ORIE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5358	#define UART0_C3_TXINV_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5359	#define UART0_C3_TXINV_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5360	#define UART0_C3_TXDIR_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5361	#define UART0_C3_TXDIR_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5362	#define UART0_C3_R9T8_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5363	#define UART0_C3_R9T8_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5364	#define UART0_C3_R8T9_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5365	#define UART0_C3_R8T9_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5366	/* D Bit Fields */
Piasiv1206	4:ec3f71ef8732	5367	#define UART0_D_R0T0_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5368	#define UART0_D_R0T0_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5369	#define UART0_D_R1T1_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5370	#define UART0_D_R1T1_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5371	#define UART0_D_R2T2_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5372	#define UART0_D_R2T2_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5373	#define UART0_D_R3T3_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5374	#define UART0_D_R3T3_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5375	#define UART0_D_R4T4_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5376	#define UART0_D_R4T4_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5377	#define UART0_D_R5T5_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5378	#define UART0_D_R5T5_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5379	#define UART0_D_R6T6_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5380	#define UART0_D_R6T6_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5381	#define UART0_D_R7T7_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5382	#define UART0_D_R7T7_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5383	/* MA1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5384	#define UART0_MA1_MA_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5385	#define UART0_MA1_MA_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5386	#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
Piasiv1206	4:ec3f71ef8732	5387	/* MA2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5388	#define UART0_MA2_MA_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5389	#define UART0_MA2_MA_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5390	#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
Piasiv1206	4:ec3f71ef8732	5391	/* C4 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5392	#define UART0_C4_OSR_MASK 0x1Fu
Piasiv1206	4:ec3f71ef8732	5393	#define UART0_C4_OSR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5394	#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
Piasiv1206	4:ec3f71ef8732	5395	#define UART0_C4_M10_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5396	#define UART0_C4_M10_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5397	#define UART0_C4_MAEN2_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5398	#define UART0_C4_MAEN2_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5399	#define UART0_C4_MAEN1_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5400	#define UART0_C4_MAEN1_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5401	/* C5 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5402	#define UART0_C5_RESYNCDIS_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5403	#define UART0_C5_RESYNCDIS_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5404	#define UART0_C5_BOTHEDGE_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5405	#define UART0_C5_BOTHEDGE_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5406	#define UART0_C5_RDMAE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5407	#define UART0_C5_RDMAE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5408	#define UART0_C5_TDMAE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5409	#define UART0_C5_TDMAE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5410
Piasiv1206	4:ec3f71ef8732	5411	/*!
Piasiv1206	4:ec3f71ef8732	5412	* @}
Piasiv1206	4:ec3f71ef8732	5413	/ / end of group UART0_Register_Masks */
Piasiv1206	4:ec3f71ef8732	5414
Piasiv1206	4:ec3f71ef8732	5415
Piasiv1206	4:ec3f71ef8732	5416	/* UART0 - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	5417	/** Peripheral UART0 base address */
Piasiv1206	4:ec3f71ef8732	5418	#define UART0_BASE (0x4006A000u)
Piasiv1206	4:ec3f71ef8732	5419	/** Peripheral UART0 base pointer */
Piasiv1206	4:ec3f71ef8732	5420	#define UART0 ((UART0_Type *)UART0_BASE)
Piasiv1206	4:ec3f71ef8732	5421	/** Array initializer of UART0 peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	5422	#define UART0_BASES { UART0 }
Piasiv1206	4:ec3f71ef8732	5423
Piasiv1206	4:ec3f71ef8732	5424	/*!
Piasiv1206	4:ec3f71ef8732	5425	* @}
Piasiv1206	4:ec3f71ef8732	5426	/ / end of group UART0_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	5427
Piasiv1206	4:ec3f71ef8732	5428
Piasiv1206	4:ec3f71ef8732	5429	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	5430	-- USB Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	5431	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	5432
Piasiv1206	4:ec3f71ef8732	5433	/*!
Piasiv1206	4:ec3f71ef8732	5434	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
Piasiv1206	4:ec3f71ef8732	5435	* @{
Piasiv1206	4:ec3f71ef8732	5436	*/
Piasiv1206	4:ec3f71ef8732	5437
Piasiv1206	4:ec3f71ef8732	5438	/** USB - Register Layout Typedef */
Piasiv1206	4:ec3f71ef8732	5439	typedef struct {
Piasiv1206	4:ec3f71ef8732	5440	__I uint8_t PERID; /*< Peripheral ID register, offset: 0x0 /
Piasiv1206	4:ec3f71ef8732	5441	uint8_t RESERVED_0[3];
Piasiv1206	4:ec3f71ef8732	5442	__I uint8_t IDCOMP; /*< Peripheral ID Complement register, offset: 0x4 /
Piasiv1206	4:ec3f71ef8732	5443	uint8_t RESERVED_1[3];
Piasiv1206	4:ec3f71ef8732	5444	__I uint8_t REV; /*< Peripheral Revision register, offset: 0x8 /
Piasiv1206	4:ec3f71ef8732	5445	uint8_t RESERVED_2[3];
Piasiv1206	4:ec3f71ef8732	5446	__I uint8_t ADDINFO; /*< Peripheral Additional Info register, offset: 0xC /
Piasiv1206	4:ec3f71ef8732	5447	uint8_t RESERVED_3[3];
Piasiv1206	4:ec3f71ef8732	5448	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status register, offset: 0x10 /
Piasiv1206	4:ec3f71ef8732	5449	uint8_t RESERVED_4[3];
Piasiv1206	4:ec3f71ef8732	5450	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
Piasiv1206	4:ec3f71ef8732	5451	uint8_t RESERVED_5[3];
Piasiv1206	4:ec3f71ef8732	5452	__IO uint8_t OTGSTAT; /*< OTG Status register, offset: 0x18 /
Piasiv1206	4:ec3f71ef8732	5453	uint8_t RESERVED_6[3];
Piasiv1206	4:ec3f71ef8732	5454	__IO uint8_t OTGCTL; /*< OTG Control register, offset: 0x1C /
Piasiv1206	4:ec3f71ef8732	5455	uint8_t RESERVED_7[99];
Piasiv1206	4:ec3f71ef8732	5456	__IO uint8_t ISTAT; /*< Interrupt Status register, offset: 0x80 /
Piasiv1206	4:ec3f71ef8732	5457	uint8_t RESERVED_8[3];
Piasiv1206	4:ec3f71ef8732	5458	__IO uint8_t INTEN; /*< Interrupt Enable register, offset: 0x84 /
Piasiv1206	4:ec3f71ef8732	5459	uint8_t RESERVED_9[3];
Piasiv1206	4:ec3f71ef8732	5460	__IO uint8_t ERRSTAT; /*< Error Interrupt Status register, offset: 0x88 /
Piasiv1206	4:ec3f71ef8732	5461	uint8_t RESERVED_10[3];
Piasiv1206	4:ec3f71ef8732	5462	__IO uint8_t ERREN; /*< Error Interrupt Enable register, offset: 0x8C /
Piasiv1206	4:ec3f71ef8732	5463	uint8_t RESERVED_11[3];
Piasiv1206	4:ec3f71ef8732	5464	__I uint8_t STAT; /*< Status register, offset: 0x90 /
Piasiv1206	4:ec3f71ef8732	5465	uint8_t RESERVED_12[3];
Piasiv1206	4:ec3f71ef8732	5466	__IO uint8_t CTL; /*< Control register, offset: 0x94 /
Piasiv1206	4:ec3f71ef8732	5467	uint8_t RESERVED_13[3];
Piasiv1206	4:ec3f71ef8732	5468	__IO uint8_t ADDR; /*< Address register, offset: 0x98 /
Piasiv1206	4:ec3f71ef8732	5469	uint8_t RESERVED_14[3];
Piasiv1206	4:ec3f71ef8732	5470	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
Piasiv1206	4:ec3f71ef8732	5471	uint8_t RESERVED_15[3];
Piasiv1206	4:ec3f71ef8732	5472	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
Piasiv1206	4:ec3f71ef8732	5473	uint8_t RESERVED_16[3];
Piasiv1206	4:ec3f71ef8732	5474	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
Piasiv1206	4:ec3f71ef8732	5475	uint8_t RESERVED_17[3];
Piasiv1206	4:ec3f71ef8732	5476	__IO uint8_t TOKEN; /*< Token register, offset: 0xA8 /
Piasiv1206	4:ec3f71ef8732	5477	uint8_t RESERVED_18[3];
Piasiv1206	4:ec3f71ef8732	5478	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
Piasiv1206	4:ec3f71ef8732	5479	uint8_t RESERVED_19[3];
Piasiv1206	4:ec3f71ef8732	5480	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
Piasiv1206	4:ec3f71ef8732	5481	uint8_t RESERVED_20[3];
Piasiv1206	4:ec3f71ef8732	5482	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
Piasiv1206	4:ec3f71ef8732	5483	uint8_t RESERVED_21[11];
Piasiv1206	4:ec3f71ef8732	5484	struct { /* offset: 0xC0, array step: 0x4 */
Piasiv1206	4:ec3f71ef8732	5485	__IO uint8_t ENDPT; /*< Endpoint Control register, array offset: 0xC0, array step: 0x4 /
Piasiv1206	4:ec3f71ef8732	5486	uint8_t RESERVED_0[3];
Piasiv1206	4:ec3f71ef8732	5487	} ENDPOINT[16];
Piasiv1206	4:ec3f71ef8732	5488	__IO uint8_t USBCTRL; /*< USB Control register, offset: 0x100 /
Piasiv1206	4:ec3f71ef8732	5489	uint8_t RESERVED_22[3];
Piasiv1206	4:ec3f71ef8732	5490	__I uint8_t OBSERVE; /*< USB OTG Observe register, offset: 0x104 /
Piasiv1206	4:ec3f71ef8732	5491	uint8_t RESERVED_23[3];
Piasiv1206	4:ec3f71ef8732	5492	__IO uint8_t CONTROL; /*< USB OTG Control register, offset: 0x108 /
Piasiv1206	4:ec3f71ef8732	5493	uint8_t RESERVED_24[3];
Piasiv1206	4:ec3f71ef8732	5494	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
Piasiv1206	4:ec3f71ef8732	5495	uint8_t RESERVED_25[7];
Piasiv1206	4:ec3f71ef8732	5496	__IO uint8_t USBFRMADJUST; /*< Frame Adjust Register, offset: 0x114 /
Piasiv1206	4:ec3f71ef8732	5497	} USB_Type;
Piasiv1206	4:ec3f71ef8732	5498
Piasiv1206	4:ec3f71ef8732	5499	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	5500	-- USB Register Masks
Piasiv1206	4:ec3f71ef8732	5501	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	5502
Piasiv1206	4:ec3f71ef8732	5503	/*!
Piasiv1206	4:ec3f71ef8732	5504	* @addtogroup USB_Register_Masks USB Register Masks
Piasiv1206	4:ec3f71ef8732	5505	* @{
Piasiv1206	4:ec3f71ef8732	5506	*/
Piasiv1206	4:ec3f71ef8732	5507
Piasiv1206	4:ec3f71ef8732	5508	/* PERID Bit Fields */
Piasiv1206	4:ec3f71ef8732	5509	#define USB_PERID_ID_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	5510	#define USB_PERID_ID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5511	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
Piasiv1206	4:ec3f71ef8732	5512	/* IDCOMP Bit Fields */
Piasiv1206	4:ec3f71ef8732	5513	#define USB_IDCOMP_NID_MASK 0x3Fu
Piasiv1206	4:ec3f71ef8732	5514	#define USB_IDCOMP_NID_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5515	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
Piasiv1206	4:ec3f71ef8732	5516	/* REV Bit Fields */
Piasiv1206	4:ec3f71ef8732	5517	#define USB_REV_REV_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5518	#define USB_REV_REV_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5519	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
Piasiv1206	4:ec3f71ef8732	5520	/* ADDINFO Bit Fields */
Piasiv1206	4:ec3f71ef8732	5521	#define USB_ADDINFO_IEHOST_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5522	#define USB_ADDINFO_IEHOST_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5523	#define USB_ADDINFO_IRQNUM_MASK 0xF8u
Piasiv1206	4:ec3f71ef8732	5524	#define USB_ADDINFO_IRQNUM_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5525	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
Piasiv1206	4:ec3f71ef8732	5526	/* OTGISTAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	5527	#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5528	#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5529	#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5530	#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5531	#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5532	#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5533	#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5534	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5535	#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5536	#define USB_OTGISTAT_ONEMSEC_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5537	#define USB_OTGISTAT_IDCHG_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5538	#define USB_OTGISTAT_IDCHG_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5539	/* OTGICR Bit Fields */
Piasiv1206	4:ec3f71ef8732	5540	#define USB_OTGICR_AVBUSEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5541	#define USB_OTGICR_AVBUSEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5542	#define USB_OTGICR_BSESSEN_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5543	#define USB_OTGICR_BSESSEN_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5544	#define USB_OTGICR_SESSVLDEN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5545	#define USB_OTGICR_SESSVLDEN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5546	#define USB_OTGICR_LINESTATEEN_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5547	#define USB_OTGICR_LINESTATEEN_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5548	#define USB_OTGICR_ONEMSECEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5549	#define USB_OTGICR_ONEMSECEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5550	#define USB_OTGICR_IDEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5551	#define USB_OTGICR_IDEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5552	/* OTGSTAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	5553	#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5554	#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5555	#define USB_OTGSTAT_BSESSEND_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5556	#define USB_OTGSTAT_BSESSEND_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5557	#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5558	#define USB_OTGSTAT_SESS_VLD_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5559	#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5560	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5561	#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5562	#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5563	#define USB_OTGSTAT_ID_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5564	#define USB_OTGSTAT_ID_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5565	/* OTGCTL Bit Fields */
Piasiv1206	4:ec3f71ef8732	5566	#define USB_OTGCTL_OTGEN_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5567	#define USB_OTGCTL_OTGEN_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5568	#define USB_OTGCTL_DMLOW_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5569	#define USB_OTGCTL_DMLOW_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5570	#define USB_OTGCTL_DPLOW_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5571	#define USB_OTGCTL_DPLOW_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5572	#define USB_OTGCTL_DPHIGH_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5573	#define USB_OTGCTL_DPHIGH_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5574	/* ISTAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	5575	#define USB_ISTAT_USBRST_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5576	#define USB_ISTAT_USBRST_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5577	#define USB_ISTAT_ERROR_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5578	#define USB_ISTAT_ERROR_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5579	#define USB_ISTAT_SOFTOK_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5580	#define USB_ISTAT_SOFTOK_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5581	#define USB_ISTAT_TOKDNE_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5582	#define USB_ISTAT_TOKDNE_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5583	#define USB_ISTAT_SLEEP_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5584	#define USB_ISTAT_SLEEP_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5585	#define USB_ISTAT_RESUME_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5586	#define USB_ISTAT_RESUME_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5587	#define USB_ISTAT_ATTACH_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5588	#define USB_ISTAT_ATTACH_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5589	#define USB_ISTAT_STALL_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5590	#define USB_ISTAT_STALL_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5591	/* INTEN Bit Fields */
Piasiv1206	4:ec3f71ef8732	5592	#define USB_INTEN_USBRSTEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5593	#define USB_INTEN_USBRSTEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5594	#define USB_INTEN_ERROREN_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5595	#define USB_INTEN_ERROREN_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5596	#define USB_INTEN_SOFTOKEN_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5597	#define USB_INTEN_SOFTOKEN_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5598	#define USB_INTEN_TOKDNEEN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5599	#define USB_INTEN_TOKDNEEN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5600	#define USB_INTEN_SLEEPEN_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5601	#define USB_INTEN_SLEEPEN_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5602	#define USB_INTEN_RESUMEEN_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5603	#define USB_INTEN_RESUMEEN_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5604	#define USB_INTEN_ATTACHEN_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5605	#define USB_INTEN_ATTACHEN_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5606	#define USB_INTEN_STALLEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5607	#define USB_INTEN_STALLEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5608	/* ERRSTAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	5609	#define USB_ERRSTAT_PIDERR_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5610	#define USB_ERRSTAT_PIDERR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5611	#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5612	#define USB_ERRSTAT_CRC5EOF_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5613	#define USB_ERRSTAT_CRC16_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5614	#define USB_ERRSTAT_CRC16_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5615	#define USB_ERRSTAT_DFN8_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5616	#define USB_ERRSTAT_DFN8_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5617	#define USB_ERRSTAT_BTOERR_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5618	#define USB_ERRSTAT_BTOERR_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5619	#define USB_ERRSTAT_DMAERR_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5620	#define USB_ERRSTAT_DMAERR_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5621	#define USB_ERRSTAT_BTSERR_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5622	#define USB_ERRSTAT_BTSERR_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5623	/* ERREN Bit Fields */
Piasiv1206	4:ec3f71ef8732	5624	#define USB_ERREN_PIDERREN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5625	#define USB_ERREN_PIDERREN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5626	#define USB_ERREN_CRC5EOFEN_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5627	#define USB_ERREN_CRC5EOFEN_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5628	#define USB_ERREN_CRC16EN_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5629	#define USB_ERREN_CRC16EN_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5630	#define USB_ERREN_DFN8EN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5631	#define USB_ERREN_DFN8EN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5632	#define USB_ERREN_BTOERREN_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5633	#define USB_ERREN_BTOERREN_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5634	#define USB_ERREN_DMAERREN_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5635	#define USB_ERREN_DMAERREN_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5636	#define USB_ERREN_BTSERREN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5637	#define USB_ERREN_BTSERREN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5638	/* STAT Bit Fields */
Piasiv1206	4:ec3f71ef8732	5639	#define USB_STAT_ODD_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5640	#define USB_STAT_ODD_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5641	#define USB_STAT_TX_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5642	#define USB_STAT_TX_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5643	#define USB_STAT_ENDP_MASK 0xF0u
Piasiv1206	4:ec3f71ef8732	5644	#define USB_STAT_ENDP_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5645	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
Piasiv1206	4:ec3f71ef8732	5646	/* CTL Bit Fields */
Piasiv1206	4:ec3f71ef8732	5647	#define USB_CTL_USBENSOFEN_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5648	#define USB_CTL_USBENSOFEN_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5649	#define USB_CTL_ODDRST_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5650	#define USB_CTL_ODDRST_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5651	#define USB_CTL_RESUME_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5652	#define USB_CTL_RESUME_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5653	#define USB_CTL_HOSTMODEEN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5654	#define USB_CTL_HOSTMODEEN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5655	#define USB_CTL_RESET_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5656	#define USB_CTL_RESET_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5657	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5658	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5659	#define USB_CTL_SE0_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5660	#define USB_CTL_SE0_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5661	#define USB_CTL_JSTATE_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5662	#define USB_CTL_JSTATE_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5663	/* ADDR Bit Fields */
Piasiv1206	4:ec3f71ef8732	5664	#define USB_ADDR_ADDR_MASK 0x7Fu
Piasiv1206	4:ec3f71ef8732	5665	#define USB_ADDR_ADDR_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5666	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
Piasiv1206	4:ec3f71ef8732	5667	#define USB_ADDR_LSEN_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5668	#define USB_ADDR_LSEN_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5669	/* BDTPAGE1 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5670	#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
Piasiv1206	4:ec3f71ef8732	5671	#define USB_BDTPAGE1_BDTBA_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5672	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
Piasiv1206	4:ec3f71ef8732	5673	/* FRMNUML Bit Fields */
Piasiv1206	4:ec3f71ef8732	5674	#define USB_FRMNUML_FRM_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5675	#define USB_FRMNUML_FRM_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5676	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
Piasiv1206	4:ec3f71ef8732	5677	/* FRMNUMH Bit Fields */
Piasiv1206	4:ec3f71ef8732	5678	#define USB_FRMNUMH_FRM_MASK 0x7u
Piasiv1206	4:ec3f71ef8732	5679	#define USB_FRMNUMH_FRM_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5680	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
Piasiv1206	4:ec3f71ef8732	5681	/* TOKEN Bit Fields */
Piasiv1206	4:ec3f71ef8732	5682	#define USB_TOKEN_TOKENENDPT_MASK 0xFu
Piasiv1206	4:ec3f71ef8732	5683	#define USB_TOKEN_TOKENENDPT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5684	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
Piasiv1206	4:ec3f71ef8732	5685	#define USB_TOKEN_TOKENPID_MASK 0xF0u
Piasiv1206	4:ec3f71ef8732	5686	#define USB_TOKEN_TOKENPID_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5687	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
Piasiv1206	4:ec3f71ef8732	5688	/* SOFTHLD Bit Fields */
Piasiv1206	4:ec3f71ef8732	5689	#define USB_SOFTHLD_CNT_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5690	#define USB_SOFTHLD_CNT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5691	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
Piasiv1206	4:ec3f71ef8732	5692	/* BDTPAGE2 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5693	#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5694	#define USB_BDTPAGE2_BDTBA_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5695	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
Piasiv1206	4:ec3f71ef8732	5696	/* BDTPAGE3 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5697	#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5698	#define USB_BDTPAGE3_BDTBA_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5699	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
Piasiv1206	4:ec3f71ef8732	5700	/* ENDPT Bit Fields */
Piasiv1206	4:ec3f71ef8732	5701	#define USB_ENDPT_EPHSHK_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5702	#define USB_ENDPT_EPHSHK_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5703	#define USB_ENDPT_EPSTALL_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5704	#define USB_ENDPT_EPSTALL_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5705	#define USB_ENDPT_EPTXEN_MASK 0x4u
Piasiv1206	4:ec3f71ef8732	5706	#define USB_ENDPT_EPTXEN_SHIFT 2
Piasiv1206	4:ec3f71ef8732	5707	#define USB_ENDPT_EPRXEN_MASK 0x8u
Piasiv1206	4:ec3f71ef8732	5708	#define USB_ENDPT_EPRXEN_SHIFT 3
Piasiv1206	4:ec3f71ef8732	5709	#define USB_ENDPT_EPCTLDIS_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5710	#define USB_ENDPT_EPCTLDIS_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5711	#define USB_ENDPT_RETRYDIS_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5712	#define USB_ENDPT_RETRYDIS_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5713	#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5714	#define USB_ENDPT_HOSTWOHUB_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5715	/* USBCTRL Bit Fields */
Piasiv1206	4:ec3f71ef8732	5716	#define USB_USBCTRL_PDE_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5717	#define USB_USBCTRL_PDE_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5718	#define USB_USBCTRL_SUSP_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5719	#define USB_USBCTRL_SUSP_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5720	/* OBSERVE Bit Fields */
Piasiv1206	4:ec3f71ef8732	5721	#define USB_OBSERVE_DMPD_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5722	#define USB_OBSERVE_DMPD_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5723	#define USB_OBSERVE_DPPD_MASK 0x40u
Piasiv1206	4:ec3f71ef8732	5724	#define USB_OBSERVE_DPPD_SHIFT 6
Piasiv1206	4:ec3f71ef8732	5725	#define USB_OBSERVE_DPPU_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5726	#define USB_OBSERVE_DPPU_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5727	/* CONTROL Bit Fields */
Piasiv1206	4:ec3f71ef8732	5728	#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
Piasiv1206	4:ec3f71ef8732	5729	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
Piasiv1206	4:ec3f71ef8732	5730	/* USBTRC0 Bit Fields */
Piasiv1206	4:ec3f71ef8732	5731	#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
Piasiv1206	4:ec3f71ef8732	5732	#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5733	#define USB_USBTRC0_SYNC_DET_MASK 0x2u
Piasiv1206	4:ec3f71ef8732	5734	#define USB_USBTRC0_SYNC_DET_SHIFT 1
Piasiv1206	4:ec3f71ef8732	5735	#define USB_USBTRC0_USBRESMEN_MASK 0x20u
Piasiv1206	4:ec3f71ef8732	5736	#define USB_USBTRC0_USBRESMEN_SHIFT 5
Piasiv1206	4:ec3f71ef8732	5737	#define USB_USBTRC0_USBRESET_MASK 0x80u
Piasiv1206	4:ec3f71ef8732	5738	#define USB_USBTRC0_USBRESET_SHIFT 7
Piasiv1206	4:ec3f71ef8732	5739	/* USBFRMADJUST Bit Fields */
Piasiv1206	4:ec3f71ef8732	5740	#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
Piasiv1206	4:ec3f71ef8732	5741	#define USB_USBFRMADJUST_ADJ_SHIFT 0
Piasiv1206	4:ec3f71ef8732	5742	#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
Piasiv1206	4:ec3f71ef8732	5743
Piasiv1206	4:ec3f71ef8732	5744	/*!
Piasiv1206	4:ec3f71ef8732	5745	* @}
Piasiv1206	4:ec3f71ef8732	5746	/ / end of group USB_Register_Masks */
Piasiv1206	4:ec3f71ef8732	5747
Piasiv1206	4:ec3f71ef8732	5748
Piasiv1206	4:ec3f71ef8732	5749	/* USB - Peripheral instance base addresses */
Piasiv1206	4:ec3f71ef8732	5750	/** Peripheral USB0 base address */
Piasiv1206	4:ec3f71ef8732	5751	#define USB0_BASE (0x40072000u)
Piasiv1206	4:ec3f71ef8732	5752	/** Peripheral USB0 base pointer */
Piasiv1206	4:ec3f71ef8732	5753	#define USB0 ((USB_Type *)USB0_BASE)
Piasiv1206	4:ec3f71ef8732	5754	/** Array initializer of USB peripheral base pointers */
Piasiv1206	4:ec3f71ef8732	5755	#define USB_BASES { USB0 }
Piasiv1206	4:ec3f71ef8732	5756
Piasiv1206	4:ec3f71ef8732	5757	/*!
Piasiv1206	4:ec3f71ef8732	5758	* @}
Piasiv1206	4:ec3f71ef8732	5759	/ / end of group USB_Peripheral_Access_Layer */
Piasiv1206	4:ec3f71ef8732	5760
Piasiv1206	4:ec3f71ef8732	5761
Piasiv1206	4:ec3f71ef8732	5762	/*
Piasiv1206	4:ec3f71ef8732	5763	** End of section using anonymous unions
Piasiv1206	4:ec3f71ef8732	5764	*/
Piasiv1206	4:ec3f71ef8732	5765
Piasiv1206	4:ec3f71ef8732	5766	#if defined(__ARMCC_VERSION)
Piasiv1206	4:ec3f71ef8732	5767	#pragma pop
Piasiv1206	4:ec3f71ef8732	5768	#elif defined(__CWCC__)
Piasiv1206	4:ec3f71ef8732	5769	#pragma pop
Piasiv1206	4:ec3f71ef8732	5770	#elif defined(__GNUC__)
Piasiv1206	4:ec3f71ef8732	5771	/* leave anonymous unions enabled */
Piasiv1206	4:ec3f71ef8732	5772	#elif defined(__IAR_SYSTEMS_ICC__)
Piasiv1206	4:ec3f71ef8732	5773	#pragma language=default
Piasiv1206	4:ec3f71ef8732	5774	#else
Piasiv1206	4:ec3f71ef8732	5775	#error Not supported compiler type
Piasiv1206	4:ec3f71ef8732	5776	#endif
Piasiv1206	4:ec3f71ef8732	5777
Piasiv1206	4:ec3f71ef8732	5778	/*!
Piasiv1206	4:ec3f71ef8732	5779	* @}
Piasiv1206	4:ec3f71ef8732	5780	/ / end of group Peripheral_access_layer */
Piasiv1206	4:ec3f71ef8732	5781
Piasiv1206	4:ec3f71ef8732	5782
Piasiv1206	4:ec3f71ef8732	5783	/* ----------------------------------------------------------------------------
Piasiv1206	4:ec3f71ef8732	5784	-- Backward Compatibility
Piasiv1206	4:ec3f71ef8732	5785	---------------------------------------------------------------------------- */
Piasiv1206	4:ec3f71ef8732	5786
Piasiv1206	4:ec3f71ef8732	5787	/*!
Piasiv1206	4:ec3f71ef8732	5788	* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
Piasiv1206	4:ec3f71ef8732	5789	* @{
Piasiv1206	4:ec3f71ef8732	5790	*/
Piasiv1206	4:ec3f71ef8732	5791
Piasiv1206	4:ec3f71ef8732	5792	/* No backward compatibility issues. */
Piasiv1206	4:ec3f71ef8732	5793
Piasiv1206	4:ec3f71ef8732	5794	/*!
Piasiv1206	4:ec3f71ef8732	5795	* @}
Piasiv1206	4:ec3f71ef8732	5796	/ / end of group Backward_Compatibility_Symbols */
Piasiv1206	4:ec3f71ef8732	5797
Piasiv1206	4:ec3f71ef8732	5798
Piasiv1206	4:ec3f71ef8732	5799	#endif /* #if !defined(MKL46Z4_H_) */
Piasiv1206	4:ec3f71ef8732	5800
Piasiv1206	4:ec3f71ef8732	5801	/* MKL46Z4.h, eof. */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	27 Feb 2016
Imports:	1
Forks:	0
Commits:	7
Dependents:	0
Dependencies:	1
Followers:	1

MKL46Z4.h@6:090151fca074, 2016-02-27 (annotated)

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