Remi Beges / FRDM-TFC-HBRIDGE

Fork of the official library for the FRDM-TFC shield to add measurement of H-bridge sense currents

Dependents:   telemetry_demo_FRDM-TFC

Fork of FRDM-TFC by Eli Hughes

TFC.cpp@10:86c5fc9a53d9, 2016-02-17 (annotated)

Committer:
Overdrivr
Date:
Wed Feb 17 20:42:32 2016 +0000
Revision:
10:86c5fc9a53d9
Parent:
9:1c4fc3e224b5
Child:
11:787a9a24dbfb
Working on the ADC code to read current sense from HBridge. Not functionnal yet, adc outputs 0 on HBridge B, and battery measurement seems cut off as well

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emh203 1:6f37253dab87 1 #include "mbed.h"
emh203 1:6f37253dab87 2 #include "TFC.h"
emh203 1:6f37253dab87 3
emh203 1:6f37253dab87 4 #define FTM1_CLK_PRESCALE 6// Prescale Selector value - see comments in Status Control (SC) section for more details
emh203 1:6f37253dab87 5 #define SERVO_DEFAULT_PERIOD (float)(.020) // Desired Frequency of PWM Signal - Here 50Hz => 20ms period
emh203 1:6f37253dab87 6 // use these to dial in servo steering to your particular servo
emh203 8:24430a0d7fd8 7 #define SERVO_MIN_PULSE_WIDTH_DEFAULT (float)(.00095) // The number here should be be *pulse width* in seconds to move servo to its left limit
emh203 8:24430a0d7fd8 8 #define SERVO_MAX_PULSE_WIDTH_DEFAULT (float)(.00160) // The number here should be be *pulse width* in seconds to move servo to its left limit
emh203 1:6f37253dab87 9
emh203 1:6f37253dab87 10
emh203 1:6f37253dab87 11 #define FTM0_CLOCK (SystemCoreClock/2)
emh203 1:6f37253dab87 12 #define FTM0_CLK_PRESCALE (0) // Prescale Selector value - see comments in Status Control (SC) section for more details
emh203 1:6f37253dab87 13 #define FTM0_DEFAULT_SWITCHING_FREQUENCY (4000.0)
emh203 1:6f37253dab87 14
emh203 1:6f37253dab87 15 #define ADC_MAX_CODE (4095)
emh203 1:6f37253dab87 16
emh203 1:6f37253dab87 17 #define TAOS_CLK_HIGH PTE->PSOR = (1<<1)
emh203 1:6f37253dab87 18 #define TAOS_CLK_LOW PTE->PCOR = (1<<1)
emh203 1:6f37253dab87 19 #define TAOS_SI_HIGH PTD->PSOR = (1<<7)
emh203 1:6f37253dab87 20 #define TAOS_SI_LOW PTD->PCOR = (1<<7)
emh203 1:6f37253dab87 21
emh203 1:6f37253dab87 22 #define ADC_STATE_INIT 0
emh203 1:6f37253dab87 23 #define ADC_STATE_CAPTURE_POT_0 1
emh203 1:6f37253dab87 24 #define ADC_STATE_CAPTURE_POT_1 2
emh203 1:6f37253dab87 25 #define ADC_STATE_CAPTURE_BATTERY_LEVEL 3
emh203 1:6f37253dab87 26 #define ADC_STATE_CAPTURE_LINE_SCAN 4
Overdrivr 10:86c5fc9a53d9 27 #define ADC_STATE_CAPTURE_I_HBRIDGE_A 5
Overdrivr 10:86c5fc9a53d9 28 #define ADC_STATE_CAPTURE_I_HBRIDGE_B 6
emh203 1:6f37253dab87 29
emh203 1:6f37253dab87 30 #define TFC_POT_0_ADC_CHANNEL 13
emh203 1:6f37253dab87 31 #define TFC_POT_1_ADC_CHANNEL 12
emh203 1:6f37253dab87 32 #define TFC_BAT_SENSE_CHANNEL 4
Overdrivr 10:86c5fc9a53d9 33 #define TFC_LINESCAN0_ADC_CHANNEL 6 // Mux B
Overdrivr 10:86c5fc9a53d9 34 #define TFC_LINESCAN1_ADC_CHANNEL 7 // Mux B
Overdrivr 10:86c5fc9a53d9 35 // RAJOUTER UN CHANNEL ICI
Overdrivr 10:86c5fc9a53d9 36 #define TFC_I_HBRIDGE_0_SENSE_ADC_CHANNEL 7 // Mux A
Overdrivr 10:86c5fc9a53d9 37 #define TFC_I_HBRIDGE_1_SENSE_ADC_CHANNEL 3 // Mux A
emh203 1:6f37253dab87 38
emh203 1:6f37253dab87 39
emh203 1:6f37253dab87 40 #define ADC0_irq_no 57
emh203 1:6f37253dab87 41 #define ADC1_irq_no 58
emh203 1:6f37253dab87 42
emh203 1:6f37253dab87 43 #define ADC0_CHANA 19 // set to desired ADC0 channel trigger A
emh203 1:6f37253dab87 44 #define ADC0_CHANB 20 // set to desired ADC0 channel trigger B
emh203 1:6f37253dab87 45
emh203 1:6f37253dab87 46 #define ADC1_CHANA 20 // set to desired ADC1 channel trigger A 20 defaults to potentiometer in TWRK60
emh203 1:6f37253dab87 47 #define ADC1_CHANB 20 // set to desired ADC1 channel trigger B
emh203 1:6f37253dab87 48
emh203 1:6f37253dab87 49 #define ADC0_DLYA 0x2000 // ADC0 trigger A delay
emh203 1:6f37253dab87 50 #define ADC0_DLYB 0x4000 // ADC0 trigger B delay
emh203 1:6f37253dab87 51 #define ADC1_DLYA 0x6000 // ADC1 trigger A delay
emh203 1:6f37253dab87 52 #define ADC1_DLYB 0x7fff // ADC1 trigger B delay
emh203 1:6f37253dab87 53
emh203 1:6f37253dab87 54
emh203 1:6f37253dab87 55 #define ADC0A_DONE 0x01
emh203 1:6f37253dab87 56 #define ADC0B_DONE 0x02
emh203 1:6f37253dab87 57 #define ADC1A_DONE 0x04
emh203 1:6f37253dab87 58 #define ADC1B_DONE 0x08
emh203 1:6f37253dab87 59
emh203 1:6f37253dab87 60
emh203 1:6f37253dab87 61 // Bit shifting of bitfiled is already taken into account so
emh203 1:6f37253dab87 62 // bitfiled values are always represented as relative to their position.
emh203 1:6f37253dab87 63
emh203 1:6f37253dab87 64 /************************* #Defines ******************************************/
emh203 1:6f37253dab87 65
emh203 1:6f37253dab87 66 #define A 0x0
emh203 1:6f37253dab87 67 #define B 0x1
emh203 1:6f37253dab87 68
emh203 1:6f37253dab87 69 /////// NOTE: the following defines relate to the ADC register definitions
emh203 1:6f37253dab87 70 /////// and the content follows the reference manual, using the same symbols.
emh203 1:6f37253dab87 71
emh203 1:6f37253dab87 72
emh203 1:6f37253dab87 73 //// ADCSC1 (register)
emh203 1:6f37253dab87 74
emh203 1:6f37253dab87 75 // Conversion Complete (COCO) mask
emh203 1:6f37253dab87 76 #define COCO_COMPLETE ADC_SC1_COCO_MASK
emh203 1:6f37253dab87 77 #define COCO_NOT 0x00
emh203 1:6f37253dab87 78
emh203 1:6f37253dab87 79 // ADC interrupts: enabled, or disabled.
emh203 1:6f37253dab87 80 #define AIEN_ON ADC_SC1_AIEN_MASK
emh203 1:6f37253dab87 81 #define AIEN_OFF 0x00
emh203 1:6f37253dab87 82
emh203 1:6f37253dab87 83 // Differential or Single ended ADC input
emh203 1:6f37253dab87 84 #define DIFF_SINGLE 0x00
emh203 1:6f37253dab87 85 #define DIFF_DIFFERENTIAL ADC_SC1_DIFF_MASK
emh203 1:6f37253dab87 86
emh203 1:6f37253dab87 87 //// ADCCFG1
emh203 1:6f37253dab87 88
emh203 1:6f37253dab87 89 // Power setting of ADC
emh203 1:6f37253dab87 90 #define ADLPC_LOW ADC_CFG1_ADLPC_MASK
emh203 1:6f37253dab87 91 #define ADLPC_NORMAL 0x00
emh203 1:6f37253dab87 92
emh203 1:6f37253dab87 93 // Clock divisor
emh203 1:6f37253dab87 94 #define ADIV_1 0x00
emh203 1:6f37253dab87 95 #define ADIV_2 0x01
emh203 1:6f37253dab87 96 #define ADIV_4 0x02
emh203 1:6f37253dab87 97 #define ADIV_8 0x03
emh203 1:6f37253dab87 98
emh203 1:6f37253dab87 99 // Long samle time, or Short sample time
emh203 1:6f37253dab87 100 #define ADLSMP_LONG ADC_CFG1_ADLSMP_MASK
emh203 1:6f37253dab87 101 #define ADLSMP_SHORT 0x00
emh203 1:6f37253dab87 102
emh203 1:6f37253dab87 103 // How many bits for the conversion? 8, 12, 10, or 16 (single ended).
emh203 1:6f37253dab87 104 #define MODE_8 0x00
emh203 1:6f37253dab87 105 #define MODE_12 0x01
emh203 1:6f37253dab87 106 #define MODE_10 0x02
emh203 1:6f37253dab87 107 #define MODE_16 0x03
emh203 1:6f37253dab87 108
emh203 1:6f37253dab87 109
emh203 1:6f37253dab87 110
emh203 1:6f37253dab87 111 // ADC Input Clock Source choice? Bus clock, Bus clock/2, "altclk", or the
emh203 1:6f37253dab87 112 // ADC's own asynchronous clock for less noise
emh203 1:6f37253dab87 113 #define ADICLK_BUS 0x00
emh203 1:6f37253dab87 114 #define ADICLK_BUS_2 0x01
emh203 1:6f37253dab87 115 #define ADICLK_ALTCLK 0x02
emh203 1:6f37253dab87 116 #define ADICLK_ADACK 0x03
emh203 1:6f37253dab87 117
emh203 1:6f37253dab87 118 //// ADCCFG2
emh203 1:6f37253dab87 119
emh203 1:6f37253dab87 120 // Select between B or A channels
emh203 1:6f37253dab87 121 #define MUXSEL_ADCB ADC_CFG2_MUXSEL_MASK
emh203 1:6f37253dab87 122 #define MUXSEL_ADCA 0x00
emh203 1:6f37253dab87 123
emh203 1:6f37253dab87 124 // Ansync clock output enable: enable, or disable the output of it
emh203 1:6f37253dab87 125 #define ADACKEN_ENABLED ADC_CFG2_ADACKEN_MASK
emh203 1:6f37253dab87 126 #define ADACKEN_DISABLED 0x00
emh203 1:6f37253dab87 127
emh203 1:6f37253dab87 128 // High speed or low speed conversion mode
emh203 1:6f37253dab87 129 #define ADHSC_HISPEED ADC_CFG2_ADHSC_MASK
emh203 1:6f37253dab87 130 #define ADHSC_NORMAL 0x00
emh203 1:6f37253dab87 131
emh203 1:6f37253dab87 132 // Long Sample Time selector: 20, 12, 6, or 2 extra clocks for a longer sample time
emh203 1:6f37253dab87 133 #define ADLSTS_20 0x00
emh203 1:6f37253dab87 134 #define ADLSTS_12 0x01
emh203 1:6f37253dab87 135 #define ADLSTS_6 0x02
emh203 1:6f37253dab87 136 #define ADLSTS_2 0x03
emh203 1:6f37253dab87 137
emh203 1:6f37253dab87 138 ////ADCSC2
emh203 1:6f37253dab87 139
emh203 1:6f37253dab87 140 // Read-only status bit indicating conversion status
emh203 1:6f37253dab87 141 #define ADACT_ACTIVE ADC_SC2_ADACT_MASK
emh203 1:6f37253dab87 142 #define ADACT_INACTIVE 0x00
emh203 1:6f37253dab87 143
emh203 1:6f37253dab87 144 // Trigger for starting conversion: Hardware trigger, or software trigger.
emh203 1:6f37253dab87 145 // For using PDB, the Hardware trigger option is selected.
emh203 1:6f37253dab87 146 #define ADTRG_HW ADC_SC2_ADTRG_MASK
emh203 1:6f37253dab87 147 #define ADTRG_SW 0x00
emh203 1:6f37253dab87 148
emh203 1:6f37253dab87 149 // ADC Compare Function Enable: Disabled, or Enabled.
emh203 1:6f37253dab87 150 #define ACFE_DISABLED 0x00
emh203 1:6f37253dab87 151 #define ACFE_ENABLED ADC_SC2_ACFE_MASK
emh203 1:6f37253dab87 152
emh203 1:6f37253dab87 153 // Compare Function Greater Than Enable: Greater, or Less.
emh203 1:6f37253dab87 154 #define ACFGT_GREATER ADC_SC2_ACFGT_MASK
emh203 1:6f37253dab87 155 #define ACFGT_LESS 0x00
emh203 1:6f37253dab87 156
emh203 1:6f37253dab87 157 // Compare Function Range Enable: Enabled or Disabled.
emh203 1:6f37253dab87 158 #define ACREN_ENABLED ADC_SC2_ACREN_MASK
emh203 1:6f37253dab87 159 #define ACREN_DISABLED 0x00
emh203 1:6f37253dab87 160
emh203 1:6f37253dab87 161 // DMA enable: enabled or disabled.
emh203 1:6f37253dab87 162 #define DMAEN_ENABLED ADC_SC2_DMAEN_MASK
emh203 1:6f37253dab87 163 #define DMAEN_DISABLED 0x00
emh203 1:6f37253dab87 164
emh203 1:6f37253dab87 165 // Voltage Reference selection for the ADC conversions
emh203 1:6f37253dab87 166 // (***not*** the PGA which uses VREFO only).
emh203 1:6f37253dab87 167 // VREFH and VREFL (0) , or VREFO (1).
emh203 1:6f37253dab87 168
emh203 1:6f37253dab87 169 #define REFSEL_EXT 0x00
emh203 1:6f37253dab87 170 #define REFSEL_ALT 0x01
emh203 1:6f37253dab87 171 #define REFSEL_RES 0x02 /* reserved */
emh203 1:6f37253dab87 172 #define REFSEL_RES_EXT 0x03 /* reserved but defaults to Vref */
emh203 1:6f37253dab87 173
emh203 1:6f37253dab87 174 ////ADCSC3
emh203 1:6f37253dab87 175
emh203 1:6f37253dab87 176 // Calibration begin or off
emh203 1:6f37253dab87 177 #define CAL_BEGIN ADC_SC3_CAL_MASK
emh203 1:6f37253dab87 178 #define CAL_OFF 0x00
emh203 1:6f37253dab87 179
emh203 1:6f37253dab87 180 // Status indicating Calibration failed, or normal success
emh203 1:6f37253dab87 181 #define CALF_FAIL ADC_SC3_CALF_MASK
emh203 1:6f37253dab87 182 #define CALF_NORMAL 0x00
emh203 1:6f37253dab87 183
emh203 1:6f37253dab87 184 // ADC to continously convert, or do a sinle conversion
emh203 1:6f37253dab87 185 #define ADCO_CONTINUOUS ADC_SC3_ADCO_MASK
emh203 1:6f37253dab87 186 #define ADCO_SINGLE 0x00
emh203 1:6f37253dab87 187
emh203 1:6f37253dab87 188 // Averaging enabled in the ADC, or not.
emh203 1:6f37253dab87 189 #define AVGE_ENABLED ADC_SC3_AVGE_MASK
emh203 1:6f37253dab87 190 #define AVGE_DISABLED 0x00
emh203 1:6f37253dab87 191
emh203 1:6f37253dab87 192 // How many to average prior to "interrupting" the MCU? 4, 8, 16, or 32
emh203 1:6f37253dab87 193 #define AVGS_4 0x00
emh203 1:6f37253dab87 194 #define AVGS_8 0x01
emh203 1:6f37253dab87 195 #define AVGS_16 0x02
emh203 1:6f37253dab87 196 #define AVGS_32 0x03
emh203 1:6f37253dab87 197
emh203 1:6f37253dab87 198 ////PGA
emh203 1:6f37253dab87 199
emh203 1:6f37253dab87 200 // PGA enabled or not?
emh203 1:6f37253dab87 201 #define PGAEN_ENABLED ADC_PGA_PGAEN_MASK
emh203 1:6f37253dab87 202 #define PGAEN_DISABLED 0x00
emh203 1:6f37253dab87 203
emh203 1:6f37253dab87 204 // Chopper stabilization of the amplifier, or not.
emh203 1:6f37253dab87 205 #define PGACHP_CHOP ADC_PGA_PGACHP_MASK
emh203 1:6f37253dab87 206 #define PGACHP_NOCHOP 0x00
emh203 1:6f37253dab87 207
emh203 1:6f37253dab87 208 // PGA in low power mode, or normal mode.
emh203 1:6f37253dab87 209 #define PGALP_LOW ADC_PGA_PGALP_MASK
emh203 1:6f37253dab87 210 #define PGALP_NORMAL 0x00
emh203 1:6f37253dab87 211
emh203 1:6f37253dab87 212 // Gain of PGA. Selectable from 1 to 64.
emh203 1:6f37253dab87 213 #define PGAG_1 0x00
emh203 1:6f37253dab87 214 #define PGAG_2 0x01
emh203 1:6f37253dab87 215 #define PGAG_4 0x02
emh203 1:6f37253dab87 216 #define PGAG_8 0x03
emh203 1:6f37253dab87 217 #define PGAG_16 0x04
emh203 1:6f37253dab87 218 #define PGAG_32 0x05
emh203 1:6f37253dab87 219 #define PGAG_64 0x06
emh203 1:6f37253dab87 220
emh203 1:6f37253dab87 221
emh203 1:6f37253dab87 222 #define ADC_STATE_INIT 0
emh203 1:6f37253dab87 223 #define ADC_STATE_CAPTURE_POT_0 1
emh203 1:6f37253dab87 224 #define ADC_STATE_CAPTURE_POT_1 2
emh203 1:6f37253dab87 225 #define ADC_STATE_CAPTURE_BATTERY_LEVEL 3
emh203 1:6f37253dab87 226 #define ADC_STATE_CAPTURE_LINE_SCAN 4
emh203 1:6f37253dab87 227
emh203 1:6f37253dab87 228
emh203 1:6f37253dab87 229 /////////// The above values fit into the structure below to select ADC/PGA
emh203 1:6f37253dab87 230 /////////// configuration desired:
emh203 1:6f37253dab87 231
emh203 1:6f37253dab87 232 typedef struct adc_cfg {
emh203 1:6f37253dab87 233 uint8_t CONFIG1;
emh203 1:6f37253dab87 234 uint8_t CONFIG2;
emh203 1:6f37253dab87 235 uint16_t COMPARE1;
emh203 1:6f37253dab87 236 uint16_t COMPARE2;
emh203 1:6f37253dab87 237 uint8_t STATUS2;
emh203 1:6f37253dab87 238 uint8_t STATUS3;
emh203 1:6f37253dab87 239 uint8_t STATUS1A;
emh203 1:6f37253dab87 240 uint8_t STATUS1B;
emh203 1:6f37253dab87 241 uint32_t PGA;
emh203 1:6f37253dab87 242 } *tADC_ConfigPtr, tADC_Config ;
emh203 1:6f37253dab87 243
emh203 1:6f37253dab87 244
emh203 1:6f37253dab87 245 #define CAL_BLK_NUMREC 18
emh203 1:6f37253dab87 246
emh203 1:6f37253dab87 247 typedef struct adc_cal {
emh203 1:6f37253dab87 248
emh203 1:6f37253dab87 249 uint16_t OFS;
emh203 1:6f37253dab87 250 uint16_t PG;
emh203 1:6f37253dab87 251 uint16_t MG;
emh203 1:6f37253dab87 252 uint8_t CLPD;
emh203 1:6f37253dab87 253 uint8_t CLPS;
emh203 1:6f37253dab87 254 uint16_t CLP4;
emh203 1:6f37253dab87 255 uint16_t CLP3;
emh203 1:6f37253dab87 256 uint8_t CLP2;
emh203 1:6f37253dab87 257 uint8_t CLP1;
emh203 1:6f37253dab87 258 uint8_t CLP0;
emh203 1:6f37253dab87 259 uint8_t dummy;
emh203 1:6f37253dab87 260 uint8_t CLMD;
emh203 1:6f37253dab87 261 uint8_t CLMS;
emh203 1:6f37253dab87 262 uint16_t CLM4;
emh203 1:6f37253dab87 263 uint16_t CLM3;
emh203 1:6f37253dab87 264 uint8_t CLM2;
emh203 1:6f37253dab87 265 uint8_t CLM1;
emh203 1:6f37253dab87 266 uint8_t CLM0;
emh203 1:6f37253dab87 267 } tADC_Cal_Blk ;
emh203 1:6f37253dab87 268
emh203 1:6f37253dab87 269 typedef struct ADC_MemMap {
emh203 1:6f37253dab87 270 uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
emh203 1:6f37253dab87 271 uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
emh203 1:6f37253dab87 272 uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
emh203 1:6f37253dab87 273 uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
emh203 1:6f37253dab87 274 uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
emh203 1:6f37253dab87 275 uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
emh203 1:6f37253dab87 276 uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
emh203 1:6f37253dab87 277 uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
emh203 1:6f37253dab87 278 uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
emh203 1:6f37253dab87 279 uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
emh203 1:6f37253dab87 280 uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
emh203 1:6f37253dab87 281 uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
emh203 1:6f37253dab87 282 uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
emh203 1:6f37253dab87 283 uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
emh203 1:6f37253dab87 284 uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
emh203 1:6f37253dab87 285 uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
emh203 1:6f37253dab87 286 uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
emh203 1:6f37253dab87 287 uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
emh203 1:6f37253dab87 288 uint8_t RESERVED_0[4];
emh203 1:6f37253dab87 289 uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
emh203 1:6f37253dab87 290 uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
emh203 1:6f37253dab87 291 uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
emh203 1:6f37253dab87 292 uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
emh203 1:6f37253dab87 293 uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
emh203 1:6f37253dab87 294 uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
emh203 1:6f37253dab87 295 uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
emh203 1:6f37253dab87 296 } volatile *ADC_MemMapPtr;
emh203 1:6f37253dab87 297
emh203 1:6f37253dab87 298
emh203 1:6f37253dab87 299
emh203 1:6f37253dab87 300 /* ADC - Register accessors */
emh203 1:6f37253dab87 301 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
emh203 1:6f37253dab87 302 #define ADC_CFG1_REG(base) ((base)->CFG1)
emh203 1:6f37253dab87 303 #define ADC_CFG2_REG(base) ((base)->CFG2)
emh203 1:6f37253dab87 304 #define ADC_R_REG(base,index) ((base)->R[index])
emh203 1:6f37253dab87 305 #define ADC_CV1_REG(base) ((base)->CV1)
emh203 1:6f37253dab87 306 #define ADC_CV2_REG(base) ((base)->CV2)
emh203 1:6f37253dab87 307 #define ADC_SC2_REG(base) ((base)->SC2)
emh203 1:6f37253dab87 308 #define ADC_SC3_REG(base) ((base)->SC3)
emh203 1:6f37253dab87 309 #define ADC_OFS_REG(base) ((base)->OFS)
emh203 1:6f37253dab87 310 #define ADC_PG_REG(base) ((base)->PG)
emh203 1:6f37253dab87 311 #define ADC_MG_REG(base) ((base)->MG)
emh203 1:6f37253dab87 312 #define ADC_CLPD_REG(base) ((base)->CLPD)
emh203 1:6f37253dab87 313 #define ADC_CLPS_REG(base) ((base)->CLPS)
emh203 1:6f37253dab87 314 #define ADC_CLP4_REG(base) ((base)->CLP4)
emh203 1:6f37253dab87 315 #define ADC_CLP3_REG(base) ((base)->CLP3)
emh203 1:6f37253dab87 316 #define ADC_CLP2_REG(base) ((base)->CLP2)
emh203 1:6f37253dab87 317 #define ADC_CLP1_REG(base) ((base)->CLP1)
emh203 1:6f37253dab87 318 #define ADC_CLP0_REG(base) ((base)->CLP0)
emh203 1:6f37253dab87 319 #define ADC_CLMD_REG(base) ((base)->CLMD)
emh203 1:6f37253dab87 320 #define ADC_CLMS_REG(base) ((base)->CLMS)
emh203 1:6f37253dab87 321 #define ADC_CLM4_REG(base) ((base)->CLM4)
emh203 1:6f37253dab87 322 #define ADC_CLM3_REG(base) ((base)->CLM3)
emh203 1:6f37253dab87 323 #define ADC_CLM2_REG(base) ((base)->CLM2)
emh203 1:6f37253dab87 324 #define ADC_CLM1_REG(base) ((base)->CLM1)
emh203 1:6f37253dab87 325 #define ADC_CLM0_REG(base) ((base)->CLM0)
emh203 1:6f37253dab87 326
emh203 1:6f37253dab87 327 #define ADC0_BASE_PTR ((ADC_MemMapPtr)0x4003B000u)
emh203 1:6f37253dab87 328 /** Array initializer of ADC peripheral base pointers */
emh203 1:6f37253dab87 329 #define ADC_BASE_PTRS { ADC0_BASE_PTR }
emh203 1:6f37253dab87 330
emh203 1:6f37253dab87 331
emh203 1:6f37253dab87 332 float _ServoDutyCycleMin;
emh203 1:6f37253dab87 333 float _ServoDutyCycleMax;
emh203 1:6f37253dab87 334 float _ServoPeriod;
emh203 1:6f37253dab87 335
emh203 1:6f37253dab87 336 volatile uint16_t QueuedServo0Val;
emh203 1:6f37253dab87 337 volatile uint16_t QueuedServo1Val;
emh203 1:6f37253dab87 338
emh203 1:6f37253dab87 339 volatile uint16_t *LineScanImage0WorkingBuffer;
emh203 1:6f37253dab87 340 volatile uint16_t *LineScanImage1WorkingBuffer;
emh203 1:6f37253dab87 341
emh203 1:6f37253dab87 342 volatile uint16_t LineScanImage0Buffer[2][128];
emh203 1:6f37253dab87 343 volatile uint16_t LineScanImage1Buffer[2][128];
emh203 1:6f37253dab87 344 volatile uint8_t LineScanWorkingBuffer;
emh203 1:6f37253dab87 345
emh203 3:23cce037011f 346 volatile uint16_t * TFC_LineScanImage0;
emh203 3:23cce037011f 347 volatile uint16_t * TFC_LineScanImage1;
emh203 3:23cce037011f 348 volatile uint8_t TFC_LineScanImageReady;
emh203 3:23cce037011f 349
emh203 1:6f37253dab87 350 volatile uint16_t PotADC_Value[2];
emh203 1:6f37253dab87 351 volatile uint16_t BatSenseADC_Value;
emh203 1:6f37253dab87 352 volatile uint16_t CurrentADC_State;
emh203 1:6f37253dab87 353 volatile uint8_t CurrentLineScanPixel;
emh203 1:6f37253dab87 354 volatile uint8_t CurrentLineScanChannel;
emh203 1:6f37253dab87 355 volatile uint32_t TFC_ServoTicker;
emh203 3:23cce037011f 356
Overdrivr 10:86c5fc9a53d9 357 volatile uint16_t HBridge_0_current_value;
Overdrivr 10:86c5fc9a53d9 358 volatile uint16_t HBridge_1_current_value;
Overdrivr 10:86c5fc9a53d9 359
emh203 1:6f37253dab87 360
emh203 1:6f37253dab87 361 void TFC_SetServoDutyCycle(uint8_t ServoNumber, float DutyCycle);
emh203 1:6f37253dab87 362 void TFC_InitLineScanCamera();
emh203 1:6f37253dab87 363 uint8_t ADC_Cal(ADC_MemMapPtr adcmap);
emh203 1:6f37253dab87 364 void ADC_Config_Alt(ADC_MemMapPtr adcmap, tADC_ConfigPtr ADC_CfgPtr);
emh203 1:6f37253dab87 365 void ADC_Read_Cal(ADC_MemMapPtr adcmap, tADC_Cal_Blk *blk);
emh203 1:6f37253dab87 366 void TFC_InitADC0();
emh203 1:6f37253dab87 367 void TFC_InitADC_System();
emh203 1:6f37253dab87 368 void TFC_GPIO_Init();
emh203 1:6f37253dab87 369 void ADC0_Handler();
emh203 1:6f37253dab87 370 void TPM1_Handler();
emh203 1:6f37253dab87 371
emh203 1:6f37253dab87 372
emh203 1:6f37253dab87 373 void TFC_Init()
emh203 1:6f37253dab87 374 {
emh203 1:6f37253dab87 375
emh203 1:6f37253dab87 376 TFC_GPIO_Init();
emh203 1:6f37253dab87 377
emh203 1:6f37253dab87 378 TFC_InitADC_System(); // Always call this before the Servo init function.... The IRQ for the Servo code modifies ADC registers and the clocks need enable to the ADC peripherals 1st!
emh203 1:6f37253dab87 379
emh203 1:6f37253dab87 380 TFC_InitLineScanCamera();
emh203 1:6f37253dab87 381
emh203 1:6f37253dab87 382 TFC_InitServos(SERVO_MIN_PULSE_WIDTH_DEFAULT , SERVO_MAX_PULSE_WIDTH_DEFAULT, SERVO_DEFAULT_PERIOD);
emh203 1:6f37253dab87 383
emh203 1:6f37253dab87 384 TFC_ServoTicker = 0;
emh203 1:6f37253dab87 385
emh203 1:6f37253dab87 386 TFC_InitMotorPWM(FTM0_DEFAULT_SWITCHING_FREQUENCY);
emh203 1:6f37253dab87 387
emh203 1:6f37253dab87 388 }
emh203 1:6f37253dab87 389
emh203 1:6f37253dab87 390
emh203 1:6f37253dab87 391 void TFC_GPIO_Init()
emh203 1:6f37253dab87 392 {
emh203 1:6f37253dab87 393
emh203 1:6f37253dab87 394 //enable Clocks to all ports
emh203 1:6f37253dab87 395
emh203 1:6f37253dab87 396 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
emh203 1:6f37253dab87 397
emh203 1:6f37253dab87 398 //Setup Pins as GPIO
emh203 1:6f37253dab87 399 PORTE->PCR[21] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
emh203 1:6f37253dab87 400 PORTE->PCR[20] = PORT_PCR_MUX(1);
emh203 1:6f37253dab87 401
emh203 1:6f37253dab87 402 //Port for Pushbuttons
emh203 1:6f37253dab87 403 PORTC->PCR[13] = PORT_PCR_MUX(1);
emh203 1:6f37253dab87 404 PORTC->PCR[17] = PORT_PCR_MUX(1);
emh203 1:6f37253dab87 405
emh203 1:6f37253dab87 406
emh203 1:6f37253dab87 407 //Ports for DIP Switches
emh203 1:6f37253dab87 408 PORTE->PCR[2] = PORT_PCR_MUX(1);
emh203 1:6f37253dab87 409 PORTE->PCR[3] = PORT_PCR_MUX(1);
emh203 1:6f37253dab87 410 PORTE->PCR[4] = PORT_PCR_MUX(1);
emh203 1:6f37253dab87 411 PORTE->PCR[5] = PORT_PCR_MUX(1);
emh203 1:6f37253dab87 412
emh203 1:6f37253dab87 413 //Ports for LEDs
emh203 1:6f37253dab87 414 PORTB->PCR[8] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
emh203 1:6f37253dab87 415 PORTB->PCR[9] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
emh203 1:6f37253dab87 416 PORTB->PCR[10] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
emh203 1:6f37253dab87 417 PORTB->PCR[11] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
emh203 1:6f37253dab87 418
emh203 1:6f37253dab87 419
emh203 1:6f37253dab87 420 //Setup the output pins
emh203 1:6f37253dab87 421 PTE->PDDR = TFC_HBRIDGE_EN_LOC;
emh203 1:6f37253dab87 422 PTB->PDDR = TFC_BAT_LED0_LOC | TFC_BAT_LED1_LOC | TFC_BAT_LED2_LOC | TFC_BAT_LED3_LOC;
emh203 1:6f37253dab87 423
emh203 1:6f37253dab87 424 TFC_SetBatteryLED(0);
emh203 1:6f37253dab87 425 TFC_HBRIDGE_DISABLE;
emh203 1:6f37253dab87 426 }
emh203 1:6f37253dab87 427
emh203 1:6f37253dab87 428 void TFC_SetBatteryLED(uint8_t Value)
emh203 1:6f37253dab87 429 {
emh203 1:6f37253dab87 430 if(Value & 0x01)
emh203 1:6f37253dab87 431 TFC_BAT_LED0_ON;
emh203 1:6f37253dab87 432 else
emh203 1:6f37253dab87 433 TFC_BAT_LED0_OFF;
emh203 1:6f37253dab87 434
emh203 1:6f37253dab87 435 if(Value & 0x02)
emh203 1:6f37253dab87 436 TFC_BAT_LED1_ON;
emh203 1:6f37253dab87 437 else
emh203 1:6f37253dab87 438 TFC_BAT_LED1_OFF;
emh203 1:6f37253dab87 439
emh203 1:6f37253dab87 440 if(Value & 0x04)
emh203 1:6f37253dab87 441 TFC_BAT_LED2_ON;
emh203 1:6f37253dab87 442 else
emh203 1:6f37253dab87 443 TFC_BAT_LED2_OFF;
emh203 1:6f37253dab87 444
emh203 1:6f37253dab87 445 if(Value & 0x08)
emh203 1:6f37253dab87 446 TFC_BAT_LED3_ON;
emh203 1:6f37253dab87 447 else
emh203 1:6f37253dab87 448 TFC_BAT_LED3_OFF;
emh203 1:6f37253dab87 449 }
emh203 1:6f37253dab87 450
emh203 1:6f37253dab87 451 uint8_t TFC_GetDIP_Switch()
emh203 1:6f37253dab87 452 {
emh203 1:6f37253dab87 453 uint8_t DIP_Val=0;
emh203 1:6f37253dab87 454
emh203 1:6f37253dab87 455 DIP_Val = (PTE->PDIR>>2) & 0xF;
emh203 1:6f37253dab87 456
emh203 1:6f37253dab87 457 return DIP_Val;
emh203 1:6f37253dab87 458 }
emh203 1:6f37253dab87 459
emh203 1:6f37253dab87 460 uint8_t TFC_ReadPushButton(uint8_t Index)
emh203 1:6f37253dab87 461 {
emh203 1:6f37253dab87 462 if(Index == 0) {
emh203 1:6f37253dab87 463 return TFC_PUSH_BUTTON_0_PRESSED;
emh203 1:6f37253dab87 464 } else {
emh203 1:6f37253dab87 465 return TFC_PUSH_BUTTON_1_PRESSED;
emh203 1:6f37253dab87 466 }
emh203 1:6f37253dab87 467 }
emh203 1:6f37253dab87 468
emh203 1:6f37253dab87 469 extern "C" void TPM1_IRQHandler()
emh203 1:6f37253dab87 470 {
emh203 1:6f37253dab87 471 //Clear the overflow mask if set. According to the reference manual, we clear by writing a logic one!
emh203 1:6f37253dab87 472 if(TPM1->SC & TPM_SC_TOF_MASK)
emh203 1:6f37253dab87 473 TPM1->SC |= TPM_SC_TOF_MASK;
emh203 1:6f37253dab87 474
emh203 1:6f37253dab87 475 //Dump the queued values to the timer channels
emh203 1:6f37253dab87 476 TPM1->CONTROLS[0].CnV = QueuedServo0Val;
emh203 1:6f37253dab87 477 TPM1->CONTROLS[1].CnV = QueuedServo1Val;
emh203 1:6f37253dab87 478
emh203 1:6f37253dab87 479
emh203 1:6f37253dab87 480 //Prime the next ADC capture cycle
emh203 1:6f37253dab87 481 TAOS_SI_HIGH;
emh203 1:6f37253dab87 482 //Prime the ADC pump and start capturing POT 0
emh203 1:6f37253dab87 483 CurrentADC_State = ADC_STATE_CAPTURE_POT_0;
emh203 1:6f37253dab87 484
emh203 1:6f37253dab87 485 ADC0->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; //Select the A side of the mux
emh203 1:6f37253dab87 486 ADC0->SC1[0] = TFC_POT_0_ADC_CHANNEL | ADC_SC1_AIEN_MASK; //Start the State machine at POT0
emh203 1:6f37253dab87 487
emh203 1:6f37253dab87 488 //Flag that a new cervo cycle will start
emh203 1:6f37253dab87 489 if (TFC_ServoTicker < 0xffffffff)//if servo tick less than max value, count up...
emh203 1:6f37253dab87 490 TFC_ServoTicker++;
emh203 1:6f37253dab87 491
emh203 1:6f37253dab87 492 }
emh203 1:6f37253dab87 493
emh203 1:6f37253dab87 494
emh203 1:6f37253dab87 495 void TFC_InitServos(float PulseWidthMin, float PulseWidthMax, float ServoPeriod)
emh203 1:6f37253dab87 496 {
emh203 1:6f37253dab87 497
emh203 1:6f37253dab87 498 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
emh203 1:6f37253dab87 499
emh203 1:6f37253dab87 500 _ServoPeriod = ServoPeriod;
emh203 1:6f37253dab87 501 _ServoDutyCycleMin = PulseWidthMin/ServoPeriod;
emh203 1:6f37253dab87 502 _ServoDutyCycleMax = PulseWidthMax/ServoPeriod;
emh203 1:6f37253dab87 503
emh203 1:6f37253dab87 504 //Clock Setup for the TPM requires a couple steps.
emh203 1:6f37253dab87 505 SIM->SCGC6 &= ~SIM_SCGC6_TPM1_MASK;
emh203 1:6f37253dab87 506 //1st, set the clock mux
emh203 1:6f37253dab87 507 //See Page 124 of f the KL25 Sub-Family Reference Manual, Rev. 3, September 2012
emh203 1:6f37253dab87 508 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;// We Want MCGPLLCLK/2 (See Page 196 of the KL25 Sub-Family Reference Manual, Rev. 3, September 2012)
emh203 1:6f37253dab87 509 SIM->SOPT2 &= ~(SIM_SOPT2_TPMSRC_MASK);
emh203 1:6f37253dab87 510 SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1);
emh203 1:6f37253dab87 511
emh203 1:6f37253dab87 512 //Enable the Clock to the FTM0 Module
emh203 1:6f37253dab87 513 //See Page 207 of f the KL25 Sub-Family Reference Manual, Rev. 3, September 2012
emh203 1:6f37253dab87 514 SIM->SCGC6 |= SIM_SCGC6_TPM1_MASK;
emh203 1:6f37253dab87 515
emh203 1:6f37253dab87 516 //The TPM Module has Clock. Now set up the peripheral
emh203 1:6f37253dab87 517
emh203 1:6f37253dab87 518 //Blow away the control registers to ensure that the counter is not running
emh203 1:6f37253dab87 519 TPM1->SC = 0;
emh203 1:6f37253dab87 520 TPM1->CONF = 0;
emh203 1:6f37253dab87 521
emh203 1:6f37253dab87 522 //While the counter is disabled we can setup the prescaler
emh203 1:6f37253dab87 523
emh203 1:6f37253dab87 524 TPM1->SC = TPM_SC_PS(FTM1_CLK_PRESCALE);
emh203 1:6f37253dab87 525 TPM1->SC |= TPM_SC_TOIE_MASK; //Enable Interrupts for the Timer Overflow
emh203 1:6f37253dab87 526
emh203 1:6f37253dab87 527 //Setup the mod register to get the correct PWM Period
emh203 1:6f37253dab87 528
emh203 1:6f37253dab87 529 TPM1->MOD = (SystemCoreClock/(1<<(FTM1_CLK_PRESCALE))) * _ServoPeriod;
emh203 1:6f37253dab87 530 //Setup Channels 0 and 1
emh203 1:6f37253dab87 531
emh203 1:6f37253dab87 532 TPM1->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
emh203 1:6f37253dab87 533 TPM1->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
emh203 1:6f37253dab87 534
emh203 1:6f37253dab87 535
emh203 1:6f37253dab87 536 //Set the Default duty cycle to servo neutral
emh203 1:6f37253dab87 537 TFC_SetServo(0, 0.0);
emh203 1:6f37253dab87 538 TFC_SetServo(1, 0.0);
emh203 1:6f37253dab87 539
emh203 1:6f37253dab87 540 //Enable the TPM COunter
emh203 1:6f37253dab87 541 TPM1->SC |= TPM_SC_CMOD(1);
emh203 1:6f37253dab87 542
emh203 1:6f37253dab87 543 //Enable TPM1 IRQ on the NVIC
emh203 1:6f37253dab87 544
emh203 1:6f37253dab87 545 //NVIC_SetVector(TPM1_IRQn,(uint32_t)TPM1_Handler);
emh203 1:6f37253dab87 546 NVIC_EnableIRQ(TPM1_IRQn);
emh203 1:6f37253dab87 547
emh203 1:6f37253dab87 548 //Enable the FTM functions on the the port
emh203 1:6f37253dab87 549
emh203 1:6f37253dab87 550 PORTB->PCR[0] = PORT_PCR_MUX(3);
emh203 1:6f37253dab87 551 PORTB->PCR[1] = PORT_PCR_MUX(3);
emh203 1:6f37253dab87 552
emh203 1:6f37253dab87 553 }
emh203 1:6f37253dab87 554
emh203 1:6f37253dab87 555
emh203 1:6f37253dab87 556 void TFC_SetServoDutyCycle(uint8_t ServoNumber, float DutyCycle)
emh203 1:6f37253dab87 557 {
emh203 1:6f37253dab87 558 switch(ServoNumber) {
emh203 1:6f37253dab87 559 default:
emh203 1:6f37253dab87 560 case 0:
emh203 1:6f37253dab87 561
emh203 1:6f37253dab87 562 QueuedServo0Val = TPM1->MOD * DutyCycle;
emh203 1:6f37253dab87 563
emh203 1:6f37253dab87 564 break;
emh203 1:6f37253dab87 565
emh203 1:6f37253dab87 566 case 1:
emh203 1:6f37253dab87 567
emh203 1:6f37253dab87 568 QueuedServo1Val = TPM1->MOD * DutyCycle;
emh203 1:6f37253dab87 569
emh203 1:6f37253dab87 570 break;
emh203 1:6f37253dab87 571 }
emh203 1:6f37253dab87 572 }
emh203 1:6f37253dab87 573
emh203 1:6f37253dab87 574 void TFC_SetServo(uint8_t ServoNumber, float Position)
emh203 1:6f37253dab87 575 {
emh203 1:6f37253dab87 576 TFC_SetServoDutyCycle(ServoNumber ,
emh203 3:23cce037011f 577 ((Position + 1.0)/2) * ((_ServoDutyCycleMax - _ServoDutyCycleMin))+_ServoDutyCycleMin) ;
emh203 1:6f37253dab87 578
emh203 1:6f37253dab87 579 }
emh203 1:6f37253dab87 580
emh203 1:6f37253dab87 581 //********************************************************************************************************
emh203 1:6f37253dab87 582 //********************************************************************************************************
emh203 1:6f37253dab87 583 //********************************************************************************************************
emh203 1:6f37253dab87 584 // _____ _____ ______ _ _ _ _ _____ _______ _____ ____ _ _ _____
emh203 1:6f37253dab87 585 // /\ | __ \ / ____| | ____| | | | \ | |/ ____|__ __|_ _/ __ \| \ | |/ ____|
emh203 1:6f37253dab87 586 // / \ | | | | | | |__ | | | | \| | | | | | || | | | \| | (___
emh203 1:6f37253dab87 587 // / /\ \ | | | | | | __| | | | | . ` | | | | | || | | | . ` |\___ \
emh203 1:6f37253dab87 588 // / ____ \| |__| | |____ | | | |__| | |\ | |____ | | _| || |__| | |\ |____) |
emh203 1:6f37253dab87 589 // /_/ \_\_____/ \_____| |_| \____/|_| \_|\_____| |_| |_____\____/|_| \_|_____/
emh203 1:6f37253dab87 590 // ********************************************************************************************************
emh203 1:6f37253dab87 591 // ********************************************************************************************************
emh203 1:6f37253dab87 592 // ********************************************************************************************************
emh203 1:6f37253dab87 593
emh203 1:6f37253dab87 594
emh203 1:6f37253dab87 595
emh203 1:6f37253dab87 596
emh203 1:6f37253dab87 597
emh203 1:6f37253dab87 598 uint8_t ADC_Cal(ADC_MemMapPtr adcmap)
emh203 1:6f37253dab87 599 {
emh203 1:6f37253dab87 600
emh203 1:6f37253dab87 601 uint16_t cal_var;
emh203 1:6f37253dab87 602
emh203 1:6f37253dab87 603 ADC_SC2_REG(adcmap) &= ~ADC_SC2_ADTRG_MASK ; // Enable Software Conversion Trigger for Calibration Process - ADC0_SC2 = ADC0_SC2 | ADC_SC2_ADTRGW(0);
emh203 1:6f37253dab87 604 ADC_SC3_REG(adcmap) &= ( ~ADC_SC3_ADCO_MASK & ~ADC_SC3_AVGS_MASK ); // set single conversion, clear avgs bitfield for next writing
emh203 1:6f37253dab87 605 ADC_SC3_REG(adcmap) |= ( ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(AVGS_32) ); // Turn averaging ON and set at max value ( 32 )
emh203 1:6f37253dab87 606
emh203 1:6f37253dab87 607
emh203 1:6f37253dab87 608 ADC_SC3_REG(adcmap) |= ADC_SC3_CAL_MASK ; // Start CAL
emh203 1:6f37253dab87 609 while ( (ADC_SC1_REG(adcmap,A) & ADC_SC1_COCO_MASK ) == COCO_NOT ); // Wait calibration end
emh203 1:6f37253dab87 610
emh203 1:6f37253dab87 611 if ((ADC_SC3_REG(adcmap)& ADC_SC3_CALF_MASK) == CALF_FAIL ) {
emh203 1:6f37253dab87 612 return(1); // Check for Calibration fail error and return
emh203 1:6f37253dab87 613 }
emh203 1:6f37253dab87 614 // Calculate plus-side calibration
emh203 1:6f37253dab87 615 cal_var = 0x00;
emh203 1:6f37253dab87 616
emh203 1:6f37253dab87 617 cal_var = ADC_CLP0_REG(adcmap);
emh203 1:6f37253dab87 618 cal_var += ADC_CLP1_REG(adcmap);
emh203 1:6f37253dab87 619 cal_var += ADC_CLP2_REG(adcmap);
emh203 1:6f37253dab87 620 cal_var += ADC_CLP3_REG(adcmap);
emh203 1:6f37253dab87 621 cal_var += ADC_CLP4_REG(adcmap);
emh203 1:6f37253dab87 622 cal_var += ADC_CLPS_REG(adcmap);
emh203 1:6f37253dab87 623
emh203 1:6f37253dab87 624 cal_var = cal_var/2;
emh203 1:6f37253dab87 625 cal_var |= 0x8000; // Set MSB
emh203 1:6f37253dab87 626
emh203 1:6f37253dab87 627 ADC_PG_REG(adcmap) = ADC_PG_PG(cal_var);
emh203 1:6f37253dab87 628
emh203 1:6f37253dab87 629
emh203 1:6f37253dab87 630 // Calculate minus-side calibration
emh203 1:6f37253dab87 631 cal_var = 0x00;
emh203 1:6f37253dab87 632
emh203 1:6f37253dab87 633 cal_var = ADC_CLM0_REG(adcmap);
emh203 1:6f37253dab87 634 cal_var += ADC_CLM1_REG(adcmap);
emh203 1:6f37253dab87 635 cal_var += ADC_CLM2_REG(adcmap);
emh203 1:6f37253dab87 636 cal_var += ADC_CLM3_REG(adcmap);
emh203 1:6f37253dab87 637 cal_var += ADC_CLM4_REG(adcmap);
emh203 1:6f37253dab87 638 cal_var += ADC_CLMS_REG(adcmap);
emh203 1:6f37253dab87 639
emh203 1:6f37253dab87 640 cal_var = cal_var/2;
emh203 1:6f37253dab87 641
emh203 1:6f37253dab87 642 cal_var |= 0x8000; // Set MSB
emh203 1:6f37253dab87 643
emh203 1:6f37253dab87 644 ADC_MG_REG(adcmap) = ADC_MG_MG(cal_var);
emh203 1:6f37253dab87 645
emh203 1:6f37253dab87 646 ADC_SC3_REG(adcmap) &= ~ADC_SC3_CAL_MASK ; /* Clear CAL bit */
emh203 1:6f37253dab87 647
emh203 1:6f37253dab87 648 return(0);
emh203 1:6f37253dab87 649 }
emh203 1:6f37253dab87 650
emh203 1:6f37253dab87 651
emh203 1:6f37253dab87 652 void ADC_Config_Alt(ADC_MemMapPtr adcmap, tADC_ConfigPtr ADC_CfgPtr)
emh203 1:6f37253dab87 653 {
emh203 1:6f37253dab87 654 ADC_CFG1_REG(adcmap) = ADC_CfgPtr->CONFIG1;
emh203 1:6f37253dab87 655 ADC_CFG2_REG(adcmap) = ADC_CfgPtr->CONFIG2;
emh203 1:6f37253dab87 656 ADC_CV1_REG(adcmap) = ADC_CfgPtr->COMPARE1;
emh203 1:6f37253dab87 657 ADC_CV2_REG(adcmap) = ADC_CfgPtr->COMPARE2;
emh203 1:6f37253dab87 658 ADC_SC2_REG(adcmap) = ADC_CfgPtr->STATUS2;
emh203 1:6f37253dab87 659 ADC_SC3_REG(adcmap) = ADC_CfgPtr->STATUS3;
emh203 1:6f37253dab87 660 //ADC_PGA_REG(adcmap) = ADC_CfgPtr->PGA;
emh203 1:6f37253dab87 661 ADC_SC1_REG(adcmap,A)= ADC_CfgPtr->STATUS1A;
emh203 1:6f37253dab87 662 ADC_SC1_REG(adcmap,B)= ADC_CfgPtr->STATUS1B;
emh203 1:6f37253dab87 663 }
emh203 1:6f37253dab87 664
emh203 1:6f37253dab87 665
emh203 1:6f37253dab87 666 void ADC_Read_Cal(ADC_MemMapPtr adcmap, tADC_Cal_Blk *blk)
emh203 1:6f37253dab87 667 {
emh203 1:6f37253dab87 668 blk->OFS = ADC_OFS_REG(adcmap);
emh203 1:6f37253dab87 669 blk->PG = ADC_PG_REG(adcmap);
emh203 1:6f37253dab87 670 blk->MG = ADC_MG_REG(adcmap);
emh203 1:6f37253dab87 671 blk->CLPD = ADC_CLPD_REG(adcmap);
emh203 1:6f37253dab87 672 blk->CLPS = ADC_CLPS_REG(adcmap);
emh203 1:6f37253dab87 673 blk->CLP4 = ADC_CLP4_REG(adcmap);
emh203 1:6f37253dab87 674 blk->CLP3 = ADC_CLP3_REG(adcmap);
emh203 1:6f37253dab87 675 blk->CLP2 = ADC_CLP2_REG(adcmap);
emh203 1:6f37253dab87 676 blk->CLP1 = ADC_CLP1_REG(adcmap);
emh203 1:6f37253dab87 677 blk->CLP0 = ADC_CLP0_REG(adcmap);
emh203 1:6f37253dab87 678 blk->CLMD = ADC_CLMD_REG(adcmap);
emh203 1:6f37253dab87 679 blk->CLMS = ADC_CLMS_REG(adcmap);
emh203 1:6f37253dab87 680 blk->CLM4 = ADC_CLM4_REG(adcmap);
emh203 1:6f37253dab87 681 blk->CLM3 = ADC_CLM3_REG(adcmap);
emh203 1:6f37253dab87 682 blk->CLM2 = ADC_CLM2_REG(adcmap);
emh203 1:6f37253dab87 683 blk->CLM1 = ADC_CLM1_REG(adcmap);
emh203 1:6f37253dab87 684 blk->CLM0 = ADC_CLM0_REG(adcmap);
emh203 1:6f37253dab87 685
emh203 1:6f37253dab87 686 }
emh203 1:6f37253dab87 687
emh203 1:6f37253dab87 688
emh203 1:6f37253dab87 689 void TFC_InitADC0()
emh203 1:6f37253dab87 690 {
emh203 1:6f37253dab87 691 tADC_Config Master_Adc0_Config;
emh203 1:6f37253dab87 692
emh203 1:6f37253dab87 693
emh203 1:6f37253dab87 694 SIM->SCGC6 |= (SIM_SCGC6_ADC0_MASK);
emh203 1:6f37253dab87 695
emh203 1:6f37253dab87 696 //Lets calibrate the ADC. 1st setup how the channel will be used.
emh203 1:6f37253dab87 697
emh203 1:6f37253dab87 698
emh203 1:6f37253dab87 699 Master_Adc0_Config.CONFIG1 = ADLPC_NORMAL //No low power mode
emh203 1:6f37253dab87 700 | ADC_CFG1_ADIV(ADIV_4) //divide input by 4
emh203 1:6f37253dab87 701 | ADLSMP_LONG //long sample time
emh203 1:6f37253dab87 702 | ADC_CFG1_MODE(MODE_12)//single ended 8-bit conversion
emh203 1:6f37253dab87 703 | ADC_CFG1_ADICLK(ADICLK_BUS);
emh203 1:6f37253dab87 704
emh203 1:6f37253dab87 705 Master_Adc0_Config.CONFIG2 = MUXSEL_ADCA // select the A side of the ADC channel.
emh203 1:6f37253dab87 706 | ADACKEN_DISABLED
emh203 1:6f37253dab87 707 | ADHSC_HISPEED
emh203 1:6f37253dab87 708 | ADC_CFG2_ADLSTS(ADLSTS_2);//Extra long sample Time (20 extra clocks)
emh203 1:6f37253dab87 709
emh203 1:6f37253dab87 710
emh203 1:6f37253dab87 711 Master_Adc0_Config.COMPARE1 = 00000; // Comparators don't matter for calibration
emh203 1:6f37253dab87 712 Master_Adc0_Config.COMPARE1 = 0xFFFF;
emh203 1:6f37253dab87 713
emh203 1:6f37253dab87 714 Master_Adc0_Config.STATUS2 = ADTRG_HW //hardware triggers for calibration
emh203 1:6f37253dab87 715 | ACFE_DISABLED //disable comparator
emh203 1:6f37253dab87 716 | ACFGT_GREATER
emh203 1:6f37253dab87 717 | ACREN_ENABLED
emh203 1:6f37253dab87 718 | DMAEN_DISABLED //Disable DMA
emh203 1:6f37253dab87 719 | ADC_SC2_REFSEL(REFSEL_EXT); //External Reference
emh203 1:6f37253dab87 720
emh203 1:6f37253dab87 721 Master_Adc0_Config.STATUS3 = CAL_OFF
emh203 1:6f37253dab87 722 | ADCO_SINGLE
emh203 1:6f37253dab87 723 | AVGE_ENABLED;
emh203 1:6f37253dab87 724 // | ADC_SC3_AVGS(AVGS_4);
emh203 1:6f37253dab87 725
emh203 1:6f37253dab87 726 Master_Adc0_Config.PGA = 0; // Disable the PGA
emh203 1:6f37253dab87 727
emh203 1:6f37253dab87 728
emh203 1:6f37253dab87 729 // Configure ADC as it will be used, but because ADC_SC1_ADCH is 31,
emh203 1:6f37253dab87 730 // the ADC will be inactive. Channel 31 is just disable function.
emh203 1:6f37253dab87 731 // There really is no channel 31.
emh203 1:6f37253dab87 732
emh203 1:6f37253dab87 733 Master_Adc0_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31);
emh203 1:6f37253dab87 734
emh203 1:6f37253dab87 735
emh203 1:6f37253dab87 736 ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc0_Config); // config ADC
emh203 1:6f37253dab87 737
emh203 1:6f37253dab87 738 // Calibrate the ADC in the configuration in which it will be used:
emh203 1:6f37253dab87 739 ADC_Cal(ADC0_BASE_PTR); // do the calibration
emh203 1:6f37253dab87 740
emh203 1:6f37253dab87 741
emh203 1:6f37253dab87 742 Master_Adc0_Config.STATUS2 = ACFE_DISABLED //disable comparator
emh203 1:6f37253dab87 743 | ACFGT_GREATER
emh203 1:6f37253dab87 744 | ACREN_ENABLED
emh203 1:6f37253dab87 745 | DMAEN_DISABLED //Disable DMA
emh203 1:6f37253dab87 746 | ADC_SC2_REFSEL(REFSEL_EXT); //External Reference
emh203 1:6f37253dab87 747
emh203 1:6f37253dab87 748 Master_Adc0_Config.STATUS3 = CAL_OFF
emh203 1:6f37253dab87 749 | ADCO_SINGLE;
emh203 1:6f37253dab87 750
emh203 1:6f37253dab87 751
emh203 1:6f37253dab87 752
emh203 1:6f37253dab87 753 ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc0_Config);
emh203 1:6f37253dab87 754 }
emh203 1:6f37253dab87 755
emh203 1:6f37253dab87 756
emh203 1:6f37253dab87 757 void TFC_InitADC_System()
emh203 1:6f37253dab87 758 {
emh203 1:6f37253dab87 759
emh203 1:6f37253dab87 760 TFC_InitADC0();
emh203 1:6f37253dab87 761
emh203 1:6f37253dab87 762
emh203 1:6f37253dab87 763 //All Adc processing of the Pots and linescan will be done in the ADC0 IRQ!
emh203 1:6f37253dab87 764 //A state machine will scan through the channels.
emh203 1:6f37253dab87 765 //This is done to automate the linescan capture on Channel 0 to ensure that timing is very even
emh203 1:6f37253dab87 766 CurrentADC_State = ADC_STATE_INIT;
emh203 1:6f37253dab87 767
emh203 1:6f37253dab87 768 //The pump will be primed with the TPM1 interrupt. upon timeout/interrupt it will set the SI signal high
emh203 1:6f37253dab87 769 //for the camera and then start the conversions for the pots.
emh203 1:6f37253dab87 770
emh203 1:6f37253dab87 771 // NVIC_SetVector(ADC0_IRQn,(uint32_t)ADC0_Handler);
emh203 1:6f37253dab87 772 NVIC_EnableIRQ(ADC0_IRQn);
emh203 1:6f37253dab87 773
emh203 1:6f37253dab87 774 }
emh203 1:6f37253dab87 775
emh203 1:6f37253dab87 776 extern "C" void ADC0_IRQHandler()
emh203 1:6f37253dab87 777 {
emh203 1:6f37253dab87 778 uint8_t Junk;
emh203 1:6f37253dab87 779
emh203 1:6f37253dab87 780 switch(CurrentADC_State) {
emh203 1:6f37253dab87 781 default:
emh203 1:6f37253dab87 782 Junk = ADC0->R[0];
emh203 1:6f37253dab87 783 break;
emh203 1:6f37253dab87 784
emh203 1:6f37253dab87 785 case ADC_STATE_CAPTURE_POT_0:
emh203 1:6f37253dab87 786
emh203 1:6f37253dab87 787 PotADC_Value[0] = ADC0->R[0];
emh203 1:6f37253dab87 788 ADC0->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; //Select the A side of the mux
emh203 1:6f37253dab87 789 ADC0->SC1[0] = TFC_POT_1_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
emh203 1:6f37253dab87 790 CurrentADC_State = ADC_STATE_CAPTURE_POT_1;
emh203 1:6f37253dab87 791
emh203 1:6f37253dab87 792 break;
emh203 1:6f37253dab87 793
emh203 1:6f37253dab87 794 case ADC_STATE_CAPTURE_POT_1:
emh203 1:6f37253dab87 795
emh203 1:6f37253dab87 796 PotADC_Value[1] = ADC0->R[0];
Overdrivr 10:86c5fc9a53d9 797
Overdrivr 10:86c5fc9a53d9 798 CurrentADC_State = ADC_STATE_CAPTURE_I_HBRIDGE_A;
Overdrivr 10:86c5fc9a53d9 799 ADC0->SC1[0] = TFC_I_HBRIDGE_0_SENSE_ADC_CHANNEL | ADC_SC1_AIEN_MASK; // HBRIDGE channel
Overdrivr 10:86c5fc9a53d9 800 ADC0->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; //Select the A side of the mux
Overdrivr 10:86c5fc9a53d9 801 break;
Overdrivr 10:86c5fc9a53d9 802
Overdrivr 10:86c5fc9a53d9 803
Overdrivr 10:86c5fc9a53d9 804 // NEW STATES
Overdrivr 10:86c5fc9a53d9 805 case ADC_STATE_CAPTURE_I_HBRIDGE_A:
Overdrivr 10:86c5fc9a53d9 806 // Read ADC value
Overdrivr 10:86c5fc9a53d9 807 HBridge_0_current_value = ADC0->R[0];
Overdrivr 10:86c5fc9a53d9 808 // Change the ADC active channel
Overdrivr 10:86c5fc9a53d9 809 ADC0->SC1[0] = TFC_I_HBRIDGE_1_SENSE_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
Overdrivr 10:86c5fc9a53d9 810 // Update the state machine
Overdrivr 10:86c5fc9a53d9 811 CurrentADC_State = ADC_STATE_CAPTURE_I_HBRIDGE_B;
Overdrivr 10:86c5fc9a53d9 812 break;
Overdrivr 10:86c5fc9a53d9 813
Overdrivr 10:86c5fc9a53d9 814 case ADC_STATE_CAPTURE_I_HBRIDGE_B:
Overdrivr 10:86c5fc9a53d9 815 HBridge_1_current_value = ADC0->R[0];
emh203 1:6f37253dab87 816 ADC0->CFG2 |= ADC_CFG2_MUXSEL_MASK; //Select the B side of the mux
emh203 1:6f37253dab87 817 ADC0->SC1[0] = TFC_BAT_SENSE_CHANNEL| ADC_SC1_AIEN_MASK;
emh203 1:6f37253dab87 818 CurrentADC_State = ADC_STATE_CAPTURE_BATTERY_LEVEL;
emh203 1:6f37253dab87 819 break;
emh203 1:6f37253dab87 820
emh203 1:6f37253dab87 821 case ADC_STATE_CAPTURE_BATTERY_LEVEL:
emh203 1:6f37253dab87 822
emh203 1:6f37253dab87 823 BatSenseADC_Value = ADC0->R[0];
emh203 1:6f37253dab87 824
emh203 1:6f37253dab87 825 //Now we will start the sequence for the Linescan camera
emh203 1:6f37253dab87 826
emh203 1:6f37253dab87 827 TAOS_CLK_HIGH;
emh203 1:6f37253dab87 828
emh203 1:6f37253dab87 829 for(Junk = 0; Junk<50; Junk++) {
emh203 1:6f37253dab87 830 }
emh203 1:6f37253dab87 831
emh203 1:6f37253dab87 832 TAOS_SI_LOW;
emh203 1:6f37253dab87 833
emh203 1:6f37253dab87 834
emh203 1:6f37253dab87 835 CurrentLineScanPixel = 0;
emh203 1:6f37253dab87 836 CurrentLineScanChannel = 0;
emh203 1:6f37253dab87 837 CurrentADC_State = ADC_STATE_CAPTURE_LINE_SCAN;
emh203 1:6f37253dab87 838 ADC0->CFG2 |= ADC_CFG2_MUXSEL_MASK; //Select the B side of the mux
emh203 1:6f37253dab87 839 ADC0->SC1[0] = TFC_LINESCAN0_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
emh203 1:6f37253dab87 840
emh203 1:6f37253dab87 841 break;
emh203 1:6f37253dab87 842
emh203 1:6f37253dab87 843 case ADC_STATE_CAPTURE_LINE_SCAN:
emh203 1:6f37253dab87 844
emh203 1:6f37253dab87 845 if(CurrentLineScanPixel<128) {
emh203 1:6f37253dab87 846 if(CurrentLineScanChannel == 0) {
emh203 1:6f37253dab87 847 LineScanImage0WorkingBuffer[CurrentLineScanPixel] = ADC0->R[0];
emh203 1:6f37253dab87 848 ADC0->SC1[0] = TFC_LINESCAN1_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
emh203 1:6f37253dab87 849 CurrentLineScanChannel = 1;
emh203 1:6f37253dab87 850
emh203 1:6f37253dab87 851 } else {
emh203 1:6f37253dab87 852 LineScanImage1WorkingBuffer[CurrentLineScanPixel] = ADC0->R[0];
emh203 1:6f37253dab87 853 ADC0->SC1[0] = TFC_LINESCAN0_ADC_CHANNEL | ADC_SC1_AIEN_MASK;
emh203 1:6f37253dab87 854 CurrentLineScanChannel = 0;
emh203 1:6f37253dab87 855 CurrentLineScanPixel++;
emh203 1:6f37253dab87 856
emh203 1:6f37253dab87 857 TAOS_CLK_LOW;
emh203 1:6f37253dab87 858 for(Junk = 0; Junk<50; Junk++) {
emh203 1:6f37253dab87 859 }
emh203 1:6f37253dab87 860 TAOS_CLK_HIGH;
emh203 1:6f37253dab87 861
emh203 1:6f37253dab87 862 }
emh203 1:6f37253dab87 863
emh203 1:6f37253dab87 864 } else {
emh203 1:6f37253dab87 865 // done with the capture sequence. we can wait for the PIT0 IRQ to restart
emh203 1:6f37253dab87 866
emh203 1:6f37253dab87 867 TAOS_CLK_HIGH;
emh203 1:6f37253dab87 868
emh203 1:6f37253dab87 869 for(Junk = 0; Junk<50; Junk++) {
emh203 1:6f37253dab87 870 }
emh203 1:6f37253dab87 871
emh203 1:6f37253dab87 872 TAOS_CLK_LOW;
emh203 1:6f37253dab87 873 CurrentADC_State = ADC_STATE_INIT;
Overdrivr 10:86c5fc9a53d9 874
emh203 1:6f37253dab87 875 //swap the buffer
emh203 1:6f37253dab87 876
emh203 1:6f37253dab87 877 if(LineScanWorkingBuffer == 0) {
emh203 1:6f37253dab87 878 LineScanWorkingBuffer = 1;
emh203 1:6f37253dab87 879
emh203 1:6f37253dab87 880 LineScanImage0WorkingBuffer = &LineScanImage0Buffer[1][0];
emh203 1:6f37253dab87 881 LineScanImage1WorkingBuffer = &LineScanImage1Buffer[1][0];
emh203 1:6f37253dab87 882
emh203 3:23cce037011f 883 TFC_LineScanImage0 = &LineScanImage0Buffer[0][0];
emh203 3:23cce037011f 884 TFC_LineScanImage1 = &LineScanImage1Buffer[0][0];
emh203 1:6f37253dab87 885 } else {
emh203 1:6f37253dab87 886 LineScanWorkingBuffer = 0;
emh203 1:6f37253dab87 887 LineScanImage0WorkingBuffer = &LineScanImage0Buffer[0][0];
emh203 1:6f37253dab87 888 LineScanImage1WorkingBuffer = &LineScanImage1Buffer[0][0];
emh203 1:6f37253dab87 889
emh203 3:23cce037011f 890 TFC_LineScanImage0 = &LineScanImage0Buffer[1][0];
emh203 3:23cce037011f 891 TFC_LineScanImage1 = &LineScanImage1Buffer[1][0];
emh203 1:6f37253dab87 892 }
emh203 1:6f37253dab87 893
emh203 3:23cce037011f 894 TFC_LineScanImageReady++;
emh203 1:6f37253dab87 895 }
emh203 1:6f37253dab87 896
emh203 1:6f37253dab87 897 break;
emh203 1:6f37253dab87 898 }
emh203 1:6f37253dab87 899
emh203 1:6f37253dab87 900 }
emh203 1:6f37253dab87 901
emh203 1:6f37253dab87 902 void TFC_InitLineScanCamera()
emh203 1:6f37253dab87 903 {
emh203 1:6f37253dab87 904 SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTD_MASK; //Make sure the clock is enabled for PORTE;
emh203 1:6f37253dab87 905 PORTE->PCR[1] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //Enable GPIO on on the pin for the CLOCK Signal
emh203 1:6f37253dab87 906 PORTD->PCR[7] = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //Enable GPIO on on the pin for SI signal
emh203 1:6f37253dab87 907
emh203 1:6f37253dab87 908 PORTD->PCR[5] = PORT_PCR_MUX(0); //Make sure AO signal goes to an analog input
emh203 1:6f37253dab87 909 PORTD->PCR[6] = PORT_PCR_MUX(0); //Make sure AO signal goes to an analog input
emh203 1:6f37253dab87 910
emh203 1:6f37253dab87 911 //Make sure the Clock and SI pins are outputs
emh203 1:6f37253dab87 912 PTD->PDDR |= (1<<7);
emh203 1:6f37253dab87 913 PTE->PDDR |= (1<<1);
emh203 1:6f37253dab87 914
emh203 1:6f37253dab87 915 TAOS_CLK_LOW;
emh203 1:6f37253dab87 916 TAOS_SI_LOW;
emh203 1:6f37253dab87 917
emh203 1:6f37253dab87 918 LineScanWorkingBuffer = 0;
emh203 1:6f37253dab87 919
emh203 1:6f37253dab87 920 LineScanImage0WorkingBuffer = &LineScanImage0Buffer[LineScanWorkingBuffer][0];
emh203 1:6f37253dab87 921 LineScanImage1WorkingBuffer = &LineScanImage1Buffer[LineScanWorkingBuffer][0];
emh203 1:6f37253dab87 922
emh203 3:23cce037011f 923 TFC_LineScanImage0 = &LineScanImage0Buffer[1][0];
emh203 3:23cce037011f 924 TFC_LineScanImage1 = &LineScanImage1Buffer[1][0];
emh203 1:6f37253dab87 925 }
emh203 1:6f37253dab87 926
emh203 1:6f37253dab87 927
emh203 1:6f37253dab87 928
emh203 1:6f37253dab87 929
emh203 1:6f37253dab87 930
emh203 1:6f37253dab87 931 /** Initialized TPM0 to be used for generating PWM signals for the the dual drive motors. This method is called in the TFC constructor with a default value of 4000.0Hz
emh203 1:6f37253dab87 932 *
emh203 1:6f37253dab87 933 * @param SwitchingFrequency PWM Switching Frequency in floating point format. Pick something between 1000 and 9000. Maybe you can modulate it and make a tune.
emh203 1:6f37253dab87 934 */
emh203 1:6f37253dab87 935 void TFC_InitMotorPWM(float SwitchingFrequency)
emh203 1:6f37253dab87 936 {
emh203 1:6f37253dab87 937 //Clock Setup for the TPM requires a couple steps.
emh203 1:6f37253dab87 938
emh203 1:6f37253dab87 939 //1st, set the clock mux
emh203 1:6f37253dab87 940 //See Page 124 of f the KL25 Sub-Family Reference Manual, Rev. 3, September 2012
emh203 3:23cce037011f 941 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;// We Want MCGPLLCLK/2 (See Page 196 of the KL25 Sub-Family Reference Manual, Rev. 3, September 2012)
emh203 3:23cce037011f 942 SIM->SOPT2 &= ~(SIM_SOPT2_TPMSRC_MASK);
emh203 3:23cce037011f 943 SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); //We want the MCGPLLCLK/2 (See Page 196 of the KL25 Sub-Family Reference Manual, Rev. 3, September 2012)
emh203 1:6f37253dab87 944
emh203 1:6f37253dab87 945
emh203 1:6f37253dab87 946 //Enable the Clock to the FTM0 Module
emh203 1:6f37253dab87 947 //See Page 207 of f the KL25 Sub-Family Reference Manual, Rev. 3, September 2012
emh203 1:6f37253dab87 948 SIM->SCGC6 |= SIM_SCGC6_TPM0_MASK;
emh203 1:6f37253dab87 949
emh203 1:6f37253dab87 950 //The TPM Module has Clock. Now set up the peripheral
emh203 1:6f37253dab87 951
emh203 1:6f37253dab87 952 //Blow away the control registers to ensure that the counter is not running
emh203 1:6f37253dab87 953 TPM0->SC = 0;
emh203 1:6f37253dab87 954 TPM0->CONF = 0;
emh203 1:6f37253dab87 955
emh203 1:6f37253dab87 956 //While the counter is disabled we can setup the prescaler
emh203 1:6f37253dab87 957
emh203 1:6f37253dab87 958 TPM0->SC = TPM_SC_PS(FTM0_CLK_PRESCALE);
emh203 1:6f37253dab87 959
emh203 1:6f37253dab87 960 //Setup the mod register to get the correct PWM Period
emh203 1:6f37253dab87 961
emh203 1:6f37253dab87 962 TPM0->MOD = (uint32_t)((float)(FTM0_CLOCK/(1<<FTM0_CLK_PRESCALE))/SwitchingFrequency);
emh203 1:6f37253dab87 963
emh203 1:6f37253dab87 964 //Setup Channels 0,1,2,3
emh203 1:6f37253dab87 965 TPM0->CONTROLS[0].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
emh203 1:6f37253dab87 966 TPM0->CONTROLS[1].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK; // invert the second PWM signal for a complimentary output;
emh203 1:6f37253dab87 967 TPM0->CONTROLS[2].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSB_MASK;
emh203 1:6f37253dab87 968 TPM0->CONTROLS[3].CnSC = TPM_CnSC_MSB_MASK | TPM_CnSC_ELSA_MASK; // invert the second PWM signal for a complimentary output;
emh203 1:6f37253dab87 969
emh203 1:6f37253dab87 970 //Enable the Counter
emh203 1:6f37253dab87 971
emh203 1:6f37253dab87 972 //Set the Default duty cycle to 50% duty cycle
emh203 1:6f37253dab87 973 TFC_SetMotorPWM(0.0,0.0);
emh203 1:6f37253dab87 974
emh203 1:6f37253dab87 975 //Enable the TPM COunter
emh203 1:6f37253dab87 976 TPM0->SC |= TPM_SC_CMOD(1);
emh203 1:6f37253dab87 977
emh203 1:6f37253dab87 978 //Enable the FTM functions on the the port
emh203 1:6f37253dab87 979 PORTC->PCR[1] = PORT_PCR_MUX(4);
emh203 1:6f37253dab87 980 PORTC->PCR[2] = PORT_PCR_MUX(4);
emh203 1:6f37253dab87 981 PORTC->PCR[3] = PORT_PCR_MUX(4);
emh203 1:6f37253dab87 982 PORTC->PCR[4] = PORT_PCR_MUX(4);
emh203 1:6f37253dab87 983
emh203 1:6f37253dab87 984 }
emh203 1:6f37253dab87 985
emh203 1:6f37253dab87 986 void TFC_SetMotorPWM(float MotorA , float MotorB)
emh203 1:6f37253dab87 987 {
emh203 1:6f37253dab87 988 if(MotorA>1.0)
emh203 1:6f37253dab87 989 MotorA = 1.0;
emh203 1:6f37253dab87 990 else if(MotorA<-1.0)
emh203 1:6f37253dab87 991 MotorA = -1.0;
emh203 1:6f37253dab87 992
emh203 1:6f37253dab87 993 if(MotorB>1.0)
emh203 1:6f37253dab87 994 MotorB = 1.0;
emh203 1:6f37253dab87 995 else if(MotorB<-1.0)
emh203 1:6f37253dab87 996 MotorB = -1.0;
emh203 1:6f37253dab87 997
emh203 1:6f37253dab87 998 TPM0->CONTROLS[2].CnV = (uint16_t) ((float)TPM0->MOD * (float)((MotorA + 1.0)/2.0));
emh203 1:6f37253dab87 999 TPM0->CONTROLS[3].CnV = TPM0->CONTROLS[2].CnV;
emh203 1:6f37253dab87 1000 TPM0->CONTROLS[0].CnV = (uint16_t) ((float)TPM0->MOD * (float)((MotorB + 1.0)/2.0));
emh203 1:6f37253dab87 1001 TPM0->CONTROLS[1].CnV = TPM0->CONTROLS[0].CnV;
emh203 1:6f37253dab87 1002
emh203 1:6f37253dab87 1003 }
emh203 1:6f37253dab87 1004
emh203 1:6f37253dab87 1005 //Pot Reading is Scaled to return a value of -1.0 to 1.0
emh203 1:6f37253dab87 1006 float TFC_ReadPot(uint8_t Channel)
emh203 1:6f37253dab87 1007 {
emh203 1:6f37253dab87 1008 if(Channel == 0)
emh203 1:6f37253dab87 1009 return ((float)PotADC_Value[0]/-((float)ADC_MAX_CODE/2.0))+1.0;
emh203 1:6f37253dab87 1010 else
emh203 1:6f37253dab87 1011 return ((float)PotADC_Value[1]/-((float)ADC_MAX_CODE/2.0))+1.0;
emh203 1:6f37253dab87 1012 }
emh203 1:6f37253dab87 1013
emh203 1:6f37253dab87 1014 float TFC_ReadBatteryVoltage()
emh203 1:6f37253dab87 1015 {
emh203 1:6f37253dab87 1016 return (((float)BatSenseADC_Value/(float)(ADC_MAX_CODE)) * 3.0);// * ((47000.0+10000.0)/10000.0);
emh203 1:6f37253dab87 1017 }
emh203 3:23cce037011f 1018
Overdrivr 9:1c4fc3e224b5 1019 float TFC_ReadMotorCurrent(uint8_t motorChannel)
Overdrivr 9:1c4fc3e224b5 1020 {
Overdrivr 10:86c5fc9a53d9 1021 if(motorChannel)
Overdrivr 10:86c5fc9a53d9 1022 return ((float)(HBridge_0_current_value)/(float)(ADC_MAX_CODE));//TODO : Coefficient ?
Overdrivr 10:86c5fc9a53d9 1023 else
Overdrivr 10:86c5fc9a53d9 1024 return ((float)(HBridge_1_current_value)/(float)(ADC_MAX_CODE));//TODO : Coefficient ?
Overdrivr 9:1c4fc3e224b5 1025 }
Overdrivr 9:1c4fc3e224b5 1026
emh203 3:23cce037011f 1027
emh203 3:23cce037011f 1028 void TFC_SetBatteryLED_Level(uint8_t BattLevel)
emh203 3:23cce037011f 1029 {
emh203 3:23cce037011f 1030 switch(BattLevel)
emh203 3:23cce037011f 1031 {
emh203 3:23cce037011f 1032 default:
emh203 3:23cce037011f 1033 case 0:
emh203 3:23cce037011f 1034 TFC_BAT_LED0_OFF;
emh203 3:23cce037011f 1035 TFC_BAT_LED1_OFF;
emh203 3:23cce037011f 1036 TFC_BAT_LED2_OFF;
emh203 3:23cce037011f 1037 TFC_BAT_LED3_OFF;
emh203 3:23cce037011f 1038 break;
emh203 3:23cce037011f 1039
emh203 3:23cce037011f 1040 case 1:
emh203 3:23cce037011f 1041 TFC_BAT_LED0_ON;
emh203 3:23cce037011f 1042 TFC_BAT_LED1_OFF;
emh203 3:23cce037011f 1043 TFC_BAT_LED2_OFF;
emh203 3:23cce037011f 1044 TFC_BAT_LED3_OFF;
emh203 3:23cce037011f 1045 break;
emh203 3:23cce037011f 1046
emh203 3:23cce037011f 1047 case 2:
emh203 3:23cce037011f 1048 TFC_BAT_LED0_ON;
emh203 3:23cce037011f 1049 TFC_BAT_LED1_ON;
emh203 3:23cce037011f 1050 TFC_BAT_LED2_OFF;
emh203 3:23cce037011f 1051 TFC_BAT_LED3_OFF;
emh203 3:23cce037011f 1052 break;
emh203 3:23cce037011f 1053
emh203 3:23cce037011f 1054 case 3:
emh203 3:23cce037011f 1055 TFC_BAT_LED0_ON;
emh203 3:23cce037011f 1056 TFC_BAT_LED1_ON;
emh203 3:23cce037011f 1057 TFC_BAT_LED2_ON;
emh203 3:23cce037011f 1058 TFC_BAT_LED3_OFF;
emh203 3:23cce037011f 1059 break;
emh203 3:23cce037011f 1060
emh203 3:23cce037011f 1061 case 4:
emh203 3:23cce037011f 1062 TFC_BAT_LED0_ON;
emh203 3:23cce037011f 1063 TFC_BAT_LED1_ON;
emh203 3:23cce037011f 1064 TFC_BAT_LED2_ON;
emh203 3:23cce037011f 1065 TFC_BAT_LED3_ON;
emh203 3:23cce037011f 1066 break;
emh203 3:23cce037011f 1067
emh203 3:23cce037011f 1068 }
emh203 3:23cce037011f 1069 }