Nirvana Jay / BSP_DISCO_F746NG_patch

patch for F746 demo

Dependents:   F7DISCO_Demo

Fork of BSP_DISCO_F746NG by ST

Components/mfxstm32l152/mfxstm32l152.c@1:e8fac4061a5b, 2015-11-02 (annotated)

Committer:
NirT
Date:
Mon Nov 02 23:35:17 2015 +0000
Revision:
1:e8fac4061a5b
Error: Incomplete type is not allowed in "patch/LwIP/src/include/lwip/dhcp.h", Line: 83, Col: 4; ; and more like this.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NirT 1:e8fac4061a5b 1 /**
NirT 1:e8fac4061a5b 2 ******************************************************************************
NirT 1:e8fac4061a5b 3 * @file mfxstm32l152.c
NirT 1:e8fac4061a5b 4 * @author MCD Application Team
NirT 1:e8fac4061a5b 5 * @version V2.0.0
NirT 1:e8fac4061a5b 6 * @date 24-June-2015
NirT 1:e8fac4061a5b 7 * @brief This file provides a set of functions needed to manage the MFXSTM32L152
NirT 1:e8fac4061a5b 8 * IO Expander devices.
NirT 1:e8fac4061a5b 9 ******************************************************************************
NirT 1:e8fac4061a5b 10 * @attention
NirT 1:e8fac4061a5b 11 *
NirT 1:e8fac4061a5b 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
NirT 1:e8fac4061a5b 13 *
NirT 1:e8fac4061a5b 14 * Redistribution and use in source and binary forms, with or without modification,
NirT 1:e8fac4061a5b 15 * are permitted provided that the following conditions are met:
NirT 1:e8fac4061a5b 16 * 1. Redistributions of source code must retain the above copyright notice,
NirT 1:e8fac4061a5b 17 * this list of conditions and the following disclaimer.
NirT 1:e8fac4061a5b 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
NirT 1:e8fac4061a5b 19 * this list of conditions and the following disclaimer in the documentation
NirT 1:e8fac4061a5b 20 * and/or other materials provided with the distribution.
NirT 1:e8fac4061a5b 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NirT 1:e8fac4061a5b 22 * may be used to endorse or promote products derived from this software
NirT 1:e8fac4061a5b 23 * without specific prior written permission.
NirT 1:e8fac4061a5b 24 *
NirT 1:e8fac4061a5b 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NirT 1:e8fac4061a5b 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NirT 1:e8fac4061a5b 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NirT 1:e8fac4061a5b 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NirT 1:e8fac4061a5b 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NirT 1:e8fac4061a5b 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NirT 1:e8fac4061a5b 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NirT 1:e8fac4061a5b 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NirT 1:e8fac4061a5b 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NirT 1:e8fac4061a5b 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NirT 1:e8fac4061a5b 35 *
NirT 1:e8fac4061a5b 36 ******************************************************************************
NirT 1:e8fac4061a5b 37 */
NirT 1:e8fac4061a5b 38
NirT 1:e8fac4061a5b 39 /* Includes ------------------------------------------------------------------*/
NirT 1:e8fac4061a5b 40 #include "mfxstm32l152.h"
NirT 1:e8fac4061a5b 41
NirT 1:e8fac4061a5b 42 /** @addtogroup BSP
NirT 1:e8fac4061a5b 43 * @{
NirT 1:e8fac4061a5b 44 */
NirT 1:e8fac4061a5b 45
NirT 1:e8fac4061a5b 46 /** @addtogroup Component
NirT 1:e8fac4061a5b 47 * @{
NirT 1:e8fac4061a5b 48 */
NirT 1:e8fac4061a5b 49
NirT 1:e8fac4061a5b 50 /** @defgroup MFXSTM32L152
NirT 1:e8fac4061a5b 51 * @{
NirT 1:e8fac4061a5b 52 */
NirT 1:e8fac4061a5b 53
NirT 1:e8fac4061a5b 54 /* Private typedef -----------------------------------------------------------*/
NirT 1:e8fac4061a5b 55
NirT 1:e8fac4061a5b 56 /** @defgroup MFXSTM32L152_Private_Types_Definitions
NirT 1:e8fac4061a5b 57 * @{
NirT 1:e8fac4061a5b 58 */
NirT 1:e8fac4061a5b 59
NirT 1:e8fac4061a5b 60 /* Private define ------------------------------------------------------------*/
NirT 1:e8fac4061a5b 61
NirT 1:e8fac4061a5b 62 /** @defgroup MFXSTM32L152_Private_Defines
NirT 1:e8fac4061a5b 63 * @{
NirT 1:e8fac4061a5b 64 */
NirT 1:e8fac4061a5b 65 #define MFXSTM32L152_MAX_INSTANCE 3
NirT 1:e8fac4061a5b 66
NirT 1:e8fac4061a5b 67 /* Private macro -------------------------------------------------------------*/
NirT 1:e8fac4061a5b 68
NirT 1:e8fac4061a5b 69 /** @defgroup MFXSTM32L152_Private_Macros
NirT 1:e8fac4061a5b 70 * @{
NirT 1:e8fac4061a5b 71 */
NirT 1:e8fac4061a5b 72
NirT 1:e8fac4061a5b 73 /* Private variables ---------------------------------------------------------*/
NirT 1:e8fac4061a5b 74
NirT 1:e8fac4061a5b 75 /** @defgroup MFXSTM32L152_Private_Variables
NirT 1:e8fac4061a5b 76 * @{
NirT 1:e8fac4061a5b 77 */
NirT 1:e8fac4061a5b 78
NirT 1:e8fac4061a5b 79 /* Touch screen driver structure initialization */
NirT 1:e8fac4061a5b 80 TS_DrvTypeDef mfxstm32l152_ts_drv =
NirT 1:e8fac4061a5b 81 {
NirT 1:e8fac4061a5b 82 mfxstm32l152_Init,
NirT 1:e8fac4061a5b 83 mfxstm32l152_ReadID,
NirT 1:e8fac4061a5b 84 mfxstm32l152_Reset,
NirT 1:e8fac4061a5b 85
NirT 1:e8fac4061a5b 86 mfxstm32l152_TS_Start,
NirT 1:e8fac4061a5b 87 mfxstm32l152_TS_DetectTouch,
NirT 1:e8fac4061a5b 88 mfxstm32l152_TS_GetXY,
NirT 1:e8fac4061a5b 89
NirT 1:e8fac4061a5b 90 mfxstm32l152_TS_EnableIT,
NirT 1:e8fac4061a5b 91 mfxstm32l152_TS_ClearIT,
NirT 1:e8fac4061a5b 92 mfxstm32l152_TS_ITStatus,
NirT 1:e8fac4061a5b 93 mfxstm32l152_TS_DisableIT,
NirT 1:e8fac4061a5b 94 };
NirT 1:e8fac4061a5b 95
NirT 1:e8fac4061a5b 96 /* IO driver structure initialization */
NirT 1:e8fac4061a5b 97 IO_DrvTypeDef mfxstm32l152_io_drv =
NirT 1:e8fac4061a5b 98 {
NirT 1:e8fac4061a5b 99 mfxstm32l152_Init,
NirT 1:e8fac4061a5b 100 mfxstm32l152_ReadID,
NirT 1:e8fac4061a5b 101 mfxstm32l152_Reset,
NirT 1:e8fac4061a5b 102
NirT 1:e8fac4061a5b 103 mfxstm32l152_IO_Start,
NirT 1:e8fac4061a5b 104 mfxstm32l152_IO_Config,
NirT 1:e8fac4061a5b 105 mfxstm32l152_IO_WritePin,
NirT 1:e8fac4061a5b 106 mfxstm32l152_IO_ReadPin,
NirT 1:e8fac4061a5b 107
NirT 1:e8fac4061a5b 108 mfxstm32l152_IO_EnableIT,
NirT 1:e8fac4061a5b 109 mfxstm32l152_IO_DisableIT,
NirT 1:e8fac4061a5b 110 mfxstm32l152_IO_ITStatus,
NirT 1:e8fac4061a5b 111 mfxstm32l152_IO_ClearIT,
NirT 1:e8fac4061a5b 112 };
NirT 1:e8fac4061a5b 113
NirT 1:e8fac4061a5b 114 /* IDD driver structure initialization */
NirT 1:e8fac4061a5b 115 IDD_DrvTypeDef mfxstm32l152_idd_drv =
NirT 1:e8fac4061a5b 116 {
NirT 1:e8fac4061a5b 117 mfxstm32l152_Init,
NirT 1:e8fac4061a5b 118 mfxstm32l152_DeInit,
NirT 1:e8fac4061a5b 119 mfxstm32l152_ReadID,
NirT 1:e8fac4061a5b 120 mfxstm32l152_Reset,
NirT 1:e8fac4061a5b 121 mfxstm32l152_LowPower,
NirT 1:e8fac4061a5b 122 mfxstm32l152_WakeUp,
NirT 1:e8fac4061a5b 123
NirT 1:e8fac4061a5b 124 mfxstm32l152_IDD_Start,
NirT 1:e8fac4061a5b 125 mfxstm32l152_IDD_Config,
NirT 1:e8fac4061a5b 126 mfxstm32l152_IDD_GetValue,
NirT 1:e8fac4061a5b 127
NirT 1:e8fac4061a5b 128 mfxstm32l152_IDD_EnableIT,
NirT 1:e8fac4061a5b 129 mfxstm32l152_IDD_ClearIT,
NirT 1:e8fac4061a5b 130 mfxstm32l152_IDD_GetITStatus,
NirT 1:e8fac4061a5b 131 mfxstm32l152_IDD_DisableIT,
NirT 1:e8fac4061a5b 132
NirT 1:e8fac4061a5b 133 mfxstm32l152_Error_EnableIT,
NirT 1:e8fac4061a5b 134 mfxstm32l152_Error_ClearIT,
NirT 1:e8fac4061a5b 135 mfxstm32l152_Error_GetITStatus,
NirT 1:e8fac4061a5b 136 mfxstm32l152_Error_DisableIT,
NirT 1:e8fac4061a5b 137 mfxstm32l152_Error_ReadSrc,
NirT 1:e8fac4061a5b 138 mfxstm32l152_Error_ReadMsg
NirT 1:e8fac4061a5b 139 };
NirT 1:e8fac4061a5b 140
NirT 1:e8fac4061a5b 141
NirT 1:e8fac4061a5b 142 /* mfxstm32l152 instances by address */
NirT 1:e8fac4061a5b 143 uint8_t mfxstm32l152[MFXSTM32L152_MAX_INSTANCE] = {0};
NirT 1:e8fac4061a5b 144 /**
NirT 1:e8fac4061a5b 145 * @}
NirT 1:e8fac4061a5b 146 */
NirT 1:e8fac4061a5b 147
NirT 1:e8fac4061a5b 148 /* Private function prototypes -----------------------------------------------*/
NirT 1:e8fac4061a5b 149
NirT 1:e8fac4061a5b 150 /** @defgroup MFXSTM32L152_Private_Function_Prototypes
NirT 1:e8fac4061a5b 151 * @{
NirT 1:e8fac4061a5b 152 */
NirT 1:e8fac4061a5b 153 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 154 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr);
NirT 1:e8fac4061a5b 155 static void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue );
NirT 1:e8fac4061a5b 156
NirT 1:e8fac4061a5b 157 /* Private functions ---------------------------------------------------------*/
NirT 1:e8fac4061a5b 158
NirT 1:e8fac4061a5b 159 /** @defgroup MFXSTM32L152_Private_Functions
NirT 1:e8fac4061a5b 160 * @{
NirT 1:e8fac4061a5b 161 */
NirT 1:e8fac4061a5b 162
NirT 1:e8fac4061a5b 163 /**
NirT 1:e8fac4061a5b 164 * @brief Initialize the mfxstm32l152 and configure the needed hardware resources
NirT 1:e8fac4061a5b 165 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 166 * @retval None
NirT 1:e8fac4061a5b 167 */
NirT 1:e8fac4061a5b 168 void mfxstm32l152_Init(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 169 {
NirT 1:e8fac4061a5b 170 uint8_t instance;
NirT 1:e8fac4061a5b 171 uint8_t empty;
NirT 1:e8fac4061a5b 172
NirT 1:e8fac4061a5b 173 /* Check if device instance already exists */
NirT 1:e8fac4061a5b 174 instance = mfxstm32l152_GetInstance(DeviceAddr);
NirT 1:e8fac4061a5b 175
NirT 1:e8fac4061a5b 176 /* To prevent double initialization */
NirT 1:e8fac4061a5b 177 if(instance == 0xFF)
NirT 1:e8fac4061a5b 178 {
NirT 1:e8fac4061a5b 179 /* Look for empty instance */
NirT 1:e8fac4061a5b 180 empty = mfxstm32l152_GetInstance(0);
NirT 1:e8fac4061a5b 181
NirT 1:e8fac4061a5b 182 if(empty < MFXSTM32L152_MAX_INSTANCE)
NirT 1:e8fac4061a5b 183 {
NirT 1:e8fac4061a5b 184 /* Register the current device instance */
NirT 1:e8fac4061a5b 185 mfxstm32l152[empty] = DeviceAddr;
NirT 1:e8fac4061a5b 186
NirT 1:e8fac4061a5b 187 /* Initialize IO BUS layer */
NirT 1:e8fac4061a5b 188 MFX_IO_Init();
NirT 1:e8fac4061a5b 189 }
NirT 1:e8fac4061a5b 190 }
NirT 1:e8fac4061a5b 191
NirT 1:e8fac4061a5b 192 mfxstm32l152_SetIrqOutPinPolarity(DeviceAddr, MFXSTM32L152_OUT_PIN_POLARITY_HIGH);
NirT 1:e8fac4061a5b 193 mfxstm32l152_SetIrqOutPinType(DeviceAddr, MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL);
NirT 1:e8fac4061a5b 194 }
NirT 1:e8fac4061a5b 195
NirT 1:e8fac4061a5b 196 /**
NirT 1:e8fac4061a5b 197 * @brief DeInitialize the mfxstm32l152 and unconfigure the needed hardware resources
NirT 1:e8fac4061a5b 198 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 199 * @retval None
NirT 1:e8fac4061a5b 200 */
NirT 1:e8fac4061a5b 201 void mfxstm32l152_DeInit(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 202 {
NirT 1:e8fac4061a5b 203 uint8_t instance;
NirT 1:e8fac4061a5b 204
NirT 1:e8fac4061a5b 205 /* release existing instance */
NirT 1:e8fac4061a5b 206 instance = mfxstm32l152_ReleaseInstance(DeviceAddr);
NirT 1:e8fac4061a5b 207
NirT 1:e8fac4061a5b 208 /* De-Init only if instance was previously registered */
NirT 1:e8fac4061a5b 209 if(instance != 0xFF)
NirT 1:e8fac4061a5b 210 {
NirT 1:e8fac4061a5b 211 /* De-Initialize IO BUS layer */
NirT 1:e8fac4061a5b 212 MFX_IO_DeInit();
NirT 1:e8fac4061a5b 213 }
NirT 1:e8fac4061a5b 214 }
NirT 1:e8fac4061a5b 215
NirT 1:e8fac4061a5b 216 /**
NirT 1:e8fac4061a5b 217 * @brief Reset the mfxstm32l152 by Software.
NirT 1:e8fac4061a5b 218 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 219 * @retval None
NirT 1:e8fac4061a5b 220 */
NirT 1:e8fac4061a5b 221 void mfxstm32l152_Reset(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 222 {
NirT 1:e8fac4061a5b 223 /* Soft Reset */
NirT 1:e8fac4061a5b 224 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_SWRST);
NirT 1:e8fac4061a5b 225
NirT 1:e8fac4061a5b 226 /* Wait for a delay to ensure registers erasing */
NirT 1:e8fac4061a5b 227 MFX_IO_Delay(10);
NirT 1:e8fac4061a5b 228 }
NirT 1:e8fac4061a5b 229
NirT 1:e8fac4061a5b 230 /**
NirT 1:e8fac4061a5b 231 * @brief Put mfxstm32l152 Device in Low Power standby mode
NirT 1:e8fac4061a5b 232 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 233 * @retval None
NirT 1:e8fac4061a5b 234 */
NirT 1:e8fac4061a5b 235 void mfxstm32l152_LowPower(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 236 {
NirT 1:e8fac4061a5b 237 /* Enter standby mode */
NirT 1:e8fac4061a5b 238 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, MFXSTM32L152_STANDBY);
NirT 1:e8fac4061a5b 239
NirT 1:e8fac4061a5b 240 /* enable wakeup pin */
NirT 1:e8fac4061a5b 241 MFX_IO_EnableWakeupPin();
NirT 1:e8fac4061a5b 242 }
NirT 1:e8fac4061a5b 243
NirT 1:e8fac4061a5b 244 /**
NirT 1:e8fac4061a5b 245 * @brief WakeUp mfxstm32l152 from standby mode
NirT 1:e8fac4061a5b 246 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 247 * @retval None
NirT 1:e8fac4061a5b 248 */
NirT 1:e8fac4061a5b 249 void mfxstm32l152_WakeUp(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 250 {
NirT 1:e8fac4061a5b 251 uint8_t instance;
NirT 1:e8fac4061a5b 252
NirT 1:e8fac4061a5b 253 /* Check if device instance already exists */
NirT 1:e8fac4061a5b 254 instance = mfxstm32l152_GetInstance(DeviceAddr);
NirT 1:e8fac4061a5b 255
NirT 1:e8fac4061a5b 256 /* if instance does not exist, first initialize pins*/
NirT 1:e8fac4061a5b 257 if(instance == 0xFF)
NirT 1:e8fac4061a5b 258 {
NirT 1:e8fac4061a5b 259 /* enable wakeup pin */
NirT 1:e8fac4061a5b 260 MFX_IO_EnableWakeupPin();
NirT 1:e8fac4061a5b 261 }
NirT 1:e8fac4061a5b 262
NirT 1:e8fac4061a5b 263 /* toggle wakeup pin */
NirT 1:e8fac4061a5b 264 MFX_IO_Wakeup();
NirT 1:e8fac4061a5b 265 }
NirT 1:e8fac4061a5b 266
NirT 1:e8fac4061a5b 267 /**
NirT 1:e8fac4061a5b 268 * @brief Read the MFXSTM32L152 IO Expander device ID.
NirT 1:e8fac4061a5b 269 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 270 * @retval The Device ID (two bytes).
NirT 1:e8fac4061a5b 271 */
NirT 1:e8fac4061a5b 272 uint16_t mfxstm32l152_ReadID(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 273 {
NirT 1:e8fac4061a5b 274 uint8_t id;
NirT 1:e8fac4061a5b 275
NirT 1:e8fac4061a5b 276 /* Wait for a delay to ensure the state of registers */
NirT 1:e8fac4061a5b 277 MFX_IO_Delay(1);
NirT 1:e8fac4061a5b 278
NirT 1:e8fac4061a5b 279 /* Initialize IO BUS layer */
NirT 1:e8fac4061a5b 280 MFX_IO_Init();
NirT 1:e8fac4061a5b 281
NirT 1:e8fac4061a5b 282 id = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_ID);
NirT 1:e8fac4061a5b 283
NirT 1:e8fac4061a5b 284 /* Return the device ID value */
NirT 1:e8fac4061a5b 285 return (id);
NirT 1:e8fac4061a5b 286 }
NirT 1:e8fac4061a5b 287
NirT 1:e8fac4061a5b 288 /**
NirT 1:e8fac4061a5b 289 * @brief Read the MFXSTM32L152 device firmware version.
NirT 1:e8fac4061a5b 290 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 291 * @retval The Device FW version (two bytes).
NirT 1:e8fac4061a5b 292 */
NirT 1:e8fac4061a5b 293 uint16_t mfxstm32l152_ReadFwVersion(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 294 {
NirT 1:e8fac4061a5b 295 uint8_t data[2];
NirT 1:e8fac4061a5b 296
NirT 1:e8fac4061a5b 297 MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_FW_VERSION_MSB, data, sizeof(data)) ;
NirT 1:e8fac4061a5b 298
NirT 1:e8fac4061a5b 299 /* Recompose MFX firmware value */
NirT 1:e8fac4061a5b 300 return ((data[0] << 8) | data[1]);
NirT 1:e8fac4061a5b 301 }
NirT 1:e8fac4061a5b 302
NirT 1:e8fac4061a5b 303 /**
NirT 1:e8fac4061a5b 304 * @brief Enable the interrupt mode for the selected IT source
NirT 1:e8fac4061a5b 305 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 306 * @param Source: The interrupt source to be configured, could be:
NirT 1:e8fac4061a5b 307 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
NirT 1:e8fac4061a5b 308 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
NirT 1:e8fac4061a5b 309 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
NirT 1:e8fac4061a5b 310 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
NirT 1:e8fac4061a5b 311 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
NirT 1:e8fac4061a5b 312 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
NirT 1:e8fac4061a5b 313 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
NirT 1:e8fac4061a5b 314 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
NirT 1:e8fac4061a5b 315 * @retval None
NirT 1:e8fac4061a5b 316 */
NirT 1:e8fac4061a5b 317 void mfxstm32l152_EnableITSource(uint16_t DeviceAddr, uint8_t Source)
NirT 1:e8fac4061a5b 318 {
NirT 1:e8fac4061a5b 319 uint8_t tmp = 0;
NirT 1:e8fac4061a5b 320
NirT 1:e8fac4061a5b 321 /* Get the current value of the INT_EN register */
NirT 1:e8fac4061a5b 322 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
NirT 1:e8fac4061a5b 323
NirT 1:e8fac4061a5b 324 /* Set the interrupts to be Enabled */
NirT 1:e8fac4061a5b 325 tmp |= Source;
NirT 1:e8fac4061a5b 326
NirT 1:e8fac4061a5b 327 /* Set the register */
NirT 1:e8fac4061a5b 328 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
NirT 1:e8fac4061a5b 329 }
NirT 1:e8fac4061a5b 330
NirT 1:e8fac4061a5b 331 /**
NirT 1:e8fac4061a5b 332 * @brief Disable the interrupt mode for the selected IT source
NirT 1:e8fac4061a5b 333 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 334 * @param Source: The interrupt source to be configured, could be:
NirT 1:e8fac4061a5b 335 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
NirT 1:e8fac4061a5b 336 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
NirT 1:e8fac4061a5b 337 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
NirT 1:e8fac4061a5b 338 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
NirT 1:e8fac4061a5b 339 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
NirT 1:e8fac4061a5b 340 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
NirT 1:e8fac4061a5b 341 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
NirT 1:e8fac4061a5b 342 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
NirT 1:e8fac4061a5b 343 * @retval None
NirT 1:e8fac4061a5b 344 */
NirT 1:e8fac4061a5b 345 void mfxstm32l152_DisableITSource(uint16_t DeviceAddr, uint8_t Source)
NirT 1:e8fac4061a5b 346 {
NirT 1:e8fac4061a5b 347 uint8_t tmp = 0;
NirT 1:e8fac4061a5b 348
NirT 1:e8fac4061a5b 349 /* Get the current value of the INT_EN register */
NirT 1:e8fac4061a5b 350 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN);
NirT 1:e8fac4061a5b 351
NirT 1:e8fac4061a5b 352 /* Set the interrupts to be Enabled */
NirT 1:e8fac4061a5b 353 tmp &= ~Source;
NirT 1:e8fac4061a5b 354
NirT 1:e8fac4061a5b 355 /* Set the register */
NirT 1:e8fac4061a5b 356 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_SRC_EN, tmp);
NirT 1:e8fac4061a5b 357 }
NirT 1:e8fac4061a5b 358
NirT 1:e8fac4061a5b 359
NirT 1:e8fac4061a5b 360 /**
NirT 1:e8fac4061a5b 361 * @brief Returns the selected Global interrupt source pending bit value
NirT 1:e8fac4061a5b 362 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 363 * @param Source: the Global interrupt source to be checked, could be:
NirT 1:e8fac4061a5b 364 * @arg MFXSTM32L152_IRQ_GPIO: IO interrupt
NirT 1:e8fac4061a5b 365 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
NirT 1:e8fac4061a5b 366 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
NirT 1:e8fac4061a5b 367 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
NirT 1:e8fac4061a5b 368 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
NirT 1:e8fac4061a5b 369 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
NirT 1:e8fac4061a5b 370 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
NirT 1:e8fac4061a5b 371 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
NirT 1:e8fac4061a5b 372 * @retval The value of the checked Global interrupt source status.
NirT 1:e8fac4061a5b 373 */
NirT 1:e8fac4061a5b 374 uint8_t mfxstm32l152_GlobalITStatus(uint16_t DeviceAddr, uint8_t Source)
NirT 1:e8fac4061a5b 375 {
NirT 1:e8fac4061a5b 376 /* Return the global IT source status (pending or not)*/
NirT 1:e8fac4061a5b 377 return((MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_PENDING) & Source));
NirT 1:e8fac4061a5b 378 }
NirT 1:e8fac4061a5b 379
NirT 1:e8fac4061a5b 380 /**
NirT 1:e8fac4061a5b 381 * @brief Clear the selected Global interrupt pending bit(s)
NirT 1:e8fac4061a5b 382 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 383 * @param Source: the Global interrupt source to be cleared, could be any combination
NirT 1:e8fac4061a5b 384 * of the below values. The acknowledge signal for MFXSTM32L152_GPIOs configured in input
NirT 1:e8fac4061a5b 385 * with interrupt is not on this register but in IRQ_GPI_ACK1, IRQ_GPI_ACK2 registers.
NirT 1:e8fac4061a5b 386 * @arg MFXSTM32L152_IRQ_IDD : IDD interrupt
NirT 1:e8fac4061a5b 387 * @arg MFXSTM32L152_IRQ_ERROR : Error interrupt
NirT 1:e8fac4061a5b 388 * @arg MFXSTM32L152_IRQ_TS_DET : Touch Screen Controller Touch Detected interrupt
NirT 1:e8fac4061a5b 389 * @arg MFXSTM32L152_IRQ_TS_NE : Touch Screen FIFO Not Empty
NirT 1:e8fac4061a5b 390 * @arg MFXSTM32L152_IRQ_TS_TH : Touch Screen FIFO threshold triggered
NirT 1:e8fac4061a5b 391 * @arg MFXSTM32L152_IRQ_TS_FULL : Touch Screen FIFO Full
NirT 1:e8fac4061a5b 392 * @arg MFXSTM32L152_IRQ_TS_OVF : Touch Screen FIFO Overflow
NirT 1:e8fac4061a5b 393 * /\/\ IMPORTANT NOTE /\/\ must not use MFXSTM32L152_IRQ_GPIO as argument, see IRQ_GPI_ACK1 and IRQ_GPI_ACK2 registers
NirT 1:e8fac4061a5b 394 * @retval None
NirT 1:e8fac4061a5b 395 */
NirT 1:e8fac4061a5b 396 void mfxstm32l152_ClearGlobalIT(uint16_t DeviceAddr, uint8_t Source)
NirT 1:e8fac4061a5b 397 {
NirT 1:e8fac4061a5b 398 /* Write 1 to the bits that have to be cleared */
NirT 1:e8fac4061a5b 399 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_ACK, Source);
NirT 1:e8fac4061a5b 400 }
NirT 1:e8fac4061a5b 401
NirT 1:e8fac4061a5b 402 /**
NirT 1:e8fac4061a5b 403 * @brief Set the global interrupt Polarity of IRQ_OUT_PIN.
NirT 1:e8fac4061a5b 404 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 405 * @param Polarity: the IT mode polarity, could be one of the following values:
NirT 1:e8fac4061a5b 406 * @arg MFXSTM32L152_OUT_PIN_POLARITY_LOW: Interrupt output line is active Low edge
NirT 1:e8fac4061a5b 407 * @arg MFXSTM32L152_OUT_PIN_POLARITY_HIGH: Interrupt line output is active High edge
NirT 1:e8fac4061a5b 408 * @retval None
NirT 1:e8fac4061a5b 409 */
NirT 1:e8fac4061a5b 410 void mfxstm32l152_SetIrqOutPinPolarity(uint16_t DeviceAddr, uint8_t Polarity)
NirT 1:e8fac4061a5b 411 {
NirT 1:e8fac4061a5b 412 uint8_t tmp = 0;
NirT 1:e8fac4061a5b 413
NirT 1:e8fac4061a5b 414 /* Get the current register value */
NirT 1:e8fac4061a5b 415 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
NirT 1:e8fac4061a5b 416
NirT 1:e8fac4061a5b 417 /* Mask the polarity bits */
NirT 1:e8fac4061a5b 418 tmp &= ~(uint8_t)0x02;
NirT 1:e8fac4061a5b 419
NirT 1:e8fac4061a5b 420 /* Modify the Interrupt Output line configuration */
NirT 1:e8fac4061a5b 421 tmp |= Polarity;
NirT 1:e8fac4061a5b 422
NirT 1:e8fac4061a5b 423 /* Set the new register value */
NirT 1:e8fac4061a5b 424 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
NirT 1:e8fac4061a5b 425
NirT 1:e8fac4061a5b 426 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
NirT 1:e8fac4061a5b 427 MFX_IO_Delay(1);
NirT 1:e8fac4061a5b 428
NirT 1:e8fac4061a5b 429 }
NirT 1:e8fac4061a5b 430
NirT 1:e8fac4061a5b 431 /**
NirT 1:e8fac4061a5b 432 * @brief Set the global interrupt Type of IRQ_OUT_PIN.
NirT 1:e8fac4061a5b 433 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 434 * @param Type: Interrupt line activity type, could be one of the following values:
NirT 1:e8fac4061a5b 435 * @arg MFXSTM32L152_OUT_PIN_TYPE_OPENDRAIN: Open Drain output Interrupt line
NirT 1:e8fac4061a5b 436 * @arg MFXSTM32L152_OUT_PIN_TYPE_PUSHPULL: Push Pull output Interrupt line
NirT 1:e8fac4061a5b 437 * @retval None
NirT 1:e8fac4061a5b 438 */
NirT 1:e8fac4061a5b 439 void mfxstm32l152_SetIrqOutPinType(uint16_t DeviceAddr, uint8_t Type)
NirT 1:e8fac4061a5b 440 {
NirT 1:e8fac4061a5b 441 uint8_t tmp = 0;
NirT 1:e8fac4061a5b 442
NirT 1:e8fac4061a5b 443 /* Get the current register value */
NirT 1:e8fac4061a5b 444 tmp = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT);
NirT 1:e8fac4061a5b 445
NirT 1:e8fac4061a5b 446 /* Mask the type bits */
NirT 1:e8fac4061a5b 447 tmp &= ~(uint8_t)0x01;
NirT 1:e8fac4061a5b 448
NirT 1:e8fac4061a5b 449 /* Modify the Interrupt Output line configuration */
NirT 1:e8fac4061a5b 450 tmp |= Type;
NirT 1:e8fac4061a5b 451
NirT 1:e8fac4061a5b 452 /* Set the new register value */
NirT 1:e8fac4061a5b 453 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_MFX_IRQ_OUT, tmp);
NirT 1:e8fac4061a5b 454
NirT 1:e8fac4061a5b 455 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
NirT 1:e8fac4061a5b 456 MFX_IO_Delay(1);
NirT 1:e8fac4061a5b 457
NirT 1:e8fac4061a5b 458 }
NirT 1:e8fac4061a5b 459
NirT 1:e8fac4061a5b 460
NirT 1:e8fac4061a5b 461 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 462 /* ----------------------- GPIO ------------------------------------- */
NirT 1:e8fac4061a5b 463 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 464
NirT 1:e8fac4061a5b 465
NirT 1:e8fac4061a5b 466 /**
NirT 1:e8fac4061a5b 467 * @brief Start the IO functionality used and enable the AF for selected IO pin(s).
NirT 1:e8fac4061a5b 468 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 469 * @param AF_en: 0 to disable, else enabled.
NirT 1:e8fac4061a5b 470 * @retval None
NirT 1:e8fac4061a5b 471 */
NirT 1:e8fac4061a5b 472 void mfxstm32l152_IO_Start(uint16_t DeviceAddr, uint32_t IO_Pin)
NirT 1:e8fac4061a5b 473 {
NirT 1:e8fac4061a5b 474 uint8_t mode;
NirT 1:e8fac4061a5b 475
NirT 1:e8fac4061a5b 476 /* Get the current register value */
NirT 1:e8fac4061a5b 477 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
NirT 1:e8fac4061a5b 478
NirT 1:e8fac4061a5b 479 /* Set the IO Functionalities to be Enabled */
NirT 1:e8fac4061a5b 480 mode |= MFXSTM32L152_GPIO_EN;
NirT 1:e8fac4061a5b 481
NirT 1:e8fac4061a5b 482 /* Enable ALTERNATE functions */
NirT 1:e8fac4061a5b 483 /* AGPIO[0..3] can be either IDD or GPIO */
NirT 1:e8fac4061a5b 484 /* AGPIO[4..7] can be either TS or GPIO */
NirT 1:e8fac4061a5b 485 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
NirT 1:e8fac4061a5b 486 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
NirT 1:e8fac4061a5b 487 /* so if IDD and TS are both active it is better to let ALTERNATE off (0) */
NirT 1:e8fac4061a5b 488 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
NirT 1:e8fac4061a5b 489 /* remind that AGPIO are less efficient then normal GPIO (They use pooling rather then EXTI */
NirT 1:e8fac4061a5b 490 if (IO_Pin > 0xFFFF)
NirT 1:e8fac4061a5b 491 {
NirT 1:e8fac4061a5b 492 mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
NirT 1:e8fac4061a5b 493 }
NirT 1:e8fac4061a5b 494 else
NirT 1:e8fac4061a5b 495 {
NirT 1:e8fac4061a5b 496 mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
NirT 1:e8fac4061a5b 497 }
NirT 1:e8fac4061a5b 498
NirT 1:e8fac4061a5b 499 /* Write the new register value */
NirT 1:e8fac4061a5b 500 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
NirT 1:e8fac4061a5b 501
NirT 1:e8fac4061a5b 502 /* Wait for 1 ms for MFX to change IRQ_out pin config, before activate it */
NirT 1:e8fac4061a5b 503 MFX_IO_Delay(1);
NirT 1:e8fac4061a5b 504 }
NirT 1:e8fac4061a5b 505
NirT 1:e8fac4061a5b 506 /**
NirT 1:e8fac4061a5b 507 * @brief Configures the IO pin(s) according to IO mode structure value.
NirT 1:e8fac4061a5b 508 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 509 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
NirT 1:e8fac4061a5b 510 * of the following values:
NirT 1:e8fac4061a5b 511 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
NirT 1:e8fac4061a5b 512 * @param IO_Mode: The IO pin mode to configure, could be one of the following values:
NirT 1:e8fac4061a5b 513 * @arg IO_MODE_INPUT
NirT 1:e8fac4061a5b 514 * @arg IO_MODE_OUTPUT
NirT 1:e8fac4061a5b 515 * @arg IO_MODE_IT_RISING_EDGE
NirT 1:e8fac4061a5b 516 * @arg IO_MODE_IT_FALLING_EDGE
NirT 1:e8fac4061a5b 517 * @arg IO_MODE_IT_LOW_LEVEL
NirT 1:e8fac4061a5b 518 * @arg IO_MODE_IT_HIGH_LEVEL
NirT 1:e8fac4061a5b 519 * @arg IO_MODE_INPUT_PU,
NirT 1:e8fac4061a5b 520 * @arg IO_MODE_INPUT_PD,
NirT 1:e8fac4061a5b 521 * @arg IO_MODE_OUTPUT_OD_PU,
NirT 1:e8fac4061a5b 522 * @arg IO_MODE_OUTPUT_OD_PD,
NirT 1:e8fac4061a5b 523 * @arg IO_MODE_OUTPUT_PP_PU,
NirT 1:e8fac4061a5b 524 * @arg IO_MODE_OUTPUT_PP_PD,
NirT 1:e8fac4061a5b 525 * @arg IO_MODE_IT_RISING_EDGE_PU
NirT 1:e8fac4061a5b 526 * @arg IO_MODE_IT_FALLING_EDGE_PU
NirT 1:e8fac4061a5b 527 * @arg IO_MODE_IT_LOW_LEVEL_PU
NirT 1:e8fac4061a5b 528 * @arg IO_MODE_IT_HIGH_LEVEL_PU
NirT 1:e8fac4061a5b 529 * @arg IO_MODE_IT_RISING_EDGE_PD
NirT 1:e8fac4061a5b 530 * @arg IO_MODE_IT_FALLING_EDGE_PD
NirT 1:e8fac4061a5b 531 * @arg IO_MODE_IT_LOW_LEVEL_PD
NirT 1:e8fac4061a5b 532 * @arg IO_MODE_IT_HIGH_LEVEL_PD
NirT 1:e8fac4061a5b 533 * @retval None
NirT 1:e8fac4061a5b 534 */
NirT 1:e8fac4061a5b 535 uint8_t mfxstm32l152_IO_Config(uint16_t DeviceAddr, uint32_t IO_Pin, IO_ModeTypedef IO_Mode)
NirT 1:e8fac4061a5b 536 {
NirT 1:e8fac4061a5b 537 uint8_t error_code = 0;
NirT 1:e8fac4061a5b 538
NirT 1:e8fac4061a5b 539 /* Configure IO pin according to selected IO mode */
NirT 1:e8fac4061a5b 540 switch(IO_Mode)
NirT 1:e8fac4061a5b 541 {
NirT 1:e8fac4061a5b 542 case IO_MODE_OFF: /* Off or analog mode */
NirT 1:e8fac4061a5b 543 case IO_MODE_ANALOG: /* Off or analog mode */
NirT 1:e8fac4061a5b 544 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
NirT 1:e8fac4061a5b 545 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 546 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
NirT 1:e8fac4061a5b 547 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
NirT 1:e8fac4061a5b 548 break;
NirT 1:e8fac4061a5b 549
NirT 1:e8fac4061a5b 550 case IO_MODE_INPUT: /* Input mode */
NirT 1:e8fac4061a5b 551 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
NirT 1:e8fac4061a5b 552 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 553 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
NirT 1:e8fac4061a5b 554 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 555 break;
NirT 1:e8fac4061a5b 556
NirT 1:e8fac4061a5b 557 case IO_MODE_INPUT_PU: /* Input mode */
NirT 1:e8fac4061a5b 558 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
NirT 1:e8fac4061a5b 559 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 560 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 561 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 562 break;
NirT 1:e8fac4061a5b 563
NirT 1:e8fac4061a5b 564 case IO_MODE_INPUT_PD: /* Input mode */
NirT 1:e8fac4061a5b 565 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
NirT 1:e8fac4061a5b 566 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 567 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 568 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
NirT 1:e8fac4061a5b 569 break;
NirT 1:e8fac4061a5b 570
NirT 1:e8fac4061a5b 571 case IO_MODE_OUTPUT: /* Output mode */
NirT 1:e8fac4061a5b 572 case IO_MODE_OUTPUT_PP_PD: /* Output mode */
NirT 1:e8fac4061a5b 573 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
NirT 1:e8fac4061a5b 574 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
NirT 1:e8fac4061a5b 575 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
NirT 1:e8fac4061a5b 576 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
NirT 1:e8fac4061a5b 577 break;
NirT 1:e8fac4061a5b 578
NirT 1:e8fac4061a5b 579 case IO_MODE_OUTPUT_PP_PU: /* Output mode */
NirT 1:e8fac4061a5b 580 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
NirT 1:e8fac4061a5b 581 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
NirT 1:e8fac4061a5b 582 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_PUSH_PULL);
NirT 1:e8fac4061a5b 583 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 584 break;
NirT 1:e8fac4061a5b 585
NirT 1:e8fac4061a5b 586 case IO_MODE_OUTPUT_OD_PD: /* Output mode */
NirT 1:e8fac4061a5b 587 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
NirT 1:e8fac4061a5b 588 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
NirT 1:e8fac4061a5b 589 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
NirT 1:e8fac4061a5b 590 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
NirT 1:e8fac4061a5b 591 break;
NirT 1:e8fac4061a5b 592
NirT 1:e8fac4061a5b 593 case IO_MODE_OUTPUT_OD_PU: /* Output mode */
NirT 1:e8fac4061a5b 594 mfxstm32l152_IO_DisablePinIT(DeviceAddr, IO_Pin); /* first disable IT */
NirT 1:e8fac4061a5b 595 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_OUT);
NirT 1:e8fac4061a5b 596 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPO_OPEN_DRAIN);
NirT 1:e8fac4061a5b 597 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 598 break;
NirT 1:e8fac4061a5b 599
NirT 1:e8fac4061a5b 600 case IO_MODE_IT_RISING_EDGE: /* Interrupt rising edge mode */
NirT 1:e8fac4061a5b 601 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 602 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 603 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
NirT 1:e8fac4061a5b 604 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 605 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
NirT 1:e8fac4061a5b 606 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
NirT 1:e8fac4061a5b 607 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 608 break;
NirT 1:e8fac4061a5b 609
NirT 1:e8fac4061a5b 610 case IO_MODE_IT_RISING_EDGE_PU: /* Interrupt rising edge mode */
NirT 1:e8fac4061a5b 611 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 612 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 613 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 614 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 615 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
NirT 1:e8fac4061a5b 616 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
NirT 1:e8fac4061a5b 617 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 618 break;
NirT 1:e8fac4061a5b 619
NirT 1:e8fac4061a5b 620 case IO_MODE_IT_RISING_EDGE_PD: /* Interrupt rising edge mode */
NirT 1:e8fac4061a5b 621 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 622 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 623 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 624 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
NirT 1:e8fac4061a5b 625 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
NirT 1:e8fac4061a5b 626 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
NirT 1:e8fac4061a5b 627 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 628 break;
NirT 1:e8fac4061a5b 629
NirT 1:e8fac4061a5b 630 case IO_MODE_IT_FALLING_EDGE: /* Interrupt falling edge mode */
NirT 1:e8fac4061a5b 631 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 632 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 633 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
NirT 1:e8fac4061a5b 634 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 635 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
NirT 1:e8fac4061a5b 636 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
NirT 1:e8fac4061a5b 637 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 638 break;
NirT 1:e8fac4061a5b 639
NirT 1:e8fac4061a5b 640 case IO_MODE_IT_FALLING_EDGE_PU: /* Interrupt falling edge mode */
NirT 1:e8fac4061a5b 641 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 642 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 643 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 644 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 645 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
NirT 1:e8fac4061a5b 646 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
NirT 1:e8fac4061a5b 647 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 648 break;
NirT 1:e8fac4061a5b 649
NirT 1:e8fac4061a5b 650 case IO_MODE_IT_FALLING_EDGE_PD: /* Interrupt falling edge mode */
NirT 1:e8fac4061a5b 651 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 652 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 653 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 654 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
NirT 1:e8fac4061a5b 655 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_EDGE);
NirT 1:e8fac4061a5b 656 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
NirT 1:e8fac4061a5b 657 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 658 break;
NirT 1:e8fac4061a5b 659
NirT 1:e8fac4061a5b 660 case IO_MODE_IT_LOW_LEVEL: /* Low level interrupt mode */
NirT 1:e8fac4061a5b 661 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 662 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 663 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
NirT 1:e8fac4061a5b 664 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 665 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
NirT 1:e8fac4061a5b 666 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
NirT 1:e8fac4061a5b 667 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 668 break;
NirT 1:e8fac4061a5b 669
NirT 1:e8fac4061a5b 670 case IO_MODE_IT_LOW_LEVEL_PU: /* Low level interrupt mode */
NirT 1:e8fac4061a5b 671 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 672 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 673 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 674 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 675 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
NirT 1:e8fac4061a5b 676 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
NirT 1:e8fac4061a5b 677 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 678 break;
NirT 1:e8fac4061a5b 679
NirT 1:e8fac4061a5b 680 case IO_MODE_IT_LOW_LEVEL_PD: /* Low level interrupt mode */
NirT 1:e8fac4061a5b 681 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 682 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 683 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 684 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
NirT 1:e8fac4061a5b 685 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
NirT 1:e8fac4061a5b 686 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_LLFE);
NirT 1:e8fac4061a5b 687 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 688 break;
NirT 1:e8fac4061a5b 689
NirT 1:e8fac4061a5b 690 case IO_MODE_IT_HIGH_LEVEL: /* High level interrupt mode */
NirT 1:e8fac4061a5b 691 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 692 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 693 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITHOUT_PULL_RESISTOR);
NirT 1:e8fac4061a5b 694 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 695 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
NirT 1:e8fac4061a5b 696 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
NirT 1:e8fac4061a5b 697 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 698 break;
NirT 1:e8fac4061a5b 699
NirT 1:e8fac4061a5b 700 case IO_MODE_IT_HIGH_LEVEL_PU: /* High level interrupt mode */
NirT 1:e8fac4061a5b 701 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 702 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 703 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 704 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_UP);
NirT 1:e8fac4061a5b 705 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
NirT 1:e8fac4061a5b 706 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
NirT 1:e8fac4061a5b 707 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 708 break;
NirT 1:e8fac4061a5b 709
NirT 1:e8fac4061a5b 710 case IO_MODE_IT_HIGH_LEVEL_PD: /* High level interrupt mode */
NirT 1:e8fac4061a5b 711 mfxstm32l152_IO_EnableIT(DeviceAddr);
NirT 1:e8fac4061a5b 712 mfxstm32l152_IO_InitPin(DeviceAddr, IO_Pin, MFXSTM32L152_GPIO_DIR_IN);
NirT 1:e8fac4061a5b 713 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_TYPE1, IO_Pin, MFXSTM32L152_GPI_WITH_PULL_RESISTOR);
NirT 1:e8fac4061a5b 714 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_PUPD1, IO_Pin, MFXSTM32L152_GPIO_PULL_DOWN);
NirT 1:e8fac4061a5b 715 mfxstm32l152_IO_SetIrqEvtMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_EVT_LEVEL);
NirT 1:e8fac4061a5b 716 mfxstm32l152_IO_SetIrqTypeMode(DeviceAddr, IO_Pin, MFXSTM32L152_IRQ_GPI_TYPE_HLRE);
NirT 1:e8fac4061a5b 717 mfxstm32l152_IO_EnablePinIT(DeviceAddr, IO_Pin); /* last to do: enable IT */
NirT 1:e8fac4061a5b 718 break;
NirT 1:e8fac4061a5b 719
NirT 1:e8fac4061a5b 720 default:
NirT 1:e8fac4061a5b 721 error_code = (uint8_t) IO_Mode;
NirT 1:e8fac4061a5b 722 break;
NirT 1:e8fac4061a5b 723 }
NirT 1:e8fac4061a5b 724
NirT 1:e8fac4061a5b 725 return error_code;
NirT 1:e8fac4061a5b 726 }
NirT 1:e8fac4061a5b 727
NirT 1:e8fac4061a5b 728 /**
NirT 1:e8fac4061a5b 729 * @brief Initialize the selected IO pin direction.
NirT 1:e8fac4061a5b 730 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 731 * @param IO_Pin: The IO pin to be configured. This parameter could be any
NirT 1:e8fac4061a5b 732 * combination of the following values:
NirT 1:e8fac4061a5b 733 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
NirT 1:e8fac4061a5b 734 * @param Direction: could be MFXSTM32L152_GPIO_DIR_IN or MFXSTM32L152_GPIO_DIR_OUT.
NirT 1:e8fac4061a5b 735 * @retval None
NirT 1:e8fac4061a5b 736 */
NirT 1:e8fac4061a5b 737 void mfxstm32l152_IO_InitPin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Direction)
NirT 1:e8fac4061a5b 738 {
NirT 1:e8fac4061a5b 739 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_DIR1, IO_Pin, Direction);
NirT 1:e8fac4061a5b 740 }
NirT 1:e8fac4061a5b 741
NirT 1:e8fac4061a5b 742 /**
NirT 1:e8fac4061a5b 743 * @brief Set the global interrupt Type.
NirT 1:e8fac4061a5b 744 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 745 * @param IO_Pin: The IO pin to be configured. This parameter could be any
NirT 1:e8fac4061a5b 746 * combination of the following values:
NirT 1:e8fac4061a5b 747 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
NirT 1:e8fac4061a5b 748 * @param Evt: Interrupt line activity type, could be one of the following values:
NirT 1:e8fac4061a5b 749 * @arg MFXSTM32L152_IRQ_GPI_EVT_LEVEL: Interrupt line is active in level model
NirT 1:e8fac4061a5b 750 * @arg MFXSTM32L152_IRQ_GPI_EVT_EDGE: Interrupt line is active in edge model
NirT 1:e8fac4061a5b 751 * @retval None
NirT 1:e8fac4061a5b 752 */
NirT 1:e8fac4061a5b 753 void mfxstm32l152_IO_SetIrqEvtMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Evt)
NirT 1:e8fac4061a5b 754 {
NirT 1:e8fac4061a5b 755 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_EVT1, IO_Pin, Evt);
NirT 1:e8fac4061a5b 756 MFX_IO_Delay(1);
NirT 1:e8fac4061a5b 757 }
NirT 1:e8fac4061a5b 758
NirT 1:e8fac4061a5b 759 /**
NirT 1:e8fac4061a5b 760 * @brief Configure the Edge for which a transition is detectable for the
NirT 1:e8fac4061a5b 761 * selected pin.
NirT 1:e8fac4061a5b 762 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 763 * @param IO_Pin: The IO pin to be configured. This parameter could be any
NirT 1:e8fac4061a5b 764 * combination of the following values:
NirT 1:e8fac4061a5b 765 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
NirT 1:e8fac4061a5b 766 * @param Evt: Interrupt line activity type, could be one of the following values:
NirT 1:e8fac4061a5b 767 * @arg MFXSTM32L152_IRQ_GPI_TYPE_LLFE: Interrupt line is active in Low Level or Falling Edge
NirT 1:e8fac4061a5b 768 * @arg MFXSTM32L152_IRQ_GPI_TYPE_HLRE: Interrupt line is active in High Level or Rising Edge
NirT 1:e8fac4061a5b 769 * @retval None
NirT 1:e8fac4061a5b 770 */
NirT 1:e8fac4061a5b 771 void mfxstm32l152_IO_SetIrqTypeMode(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t Type)
NirT 1:e8fac4061a5b 772 {
NirT 1:e8fac4061a5b 773 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_TYPE1, IO_Pin, Type);
NirT 1:e8fac4061a5b 774 MFX_IO_Delay(1);
NirT 1:e8fac4061a5b 775 }
NirT 1:e8fac4061a5b 776
NirT 1:e8fac4061a5b 777 /**
NirT 1:e8fac4061a5b 778 * @brief When GPIO is in output mode, puts the corresponding GPO in High (1) or Low (0) level.
NirT 1:e8fac4061a5b 779 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 780 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
NirT 1:e8fac4061a5b 781 * of the following values:
NirT 1:e8fac4061a5b 782 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
NirT 1:e8fac4061a5b 783 * @param PinState: The new IO pin state.
NirT 1:e8fac4061a5b 784 * @retval None
NirT 1:e8fac4061a5b 785 */
NirT 1:e8fac4061a5b 786 void mfxstm32l152_IO_WritePin(uint16_t DeviceAddr, uint32_t IO_Pin, uint8_t PinState)
NirT 1:e8fac4061a5b 787 {
NirT 1:e8fac4061a5b 788 /* Apply the bit value to the selected pin */
NirT 1:e8fac4061a5b 789 if (PinState != 0)
NirT 1:e8fac4061a5b 790 {
NirT 1:e8fac4061a5b 791 /* Set the SET register */
NirT 1:e8fac4061a5b 792 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_SET1, IO_Pin, 1);
NirT 1:e8fac4061a5b 793 }
NirT 1:e8fac4061a5b 794 else
NirT 1:e8fac4061a5b 795 {
NirT 1:e8fac4061a5b 796 /* Set the CLEAR register */
NirT 1:e8fac4061a5b 797 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_GPO_CLR1, IO_Pin, 1);
NirT 1:e8fac4061a5b 798 }
NirT 1:e8fac4061a5b 799 }
NirT 1:e8fac4061a5b 800
NirT 1:e8fac4061a5b 801 /**
NirT 1:e8fac4061a5b 802 * @brief Return the state of the selected IO pin(s).
NirT 1:e8fac4061a5b 803 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 804 * @param IO_Pin: The output pin to be set or reset. This parameter can be one
NirT 1:e8fac4061a5b 805 * of the following values:
NirT 1:e8fac4061a5b 806 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
NirT 1:e8fac4061a5b 807 * @retval IO pin(s) state.
NirT 1:e8fac4061a5b 808 */
NirT 1:e8fac4061a5b 809 uint32_t mfxstm32l152_IO_ReadPin(uint16_t DeviceAddr, uint32_t IO_Pin)
NirT 1:e8fac4061a5b 810 {
NirT 1:e8fac4061a5b 811 uint8_t tmp1;
NirT 1:e8fac4061a5b 812 uint16_t tmp2;
NirT 1:e8fac4061a5b 813 uint32_t tmp3;
NirT 1:e8fac4061a5b 814
NirT 1:e8fac4061a5b 815 tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE1);
NirT 1:e8fac4061a5b 816 tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE2);
NirT 1:e8fac4061a5b 817 tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_GPIO_STATE3);
NirT 1:e8fac4061a5b 818 tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
NirT 1:e8fac4061a5b 819
NirT 1:e8fac4061a5b 820 return(tmp3 & IO_Pin);
NirT 1:e8fac4061a5b 821 }
NirT 1:e8fac4061a5b 822
NirT 1:e8fac4061a5b 823 /**
NirT 1:e8fac4061a5b 824 * @brief Enable the global IO interrupt source.
NirT 1:e8fac4061a5b 825 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 826 * @retval None
NirT 1:e8fac4061a5b 827 */
NirT 1:e8fac4061a5b 828 void mfxstm32l152_IO_EnableIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 829 {
NirT 1:e8fac4061a5b 830 MFX_IO_ITConfig();
NirT 1:e8fac4061a5b 831
NirT 1:e8fac4061a5b 832 /* Enable global IO IT source */
NirT 1:e8fac4061a5b 833 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
NirT 1:e8fac4061a5b 834 }
NirT 1:e8fac4061a5b 835
NirT 1:e8fac4061a5b 836 /**
NirT 1:e8fac4061a5b 837 * @brief Disable the global IO interrupt source.
NirT 1:e8fac4061a5b 838 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 839 * @retval None
NirT 1:e8fac4061a5b 840 */
NirT 1:e8fac4061a5b 841 void mfxstm32l152_IO_DisableIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 842 {
NirT 1:e8fac4061a5b 843 /* Disable global IO IT source */
NirT 1:e8fac4061a5b 844 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_GPIO);
NirT 1:e8fac4061a5b 845 }
NirT 1:e8fac4061a5b 846
NirT 1:e8fac4061a5b 847 /**
NirT 1:e8fac4061a5b 848 * @brief Enable interrupt mode for the selected IO pin(s).
NirT 1:e8fac4061a5b 849 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 850 * @param IO_Pin: The IO interrupt to be enabled. This parameter could be any
NirT 1:e8fac4061a5b 851 * combination of the following values:
NirT 1:e8fac4061a5b 852 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
NirT 1:e8fac4061a5b 853 * @retval None
NirT 1:e8fac4061a5b 854 */
NirT 1:e8fac4061a5b 855 void mfxstm32l152_IO_EnablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
NirT 1:e8fac4061a5b 856 {
NirT 1:e8fac4061a5b 857 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 1);
NirT 1:e8fac4061a5b 858 }
NirT 1:e8fac4061a5b 859
NirT 1:e8fac4061a5b 860 /**
NirT 1:e8fac4061a5b 861 * @brief Disable interrupt mode for the selected IO pin(s).
NirT 1:e8fac4061a5b 862 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 863 * @param IO_Pin: The IO interrupt to be disabled. This parameter could be any
NirT 1:e8fac4061a5b 864 * combination of the following values:
NirT 1:e8fac4061a5b 865 * @arg MFXSTM32L152_GPIO_PIN_x: where x can be from 0 to 23.
NirT 1:e8fac4061a5b 866 * @retval None
NirT 1:e8fac4061a5b 867 */
NirT 1:e8fac4061a5b 868 void mfxstm32l152_IO_DisablePinIT(uint16_t DeviceAddr, uint32_t IO_Pin)
NirT 1:e8fac4061a5b 869 {
NirT 1:e8fac4061a5b 870 mfxstm32l152_reg24_setPinValue(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_SRC1, IO_Pin, 0);
NirT 1:e8fac4061a5b 871 }
NirT 1:e8fac4061a5b 872
NirT 1:e8fac4061a5b 873
NirT 1:e8fac4061a5b 874 /**
NirT 1:e8fac4061a5b 875 * @brief Check the status of the selected IO interrupt pending bit
NirT 1:e8fac4061a5b 876 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 877 * @param IO_Pin: The IO interrupt to be checked could be:
NirT 1:e8fac4061a5b 878 * @arg MFXSTM32L152_GPIO_PIN_x Where x can be from 0 to 23.
NirT 1:e8fac4061a5b 879 * @retval Status of the checked IO pin(s).
NirT 1:e8fac4061a5b 880 */
NirT 1:e8fac4061a5b 881 uint32_t mfxstm32l152_IO_ITStatus(uint16_t DeviceAddr, uint32_t IO_Pin)
NirT 1:e8fac4061a5b 882 {
NirT 1:e8fac4061a5b 883 /* Get the Interrupt status */
NirT 1:e8fac4061a5b 884 uint8_t tmp1;
NirT 1:e8fac4061a5b 885 uint16_t tmp2;
NirT 1:e8fac4061a5b 886 uint32_t tmp3;
NirT 1:e8fac4061a5b 887
NirT 1:e8fac4061a5b 888 tmp1 = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING1);
NirT 1:e8fac4061a5b 889 tmp2 = (uint16_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING2);
NirT 1:e8fac4061a5b 890 tmp3 = (uint32_t) MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_PENDING3);
NirT 1:e8fac4061a5b 891 tmp3 = tmp1 + (tmp2 << 8) + (tmp3 << 16);
NirT 1:e8fac4061a5b 892
NirT 1:e8fac4061a5b 893 return(tmp3 & IO_Pin);
NirT 1:e8fac4061a5b 894 }
NirT 1:e8fac4061a5b 895
NirT 1:e8fac4061a5b 896 /**
NirT 1:e8fac4061a5b 897 * @brief Clear the selected IO interrupt pending bit(s). It clear automatically also the general MFXSTM32L152_REG_ADR_IRQ_PENDING
NirT 1:e8fac4061a5b 898 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 899 * @param IO_Pin: the IO interrupt to be cleared, could be:
NirT 1:e8fac4061a5b 900 * @arg MFXSTM32L152_GPIO_PIN_x: Where x can be from 0 to 23.
NirT 1:e8fac4061a5b 901 * @retval None
NirT 1:e8fac4061a5b 902 */
NirT 1:e8fac4061a5b 903 void mfxstm32l152_IO_ClearIT(uint16_t DeviceAddr, uint32_t IO_Pin)
NirT 1:e8fac4061a5b 904 {
NirT 1:e8fac4061a5b 905 /* Clear the IO IT pending bit(s) by acknowledging */
NirT 1:e8fac4061a5b 906 /* it cleans automatically also the Global IRQ_GPIO */
NirT 1:e8fac4061a5b 907 /* normally this function is called under interrupt */
NirT 1:e8fac4061a5b 908 uint8_t pin_0_7, pin_8_15, pin_16_23;
NirT 1:e8fac4061a5b 909
NirT 1:e8fac4061a5b 910 pin_0_7 = IO_Pin & 0x0000ff;
NirT 1:e8fac4061a5b 911 pin_8_15 = IO_Pin >> 8;
NirT 1:e8fac4061a5b 912 pin_8_15 = pin_8_15 & 0x00ff;
NirT 1:e8fac4061a5b 913 pin_16_23 = IO_Pin >> 16;
NirT 1:e8fac4061a5b 914
NirT 1:e8fac4061a5b 915 if (pin_0_7)
NirT 1:e8fac4061a5b 916 {
NirT 1:e8fac4061a5b 917 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK1, pin_0_7);
NirT 1:e8fac4061a5b 918 }
NirT 1:e8fac4061a5b 919 if (pin_8_15)
NirT 1:e8fac4061a5b 920 {
NirT 1:e8fac4061a5b 921 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK2, pin_8_15);
NirT 1:e8fac4061a5b 922 }
NirT 1:e8fac4061a5b 923 if (pin_16_23)
NirT 1:e8fac4061a5b 924 {
NirT 1:e8fac4061a5b 925 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_IRQ_GPI_ACK3, pin_16_23);
NirT 1:e8fac4061a5b 926 }
NirT 1:e8fac4061a5b 927 }
NirT 1:e8fac4061a5b 928
NirT 1:e8fac4061a5b 929
NirT 1:e8fac4061a5b 930 /**
NirT 1:e8fac4061a5b 931 * @brief Enable the AF for aGPIO.
NirT 1:e8fac4061a5b 932 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 933 * @retval None
NirT 1:e8fac4061a5b 934 */
NirT 1:e8fac4061a5b 935 void mfxstm32l152_IO_EnableAF(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 936 {
NirT 1:e8fac4061a5b 937 uint8_t mode;
NirT 1:e8fac4061a5b 938
NirT 1:e8fac4061a5b 939 /* Get the current register value */
NirT 1:e8fac4061a5b 940 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
NirT 1:e8fac4061a5b 941
NirT 1:e8fac4061a5b 942 /* Enable ALTERNATE functions */
NirT 1:e8fac4061a5b 943 /* AGPIO[0..3] can be either IDD or GPIO */
NirT 1:e8fac4061a5b 944 /* AGPIO[4..7] can be either TS or GPIO */
NirT 1:e8fac4061a5b 945 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
NirT 1:e8fac4061a5b 946 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
NirT 1:e8fac4061a5b 947 /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
NirT 1:e8fac4061a5b 948 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
NirT 1:e8fac4061a5b 949 /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
NirT 1:e8fac4061a5b 950 mode |= MFXSTM32L152_ALTERNATE_GPIO_EN;
NirT 1:e8fac4061a5b 951
NirT 1:e8fac4061a5b 952 /* Write the new register value */
NirT 1:e8fac4061a5b 953 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
NirT 1:e8fac4061a5b 954 }
NirT 1:e8fac4061a5b 955
NirT 1:e8fac4061a5b 956 /**
NirT 1:e8fac4061a5b 957 * @brief Disable the AF for aGPIO.
NirT 1:e8fac4061a5b 958 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 959 * @retval None
NirT 1:e8fac4061a5b 960 */
NirT 1:e8fac4061a5b 961 void mfxstm32l152_IO_DisableAF(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 962 {
NirT 1:e8fac4061a5b 963 uint8_t mode;
NirT 1:e8fac4061a5b 964
NirT 1:e8fac4061a5b 965 /* Get the current register value */
NirT 1:e8fac4061a5b 966 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
NirT 1:e8fac4061a5b 967
NirT 1:e8fac4061a5b 968 /* Enable ALTERNATE functions */
NirT 1:e8fac4061a5b 969 /* AGPIO[0..3] can be either IDD or GPIO */
NirT 1:e8fac4061a5b 970 /* AGPIO[4..7] can be either TS or GPIO */
NirT 1:e8fac4061a5b 971 /* if IDD or TS are enabled no matter the value this bit GPIO are not available for those pins */
NirT 1:e8fac4061a5b 972 /* however the MFX will waste some cycles to to handle these potential GPIO (pooling, etc) */
NirT 1:e8fac4061a5b 973 /* so if IDD and TS are both active it is better to let ALTERNATE disabled (0) */
NirT 1:e8fac4061a5b 974 /* if however IDD or TS are not connected then set it on gives more GPIOs availability */
NirT 1:e8fac4061a5b 975 /* remind that AGPIO are less efficient then normal GPIO (they use pooling rather then EXTI) */
NirT 1:e8fac4061a5b 976 mode &= ~MFXSTM32L152_ALTERNATE_GPIO_EN;
NirT 1:e8fac4061a5b 977
NirT 1:e8fac4061a5b 978 /* Write the new register value */
NirT 1:e8fac4061a5b 979 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
NirT 1:e8fac4061a5b 980
NirT 1:e8fac4061a5b 981 }
NirT 1:e8fac4061a5b 982
NirT 1:e8fac4061a5b 983
NirT 1:e8fac4061a5b 984 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 985 /* --------------------- TOUCH SCREEN ------------------------------- */
NirT 1:e8fac4061a5b 986 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 987
NirT 1:e8fac4061a5b 988 /**
NirT 1:e8fac4061a5b 989 * @brief Configures the touch Screen Controller (Single point detection)
NirT 1:e8fac4061a5b 990 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 991 * @retval None.
NirT 1:e8fac4061a5b 992 */
NirT 1:e8fac4061a5b 993 void mfxstm32l152_TS_Start(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 994 {
NirT 1:e8fac4061a5b 995 uint8_t mode;
NirT 1:e8fac4061a5b 996
NirT 1:e8fac4061a5b 997 /* Get the current register value */
NirT 1:e8fac4061a5b 998 mode = MFX_IO_Read(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
NirT 1:e8fac4061a5b 999
NirT 1:e8fac4061a5b 1000 /* Set the Functionalities to be Enabled */
NirT 1:e8fac4061a5b 1001 mode |= MFXSTM32L152_TS_EN;
NirT 1:e8fac4061a5b 1002
NirT 1:e8fac4061a5b 1003 /* Set the new register value */
NirT 1:e8fac4061a5b 1004 MFX_IO_Write(DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
NirT 1:e8fac4061a5b 1005
NirT 1:e8fac4061a5b 1006 /* Wait for 2 ms */
NirT 1:e8fac4061a5b 1007 MFX_IO_Delay(2);
NirT 1:e8fac4061a5b 1008
NirT 1:e8fac4061a5b 1009 /* Select 2 nF filter capacitor */
NirT 1:e8fac4061a5b 1010 /* Configuration:
NirT 1:e8fac4061a5b 1011 - Touch average control : 4 samples
NirT 1:e8fac4061a5b 1012 - Touch delay time : 500 uS
NirT 1:e8fac4061a5b 1013 - Panel driver setting time: 500 uS
NirT 1:e8fac4061a5b 1014 */
NirT 1:e8fac4061a5b 1015 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_SETTLING, 0x32);
NirT 1:e8fac4061a5b 1016 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TOUCH_DET_DELAY, 0x5);
NirT 1:e8fac4061a5b 1017 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_AVE, 0x04);
NirT 1:e8fac4061a5b 1018
NirT 1:e8fac4061a5b 1019 /* Configure the Touch FIFO threshold: single point reading */
NirT 1:e8fac4061a5b 1020 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, 0x01);
NirT 1:e8fac4061a5b 1021
NirT 1:e8fac4061a5b 1022 /* Clear the FIFO memory content. */
NirT 1:e8fac4061a5b 1023 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
NirT 1:e8fac4061a5b 1024
NirT 1:e8fac4061a5b 1025 /* Touch screen control configuration :
NirT 1:e8fac4061a5b 1026 - No window tracking index
NirT 1:e8fac4061a5b 1027 */
NirT 1:e8fac4061a5b 1028 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_TRACK, 0x00);
NirT 1:e8fac4061a5b 1029
NirT 1:e8fac4061a5b 1030
NirT 1:e8fac4061a5b 1031 /* Clear all the IT status pending bits if any */
NirT 1:e8fac4061a5b 1032 mfxstm32l152_IO_ClearIT(DeviceAddr, 0xFFFFFF);
NirT 1:e8fac4061a5b 1033
NirT 1:e8fac4061a5b 1034 /* Wait for 1 ms delay */
NirT 1:e8fac4061a5b 1035 MFX_IO_Delay(1);
NirT 1:e8fac4061a5b 1036 }
NirT 1:e8fac4061a5b 1037
NirT 1:e8fac4061a5b 1038 /**
NirT 1:e8fac4061a5b 1039 * @brief Return if there is touch detected or not.
NirT 1:e8fac4061a5b 1040 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1041 * @retval Touch detected state.
NirT 1:e8fac4061a5b 1042 */
NirT 1:e8fac4061a5b 1043 uint8_t mfxstm32l152_TS_DetectTouch(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1044 {
NirT 1:e8fac4061a5b 1045 uint8_t state;
NirT 1:e8fac4061a5b 1046 uint8_t ret = 0;
NirT 1:e8fac4061a5b 1047
NirT 1:e8fac4061a5b 1048 state = MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_STA);
NirT 1:e8fac4061a5b 1049 state = ((state & (uint8_t)MFXSTM32L152_TS_CTRL_STATUS) == (uint8_t)MFXSTM32L152_TS_CTRL_STATUS);
NirT 1:e8fac4061a5b 1050
NirT 1:e8fac4061a5b 1051 if(state > 0)
NirT 1:e8fac4061a5b 1052 {
NirT 1:e8fac4061a5b 1053 if(MFX_IO_Read(DeviceAddr, MFXSTM32L152_TS_FIFO_LEVEL) > 0)
NirT 1:e8fac4061a5b 1054 {
NirT 1:e8fac4061a5b 1055 ret = 1;
NirT 1:e8fac4061a5b 1056 }
NirT 1:e8fac4061a5b 1057 }
NirT 1:e8fac4061a5b 1058
NirT 1:e8fac4061a5b 1059 return ret;
NirT 1:e8fac4061a5b 1060 }
NirT 1:e8fac4061a5b 1061
NirT 1:e8fac4061a5b 1062 /**
NirT 1:e8fac4061a5b 1063 * @brief Get the touch screen X and Y positions values
NirT 1:e8fac4061a5b 1064 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1065 * @param X: Pointer to X position value
NirT 1:e8fac4061a5b 1066 * @param Y: Pointer to Y position value
NirT 1:e8fac4061a5b 1067 * @retval None.
NirT 1:e8fac4061a5b 1068 */
NirT 1:e8fac4061a5b 1069 void mfxstm32l152_TS_GetXY(uint16_t DeviceAddr, uint16_t *X, uint16_t *Y)
NirT 1:e8fac4061a5b 1070 {
NirT 1:e8fac4061a5b 1071 uint8_t data_xy[3];
NirT 1:e8fac4061a5b 1072
NirT 1:e8fac4061a5b 1073 MFX_IO_ReadMultiple(DeviceAddr, MFXSTM32L152_TS_XY_DATA, data_xy, sizeof(data_xy)) ;
NirT 1:e8fac4061a5b 1074
NirT 1:e8fac4061a5b 1075 /* Calculate positions values */
NirT 1:e8fac4061a5b 1076 *X = (data_xy[1]<<4) + (data_xy[0]>>4);
NirT 1:e8fac4061a5b 1077 *Y = (data_xy[2]<<4) + (data_xy[0]&4);
NirT 1:e8fac4061a5b 1078
NirT 1:e8fac4061a5b 1079 /* Reset the FIFO memory content. */
NirT 1:e8fac4061a5b 1080 MFX_IO_Write(DeviceAddr, MFXSTM32L152_TS_FIFO_TH, MFXSTM32L152_TS_CLEAR_FIFO);
NirT 1:e8fac4061a5b 1081 }
NirT 1:e8fac4061a5b 1082
NirT 1:e8fac4061a5b 1083 /**
NirT 1:e8fac4061a5b 1084 * @brief Configure the selected source to generate a global interrupt or not
NirT 1:e8fac4061a5b 1085 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1086 * @retval None
NirT 1:e8fac4061a5b 1087 */
NirT 1:e8fac4061a5b 1088 void mfxstm32l152_TS_EnableIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1089 {
NirT 1:e8fac4061a5b 1090 MFX_IO_ITConfig();
NirT 1:e8fac4061a5b 1091
NirT 1:e8fac4061a5b 1092 /* Enable global TS IT source */
NirT 1:e8fac4061a5b 1093 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
NirT 1:e8fac4061a5b 1094 }
NirT 1:e8fac4061a5b 1095
NirT 1:e8fac4061a5b 1096 /**
NirT 1:e8fac4061a5b 1097 * @brief Configure the selected source to generate a global interrupt or not
NirT 1:e8fac4061a5b 1098 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1099 * @retval None
NirT 1:e8fac4061a5b 1100 */
NirT 1:e8fac4061a5b 1101 void mfxstm32l152_TS_DisableIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1102 {
NirT 1:e8fac4061a5b 1103 /* Disable global TS IT source */
NirT 1:e8fac4061a5b 1104 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_TS_DET);
NirT 1:e8fac4061a5b 1105 }
NirT 1:e8fac4061a5b 1106
NirT 1:e8fac4061a5b 1107 /**
NirT 1:e8fac4061a5b 1108 * @brief Configure the selected source to generate a global interrupt or not
NirT 1:e8fac4061a5b 1109 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1110 * @retval TS interrupts status
NirT 1:e8fac4061a5b 1111 */
NirT 1:e8fac4061a5b 1112 uint8_t mfxstm32l152_TS_ITStatus(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1113 {
NirT 1:e8fac4061a5b 1114 /* Return TS interrupts status */
NirT 1:e8fac4061a5b 1115 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_TS));
NirT 1:e8fac4061a5b 1116 }
NirT 1:e8fac4061a5b 1117
NirT 1:e8fac4061a5b 1118 /**
NirT 1:e8fac4061a5b 1119 * @brief Configure the selected source to generate a global interrupt or not
NirT 1:e8fac4061a5b 1120 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1121 * @retval None
NirT 1:e8fac4061a5b 1122 */
NirT 1:e8fac4061a5b 1123 void mfxstm32l152_TS_ClearIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1124 {
NirT 1:e8fac4061a5b 1125 /* Clear the global TS IT source */
NirT 1:e8fac4061a5b 1126 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_TS);
NirT 1:e8fac4061a5b 1127 }
NirT 1:e8fac4061a5b 1128
NirT 1:e8fac4061a5b 1129 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 1130 /* --------------------- IDD MEASUREMENT ---------------------------- */
NirT 1:e8fac4061a5b 1131 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 1132
NirT 1:e8fac4061a5b 1133 /**
NirT 1:e8fac4061a5b 1134 * @brief Launch IDD current measurement
NirT 1:e8fac4061a5b 1135 * @param DeviceAddr: Device address on communication Bus
NirT 1:e8fac4061a5b 1136 * @retval None.
NirT 1:e8fac4061a5b 1137 */
NirT 1:e8fac4061a5b 1138 void mfxstm32l152_IDD_Start(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1139 {
NirT 1:e8fac4061a5b 1140 uint8_t mode = 0;
NirT 1:e8fac4061a5b 1141
NirT 1:e8fac4061a5b 1142 /* Get the current register value */
NirT 1:e8fac4061a5b 1143 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
NirT 1:e8fac4061a5b 1144
NirT 1:e8fac4061a5b 1145 /* Set the Functionalities to be enabled */
NirT 1:e8fac4061a5b 1146 mode |= MFXSTM32L152_IDD_CTRL_REQ;
NirT 1:e8fac4061a5b 1147
NirT 1:e8fac4061a5b 1148 /* Start measurement campaign */
NirT 1:e8fac4061a5b 1149 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
NirT 1:e8fac4061a5b 1150 }
NirT 1:e8fac4061a5b 1151
NirT 1:e8fac4061a5b 1152 /**
NirT 1:e8fac4061a5b 1153 * @brief Configures the IDD current measurement
NirT 1:e8fac4061a5b 1154 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1155 * @param MfxIddConfig: Parameters depending on hardware config.
NirT 1:e8fac4061a5b 1156 * @retval None
NirT 1:e8fac4061a5b 1157 */
NirT 1:e8fac4061a5b 1158 void mfxstm32l152_IDD_Config(uint16_t DeviceAddr, IDD_ConfigTypeDef MfxIddConfig)
NirT 1:e8fac4061a5b 1159 {
NirT 1:e8fac4061a5b 1160 uint8_t value = 0;
NirT 1:e8fac4061a5b 1161 uint8_t mode = 0;
NirT 1:e8fac4061a5b 1162
NirT 1:e8fac4061a5b 1163 /* Get the current register value */
NirT 1:e8fac4061a5b 1164 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL);
NirT 1:e8fac4061a5b 1165
NirT 1:e8fac4061a5b 1166 if((mode & MFXSTM32L152_IDD_EN) != MFXSTM32L152_IDD_EN)
NirT 1:e8fac4061a5b 1167 {
NirT 1:e8fac4061a5b 1168 /* Set the Functionalities to be enabled */
NirT 1:e8fac4061a5b 1169 mode |= MFXSTM32L152_IDD_EN;
NirT 1:e8fac4061a5b 1170
NirT 1:e8fac4061a5b 1171 /* Set the new register value */
NirT 1:e8fac4061a5b 1172 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_SYS_CTRL, mode);
NirT 1:e8fac4061a5b 1173 }
NirT 1:e8fac4061a5b 1174
NirT 1:e8fac4061a5b 1175 /* Control register setting: number of shunts */
NirT 1:e8fac4061a5b 1176 value = ((MfxIddConfig.ShuntNbUsed << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
NirT 1:e8fac4061a5b 1177 value |= (MfxIddConfig.VrefMeasurement & MFXSTM32L152_IDD_CTRL_VREF_DIS);
NirT 1:e8fac4061a5b 1178 value |= (MfxIddConfig.Calibration & MFXSTM32L152_IDD_CTRL_CAL_DIS);
NirT 1:e8fac4061a5b 1179 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, value);
NirT 1:e8fac4061a5b 1180
NirT 1:e8fac4061a5b 1181 /* Idd pre delay configuration: unit and value*/
NirT 1:e8fac4061a5b 1182 value = (MfxIddConfig.PreDelayUnit & MFXSTM32L152_IDD_PREDELAY_UNIT) |
NirT 1:e8fac4061a5b 1183 (MfxIddConfig.PreDelayValue & MFXSTM32L152_IDD_PREDELAY_VALUE);
NirT 1:e8fac4061a5b 1184 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_PRE_DELAY, value);
NirT 1:e8fac4061a5b 1185
NirT 1:e8fac4061a5b 1186 /* Shunt 0 register value: MSB then LSB */
NirT 1:e8fac4061a5b 1187 value = (uint8_t) (MfxIddConfig.Shunt0Value >> 8);
NirT 1:e8fac4061a5b 1188 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_MSB, value);
NirT 1:e8fac4061a5b 1189 value = (uint8_t) (MfxIddConfig.Shunt0Value);
NirT 1:e8fac4061a5b 1190 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT0_LSB, value);
NirT 1:e8fac4061a5b 1191
NirT 1:e8fac4061a5b 1192 /* Shunt 1 register value: MSB then LSB */
NirT 1:e8fac4061a5b 1193 value = (uint8_t) (MfxIddConfig.Shunt1Value >> 8);
NirT 1:e8fac4061a5b 1194 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_MSB, value);
NirT 1:e8fac4061a5b 1195 value = (uint8_t) (MfxIddConfig.Shunt1Value);
NirT 1:e8fac4061a5b 1196 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT1_LSB, value);
NirT 1:e8fac4061a5b 1197
NirT 1:e8fac4061a5b 1198 /* Shunt 2 register value: MSB then LSB */
NirT 1:e8fac4061a5b 1199 value = (uint8_t) (MfxIddConfig.Shunt2Value >> 8);
NirT 1:e8fac4061a5b 1200 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_MSB, value);
NirT 1:e8fac4061a5b 1201 value = (uint8_t) (MfxIddConfig.Shunt2Value);
NirT 1:e8fac4061a5b 1202 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT2_LSB, value);
NirT 1:e8fac4061a5b 1203
NirT 1:e8fac4061a5b 1204 /* Shunt 3 register value: MSB then LSB */
NirT 1:e8fac4061a5b 1205 value = (uint8_t) (MfxIddConfig.Shunt3Value >> 8);
NirT 1:e8fac4061a5b 1206 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_MSB, value);
NirT 1:e8fac4061a5b 1207 value = (uint8_t) (MfxIddConfig.Shunt3Value);
NirT 1:e8fac4061a5b 1208 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT3_LSB, value);
NirT 1:e8fac4061a5b 1209
NirT 1:e8fac4061a5b 1210 /* Shunt 4 register value: MSB then LSB */
NirT 1:e8fac4061a5b 1211 value = (uint8_t) (MfxIddConfig.Shunt4Value >> 8);
NirT 1:e8fac4061a5b 1212 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_MSB, value);
NirT 1:e8fac4061a5b 1213 value = (uint8_t) (MfxIddConfig.Shunt4Value);
NirT 1:e8fac4061a5b 1214 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT4_LSB, value);
NirT 1:e8fac4061a5b 1215
NirT 1:e8fac4061a5b 1216 /* Shunt 0 stabilization delay */
NirT 1:e8fac4061a5b 1217 value = MfxIddConfig.Shunt0StabDelay;
NirT 1:e8fac4061a5b 1218 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH0_STABILIZATION, value);
NirT 1:e8fac4061a5b 1219
NirT 1:e8fac4061a5b 1220 /* Shunt 1 stabilization delay */
NirT 1:e8fac4061a5b 1221 value = MfxIddConfig.Shunt1StabDelay;
NirT 1:e8fac4061a5b 1222 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH1_STABILIZATION, value);
NirT 1:e8fac4061a5b 1223
NirT 1:e8fac4061a5b 1224 /* Shunt 2 stabilization delay */
NirT 1:e8fac4061a5b 1225 value = MfxIddConfig.Shunt2StabDelay;
NirT 1:e8fac4061a5b 1226 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH2_STABILIZATION, value);
NirT 1:e8fac4061a5b 1227
NirT 1:e8fac4061a5b 1228 /* Shunt 3 stabilization delay */
NirT 1:e8fac4061a5b 1229 value = MfxIddConfig.Shunt3StabDelay;
NirT 1:e8fac4061a5b 1230 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH3_STABILIZATION, value);
NirT 1:e8fac4061a5b 1231
NirT 1:e8fac4061a5b 1232 /* Shunt 4 stabilization delay */
NirT 1:e8fac4061a5b 1233 value = MfxIddConfig.Shunt4StabDelay;
NirT 1:e8fac4061a5b 1234 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SH4_STABILIZATION, value);
NirT 1:e8fac4061a5b 1235
NirT 1:e8fac4061a5b 1236 /* Idd ampli gain value: MSB then LSB */
NirT 1:e8fac4061a5b 1237 value = (uint8_t) (MfxIddConfig.AmpliGain >> 8);
NirT 1:e8fac4061a5b 1238 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_MSB, value);
NirT 1:e8fac4061a5b 1239 value = (uint8_t) (MfxIddConfig.AmpliGain);
NirT 1:e8fac4061a5b 1240 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_GAIN_LSB, value);
NirT 1:e8fac4061a5b 1241
NirT 1:e8fac4061a5b 1242 /* Idd VDD min value: MSB then LSB */
NirT 1:e8fac4061a5b 1243 value = (uint8_t) (MfxIddConfig.VddMin >> 8);
NirT 1:e8fac4061a5b 1244 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_MSB, value);
NirT 1:e8fac4061a5b 1245 value = (uint8_t) (MfxIddConfig.VddMin);
NirT 1:e8fac4061a5b 1246 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VDD_MIN_LSB, value);
NirT 1:e8fac4061a5b 1247
NirT 1:e8fac4061a5b 1248 /* Idd number of measurements */
NirT 1:e8fac4061a5b 1249 value = MfxIddConfig.MeasureNb;
NirT 1:e8fac4061a5b 1250 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_NBR_OF_MEAS, value);
NirT 1:e8fac4061a5b 1251
NirT 1:e8fac4061a5b 1252 /* Idd delta delay configuration: unit and value */
NirT 1:e8fac4061a5b 1253 value = (MfxIddConfig.DeltaDelayUnit & MFXSTM32L152_IDD_DELTADELAY_UNIT) |
NirT 1:e8fac4061a5b 1254 (MfxIddConfig.DeltaDelayValue & MFXSTM32L152_IDD_DELTADELAY_VALUE);
NirT 1:e8fac4061a5b 1255 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_MEAS_DELTA_DELAY, value);
NirT 1:e8fac4061a5b 1256
NirT 1:e8fac4061a5b 1257 /* Idd number of shut on board */
NirT 1:e8fac4061a5b 1258 value = MfxIddConfig.ShuntNbOnBoard;
NirT 1:e8fac4061a5b 1259 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNTS_ON_BOARD, value);
NirT 1:e8fac4061a5b 1260 }
NirT 1:e8fac4061a5b 1261
NirT 1:e8fac4061a5b 1262 /**
NirT 1:e8fac4061a5b 1263 * @brief This function allows to modify number of shunt used for a measurement
NirT 1:e8fac4061a5b 1264 * @param DeviceAddr: Device address on communication Bus
NirT 1:e8fac4061a5b 1265 * @retval None.
NirT 1:e8fac4061a5b 1266 */
NirT 1:e8fac4061a5b 1267 void mfxstm32l152_IDD_ConfigShuntNbLimit(uint16_t DeviceAddr, uint8_t ShuntNbLimit)
NirT 1:e8fac4061a5b 1268 {
NirT 1:e8fac4061a5b 1269 uint8_t mode = 0;
NirT 1:e8fac4061a5b 1270
NirT 1:e8fac4061a5b 1271 /* Get the current register value */
NirT 1:e8fac4061a5b 1272 mode = MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL);
NirT 1:e8fac4061a5b 1273
NirT 1:e8fac4061a5b 1274 /* Clear number of shunt limit */
NirT 1:e8fac4061a5b 1275 mode &= ~(MFXSTM32L152_IDD_CTRL_SHUNT_NB);
NirT 1:e8fac4061a5b 1276
NirT 1:e8fac4061a5b 1277 /* Clear number of shunt limit */
NirT 1:e8fac4061a5b 1278 mode |= ((ShuntNbLimit << 1) & MFXSTM32L152_IDD_CTRL_SHUNT_NB);
NirT 1:e8fac4061a5b 1279
NirT 1:e8fac4061a5b 1280 /* Write noewx desired limit */
NirT 1:e8fac4061a5b 1281 MFX_IO_Write((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_CTRL, mode);
NirT 1:e8fac4061a5b 1282 }
NirT 1:e8fac4061a5b 1283
NirT 1:e8fac4061a5b 1284 /**
NirT 1:e8fac4061a5b 1285 * @brief Get Idd current value
NirT 1:e8fac4061a5b 1286 * @param DeviceAddr: Device address on communication Bus
NirT 1:e8fac4061a5b 1287 * @param ReadValue: Pointer on value to be read
NirT 1:e8fac4061a5b 1288 * @retval Idd value in 10 nA.
NirT 1:e8fac4061a5b 1289 */
NirT 1:e8fac4061a5b 1290 void mfxstm32l152_IDD_GetValue(uint16_t DeviceAddr, uint32_t *ReadValue)
NirT 1:e8fac4061a5b 1291 {
NirT 1:e8fac4061a5b 1292 uint8_t data[3];
NirT 1:e8fac4061a5b 1293
NirT 1:e8fac4061a5b 1294 MFX_IO_ReadMultiple((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_VALUE_MSB, data, sizeof(data)) ;
NirT 1:e8fac4061a5b 1295
NirT 1:e8fac4061a5b 1296 /* Recompose Idd current value */
NirT 1:e8fac4061a5b 1297 *ReadValue = (data[0] << 16) | (data[1] << 8) | data[2];
NirT 1:e8fac4061a5b 1298
NirT 1:e8fac4061a5b 1299 }
NirT 1:e8fac4061a5b 1300
NirT 1:e8fac4061a5b 1301 /**
NirT 1:e8fac4061a5b 1302 * @brief Get Last shunt used for measurement
NirT 1:e8fac4061a5b 1303 * @param DeviceAddr: Device address on communication Bus
NirT 1:e8fac4061a5b 1304 * @retval Last shunt used
NirT 1:e8fac4061a5b 1305 */
NirT 1:e8fac4061a5b 1306 uint8_t mfxstm32l152_IDD_GetShuntUsed(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1307 {
NirT 1:e8fac4061a5b 1308 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_IDD_SHUNT_USED));
NirT 1:e8fac4061a5b 1309 }
NirT 1:e8fac4061a5b 1310
NirT 1:e8fac4061a5b 1311 /**
NirT 1:e8fac4061a5b 1312 * @brief Configure mfx to enable Idd interrupt
NirT 1:e8fac4061a5b 1313 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1314 * @retval None
NirT 1:e8fac4061a5b 1315 */
NirT 1:e8fac4061a5b 1316 void mfxstm32l152_IDD_EnableIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1317 {
NirT 1:e8fac4061a5b 1318 MFX_IO_ITConfig();
NirT 1:e8fac4061a5b 1319
NirT 1:e8fac4061a5b 1320 /* Enable global IDD interrupt source */
NirT 1:e8fac4061a5b 1321 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
NirT 1:e8fac4061a5b 1322 }
NirT 1:e8fac4061a5b 1323
NirT 1:e8fac4061a5b 1324 /**
NirT 1:e8fac4061a5b 1325 * @brief Clear Idd global interrupt
NirT 1:e8fac4061a5b 1326 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1327 * @retval None
NirT 1:e8fac4061a5b 1328 */
NirT 1:e8fac4061a5b 1329 void mfxstm32l152_IDD_ClearIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1330 {
NirT 1:e8fac4061a5b 1331 /* Clear the global IDD interrupt source */
NirT 1:e8fac4061a5b 1332 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_IDD);
NirT 1:e8fac4061a5b 1333 }
NirT 1:e8fac4061a5b 1334
NirT 1:e8fac4061a5b 1335 /**
NirT 1:e8fac4061a5b 1336 * @brief get Idd interrupt status
NirT 1:e8fac4061a5b 1337 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1338 * @retval IDD interrupts status
NirT 1:e8fac4061a5b 1339 */
NirT 1:e8fac4061a5b 1340 uint8_t mfxstm32l152_IDD_GetITStatus(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1341 {
NirT 1:e8fac4061a5b 1342 /* Return IDD interrupt status */
NirT 1:e8fac4061a5b 1343 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_IDD));
NirT 1:e8fac4061a5b 1344 }
NirT 1:e8fac4061a5b 1345
NirT 1:e8fac4061a5b 1346 /**
NirT 1:e8fac4061a5b 1347 * @brief disable Idd interrupt
NirT 1:e8fac4061a5b 1348 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1349 * @retval None.
NirT 1:e8fac4061a5b 1350 */
NirT 1:e8fac4061a5b 1351 void mfxstm32l152_IDD_DisableIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1352 {
NirT 1:e8fac4061a5b 1353 /* Disable global IDD interrupt source */
NirT 1:e8fac4061a5b 1354 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_IDD);
NirT 1:e8fac4061a5b 1355 }
NirT 1:e8fac4061a5b 1356
NirT 1:e8fac4061a5b 1357
NirT 1:e8fac4061a5b 1358 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 1359 /* --------------------- ERROR MANAGEMENT --------------------------- */
NirT 1:e8fac4061a5b 1360 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 1361
NirT 1:e8fac4061a5b 1362 /**
NirT 1:e8fac4061a5b 1363 * @brief Read Error Source.
NirT 1:e8fac4061a5b 1364 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1365 * @retval Error message code with error source
NirT 1:e8fac4061a5b 1366 */
NirT 1:e8fac4061a5b 1367 uint8_t mfxstm32l152_Error_ReadSrc(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1368 {
NirT 1:e8fac4061a5b 1369 /* Get the current source register value */
NirT 1:e8fac4061a5b 1370 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_SRC));
NirT 1:e8fac4061a5b 1371 }
NirT 1:e8fac4061a5b 1372
NirT 1:e8fac4061a5b 1373 /**
NirT 1:e8fac4061a5b 1374 * @brief Read Error Message
NirT 1:e8fac4061a5b 1375 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1376 * @retval Error message code with error source
NirT 1:e8fac4061a5b 1377 */
NirT 1:e8fac4061a5b 1378 uint8_t mfxstm32l152_Error_ReadMsg(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1379 {
NirT 1:e8fac4061a5b 1380 /* Get the current message register value */
NirT 1:e8fac4061a5b 1381 return(MFX_IO_Read((uint8_t) DeviceAddr, MFXSTM32L152_REG_ADR_ERROR_MSG));
NirT 1:e8fac4061a5b 1382 }
NirT 1:e8fac4061a5b 1383
NirT 1:e8fac4061a5b 1384 /**
NirT 1:e8fac4061a5b 1385 * @brief Enable Error global interrupt
NirT 1:e8fac4061a5b 1386 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1387 * @retval None
NirT 1:e8fac4061a5b 1388 */
NirT 1:e8fac4061a5b 1389
NirT 1:e8fac4061a5b 1390 void mfxstm32l152_Error_EnableIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1391 {
NirT 1:e8fac4061a5b 1392 MFX_IO_ITConfig();
NirT 1:e8fac4061a5b 1393
NirT 1:e8fac4061a5b 1394 /* Enable global Error interrupt source */
NirT 1:e8fac4061a5b 1395 mfxstm32l152_EnableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
NirT 1:e8fac4061a5b 1396 }
NirT 1:e8fac4061a5b 1397
NirT 1:e8fac4061a5b 1398 /**
NirT 1:e8fac4061a5b 1399 * @brief Clear Error global interrupt
NirT 1:e8fac4061a5b 1400 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1401 * @retval None
NirT 1:e8fac4061a5b 1402 */
NirT 1:e8fac4061a5b 1403 void mfxstm32l152_Error_ClearIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1404 {
NirT 1:e8fac4061a5b 1405 /* Clear the global Error interrupt source */
NirT 1:e8fac4061a5b 1406 mfxstm32l152_ClearGlobalIT(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
NirT 1:e8fac4061a5b 1407 }
NirT 1:e8fac4061a5b 1408
NirT 1:e8fac4061a5b 1409 /**
NirT 1:e8fac4061a5b 1410 * @brief get Error interrupt status
NirT 1:e8fac4061a5b 1411 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1412 * @retval Error interrupts status
NirT 1:e8fac4061a5b 1413 */
NirT 1:e8fac4061a5b 1414 uint8_t mfxstm32l152_Error_GetITStatus(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1415 {
NirT 1:e8fac4061a5b 1416 /* Return Error interrupt status */
NirT 1:e8fac4061a5b 1417 return(mfxstm32l152_GlobalITStatus(DeviceAddr, MFXSTM32L152_IRQ_ERROR));
NirT 1:e8fac4061a5b 1418 }
NirT 1:e8fac4061a5b 1419
NirT 1:e8fac4061a5b 1420 /**
NirT 1:e8fac4061a5b 1421 * @brief disable Error interrupt
NirT 1:e8fac4061a5b 1422 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1423 * @retval None.
NirT 1:e8fac4061a5b 1424 */
NirT 1:e8fac4061a5b 1425 void mfxstm32l152_Error_DisableIT(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1426 {
NirT 1:e8fac4061a5b 1427 /* Disable global Error interrupt source */
NirT 1:e8fac4061a5b 1428 mfxstm32l152_DisableITSource(DeviceAddr, MFXSTM32L152_IRQ_ERROR);
NirT 1:e8fac4061a5b 1429 }
NirT 1:e8fac4061a5b 1430
NirT 1:e8fac4061a5b 1431 /**
NirT 1:e8fac4061a5b 1432 * @brief FOR DEBUG ONLY
NirT 1:e8fac4061a5b 1433 */
NirT 1:e8fac4061a5b 1434 uint8_t mfxstm32l152_ReadReg(uint16_t DeviceAddr, uint8_t RegAddr)
NirT 1:e8fac4061a5b 1435 {
NirT 1:e8fac4061a5b 1436 /* Get the current register value */
NirT 1:e8fac4061a5b 1437 return(MFX_IO_Read((uint8_t) DeviceAddr, RegAddr));
NirT 1:e8fac4061a5b 1438 }
NirT 1:e8fac4061a5b 1439
NirT 1:e8fac4061a5b 1440 void mfxstm32l152_WriteReg(uint16_t DeviceAddr, uint8_t RegAddr, uint8_t Value)
NirT 1:e8fac4061a5b 1441 {
NirT 1:e8fac4061a5b 1442 /* set the current register value */
NirT 1:e8fac4061a5b 1443 MFX_IO_Write((uint8_t) DeviceAddr, RegAddr, Value);
NirT 1:e8fac4061a5b 1444 }
NirT 1:e8fac4061a5b 1445
NirT 1:e8fac4061a5b 1446 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 1447 /* ----------------------- Private functions ------------------------ */
NirT 1:e8fac4061a5b 1448 /* ------------------------------------------------------------------ */
NirT 1:e8fac4061a5b 1449 /**
NirT 1:e8fac4061a5b 1450 * @brief Check if the device instance of the selected address is already registered
NirT 1:e8fac4061a5b 1451 * and return its index
NirT 1:e8fac4061a5b 1452 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1453 * @retval Index of the device instance if registered, 0xFF if not.
NirT 1:e8fac4061a5b 1454 */
NirT 1:e8fac4061a5b 1455 static uint8_t mfxstm32l152_GetInstance(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1456 {
NirT 1:e8fac4061a5b 1457 uint8_t idx = 0;
NirT 1:e8fac4061a5b 1458
NirT 1:e8fac4061a5b 1459 /* Check all the registered instances */
NirT 1:e8fac4061a5b 1460 for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
NirT 1:e8fac4061a5b 1461 {
NirT 1:e8fac4061a5b 1462 if(mfxstm32l152[idx] == DeviceAddr)
NirT 1:e8fac4061a5b 1463 {
NirT 1:e8fac4061a5b 1464 return idx;
NirT 1:e8fac4061a5b 1465 }
NirT 1:e8fac4061a5b 1466 }
NirT 1:e8fac4061a5b 1467
NirT 1:e8fac4061a5b 1468 return 0xFF;
NirT 1:e8fac4061a5b 1469 }
NirT 1:e8fac4061a5b 1470
NirT 1:e8fac4061a5b 1471 /**
NirT 1:e8fac4061a5b 1472 * @brief Release registered device instance
NirT 1:e8fac4061a5b 1473 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1474 * @retval Index of released device instance, 0xFF if not.
NirT 1:e8fac4061a5b 1475 */
NirT 1:e8fac4061a5b 1476 static uint8_t mfxstm32l152_ReleaseInstance(uint16_t DeviceAddr)
NirT 1:e8fac4061a5b 1477 {
NirT 1:e8fac4061a5b 1478 uint8_t idx = 0;
NirT 1:e8fac4061a5b 1479
NirT 1:e8fac4061a5b 1480 /* Check for all the registered instances */
NirT 1:e8fac4061a5b 1481 for(idx = 0; idx < MFXSTM32L152_MAX_INSTANCE ; idx ++)
NirT 1:e8fac4061a5b 1482 {
NirT 1:e8fac4061a5b 1483 if(mfxstm32l152[idx] == DeviceAddr)
NirT 1:e8fac4061a5b 1484 {
NirT 1:e8fac4061a5b 1485 mfxstm32l152[idx] = 0;
NirT 1:e8fac4061a5b 1486 return idx;
NirT 1:e8fac4061a5b 1487 }
NirT 1:e8fac4061a5b 1488 }
NirT 1:e8fac4061a5b 1489 return 0xFF;
NirT 1:e8fac4061a5b 1490 }
NirT 1:e8fac4061a5b 1491
NirT 1:e8fac4061a5b 1492 /**
NirT 1:e8fac4061a5b 1493 * @brief Internal routine
NirT 1:e8fac4061a5b 1494 * @param DeviceAddr: Device address on communication Bus.
NirT 1:e8fac4061a5b 1495 * @param RegisterAddr: Register Address
NirT 1:e8fac4061a5b 1496 * @param PinPosition: Pin [0:23]
NirT 1:e8fac4061a5b 1497 * @param PinValue: 0/1
NirT 1:e8fac4061a5b 1498 * @retval None
NirT 1:e8fac4061a5b 1499 */
NirT 1:e8fac4061a5b 1500 void mfxstm32l152_reg24_setPinValue(uint16_t DeviceAddr, uint8_t RegisterAddr, uint32_t PinPosition, uint8_t PinValue )
NirT 1:e8fac4061a5b 1501 {
NirT 1:e8fac4061a5b 1502 uint8_t tmp = 0;
NirT 1:e8fac4061a5b 1503 uint8_t pin_0_7, pin_8_15, pin_16_23;
NirT 1:e8fac4061a5b 1504
NirT 1:e8fac4061a5b 1505 pin_0_7 = PinPosition & 0x0000ff;
NirT 1:e8fac4061a5b 1506 pin_8_15 = PinPosition >> 8;
NirT 1:e8fac4061a5b 1507 pin_8_15 = pin_8_15 & 0x00ff;
NirT 1:e8fac4061a5b 1508 pin_16_23 = PinPosition >> 16;
NirT 1:e8fac4061a5b 1509
NirT 1:e8fac4061a5b 1510 if (pin_0_7)
NirT 1:e8fac4061a5b 1511 {
NirT 1:e8fac4061a5b 1512 /* Get the current register value */
NirT 1:e8fac4061a5b 1513 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr);
NirT 1:e8fac4061a5b 1514
NirT 1:e8fac4061a5b 1515 /* Set the selected pin direction */
NirT 1:e8fac4061a5b 1516 if (PinValue != 0)
NirT 1:e8fac4061a5b 1517 {
NirT 1:e8fac4061a5b 1518 tmp |= (uint8_t)pin_0_7;
NirT 1:e8fac4061a5b 1519 }
NirT 1:e8fac4061a5b 1520 else
NirT 1:e8fac4061a5b 1521 {
NirT 1:e8fac4061a5b 1522 tmp &= ~(uint8_t)pin_0_7;
NirT 1:e8fac4061a5b 1523 }
NirT 1:e8fac4061a5b 1524
NirT 1:e8fac4061a5b 1525 /* Set the new register value */
NirT 1:e8fac4061a5b 1526 MFX_IO_Write(DeviceAddr, RegisterAddr, tmp);
NirT 1:e8fac4061a5b 1527 }
NirT 1:e8fac4061a5b 1528
NirT 1:e8fac4061a5b 1529 if (pin_8_15)
NirT 1:e8fac4061a5b 1530 {
NirT 1:e8fac4061a5b 1531 /* Get the current register value */
NirT 1:e8fac4061a5b 1532 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+1);
NirT 1:e8fac4061a5b 1533
NirT 1:e8fac4061a5b 1534 /* Set the selected pin direction */
NirT 1:e8fac4061a5b 1535 if (PinValue != 0)
NirT 1:e8fac4061a5b 1536 {
NirT 1:e8fac4061a5b 1537 tmp |= (uint8_t)pin_8_15;
NirT 1:e8fac4061a5b 1538 }
NirT 1:e8fac4061a5b 1539 else
NirT 1:e8fac4061a5b 1540 {
NirT 1:e8fac4061a5b 1541 tmp &= ~(uint8_t)pin_8_15;
NirT 1:e8fac4061a5b 1542 }
NirT 1:e8fac4061a5b 1543
NirT 1:e8fac4061a5b 1544 /* Set the new register value */
NirT 1:e8fac4061a5b 1545 MFX_IO_Write(DeviceAddr, RegisterAddr+1, tmp);
NirT 1:e8fac4061a5b 1546 }
NirT 1:e8fac4061a5b 1547
NirT 1:e8fac4061a5b 1548 if (pin_16_23)
NirT 1:e8fac4061a5b 1549 {
NirT 1:e8fac4061a5b 1550 /* Get the current register value */
NirT 1:e8fac4061a5b 1551 tmp = MFX_IO_Read(DeviceAddr, RegisterAddr+2);
NirT 1:e8fac4061a5b 1552
NirT 1:e8fac4061a5b 1553 /* Set the selected pin direction */
NirT 1:e8fac4061a5b 1554 if (PinValue != 0)
NirT 1:e8fac4061a5b 1555 {
NirT 1:e8fac4061a5b 1556 tmp |= (uint8_t)pin_16_23;
NirT 1:e8fac4061a5b 1557 }
NirT 1:e8fac4061a5b 1558 else
NirT 1:e8fac4061a5b 1559 {
NirT 1:e8fac4061a5b 1560 tmp &= ~(uint8_t)pin_16_23;
NirT 1:e8fac4061a5b 1561 }
NirT 1:e8fac4061a5b 1562
NirT 1:e8fac4061a5b 1563 /* Set the new register value */
NirT 1:e8fac4061a5b 1564 MFX_IO_Write(DeviceAddr, RegisterAddr+2, tmp);
NirT 1:e8fac4061a5b 1565 }
NirT 1:e8fac4061a5b 1566 }
NirT 1:e8fac4061a5b 1567
NirT 1:e8fac4061a5b 1568
NirT 1:e8fac4061a5b 1569 /**
NirT 1:e8fac4061a5b 1570 * @}
NirT 1:e8fac4061a5b 1571 */
NirT 1:e8fac4061a5b 1572
NirT 1:e8fac4061a5b 1573 /**
NirT 1:e8fac4061a5b 1574 * @}
NirT 1:e8fac4061a5b 1575 */
NirT 1:e8fac4061a5b 1576
NirT 1:e8fac4061a5b 1577 /**
NirT 1:e8fac4061a5b 1578 * @}
NirT 1:e8fac4061a5b 1579 */
NirT 1:e8fac4061a5b 1580
NirT 1:e8fac4061a5b 1581 /**
NirT 1:e8fac4061a5b 1582 * @}
NirT 1:e8fac4061a5b 1583 */
NirT 1:e8fac4061a5b 1584 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/