inport from local
Dependents: Hobbyking_Cheetah_0511
targets/TARGET_STM/stm_spi_api.c@0:85b3fd62ea1a, 2020-03-16 (annotated)
- Committer:
- NYX
- Date:
- Mon Mar 16 06:35:48 2020 +0000
- Revision:
- 0:85b3fd62ea1a
reinport to mbed;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
NYX | 0:85b3fd62ea1a | 1 | /* mbed Microcontroller Library |
NYX | 0:85b3fd62ea1a | 2 | ******************************************************************************* |
NYX | 0:85b3fd62ea1a | 3 | * Copyright (c) 2015, STMicroelectronics |
NYX | 0:85b3fd62ea1a | 4 | * All rights reserved. |
NYX | 0:85b3fd62ea1a | 5 | * |
NYX | 0:85b3fd62ea1a | 6 | * Redistribution and use in source and binary forms, with or without |
NYX | 0:85b3fd62ea1a | 7 | * modification, are permitted provided that the following conditions are met: |
NYX | 0:85b3fd62ea1a | 8 | * |
NYX | 0:85b3fd62ea1a | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
NYX | 0:85b3fd62ea1a | 10 | * this list of conditions and the following disclaimer. |
NYX | 0:85b3fd62ea1a | 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
NYX | 0:85b3fd62ea1a | 12 | * this list of conditions and the following disclaimer in the documentation |
NYX | 0:85b3fd62ea1a | 13 | * and/or other materials provided with the distribution. |
NYX | 0:85b3fd62ea1a | 14 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
NYX | 0:85b3fd62ea1a | 15 | * may be used to endorse or promote products derived from this software |
NYX | 0:85b3fd62ea1a | 16 | * without specific prior written permission. |
NYX | 0:85b3fd62ea1a | 17 | * |
NYX | 0:85b3fd62ea1a | 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
NYX | 0:85b3fd62ea1a | 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
NYX | 0:85b3fd62ea1a | 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
NYX | 0:85b3fd62ea1a | 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
NYX | 0:85b3fd62ea1a | 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
NYX | 0:85b3fd62ea1a | 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
NYX | 0:85b3fd62ea1a | 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
NYX | 0:85b3fd62ea1a | 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
NYX | 0:85b3fd62ea1a | 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
NYX | 0:85b3fd62ea1a | 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
NYX | 0:85b3fd62ea1a | 28 | ******************************************************************************* |
NYX | 0:85b3fd62ea1a | 29 | */ |
NYX | 0:85b3fd62ea1a | 30 | #include "mbed_assert.h" |
NYX | 0:85b3fd62ea1a | 31 | #include "mbed_error.h" |
NYX | 0:85b3fd62ea1a | 32 | #include "spi_api.h" |
NYX | 0:85b3fd62ea1a | 33 | |
NYX | 0:85b3fd62ea1a | 34 | #if DEVICE_SPI |
NYX | 0:85b3fd62ea1a | 35 | #include <stdbool.h> |
NYX | 0:85b3fd62ea1a | 36 | #include <math.h> |
NYX | 0:85b3fd62ea1a | 37 | #include <string.h> |
NYX | 0:85b3fd62ea1a | 38 | #include "cmsis.h" |
NYX | 0:85b3fd62ea1a | 39 | #include "pinmap.h" |
NYX | 0:85b3fd62ea1a | 40 | #include "PeripheralPins.h" |
NYX | 0:85b3fd62ea1a | 41 | #include "spi_device.h" |
NYX | 0:85b3fd62ea1a | 42 | |
NYX | 0:85b3fd62ea1a | 43 | #if DEVICE_SPI_ASYNCH |
NYX | 0:85b3fd62ea1a | 44 | #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi)) |
NYX | 0:85b3fd62ea1a | 45 | #else |
NYX | 0:85b3fd62ea1a | 46 | #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi)) |
NYX | 0:85b3fd62ea1a | 47 | #endif |
NYX | 0:85b3fd62ea1a | 48 | |
NYX | 0:85b3fd62ea1a | 49 | #if DEVICE_SPI_ASYNCH |
NYX | 0:85b3fd62ea1a | 50 | #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) |
NYX | 0:85b3fd62ea1a | 51 | #else |
NYX | 0:85b3fd62ea1a | 52 | #define SPI_S(obj) (( struct spi_s *)(obj)) |
NYX | 0:85b3fd62ea1a | 53 | #endif |
NYX | 0:85b3fd62ea1a | 54 | |
NYX | 0:85b3fd62ea1a | 55 | #ifndef DEBUG_STDIO |
NYX | 0:85b3fd62ea1a | 56 | # define DEBUG_STDIO 0 |
NYX | 0:85b3fd62ea1a | 57 | #endif |
NYX | 0:85b3fd62ea1a | 58 | |
NYX | 0:85b3fd62ea1a | 59 | #if DEBUG_STDIO |
NYX | 0:85b3fd62ea1a | 60 | # include <stdio.h> |
NYX | 0:85b3fd62ea1a | 61 | # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0) |
NYX | 0:85b3fd62ea1a | 62 | #else |
NYX | 0:85b3fd62ea1a | 63 | # define DEBUG_PRINTF(...) {} |
NYX | 0:85b3fd62ea1a | 64 | #endif |
NYX | 0:85b3fd62ea1a | 65 | |
NYX | 0:85b3fd62ea1a | 66 | /* Consider 10ms as the default timeout for sending/receving 1 byte */ |
NYX | 0:85b3fd62ea1a | 67 | #define TIMEOUT_1_BYTE 10 |
NYX | 0:85b3fd62ea1a | 68 | |
NYX | 0:85b3fd62ea1a | 69 | void init_spi(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 70 | { |
NYX | 0:85b3fd62ea1a | 71 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 72 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 73 | |
NYX | 0:85b3fd62ea1a | 74 | __HAL_SPI_DISABLE(handle); |
NYX | 0:85b3fd62ea1a | 75 | |
NYX | 0:85b3fd62ea1a | 76 | DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance); |
NYX | 0:85b3fd62ea1a | 77 | if (HAL_SPI_Init(handle) != HAL_OK) { |
NYX | 0:85b3fd62ea1a | 78 | error("Cannot initialize SPI"); |
NYX | 0:85b3fd62ea1a | 79 | } |
NYX | 0:85b3fd62ea1a | 80 | |
NYX | 0:85b3fd62ea1a | 81 | /* In case of standard 4 wires SPI,PI can be kept enabled all time |
NYX | 0:85b3fd62ea1a | 82 | * and SCK will only be generated during the write operations. But in case |
NYX | 0:85b3fd62ea1a | 83 | * of 3 wires, it should be only enabled during rd/wr unitary operations, |
NYX | 0:85b3fd62ea1a | 84 | * which is handled inside STM32 HAL layer. |
NYX | 0:85b3fd62ea1a | 85 | */ |
NYX | 0:85b3fd62ea1a | 86 | if (handle->Init.Direction == SPI_DIRECTION_2LINES) { |
NYX | 0:85b3fd62ea1a | 87 | __HAL_SPI_ENABLE(handle); |
NYX | 0:85b3fd62ea1a | 88 | } |
NYX | 0:85b3fd62ea1a | 89 | } |
NYX | 0:85b3fd62ea1a | 90 | |
NYX | 0:85b3fd62ea1a | 91 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) |
NYX | 0:85b3fd62ea1a | 92 | { |
NYX | 0:85b3fd62ea1a | 93 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 94 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 95 | |
NYX | 0:85b3fd62ea1a | 96 | // Determine the SPI to use |
NYX | 0:85b3fd62ea1a | 97 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
NYX | 0:85b3fd62ea1a | 98 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
NYX | 0:85b3fd62ea1a | 99 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
NYX | 0:85b3fd62ea1a | 100 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
NYX | 0:85b3fd62ea1a | 101 | |
NYX | 0:85b3fd62ea1a | 102 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
NYX | 0:85b3fd62ea1a | 103 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
NYX | 0:85b3fd62ea1a | 104 | |
NYX | 0:85b3fd62ea1a | 105 | spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); |
NYX | 0:85b3fd62ea1a | 106 | MBED_ASSERT(spiobj->spi != (SPIName)NC); |
NYX | 0:85b3fd62ea1a | 107 | |
NYX | 0:85b3fd62ea1a | 108 | #if defined SPI1_BASE |
NYX | 0:85b3fd62ea1a | 109 | // Enable SPI clock |
NYX | 0:85b3fd62ea1a | 110 | if (spiobj->spi == SPI_1) { |
NYX | 0:85b3fd62ea1a | 111 | __HAL_RCC_SPI1_CLK_ENABLE(); |
NYX | 0:85b3fd62ea1a | 112 | spiobj->spiIRQ = SPI1_IRQn; |
NYX | 0:85b3fd62ea1a | 113 | } |
NYX | 0:85b3fd62ea1a | 114 | #endif |
NYX | 0:85b3fd62ea1a | 115 | |
NYX | 0:85b3fd62ea1a | 116 | #if defined SPI2_BASE |
NYX | 0:85b3fd62ea1a | 117 | if (spiobj->spi == SPI_2) { |
NYX | 0:85b3fd62ea1a | 118 | __HAL_RCC_SPI2_CLK_ENABLE(); |
NYX | 0:85b3fd62ea1a | 119 | spiobj->spiIRQ = SPI2_IRQn; |
NYX | 0:85b3fd62ea1a | 120 | } |
NYX | 0:85b3fd62ea1a | 121 | #endif |
NYX | 0:85b3fd62ea1a | 122 | |
NYX | 0:85b3fd62ea1a | 123 | #if defined SPI3_BASE |
NYX | 0:85b3fd62ea1a | 124 | if (spiobj->spi == SPI_3) { |
NYX | 0:85b3fd62ea1a | 125 | __HAL_RCC_SPI3_CLK_ENABLE(); |
NYX | 0:85b3fd62ea1a | 126 | spiobj->spiIRQ = SPI3_IRQn; |
NYX | 0:85b3fd62ea1a | 127 | } |
NYX | 0:85b3fd62ea1a | 128 | #endif |
NYX | 0:85b3fd62ea1a | 129 | |
NYX | 0:85b3fd62ea1a | 130 | #if defined SPI4_BASE |
NYX | 0:85b3fd62ea1a | 131 | if (spiobj->spi == SPI_4) { |
NYX | 0:85b3fd62ea1a | 132 | __HAL_RCC_SPI4_CLK_ENABLE(); |
NYX | 0:85b3fd62ea1a | 133 | spiobj->spiIRQ = SPI4_IRQn; |
NYX | 0:85b3fd62ea1a | 134 | } |
NYX | 0:85b3fd62ea1a | 135 | #endif |
NYX | 0:85b3fd62ea1a | 136 | |
NYX | 0:85b3fd62ea1a | 137 | #if defined SPI5_BASE |
NYX | 0:85b3fd62ea1a | 138 | if (spiobj->spi == SPI_5) { |
NYX | 0:85b3fd62ea1a | 139 | __HAL_RCC_SPI5_CLK_ENABLE(); |
NYX | 0:85b3fd62ea1a | 140 | spiobj->spiIRQ = SPI5_IRQn; |
NYX | 0:85b3fd62ea1a | 141 | } |
NYX | 0:85b3fd62ea1a | 142 | #endif |
NYX | 0:85b3fd62ea1a | 143 | |
NYX | 0:85b3fd62ea1a | 144 | #if defined SPI6_BASE |
NYX | 0:85b3fd62ea1a | 145 | if (spiobj->spi == SPI_6) { |
NYX | 0:85b3fd62ea1a | 146 | __HAL_RCC_SPI6_CLK_ENABLE(); |
NYX | 0:85b3fd62ea1a | 147 | spiobj->spiIRQ = SPI6_IRQn; |
NYX | 0:85b3fd62ea1a | 148 | } |
NYX | 0:85b3fd62ea1a | 149 | #endif |
NYX | 0:85b3fd62ea1a | 150 | |
NYX | 0:85b3fd62ea1a | 151 | // Configure the SPI pins |
NYX | 0:85b3fd62ea1a | 152 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
NYX | 0:85b3fd62ea1a | 153 | pinmap_pinout(miso, PinMap_SPI_MISO); |
NYX | 0:85b3fd62ea1a | 154 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
NYX | 0:85b3fd62ea1a | 155 | spiobj->pin_miso = miso; |
NYX | 0:85b3fd62ea1a | 156 | spiobj->pin_mosi = mosi; |
NYX | 0:85b3fd62ea1a | 157 | spiobj->pin_sclk = sclk; |
NYX | 0:85b3fd62ea1a | 158 | spiobj->pin_ssel = ssel; |
NYX | 0:85b3fd62ea1a | 159 | if (ssel != NC) { |
NYX | 0:85b3fd62ea1a | 160 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
NYX | 0:85b3fd62ea1a | 161 | } else { |
NYX | 0:85b3fd62ea1a | 162 | handle->Init.NSS = SPI_NSS_SOFT; |
NYX | 0:85b3fd62ea1a | 163 | } |
NYX | 0:85b3fd62ea1a | 164 | |
NYX | 0:85b3fd62ea1a | 165 | /* Fill default value */ |
NYX | 0:85b3fd62ea1a | 166 | handle->Instance = SPI_INST(obj); |
NYX | 0:85b3fd62ea1a | 167 | handle->Init.Mode = SPI_MODE_MASTER; |
NYX | 0:85b3fd62ea1a | 168 | handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256; |
NYX | 0:85b3fd62ea1a | 169 | |
NYX | 0:85b3fd62ea1a | 170 | if (miso != NC) { |
NYX | 0:85b3fd62ea1a | 171 | handle->Init.Direction = SPI_DIRECTION_2LINES; |
NYX | 0:85b3fd62ea1a | 172 | } else { |
NYX | 0:85b3fd62ea1a | 173 | handle->Init.Direction = SPI_DIRECTION_1LINE; |
NYX | 0:85b3fd62ea1a | 174 | } |
NYX | 0:85b3fd62ea1a | 175 | |
NYX | 0:85b3fd62ea1a | 176 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
NYX | 0:85b3fd62ea1a | 177 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
NYX | 0:85b3fd62ea1a | 178 | handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; |
NYX | 0:85b3fd62ea1a | 179 | handle->Init.CRCPolynomial = 7; |
NYX | 0:85b3fd62ea1a | 180 | handle->Init.DataSize = SPI_DATASIZE_8BIT; |
NYX | 0:85b3fd62ea1a | 181 | handle->Init.FirstBit = SPI_FIRSTBIT_MSB; |
NYX | 0:85b3fd62ea1a | 182 | handle->Init.TIMode = SPI_TIMODE_DISABLE; |
NYX | 0:85b3fd62ea1a | 183 | |
NYX | 0:85b3fd62ea1a | 184 | init_spi(obj); |
NYX | 0:85b3fd62ea1a | 185 | } |
NYX | 0:85b3fd62ea1a | 186 | |
NYX | 0:85b3fd62ea1a | 187 | void spi_free(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 188 | { |
NYX | 0:85b3fd62ea1a | 189 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 190 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 191 | |
NYX | 0:85b3fd62ea1a | 192 | DEBUG_PRINTF("spi_free\r\n"); |
NYX | 0:85b3fd62ea1a | 193 | |
NYX | 0:85b3fd62ea1a | 194 | __HAL_SPI_DISABLE(handle); |
NYX | 0:85b3fd62ea1a | 195 | HAL_SPI_DeInit(handle); |
NYX | 0:85b3fd62ea1a | 196 | |
NYX | 0:85b3fd62ea1a | 197 | #if defined SPI1_BASE |
NYX | 0:85b3fd62ea1a | 198 | // Reset SPI and disable clock |
NYX | 0:85b3fd62ea1a | 199 | if (spiobj->spi == SPI_1) { |
NYX | 0:85b3fd62ea1a | 200 | __HAL_RCC_SPI1_FORCE_RESET(); |
NYX | 0:85b3fd62ea1a | 201 | __HAL_RCC_SPI1_RELEASE_RESET(); |
NYX | 0:85b3fd62ea1a | 202 | __HAL_RCC_SPI1_CLK_DISABLE(); |
NYX | 0:85b3fd62ea1a | 203 | } |
NYX | 0:85b3fd62ea1a | 204 | #endif |
NYX | 0:85b3fd62ea1a | 205 | #if defined SPI2_BASE |
NYX | 0:85b3fd62ea1a | 206 | if (spiobj->spi == SPI_2) { |
NYX | 0:85b3fd62ea1a | 207 | __HAL_RCC_SPI2_FORCE_RESET(); |
NYX | 0:85b3fd62ea1a | 208 | __HAL_RCC_SPI2_RELEASE_RESET(); |
NYX | 0:85b3fd62ea1a | 209 | __HAL_RCC_SPI2_CLK_DISABLE(); |
NYX | 0:85b3fd62ea1a | 210 | } |
NYX | 0:85b3fd62ea1a | 211 | #endif |
NYX | 0:85b3fd62ea1a | 212 | |
NYX | 0:85b3fd62ea1a | 213 | #if defined SPI3_BASE |
NYX | 0:85b3fd62ea1a | 214 | if (spiobj->spi == SPI_3) { |
NYX | 0:85b3fd62ea1a | 215 | __HAL_RCC_SPI3_FORCE_RESET(); |
NYX | 0:85b3fd62ea1a | 216 | __HAL_RCC_SPI3_RELEASE_RESET(); |
NYX | 0:85b3fd62ea1a | 217 | __HAL_RCC_SPI3_CLK_DISABLE(); |
NYX | 0:85b3fd62ea1a | 218 | } |
NYX | 0:85b3fd62ea1a | 219 | #endif |
NYX | 0:85b3fd62ea1a | 220 | |
NYX | 0:85b3fd62ea1a | 221 | #if defined SPI4_BASE |
NYX | 0:85b3fd62ea1a | 222 | if (spiobj->spi == SPI_4) { |
NYX | 0:85b3fd62ea1a | 223 | __HAL_RCC_SPI4_FORCE_RESET(); |
NYX | 0:85b3fd62ea1a | 224 | __HAL_RCC_SPI4_RELEASE_RESET(); |
NYX | 0:85b3fd62ea1a | 225 | __HAL_RCC_SPI4_CLK_DISABLE(); |
NYX | 0:85b3fd62ea1a | 226 | } |
NYX | 0:85b3fd62ea1a | 227 | #endif |
NYX | 0:85b3fd62ea1a | 228 | |
NYX | 0:85b3fd62ea1a | 229 | #if defined SPI5_BASE |
NYX | 0:85b3fd62ea1a | 230 | if (spiobj->spi == SPI_5) { |
NYX | 0:85b3fd62ea1a | 231 | __HAL_RCC_SPI5_FORCE_RESET(); |
NYX | 0:85b3fd62ea1a | 232 | __HAL_RCC_SPI5_RELEASE_RESET(); |
NYX | 0:85b3fd62ea1a | 233 | __HAL_RCC_SPI5_CLK_DISABLE(); |
NYX | 0:85b3fd62ea1a | 234 | } |
NYX | 0:85b3fd62ea1a | 235 | #endif |
NYX | 0:85b3fd62ea1a | 236 | |
NYX | 0:85b3fd62ea1a | 237 | #if defined SPI6_BASE |
NYX | 0:85b3fd62ea1a | 238 | if (spiobj->spi == SPI_6) { |
NYX | 0:85b3fd62ea1a | 239 | __HAL_RCC_SPI6_FORCE_RESET(); |
NYX | 0:85b3fd62ea1a | 240 | __HAL_RCC_SPI6_RELEASE_RESET(); |
NYX | 0:85b3fd62ea1a | 241 | __HAL_RCC_SPI6_CLK_DISABLE(); |
NYX | 0:85b3fd62ea1a | 242 | } |
NYX | 0:85b3fd62ea1a | 243 | #endif |
NYX | 0:85b3fd62ea1a | 244 | |
NYX | 0:85b3fd62ea1a | 245 | // Configure GPIOs |
NYX | 0:85b3fd62ea1a | 246 | pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
NYX | 0:85b3fd62ea1a | 247 | pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
NYX | 0:85b3fd62ea1a | 248 | pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
NYX | 0:85b3fd62ea1a | 249 | if (handle->Init.NSS != SPI_NSS_SOFT) { |
NYX | 0:85b3fd62ea1a | 250 | pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
NYX | 0:85b3fd62ea1a | 251 | } |
NYX | 0:85b3fd62ea1a | 252 | } |
NYX | 0:85b3fd62ea1a | 253 | |
NYX | 0:85b3fd62ea1a | 254 | void spi_format(spi_t *obj, int bits, int mode, int slave) |
NYX | 0:85b3fd62ea1a | 255 | { |
NYX | 0:85b3fd62ea1a | 256 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 257 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 258 | |
NYX | 0:85b3fd62ea1a | 259 | DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave); |
NYX | 0:85b3fd62ea1a | 260 | |
NYX | 0:85b3fd62ea1a | 261 | // Save new values |
NYX | 0:85b3fd62ea1a | 262 | handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT; |
NYX | 0:85b3fd62ea1a | 263 | |
NYX | 0:85b3fd62ea1a | 264 | switch (mode) { |
NYX | 0:85b3fd62ea1a | 265 | case 0: |
NYX | 0:85b3fd62ea1a | 266 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
NYX | 0:85b3fd62ea1a | 267 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
NYX | 0:85b3fd62ea1a | 268 | break; |
NYX | 0:85b3fd62ea1a | 269 | case 1: |
NYX | 0:85b3fd62ea1a | 270 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
NYX | 0:85b3fd62ea1a | 271 | handle->Init.CLKPhase = SPI_PHASE_2EDGE; |
NYX | 0:85b3fd62ea1a | 272 | break; |
NYX | 0:85b3fd62ea1a | 273 | case 2: |
NYX | 0:85b3fd62ea1a | 274 | handle->Init.CLKPolarity = SPI_POLARITY_HIGH; |
NYX | 0:85b3fd62ea1a | 275 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
NYX | 0:85b3fd62ea1a | 276 | break; |
NYX | 0:85b3fd62ea1a | 277 | default: |
NYX | 0:85b3fd62ea1a | 278 | handle->Init.CLKPolarity = SPI_POLARITY_HIGH; |
NYX | 0:85b3fd62ea1a | 279 | handle->Init.CLKPhase = SPI_PHASE_2EDGE; |
NYX | 0:85b3fd62ea1a | 280 | break; |
NYX | 0:85b3fd62ea1a | 281 | } |
NYX | 0:85b3fd62ea1a | 282 | |
NYX | 0:85b3fd62ea1a | 283 | if (handle->Init.NSS != SPI_NSS_SOFT) { |
NYX | 0:85b3fd62ea1a | 284 | handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; |
NYX | 0:85b3fd62ea1a | 285 | } |
NYX | 0:85b3fd62ea1a | 286 | |
NYX | 0:85b3fd62ea1a | 287 | handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; |
NYX | 0:85b3fd62ea1a | 288 | |
NYX | 0:85b3fd62ea1a | 289 | init_spi(obj); |
NYX | 0:85b3fd62ea1a | 290 | } |
NYX | 0:85b3fd62ea1a | 291 | |
NYX | 0:85b3fd62ea1a | 292 | /* |
NYX | 0:85b3fd62ea1a | 293 | * Only the IP clock input is family dependant so it computed |
NYX | 0:85b3fd62ea1a | 294 | * separately in spi_get_clock_freq |
NYX | 0:85b3fd62ea1a | 295 | */ |
NYX | 0:85b3fd62ea1a | 296 | extern int spi_get_clock_freq(spi_t *obj); |
NYX | 0:85b3fd62ea1a | 297 | |
NYX | 0:85b3fd62ea1a | 298 | static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2, |
NYX | 0:85b3fd62ea1a | 299 | SPI_BAUDRATEPRESCALER_4, |
NYX | 0:85b3fd62ea1a | 300 | SPI_BAUDRATEPRESCALER_8, |
NYX | 0:85b3fd62ea1a | 301 | SPI_BAUDRATEPRESCALER_16, |
NYX | 0:85b3fd62ea1a | 302 | SPI_BAUDRATEPRESCALER_32, |
NYX | 0:85b3fd62ea1a | 303 | SPI_BAUDRATEPRESCALER_64, |
NYX | 0:85b3fd62ea1a | 304 | SPI_BAUDRATEPRESCALER_128, |
NYX | 0:85b3fd62ea1a | 305 | SPI_BAUDRATEPRESCALER_256}; |
NYX | 0:85b3fd62ea1a | 306 | |
NYX | 0:85b3fd62ea1a | 307 | void spi_frequency(spi_t *obj, int hz) { |
NYX | 0:85b3fd62ea1a | 308 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 309 | int spi_hz = 0; |
NYX | 0:85b3fd62ea1a | 310 | uint8_t prescaler_rank = 0; |
NYX | 0:85b3fd62ea1a | 311 | uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1; |
NYX | 0:85b3fd62ea1a | 312 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 313 | |
NYX | 0:85b3fd62ea1a | 314 | /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */ |
NYX | 0:85b3fd62ea1a | 315 | spi_hz = spi_get_clock_freq(obj) / 2; |
NYX | 0:85b3fd62ea1a | 316 | |
NYX | 0:85b3fd62ea1a | 317 | /* Define pre-scaler in order to get highest available frequency below requested frequency */ |
NYX | 0:85b3fd62ea1a | 318 | while ((spi_hz > hz) && (prescaler_rank < last_index)) { |
NYX | 0:85b3fd62ea1a | 319 | spi_hz = spi_hz / 2; |
NYX | 0:85b3fd62ea1a | 320 | prescaler_rank++; |
NYX | 0:85b3fd62ea1a | 321 | } |
NYX | 0:85b3fd62ea1a | 322 | |
NYX | 0:85b3fd62ea1a | 323 | /* Use the best fit pre-scaler */ |
NYX | 0:85b3fd62ea1a | 324 | handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank]; |
NYX | 0:85b3fd62ea1a | 325 | |
NYX | 0:85b3fd62ea1a | 326 | /* In case maximum pre-scaler still gives too high freq, raise an error */ |
NYX | 0:85b3fd62ea1a | 327 | if (spi_hz > hz) { |
NYX | 0:85b3fd62ea1a | 328 | DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz); |
NYX | 0:85b3fd62ea1a | 329 | } |
NYX | 0:85b3fd62ea1a | 330 | |
NYX | 0:85b3fd62ea1a | 331 | DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz); |
NYX | 0:85b3fd62ea1a | 332 | |
NYX | 0:85b3fd62ea1a | 333 | init_spi(obj); |
NYX | 0:85b3fd62ea1a | 334 | } |
NYX | 0:85b3fd62ea1a | 335 | |
NYX | 0:85b3fd62ea1a | 336 | static inline int ssp_readable(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 337 | { |
NYX | 0:85b3fd62ea1a | 338 | int status; |
NYX | 0:85b3fd62ea1a | 339 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 340 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 341 | |
NYX | 0:85b3fd62ea1a | 342 | // Check if data is received |
NYX | 0:85b3fd62ea1a | 343 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); |
NYX | 0:85b3fd62ea1a | 344 | return status; |
NYX | 0:85b3fd62ea1a | 345 | } |
NYX | 0:85b3fd62ea1a | 346 | |
NYX | 0:85b3fd62ea1a | 347 | static inline int ssp_writeable(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 348 | { |
NYX | 0:85b3fd62ea1a | 349 | int status; |
NYX | 0:85b3fd62ea1a | 350 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 351 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 352 | |
NYX | 0:85b3fd62ea1a | 353 | // Check if data is transmitted |
NYX | 0:85b3fd62ea1a | 354 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0); |
NYX | 0:85b3fd62ea1a | 355 | return status; |
NYX | 0:85b3fd62ea1a | 356 | } |
NYX | 0:85b3fd62ea1a | 357 | |
NYX | 0:85b3fd62ea1a | 358 | static inline int ssp_busy(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 359 | { |
NYX | 0:85b3fd62ea1a | 360 | int status; |
NYX | 0:85b3fd62ea1a | 361 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 362 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 363 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0); |
NYX | 0:85b3fd62ea1a | 364 | return status; |
NYX | 0:85b3fd62ea1a | 365 | } |
NYX | 0:85b3fd62ea1a | 366 | |
NYX | 0:85b3fd62ea1a | 367 | int spi_master_write(spi_t *obj, int value) |
NYX | 0:85b3fd62ea1a | 368 | { |
NYX | 0:85b3fd62ea1a | 369 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 370 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 371 | |
NYX | 0:85b3fd62ea1a | 372 | if (handle->Init.Direction == SPI_DIRECTION_1LINE) { |
NYX | 0:85b3fd62ea1a | 373 | return HAL_SPI_Transmit(handle, (uint8_t*)&value, 1, TIMEOUT_1_BYTE); |
NYX | 0:85b3fd62ea1a | 374 | } |
NYX | 0:85b3fd62ea1a | 375 | |
NYX | 0:85b3fd62ea1a | 376 | #if defined(LL_SPI_RX_FIFO_TH_HALF) |
NYX | 0:85b3fd62ea1a | 377 | /* Configure the default data size */ |
NYX | 0:85b3fd62ea1a | 378 | if (handle->Init.DataSize == SPI_DATASIZE_16BIT) { |
NYX | 0:85b3fd62ea1a | 379 | LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF); |
NYX | 0:85b3fd62ea1a | 380 | } else { |
NYX | 0:85b3fd62ea1a | 381 | LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER); |
NYX | 0:85b3fd62ea1a | 382 | } |
NYX | 0:85b3fd62ea1a | 383 | #endif |
NYX | 0:85b3fd62ea1a | 384 | |
NYX | 0:85b3fd62ea1a | 385 | /* Here we're using LL which means direct registers access |
NYX | 0:85b3fd62ea1a | 386 | * There is no error management, so we may end up looping |
NYX | 0:85b3fd62ea1a | 387 | * infinitely here in case of faulty device for insatnce, |
NYX | 0:85b3fd62ea1a | 388 | * but this will increase performances significantly |
NYX | 0:85b3fd62ea1a | 389 | */ |
NYX | 0:85b3fd62ea1a | 390 | |
NYX | 0:85b3fd62ea1a | 391 | /* Wait TXE flag to transmit data */ |
NYX | 0:85b3fd62ea1a | 392 | while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj))); |
NYX | 0:85b3fd62ea1a | 393 | |
NYX | 0:85b3fd62ea1a | 394 | if (handle->Init.DataSize == SPI_DATASIZE_16BIT) { |
NYX | 0:85b3fd62ea1a | 395 | LL_SPI_TransmitData16(SPI_INST(obj), value); |
NYX | 0:85b3fd62ea1a | 396 | } else { |
NYX | 0:85b3fd62ea1a | 397 | LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t) value); |
NYX | 0:85b3fd62ea1a | 398 | } |
NYX | 0:85b3fd62ea1a | 399 | |
NYX | 0:85b3fd62ea1a | 400 | /* Then wait RXE flag before reading */ |
NYX | 0:85b3fd62ea1a | 401 | while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj))); |
NYX | 0:85b3fd62ea1a | 402 | |
NYX | 0:85b3fd62ea1a | 403 | if (handle->Init.DataSize == SPI_DATASIZE_16BIT) { |
NYX | 0:85b3fd62ea1a | 404 | return LL_SPI_ReceiveData16(SPI_INST(obj)); |
NYX | 0:85b3fd62ea1a | 405 | } else { |
NYX | 0:85b3fd62ea1a | 406 | return LL_SPI_ReceiveData8(SPI_INST(obj)); |
NYX | 0:85b3fd62ea1a | 407 | } |
NYX | 0:85b3fd62ea1a | 408 | } |
NYX | 0:85b3fd62ea1a | 409 | |
NYX | 0:85b3fd62ea1a | 410 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, |
NYX | 0:85b3fd62ea1a | 411 | char *rx_buffer, int rx_length, char write_fill) |
NYX | 0:85b3fd62ea1a | 412 | { |
NYX | 0:85b3fd62ea1a | 413 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 414 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 415 | int total = (tx_length > rx_length) ? tx_length : rx_length; |
NYX | 0:85b3fd62ea1a | 416 | int i = 0; |
NYX | 0:85b3fd62ea1a | 417 | if (handle->Init.Direction == SPI_DIRECTION_2LINES) { |
NYX | 0:85b3fd62ea1a | 418 | for (i = 0; i < total; i++) { |
NYX | 0:85b3fd62ea1a | 419 | char out = (i < tx_length) ? tx_buffer[i] : write_fill; |
NYX | 0:85b3fd62ea1a | 420 | char in = spi_master_write(obj, out); |
NYX | 0:85b3fd62ea1a | 421 | if (i < rx_length) { |
NYX | 0:85b3fd62ea1a | 422 | rx_buffer[i] = in; |
NYX | 0:85b3fd62ea1a | 423 | } |
NYX | 0:85b3fd62ea1a | 424 | } |
NYX | 0:85b3fd62ea1a | 425 | } else { |
NYX | 0:85b3fd62ea1a | 426 | /* In case of 1 WIRE only, first handle TX, then Rx */ |
NYX | 0:85b3fd62ea1a | 427 | if (tx_length != 0) { |
NYX | 0:85b3fd62ea1a | 428 | if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t*)tx_buffer, tx_length, tx_length*TIMEOUT_1_BYTE)) { |
NYX | 0:85b3fd62ea1a | 429 | /* report an error */ |
NYX | 0:85b3fd62ea1a | 430 | total = 0; |
NYX | 0:85b3fd62ea1a | 431 | } |
NYX | 0:85b3fd62ea1a | 432 | } |
NYX | 0:85b3fd62ea1a | 433 | if (rx_length != 0) { |
NYX | 0:85b3fd62ea1a | 434 | if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t*)rx_buffer, rx_length, rx_length*TIMEOUT_1_BYTE)) { |
NYX | 0:85b3fd62ea1a | 435 | /* report an error */ |
NYX | 0:85b3fd62ea1a | 436 | total = 0; |
NYX | 0:85b3fd62ea1a | 437 | } |
NYX | 0:85b3fd62ea1a | 438 | } |
NYX | 0:85b3fd62ea1a | 439 | } |
NYX | 0:85b3fd62ea1a | 440 | |
NYX | 0:85b3fd62ea1a | 441 | return total; |
NYX | 0:85b3fd62ea1a | 442 | } |
NYX | 0:85b3fd62ea1a | 443 | |
NYX | 0:85b3fd62ea1a | 444 | int spi_slave_receive(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 445 | { |
NYX | 0:85b3fd62ea1a | 446 | return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); |
NYX | 0:85b3fd62ea1a | 447 | }; |
NYX | 0:85b3fd62ea1a | 448 | |
NYX | 0:85b3fd62ea1a | 449 | int spi_slave_read(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 450 | { |
NYX | 0:85b3fd62ea1a | 451 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 452 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 453 | while (!ssp_readable(obj)); |
NYX | 0:85b3fd62ea1a | 454 | if (handle->Init.DataSize == SPI_DATASIZE_16BIT) { |
NYX | 0:85b3fd62ea1a | 455 | return LL_SPI_ReceiveData16(SPI_INST(obj)); |
NYX | 0:85b3fd62ea1a | 456 | } else { |
NYX | 0:85b3fd62ea1a | 457 | return LL_SPI_ReceiveData8(SPI_INST(obj)); |
NYX | 0:85b3fd62ea1a | 458 | } |
NYX | 0:85b3fd62ea1a | 459 | } |
NYX | 0:85b3fd62ea1a | 460 | |
NYX | 0:85b3fd62ea1a | 461 | void spi_slave_write(spi_t *obj, int value) |
NYX | 0:85b3fd62ea1a | 462 | { |
NYX | 0:85b3fd62ea1a | 463 | SPI_TypeDef *spi = SPI_INST(obj); |
NYX | 0:85b3fd62ea1a | 464 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 465 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 466 | while (!ssp_writeable(obj)); |
NYX | 0:85b3fd62ea1a | 467 | if (handle->Init.DataSize == SPI_DATASIZE_8BIT) { |
NYX | 0:85b3fd62ea1a | 468 | // Force 8-bit access to the data register |
NYX | 0:85b3fd62ea1a | 469 | uint8_t *p_spi_dr = 0; |
NYX | 0:85b3fd62ea1a | 470 | p_spi_dr = (uint8_t *) & (spi->DR); |
NYX | 0:85b3fd62ea1a | 471 | *p_spi_dr = (uint8_t)value; |
NYX | 0:85b3fd62ea1a | 472 | } else { // SPI_DATASIZE_16BIT |
NYX | 0:85b3fd62ea1a | 473 | spi->DR = (uint16_t)value; |
NYX | 0:85b3fd62ea1a | 474 | } |
NYX | 0:85b3fd62ea1a | 475 | } |
NYX | 0:85b3fd62ea1a | 476 | |
NYX | 0:85b3fd62ea1a | 477 | int spi_busy(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 478 | { |
NYX | 0:85b3fd62ea1a | 479 | return ssp_busy(obj); |
NYX | 0:85b3fd62ea1a | 480 | } |
NYX | 0:85b3fd62ea1a | 481 | |
NYX | 0:85b3fd62ea1a | 482 | #ifdef DEVICE_SPI_ASYNCH |
NYX | 0:85b3fd62ea1a | 483 | typedef enum { |
NYX | 0:85b3fd62ea1a | 484 | SPI_TRANSFER_TYPE_NONE = 0, |
NYX | 0:85b3fd62ea1a | 485 | SPI_TRANSFER_TYPE_TX = 1, |
NYX | 0:85b3fd62ea1a | 486 | SPI_TRANSFER_TYPE_RX = 2, |
NYX | 0:85b3fd62ea1a | 487 | SPI_TRANSFER_TYPE_TXRX = 3, |
NYX | 0:85b3fd62ea1a | 488 | } transfer_type_t; |
NYX | 0:85b3fd62ea1a | 489 | |
NYX | 0:85b3fd62ea1a | 490 | |
NYX | 0:85b3fd62ea1a | 491 | /// @returns the number of bytes transferred, or `0` if nothing transferred |
NYX | 0:85b3fd62ea1a | 492 | static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length) |
NYX | 0:85b3fd62ea1a | 493 | { |
NYX | 0:85b3fd62ea1a | 494 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 495 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 496 | bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT); |
NYX | 0:85b3fd62ea1a | 497 | // the HAL expects number of transfers instead of number of bytes |
NYX | 0:85b3fd62ea1a | 498 | // so for 16 bit transfer width the count needs to be halved |
NYX | 0:85b3fd62ea1a | 499 | size_t words; |
NYX | 0:85b3fd62ea1a | 500 | |
NYX | 0:85b3fd62ea1a | 501 | DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length); |
NYX | 0:85b3fd62ea1a | 502 | |
NYX | 0:85b3fd62ea1a | 503 | obj->spi.transfer_type = transfer_type; |
NYX | 0:85b3fd62ea1a | 504 | |
NYX | 0:85b3fd62ea1a | 505 | if (is16bit) { |
NYX | 0:85b3fd62ea1a | 506 | words = length / 2; |
NYX | 0:85b3fd62ea1a | 507 | } else { |
NYX | 0:85b3fd62ea1a | 508 | words = length; |
NYX | 0:85b3fd62ea1a | 509 | } |
NYX | 0:85b3fd62ea1a | 510 | |
NYX | 0:85b3fd62ea1a | 511 | // enable the interrupt |
NYX | 0:85b3fd62ea1a | 512 | IRQn_Type irq_n = spiobj->spiIRQ; |
NYX | 0:85b3fd62ea1a | 513 | NVIC_DisableIRQ(irq_n); |
NYX | 0:85b3fd62ea1a | 514 | NVIC_ClearPendingIRQ(irq_n); |
NYX | 0:85b3fd62ea1a | 515 | NVIC_SetPriority(irq_n, 1); |
NYX | 0:85b3fd62ea1a | 516 | NVIC_EnableIRQ(irq_n); |
NYX | 0:85b3fd62ea1a | 517 | |
NYX | 0:85b3fd62ea1a | 518 | // enable the right hal transfer |
NYX | 0:85b3fd62ea1a | 519 | int rc = 0; |
NYX | 0:85b3fd62ea1a | 520 | switch(transfer_type) { |
NYX | 0:85b3fd62ea1a | 521 | case SPI_TRANSFER_TYPE_TXRX: |
NYX | 0:85b3fd62ea1a | 522 | rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words); |
NYX | 0:85b3fd62ea1a | 523 | break; |
NYX | 0:85b3fd62ea1a | 524 | case SPI_TRANSFER_TYPE_TX: |
NYX | 0:85b3fd62ea1a | 525 | rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words); |
NYX | 0:85b3fd62ea1a | 526 | break; |
NYX | 0:85b3fd62ea1a | 527 | case SPI_TRANSFER_TYPE_RX: |
NYX | 0:85b3fd62ea1a | 528 | // the receive function also "transmits" the receive buffer so in order |
NYX | 0:85b3fd62ea1a | 529 | // to guarantee that 0xff is on the line, we explicitly memset it here |
NYX | 0:85b3fd62ea1a | 530 | memset(rx, SPI_FILL_WORD, length); |
NYX | 0:85b3fd62ea1a | 531 | rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words); |
NYX | 0:85b3fd62ea1a | 532 | break; |
NYX | 0:85b3fd62ea1a | 533 | default: |
NYX | 0:85b3fd62ea1a | 534 | length = 0; |
NYX | 0:85b3fd62ea1a | 535 | } |
NYX | 0:85b3fd62ea1a | 536 | |
NYX | 0:85b3fd62ea1a | 537 | if (rc) { |
NYX | 0:85b3fd62ea1a | 538 | DEBUG_PRINTF("SPI: RC=%u\n", rc); |
NYX | 0:85b3fd62ea1a | 539 | length = 0; |
NYX | 0:85b3fd62ea1a | 540 | } |
NYX | 0:85b3fd62ea1a | 541 | |
NYX | 0:85b3fd62ea1a | 542 | return length; |
NYX | 0:85b3fd62ea1a | 543 | } |
NYX | 0:85b3fd62ea1a | 544 | |
NYX | 0:85b3fd62ea1a | 545 | // asynchronous API |
NYX | 0:85b3fd62ea1a | 546 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) |
NYX | 0:85b3fd62ea1a | 547 | { |
NYX | 0:85b3fd62ea1a | 548 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 549 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 550 | |
NYX | 0:85b3fd62ea1a | 551 | // TODO: DMA usage is currently ignored |
NYX | 0:85b3fd62ea1a | 552 | (void) hint; |
NYX | 0:85b3fd62ea1a | 553 | |
NYX | 0:85b3fd62ea1a | 554 | // check which use-case we have |
NYX | 0:85b3fd62ea1a | 555 | bool use_tx = (tx != NULL && tx_length > 0); |
NYX | 0:85b3fd62ea1a | 556 | bool use_rx = (rx != NULL && rx_length > 0); |
NYX | 0:85b3fd62ea1a | 557 | bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT); |
NYX | 0:85b3fd62ea1a | 558 | |
NYX | 0:85b3fd62ea1a | 559 | // don't do anything, if the buffers aren't valid |
NYX | 0:85b3fd62ea1a | 560 | if (!use_tx && !use_rx) |
NYX | 0:85b3fd62ea1a | 561 | return; |
NYX | 0:85b3fd62ea1a | 562 | |
NYX | 0:85b3fd62ea1a | 563 | // copy the buffers to the SPI object |
NYX | 0:85b3fd62ea1a | 564 | obj->tx_buff.buffer = (void *) tx; |
NYX | 0:85b3fd62ea1a | 565 | obj->tx_buff.length = tx_length; |
NYX | 0:85b3fd62ea1a | 566 | obj->tx_buff.pos = 0; |
NYX | 0:85b3fd62ea1a | 567 | obj->tx_buff.width = is16bit ? 16 : 8; |
NYX | 0:85b3fd62ea1a | 568 | |
NYX | 0:85b3fd62ea1a | 569 | obj->rx_buff.buffer = rx; |
NYX | 0:85b3fd62ea1a | 570 | obj->rx_buff.length = rx_length; |
NYX | 0:85b3fd62ea1a | 571 | obj->rx_buff.pos = 0; |
NYX | 0:85b3fd62ea1a | 572 | obj->rx_buff.width = obj->tx_buff.width; |
NYX | 0:85b3fd62ea1a | 573 | |
NYX | 0:85b3fd62ea1a | 574 | obj->spi.event = event; |
NYX | 0:85b3fd62ea1a | 575 | |
NYX | 0:85b3fd62ea1a | 576 | DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length); |
NYX | 0:85b3fd62ea1a | 577 | |
NYX | 0:85b3fd62ea1a | 578 | // register the thunking handler |
NYX | 0:85b3fd62ea1a | 579 | IRQn_Type irq_n = spiobj->spiIRQ; |
NYX | 0:85b3fd62ea1a | 580 | NVIC_SetVector(irq_n, (uint32_t)handler); |
NYX | 0:85b3fd62ea1a | 581 | |
NYX | 0:85b3fd62ea1a | 582 | // enable the right hal transfer |
NYX | 0:85b3fd62ea1a | 583 | if (use_tx && use_rx) { |
NYX | 0:85b3fd62ea1a | 584 | // we cannot manage different rx / tx sizes, let's use smaller one |
NYX | 0:85b3fd62ea1a | 585 | size_t size = (tx_length < rx_length)? tx_length : rx_length; |
NYX | 0:85b3fd62ea1a | 586 | if(tx_length != rx_length) { |
NYX | 0:85b3fd62ea1a | 587 | DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size); |
NYX | 0:85b3fd62ea1a | 588 | obj->tx_buff.length = size; |
NYX | 0:85b3fd62ea1a | 589 | obj->rx_buff.length = size; |
NYX | 0:85b3fd62ea1a | 590 | } |
NYX | 0:85b3fd62ea1a | 591 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size); |
NYX | 0:85b3fd62ea1a | 592 | } else if (use_tx) { |
NYX | 0:85b3fd62ea1a | 593 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length); |
NYX | 0:85b3fd62ea1a | 594 | } else if (use_rx) { |
NYX | 0:85b3fd62ea1a | 595 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length); |
NYX | 0:85b3fd62ea1a | 596 | } |
NYX | 0:85b3fd62ea1a | 597 | } |
NYX | 0:85b3fd62ea1a | 598 | |
NYX | 0:85b3fd62ea1a | 599 | inline uint32_t spi_irq_handler_asynch(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 600 | { |
NYX | 0:85b3fd62ea1a | 601 | int event = 0; |
NYX | 0:85b3fd62ea1a | 602 | |
NYX | 0:85b3fd62ea1a | 603 | // call the CubeF4 handler, this will update the handle |
NYX | 0:85b3fd62ea1a | 604 | HAL_SPI_IRQHandler(&obj->spi.handle); |
NYX | 0:85b3fd62ea1a | 605 | |
NYX | 0:85b3fd62ea1a | 606 | if (obj->spi.handle.State == HAL_SPI_STATE_READY) { |
NYX | 0:85b3fd62ea1a | 607 | // When HAL SPI is back to READY state, check if there was an error |
NYX | 0:85b3fd62ea1a | 608 | int error = obj->spi.handle.ErrorCode; |
NYX | 0:85b3fd62ea1a | 609 | if(error != HAL_SPI_ERROR_NONE) { |
NYX | 0:85b3fd62ea1a | 610 | // something went wrong and the transfer has definitely completed |
NYX | 0:85b3fd62ea1a | 611 | event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; |
NYX | 0:85b3fd62ea1a | 612 | |
NYX | 0:85b3fd62ea1a | 613 | if (error & HAL_SPI_ERROR_OVR) { |
NYX | 0:85b3fd62ea1a | 614 | // buffer overrun |
NYX | 0:85b3fd62ea1a | 615 | event |= SPI_EVENT_RX_OVERFLOW; |
NYX | 0:85b3fd62ea1a | 616 | } |
NYX | 0:85b3fd62ea1a | 617 | } else { |
NYX | 0:85b3fd62ea1a | 618 | // else we're done |
NYX | 0:85b3fd62ea1a | 619 | event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; |
NYX | 0:85b3fd62ea1a | 620 | } |
NYX | 0:85b3fd62ea1a | 621 | // enable the interrupt |
NYX | 0:85b3fd62ea1a | 622 | NVIC_DisableIRQ(obj->spi.spiIRQ); |
NYX | 0:85b3fd62ea1a | 623 | NVIC_ClearPendingIRQ(obj->spi.spiIRQ); |
NYX | 0:85b3fd62ea1a | 624 | } |
NYX | 0:85b3fd62ea1a | 625 | |
NYX | 0:85b3fd62ea1a | 626 | |
NYX | 0:85b3fd62ea1a | 627 | return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)); |
NYX | 0:85b3fd62ea1a | 628 | } |
NYX | 0:85b3fd62ea1a | 629 | |
NYX | 0:85b3fd62ea1a | 630 | uint8_t spi_active(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 631 | { |
NYX | 0:85b3fd62ea1a | 632 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 633 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 634 | HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle); |
NYX | 0:85b3fd62ea1a | 635 | |
NYX | 0:85b3fd62ea1a | 636 | switch(state) { |
NYX | 0:85b3fd62ea1a | 637 | case HAL_SPI_STATE_RESET: |
NYX | 0:85b3fd62ea1a | 638 | case HAL_SPI_STATE_READY: |
NYX | 0:85b3fd62ea1a | 639 | case HAL_SPI_STATE_ERROR: |
NYX | 0:85b3fd62ea1a | 640 | return 0; |
NYX | 0:85b3fd62ea1a | 641 | default: |
NYX | 0:85b3fd62ea1a | 642 | return 1; |
NYX | 0:85b3fd62ea1a | 643 | } |
NYX | 0:85b3fd62ea1a | 644 | } |
NYX | 0:85b3fd62ea1a | 645 | |
NYX | 0:85b3fd62ea1a | 646 | void spi_abort_asynch(spi_t *obj) |
NYX | 0:85b3fd62ea1a | 647 | { |
NYX | 0:85b3fd62ea1a | 648 | struct spi_s *spiobj = SPI_S(obj); |
NYX | 0:85b3fd62ea1a | 649 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
NYX | 0:85b3fd62ea1a | 650 | |
NYX | 0:85b3fd62ea1a | 651 | // disable interrupt |
NYX | 0:85b3fd62ea1a | 652 | IRQn_Type irq_n = spiobj->spiIRQ; |
NYX | 0:85b3fd62ea1a | 653 | NVIC_ClearPendingIRQ(irq_n); |
NYX | 0:85b3fd62ea1a | 654 | NVIC_DisableIRQ(irq_n); |
NYX | 0:85b3fd62ea1a | 655 | |
NYX | 0:85b3fd62ea1a | 656 | // clean-up |
NYX | 0:85b3fd62ea1a | 657 | __HAL_SPI_DISABLE(handle); |
NYX | 0:85b3fd62ea1a | 658 | HAL_SPI_DeInit(handle); |
NYX | 0:85b3fd62ea1a | 659 | HAL_SPI_Init(handle); |
NYX | 0:85b3fd62ea1a | 660 | __HAL_SPI_ENABLE(handle); |
NYX | 0:85b3fd62ea1a | 661 | } |
NYX | 0:85b3fd62ea1a | 662 | |
NYX | 0:85b3fd62ea1a | 663 | #endif //DEVICE_SPI_ASYNCH |
NYX | 0:85b3fd62ea1a | 664 | |
NYX | 0:85b3fd62ea1a | 665 | #endif |