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cmsis/core_cm4.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/************************************************************************//
NYX	0:85b3fd62ea1a	2	* @file core_cm4.h
NYX	0:85b3fd62ea1a	3	* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
NYX	0:85b3fd62ea1a	4	* @version V5.0.2
NYX	0:85b3fd62ea1a	5	* @date 13. February 2017
NYX	0:85b3fd62ea1a	6	******************************************************************************/
NYX	0:85b3fd62ea1a	7	/*
NYX	0:85b3fd62ea1a	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
NYX	0:85b3fd62ea1a	9	*
NYX	0:85b3fd62ea1a	10	* SPDX-License-Identifier: Apache-2.0
NYX	0:85b3fd62ea1a	11	*
NYX	0:85b3fd62ea1a	12	* Licensed under the Apache License, Version 2.0 (the License); you may
NYX	0:85b3fd62ea1a	13	* not use this file except in compliance with the License.
NYX	0:85b3fd62ea1a	14	* You may obtain a copy of the License at
NYX	0:85b3fd62ea1a	15	*
NYX	0:85b3fd62ea1a	16	* www.apache.org/licenses/LICENSE-2.0
NYX	0:85b3fd62ea1a	17	*
NYX	0:85b3fd62ea1a	18	* Unless required by applicable law or agreed to in writing, software
NYX	0:85b3fd62ea1a	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
NYX	0:85b3fd62ea1a	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX	0:85b3fd62ea1a	21	* See the License for the specific language governing permissions and
NYX	0:85b3fd62ea1a	22	* limitations under the License.
NYX	0:85b3fd62ea1a	23	*/
NYX	0:85b3fd62ea1a	24
NYX	0:85b3fd62ea1a	25	#if defined ( __ICCARM__ )
NYX	0:85b3fd62ea1a	26	#pragma system_include /* treat file as system include file for MISRA check */
NYX	0:85b3fd62ea1a	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX	0:85b3fd62ea1a	28	#pragma clang system_header /* treat file as system include file */
NYX	0:85b3fd62ea1a	29	#endif
NYX	0:85b3fd62ea1a	30
NYX	0:85b3fd62ea1a	31	#ifndef __CORE_CM4_H_GENERIC
NYX	0:85b3fd62ea1a	32	#define __CORE_CM4_H_GENERIC
NYX	0:85b3fd62ea1a	33
NYX	0:85b3fd62ea1a	34	#include <stdint.h>
NYX	0:85b3fd62ea1a	35
NYX	0:85b3fd62ea1a	36	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	37	extern "C" {
NYX	0:85b3fd62ea1a	38	#endif
NYX	0:85b3fd62ea1a	39
NYX	0:85b3fd62ea1a	40	/**
NYX	0:85b3fd62ea1a	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
NYX	0:85b3fd62ea1a	42	CMSIS violates the following MISRA-C:2004 rules:
NYX	0:85b3fd62ea1a	43
NYX	0:85b3fd62ea1a	44	\li Required Rule 8.5, object/function definition in header file.<br>
NYX	0:85b3fd62ea1a	45	Function definitions in header files are used to allow 'inlining'.
NYX	0:85b3fd62ea1a	46
NYX	0:85b3fd62ea1a	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
NYX	0:85b3fd62ea1a	48	Unions are used for effective representation of core registers.
NYX	0:85b3fd62ea1a	49
NYX	0:85b3fd62ea1a	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
NYX	0:85b3fd62ea1a	51	Function-like macros are used to allow more efficient code.
NYX	0:85b3fd62ea1a	52	*/
NYX	0:85b3fd62ea1a	53
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/*******************************************************************************
NYX	0:85b3fd62ea1a	56	* CMSIS definitions
NYX	0:85b3fd62ea1a	57	******************************************************************************/
NYX	0:85b3fd62ea1a	58	/**
NYX	0:85b3fd62ea1a	59	\ingroup Cortex_M4
NYX	0:85b3fd62ea1a	60	@{
NYX	0:85b3fd62ea1a	61	*/
NYX	0:85b3fd62ea1a	62
NYX	0:85b3fd62ea1a	63	/* CMSIS CM4 definitions */
NYX	0:85b3fd62ea1a	64	#define __CM4_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
NYX	0:85b3fd62ea1a	65	#define __CM4_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
NYX	0:85b3fd62ea1a	66	#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) \| \
NYX	0:85b3fd62ea1a	67	__CM4_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
NYX	0:85b3fd62ea1a	68
NYX	0:85b3fd62ea1a	69	#define __CORTEX_M (4U) /!< Cortex-M Core /
NYX	0:85b3fd62ea1a	70
NYX	0:85b3fd62ea1a	71	/** __FPU_USED indicates whether an FPU is used or not.
NYX	0:85b3fd62ea1a	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
NYX	0:85b3fd62ea1a	73	*/
NYX	0:85b3fd62ea1a	74	#if defined ( __CC_ARM )
NYX	0:85b3fd62ea1a	75	#if defined __TARGET_FPU_VFP
NYX	0:85b3fd62ea1a	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	77	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	78	#else
NYX	0:85b3fd62ea1a	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	80	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	81	#endif
NYX	0:85b3fd62ea1a	82	#else
NYX	0:85b3fd62ea1a	83	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	84	#endif
NYX	0:85b3fd62ea1a	85
NYX	0:85b3fd62ea1a	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX	0:85b3fd62ea1a	87	#if defined __ARM_PCS_VFP
NYX	0:85b3fd62ea1a	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	89	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	90	#else
NYX	0:85b3fd62ea1a	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	92	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	93	#endif
NYX	0:85b3fd62ea1a	94	#else
NYX	0:85b3fd62ea1a	95	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	96	#endif
NYX	0:85b3fd62ea1a	97
NYX	0:85b3fd62ea1a	98	#elif defined ( __GNUC__ )
NYX	0:85b3fd62ea1a	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
NYX	0:85b3fd62ea1a	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	101	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	102	#else
NYX	0:85b3fd62ea1a	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	104	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	105	#endif
NYX	0:85b3fd62ea1a	106	#else
NYX	0:85b3fd62ea1a	107	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	108	#endif
NYX	0:85b3fd62ea1a	109
NYX	0:85b3fd62ea1a	110	#elif defined ( __ICCARM__ )
NYX	0:85b3fd62ea1a	111	#if defined __ARMVFP__
NYX	0:85b3fd62ea1a	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	113	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	114	#else
NYX	0:85b3fd62ea1a	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	116	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	117	#endif
NYX	0:85b3fd62ea1a	118	#else
NYX	0:85b3fd62ea1a	119	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	120	#endif
NYX	0:85b3fd62ea1a	121
NYX	0:85b3fd62ea1a	122	#elif defined ( __TI_ARM__ )
NYX	0:85b3fd62ea1a	123	#if defined __TI_VFP_SUPPORT__
NYX	0:85b3fd62ea1a	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	125	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	126	#else
NYX	0:85b3fd62ea1a	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	128	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	129	#endif
NYX	0:85b3fd62ea1a	130	#else
NYX	0:85b3fd62ea1a	131	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	132	#endif
NYX	0:85b3fd62ea1a	133
NYX	0:85b3fd62ea1a	134	#elif defined ( __TASKING__ )
NYX	0:85b3fd62ea1a	135	#if defined __FPU_VFP__
NYX	0:85b3fd62ea1a	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	137	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	138	#else
NYX	0:85b3fd62ea1a	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	140	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	141	#endif
NYX	0:85b3fd62ea1a	142	#else
NYX	0:85b3fd62ea1a	143	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	144	#endif
NYX	0:85b3fd62ea1a	145
NYX	0:85b3fd62ea1a	146	#elif defined ( __CSMC__ )
NYX	0:85b3fd62ea1a	147	#if ( __CSMC__ & 0x400U)
NYX	0:85b3fd62ea1a	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	149	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	150	#else
NYX	0:85b3fd62ea1a	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	152	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	153	#endif
NYX	0:85b3fd62ea1a	154	#else
NYX	0:85b3fd62ea1a	155	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	156	#endif
NYX	0:85b3fd62ea1a	157
NYX	0:85b3fd62ea1a	158	#endif
NYX	0:85b3fd62ea1a	159
NYX	0:85b3fd62ea1a	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
NYX	0:85b3fd62ea1a	161
NYX	0:85b3fd62ea1a	162
NYX	0:85b3fd62ea1a	163	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	164	}
NYX	0:85b3fd62ea1a	165	#endif
NYX	0:85b3fd62ea1a	166
NYX	0:85b3fd62ea1a	167	#endif /* __CORE_CM4_H_GENERIC */
NYX	0:85b3fd62ea1a	168
NYX	0:85b3fd62ea1a	169	#ifndef __CMSIS_GENERIC
NYX	0:85b3fd62ea1a	170
NYX	0:85b3fd62ea1a	171	#ifndef __CORE_CM4_H_DEPENDANT
NYX	0:85b3fd62ea1a	172	#define __CORE_CM4_H_DEPENDANT
NYX	0:85b3fd62ea1a	173
NYX	0:85b3fd62ea1a	174	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	175	extern "C" {
NYX	0:85b3fd62ea1a	176	#endif
NYX	0:85b3fd62ea1a	177
NYX	0:85b3fd62ea1a	178	/* check device defines and use defaults */
NYX	0:85b3fd62ea1a	179	#if defined __CHECK_DEVICE_DEFINES
NYX	0:85b3fd62ea1a	180	#ifndef __CM4_REV
NYX	0:85b3fd62ea1a	181	#define __CM4_REV 0x0000U
NYX	0:85b3fd62ea1a	182	#warning "__CM4_REV not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	183	#endif
NYX	0:85b3fd62ea1a	184
NYX	0:85b3fd62ea1a	185	#ifndef __FPU_PRESENT
NYX	0:85b3fd62ea1a	186	#define __FPU_PRESENT 0U
NYX	0:85b3fd62ea1a	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	188	#endif
NYX	0:85b3fd62ea1a	189
NYX	0:85b3fd62ea1a	190	#ifndef __MPU_PRESENT
NYX	0:85b3fd62ea1a	191	#define __MPU_PRESENT 0U
NYX	0:85b3fd62ea1a	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	193	#endif
NYX	0:85b3fd62ea1a	194
NYX	0:85b3fd62ea1a	195	#ifndef __NVIC_PRIO_BITS
NYX	0:85b3fd62ea1a	196	#define __NVIC_PRIO_BITS 3U
NYX	0:85b3fd62ea1a	197	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	198	#endif
NYX	0:85b3fd62ea1a	199
NYX	0:85b3fd62ea1a	200	#ifndef __Vendor_SysTickConfig
NYX	0:85b3fd62ea1a	201	#define __Vendor_SysTickConfig 0U
NYX	0:85b3fd62ea1a	202	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	203	#endif
NYX	0:85b3fd62ea1a	204	#endif
NYX	0:85b3fd62ea1a	205
NYX	0:85b3fd62ea1a	206	/* IO definitions (access restrictions to peripheral registers) */
NYX	0:85b3fd62ea1a	207	/**
NYX	0:85b3fd62ea1a	208	\defgroup CMSIS_glob_defs CMSIS Global Defines
NYX	0:85b3fd62ea1a	209
NYX	0:85b3fd62ea1a	210	<strong>IO Type Qualifiers</strong> are used
NYX	0:85b3fd62ea1a	211	\li to specify the access to peripheral variables.
NYX	0:85b3fd62ea1a	212	\li for automatic generation of peripheral register debug information.
NYX	0:85b3fd62ea1a	213	*/
NYX	0:85b3fd62ea1a	214	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	215	#define __I volatile /!< Defines 'read only' permissions /
NYX	0:85b3fd62ea1a	216	#else
NYX	0:85b3fd62ea1a	217	#define __I volatile const /!< Defines 'read only' permissions /
NYX	0:85b3fd62ea1a	218	#endif
NYX	0:85b3fd62ea1a	219	#define __O volatile /!< Defines 'write only' permissions /
NYX	0:85b3fd62ea1a	220	#define __IO volatile /!< Defines 'read / write' permissions /
NYX	0:85b3fd62ea1a	221
NYX	0:85b3fd62ea1a	222	/* following defines should be used for structure members */
NYX	0:85b3fd62ea1a	223	#define __IM volatile const /! Defines 'read only' structure member permissions /
NYX	0:85b3fd62ea1a	224	#define __OM volatile /! Defines 'write only' structure member permissions /
NYX	0:85b3fd62ea1a	225	#define __IOM volatile /! Defines 'read / write' structure member permissions /
NYX	0:85b3fd62ea1a	226
NYX	0:85b3fd62ea1a	227	/@} end of group Cortex_M4 /
NYX	0:85b3fd62ea1a	228
NYX	0:85b3fd62ea1a	229
NYX	0:85b3fd62ea1a	230
NYX	0:85b3fd62ea1a	231	/*******************************************************************************
NYX	0:85b3fd62ea1a	232	* Register Abstraction
NYX	0:85b3fd62ea1a	233	Core Register contain:
NYX	0:85b3fd62ea1a	234	- Core Register
NYX	0:85b3fd62ea1a	235	- Core NVIC Register
NYX	0:85b3fd62ea1a	236	- Core SCB Register
NYX	0:85b3fd62ea1a	237	- Core SysTick Register
NYX	0:85b3fd62ea1a	238	- Core Debug Register
NYX	0:85b3fd62ea1a	239	- Core MPU Register
NYX	0:85b3fd62ea1a	240	- Core FPU Register
NYX	0:85b3fd62ea1a	241	******************************************************************************/
NYX	0:85b3fd62ea1a	242	/**
NYX	0:85b3fd62ea1a	243	\defgroup CMSIS_core_register Defines and Type Definitions
NYX	0:85b3fd62ea1a	244	\brief Type definitions and defines for Cortex-M processor based devices.
NYX	0:85b3fd62ea1a	245	*/
NYX	0:85b3fd62ea1a	246
NYX	0:85b3fd62ea1a	247	/**
NYX	0:85b3fd62ea1a	248	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	249	\defgroup CMSIS_CORE Status and Control Registers
NYX	0:85b3fd62ea1a	250	\brief Core Register type definitions.
NYX	0:85b3fd62ea1a	251	@{
NYX	0:85b3fd62ea1a	252	*/
NYX	0:85b3fd62ea1a	253
NYX	0:85b3fd62ea1a	254	/**
NYX	0:85b3fd62ea1a	255	\brief Union type to access the Application Program Status Register (APSR).
NYX	0:85b3fd62ea1a	256	*/
NYX	0:85b3fd62ea1a	257	typedef union
NYX	0:85b3fd62ea1a	258	{
NYX	0:85b3fd62ea1a	259	struct
NYX	0:85b3fd62ea1a	260	{
NYX	0:85b3fd62ea1a	261	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
NYX	0:85b3fd62ea1a	262	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
NYX	0:85b3fd62ea1a	263	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
NYX	0:85b3fd62ea1a	264	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
NYX	0:85b3fd62ea1a	265	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
NYX	0:85b3fd62ea1a	266	uint32_t C:1; /!< bit: 29 Carry condition code flag /
NYX	0:85b3fd62ea1a	267	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
NYX	0:85b3fd62ea1a	268	uint32_t N:1; /!< bit: 31 Negative condition code flag /
NYX	0:85b3fd62ea1a	269	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	270	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	271	} APSR_Type;
NYX	0:85b3fd62ea1a	272
NYX	0:85b3fd62ea1a	273	/* APSR Register Definitions */
NYX	0:85b3fd62ea1a	274	#define APSR_N_Pos 31U /!< APSR: N Position /
NYX	0:85b3fd62ea1a	275	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
NYX	0:85b3fd62ea1a	276
NYX	0:85b3fd62ea1a	277	#define APSR_Z_Pos 30U /!< APSR: Z Position /
NYX	0:85b3fd62ea1a	278	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
NYX	0:85b3fd62ea1a	279
NYX	0:85b3fd62ea1a	280	#define APSR_C_Pos 29U /!< APSR: C Position /
NYX	0:85b3fd62ea1a	281	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
NYX	0:85b3fd62ea1a	282
NYX	0:85b3fd62ea1a	283	#define APSR_V_Pos 28U /!< APSR: V Position /
NYX	0:85b3fd62ea1a	284	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
NYX	0:85b3fd62ea1a	285
NYX	0:85b3fd62ea1a	286	#define APSR_Q_Pos 27U /!< APSR: Q Position /
NYX	0:85b3fd62ea1a	287	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
NYX	0:85b3fd62ea1a	288
NYX	0:85b3fd62ea1a	289	#define APSR_GE_Pos 16U /!< APSR: GE Position /
NYX	0:85b3fd62ea1a	290	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
NYX	0:85b3fd62ea1a	291
NYX	0:85b3fd62ea1a	292
NYX	0:85b3fd62ea1a	293	/**
NYX	0:85b3fd62ea1a	294	\brief Union type to access the Interrupt Program Status Register (IPSR).
NYX	0:85b3fd62ea1a	295	*/
NYX	0:85b3fd62ea1a	296	typedef union
NYX	0:85b3fd62ea1a	297	{
NYX	0:85b3fd62ea1a	298	struct
NYX	0:85b3fd62ea1a	299	{
NYX	0:85b3fd62ea1a	300	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
NYX	0:85b3fd62ea1a	301	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
NYX	0:85b3fd62ea1a	302	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	303	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	304	} IPSR_Type;
NYX	0:85b3fd62ea1a	305
NYX	0:85b3fd62ea1a	306	/* IPSR Register Definitions */
NYX	0:85b3fd62ea1a	307	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
NYX	0:85b3fd62ea1a	308	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
NYX	0:85b3fd62ea1a	309
NYX	0:85b3fd62ea1a	310
NYX	0:85b3fd62ea1a	311	/**
NYX	0:85b3fd62ea1a	312	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
NYX	0:85b3fd62ea1a	313	*/
NYX	0:85b3fd62ea1a	314	typedef union
NYX	0:85b3fd62ea1a	315	{
NYX	0:85b3fd62ea1a	316	struct
NYX	0:85b3fd62ea1a	317	{
NYX	0:85b3fd62ea1a	318	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
NYX	0:85b3fd62ea1a	319	uint32_t _reserved0:1; /!< bit: 9 Reserved /
NYX	0:85b3fd62ea1a	320	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
NYX	0:85b3fd62ea1a	321	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
NYX	0:85b3fd62ea1a	322	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
NYX	0:85b3fd62ea1a	323	uint32_t T:1; /!< bit: 24 Thumb bit /
NYX	0:85b3fd62ea1a	324	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
NYX	0:85b3fd62ea1a	325	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
NYX	0:85b3fd62ea1a	326	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
NYX	0:85b3fd62ea1a	327	uint32_t C:1; /!< bit: 29 Carry condition code flag /
NYX	0:85b3fd62ea1a	328	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
NYX	0:85b3fd62ea1a	329	uint32_t N:1; /!< bit: 31 Negative condition code flag /
NYX	0:85b3fd62ea1a	330	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	331	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	332	} xPSR_Type;
NYX	0:85b3fd62ea1a	333
NYX	0:85b3fd62ea1a	334	/* xPSR Register Definitions */
NYX	0:85b3fd62ea1a	335	#define xPSR_N_Pos 31U /!< xPSR: N Position /
NYX	0:85b3fd62ea1a	336	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
NYX	0:85b3fd62ea1a	337
NYX	0:85b3fd62ea1a	338	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
NYX	0:85b3fd62ea1a	339	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
NYX	0:85b3fd62ea1a	340
NYX	0:85b3fd62ea1a	341	#define xPSR_C_Pos 29U /!< xPSR: C Position /
NYX	0:85b3fd62ea1a	342	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
NYX	0:85b3fd62ea1a	343
NYX	0:85b3fd62ea1a	344	#define xPSR_V_Pos 28U /!< xPSR: V Position /
NYX	0:85b3fd62ea1a	345	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
NYX	0:85b3fd62ea1a	346
NYX	0:85b3fd62ea1a	347	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
NYX	0:85b3fd62ea1a	348	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
NYX	0:85b3fd62ea1a	349
NYX	0:85b3fd62ea1a	350	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
NYX	0:85b3fd62ea1a	351	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
NYX	0:85b3fd62ea1a	352
NYX	0:85b3fd62ea1a	353	#define xPSR_T_Pos 24U /!< xPSR: T Position /
NYX	0:85b3fd62ea1a	354	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
NYX	0:85b3fd62ea1a	355
NYX	0:85b3fd62ea1a	356	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
NYX	0:85b3fd62ea1a	357	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
NYX	0:85b3fd62ea1a	358
NYX	0:85b3fd62ea1a	359	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
NYX	0:85b3fd62ea1a	360	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
NYX	0:85b3fd62ea1a	361
NYX	0:85b3fd62ea1a	362	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
NYX	0:85b3fd62ea1a	363	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
NYX	0:85b3fd62ea1a	364
NYX	0:85b3fd62ea1a	365
NYX	0:85b3fd62ea1a	366	/**
NYX	0:85b3fd62ea1a	367	\brief Union type to access the Control Registers (CONTROL).
NYX	0:85b3fd62ea1a	368	*/
NYX	0:85b3fd62ea1a	369	typedef union
NYX	0:85b3fd62ea1a	370	{
NYX	0:85b3fd62ea1a	371	struct
NYX	0:85b3fd62ea1a	372	{
NYX	0:85b3fd62ea1a	373	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
NYX	0:85b3fd62ea1a	374	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
NYX	0:85b3fd62ea1a	375	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
NYX	0:85b3fd62ea1a	376	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
NYX	0:85b3fd62ea1a	377	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	378	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	379	} CONTROL_Type;
NYX	0:85b3fd62ea1a	380
NYX	0:85b3fd62ea1a	381	/* CONTROL Register Definitions */
NYX	0:85b3fd62ea1a	382	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
NYX	0:85b3fd62ea1a	383	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
NYX	0:85b3fd62ea1a	384
NYX	0:85b3fd62ea1a	385	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
NYX	0:85b3fd62ea1a	386	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
NYX	0:85b3fd62ea1a	387
NYX	0:85b3fd62ea1a	388	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
NYX	0:85b3fd62ea1a	389	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
NYX	0:85b3fd62ea1a	390
NYX	0:85b3fd62ea1a	391	/@} end of group CMSIS_CORE /
NYX	0:85b3fd62ea1a	392
NYX	0:85b3fd62ea1a	393
NYX	0:85b3fd62ea1a	394	/**
NYX	0:85b3fd62ea1a	395	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	396	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
NYX	0:85b3fd62ea1a	397	\brief Type definitions for the NVIC Registers
NYX	0:85b3fd62ea1a	398	@{
NYX	0:85b3fd62ea1a	399	*/
NYX	0:85b3fd62ea1a	400
NYX	0:85b3fd62ea1a	401	/**
NYX	0:85b3fd62ea1a	402	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
NYX	0:85b3fd62ea1a	403	*/
NYX	0:85b3fd62ea1a	404	typedef struct
NYX	0:85b3fd62ea1a	405	{
NYX	0:85b3fd62ea1a	406	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
NYX	0:85b3fd62ea1a	407	uint32_t RESERVED0[24U];
NYX	0:85b3fd62ea1a	408	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
NYX	0:85b3fd62ea1a	409	uint32_t RSERVED1[24U];
NYX	0:85b3fd62ea1a	410	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
NYX	0:85b3fd62ea1a	411	uint32_t RESERVED2[24U];
NYX	0:85b3fd62ea1a	412	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
NYX	0:85b3fd62ea1a	413	uint32_t RESERVED3[24U];
NYX	0:85b3fd62ea1a	414	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
NYX	0:85b3fd62ea1a	415	uint32_t RESERVED4[56U];
NYX	0:85b3fd62ea1a	416	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
NYX	0:85b3fd62ea1a	417	uint32_t RESERVED5[644U];
NYX	0:85b3fd62ea1a	418	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
NYX	0:85b3fd62ea1a	419	} NVIC_Type;
NYX	0:85b3fd62ea1a	420
NYX	0:85b3fd62ea1a	421	/* Software Triggered Interrupt Register Definitions */
NYX	0:85b3fd62ea1a	422	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
NYX	0:85b3fd62ea1a	423	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
NYX	0:85b3fd62ea1a	424
NYX	0:85b3fd62ea1a	425	/@} end of group CMSIS_NVIC /
NYX	0:85b3fd62ea1a	426
NYX	0:85b3fd62ea1a	427
NYX	0:85b3fd62ea1a	428	/**
NYX	0:85b3fd62ea1a	429	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	430	\defgroup CMSIS_SCB System Control Block (SCB)
NYX	0:85b3fd62ea1a	431	\brief Type definitions for the System Control Block Registers
NYX	0:85b3fd62ea1a	432	@{
NYX	0:85b3fd62ea1a	433	*/
NYX	0:85b3fd62ea1a	434
NYX	0:85b3fd62ea1a	435	/**
NYX	0:85b3fd62ea1a	436	\brief Structure type to access the System Control Block (SCB).
NYX	0:85b3fd62ea1a	437	*/
NYX	0:85b3fd62ea1a	438	typedef struct
NYX	0:85b3fd62ea1a	439	{
NYX	0:85b3fd62ea1a	440	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
NYX	0:85b3fd62ea1a	441	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
NYX	0:85b3fd62ea1a	442	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
NYX	0:85b3fd62ea1a	443	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
NYX	0:85b3fd62ea1a	444	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
NYX	0:85b3fd62ea1a	445	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
NYX	0:85b3fd62ea1a	446	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
NYX	0:85b3fd62ea1a	447	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
NYX	0:85b3fd62ea1a	448	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
NYX	0:85b3fd62ea1a	449	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
NYX	0:85b3fd62ea1a	450	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
NYX	0:85b3fd62ea1a	451	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
NYX	0:85b3fd62ea1a	452	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
NYX	0:85b3fd62ea1a	453	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
NYX	0:85b3fd62ea1a	454	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
NYX	0:85b3fd62ea1a	455	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
NYX	0:85b3fd62ea1a	456	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
NYX	0:85b3fd62ea1a	457	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
NYX	0:85b3fd62ea1a	458	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
NYX	0:85b3fd62ea1a	459	uint32_t RESERVED0[5U];
NYX	0:85b3fd62ea1a	460	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
NYX	0:85b3fd62ea1a	461	} SCB_Type;
NYX	0:85b3fd62ea1a	462
NYX	0:85b3fd62ea1a	463	/* SCB CPUID Register Definitions */
NYX	0:85b3fd62ea1a	464	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
NYX	0:85b3fd62ea1a	465	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
NYX	0:85b3fd62ea1a	466
NYX	0:85b3fd62ea1a	467	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
NYX	0:85b3fd62ea1a	468	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
NYX	0:85b3fd62ea1a	469
NYX	0:85b3fd62ea1a	470	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
NYX	0:85b3fd62ea1a	471	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
NYX	0:85b3fd62ea1a	472
NYX	0:85b3fd62ea1a	473	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
NYX	0:85b3fd62ea1a	474	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
NYX	0:85b3fd62ea1a	475
NYX	0:85b3fd62ea1a	476	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
NYX	0:85b3fd62ea1a	477	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
NYX	0:85b3fd62ea1a	478
NYX	0:85b3fd62ea1a	479	/* SCB Interrupt Control State Register Definitions */
NYX	0:85b3fd62ea1a	480	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
NYX	0:85b3fd62ea1a	481	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
NYX	0:85b3fd62ea1a	482
NYX	0:85b3fd62ea1a	483	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
NYX	0:85b3fd62ea1a	484	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
NYX	0:85b3fd62ea1a	485
NYX	0:85b3fd62ea1a	486	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
NYX	0:85b3fd62ea1a	487	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
NYX	0:85b3fd62ea1a	488
NYX	0:85b3fd62ea1a	489	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
NYX	0:85b3fd62ea1a	490	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
NYX	0:85b3fd62ea1a	491
NYX	0:85b3fd62ea1a	492	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
NYX	0:85b3fd62ea1a	493	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
NYX	0:85b3fd62ea1a	494
NYX	0:85b3fd62ea1a	495	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
NYX	0:85b3fd62ea1a	496	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
NYX	0:85b3fd62ea1a	497
NYX	0:85b3fd62ea1a	498	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
NYX	0:85b3fd62ea1a	499	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
NYX	0:85b3fd62ea1a	500
NYX	0:85b3fd62ea1a	501	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
NYX	0:85b3fd62ea1a	502	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
NYX	0:85b3fd62ea1a	503
NYX	0:85b3fd62ea1a	504	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
NYX	0:85b3fd62ea1a	505	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
NYX	0:85b3fd62ea1a	506
NYX	0:85b3fd62ea1a	507	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
NYX	0:85b3fd62ea1a	508	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
NYX	0:85b3fd62ea1a	509
NYX	0:85b3fd62ea1a	510	/* SCB Vector Table Offset Register Definitions */
NYX	0:85b3fd62ea1a	511	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
NYX	0:85b3fd62ea1a	512	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
NYX	0:85b3fd62ea1a	513
NYX	0:85b3fd62ea1a	514	/* SCB Application Interrupt and Reset Control Register Definitions */
NYX	0:85b3fd62ea1a	515	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
NYX	0:85b3fd62ea1a	516	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
NYX	0:85b3fd62ea1a	517
NYX	0:85b3fd62ea1a	518	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
NYX	0:85b3fd62ea1a	519	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
NYX	0:85b3fd62ea1a	520
NYX	0:85b3fd62ea1a	521	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
NYX	0:85b3fd62ea1a	522	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
NYX	0:85b3fd62ea1a	523
NYX	0:85b3fd62ea1a	524	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
NYX	0:85b3fd62ea1a	525	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
NYX	0:85b3fd62ea1a	526
NYX	0:85b3fd62ea1a	527	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
NYX	0:85b3fd62ea1a	528	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
NYX	0:85b3fd62ea1a	529
NYX	0:85b3fd62ea1a	530	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
NYX	0:85b3fd62ea1a	531	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
NYX	0:85b3fd62ea1a	532
NYX	0:85b3fd62ea1a	533	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
NYX	0:85b3fd62ea1a	534	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
NYX	0:85b3fd62ea1a	535
NYX	0:85b3fd62ea1a	536	/* SCB System Control Register Definitions */
NYX	0:85b3fd62ea1a	537	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
NYX	0:85b3fd62ea1a	538	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
NYX	0:85b3fd62ea1a	539
NYX	0:85b3fd62ea1a	540	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
NYX	0:85b3fd62ea1a	541	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
NYX	0:85b3fd62ea1a	542
NYX	0:85b3fd62ea1a	543	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
NYX	0:85b3fd62ea1a	544	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
NYX	0:85b3fd62ea1a	545
NYX	0:85b3fd62ea1a	546	/* SCB Configuration Control Register Definitions */
NYX	0:85b3fd62ea1a	547	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
NYX	0:85b3fd62ea1a	548	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
NYX	0:85b3fd62ea1a	549
NYX	0:85b3fd62ea1a	550	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
NYX	0:85b3fd62ea1a	551	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
NYX	0:85b3fd62ea1a	552
NYX	0:85b3fd62ea1a	553	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
NYX	0:85b3fd62ea1a	554	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
NYX	0:85b3fd62ea1a	555
NYX	0:85b3fd62ea1a	556	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
NYX	0:85b3fd62ea1a	557	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
NYX	0:85b3fd62ea1a	558
NYX	0:85b3fd62ea1a	559	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
NYX	0:85b3fd62ea1a	560	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
NYX	0:85b3fd62ea1a	561
NYX	0:85b3fd62ea1a	562	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
NYX	0:85b3fd62ea1a	563	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
NYX	0:85b3fd62ea1a	564
NYX	0:85b3fd62ea1a	565	/* SCB System Handler Control and State Register Definitions */
NYX	0:85b3fd62ea1a	566	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
NYX	0:85b3fd62ea1a	567	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
NYX	0:85b3fd62ea1a	568
NYX	0:85b3fd62ea1a	569	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
NYX	0:85b3fd62ea1a	570	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
NYX	0:85b3fd62ea1a	571
NYX	0:85b3fd62ea1a	572	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
NYX	0:85b3fd62ea1a	573	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
NYX	0:85b3fd62ea1a	574
NYX	0:85b3fd62ea1a	575	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
NYX	0:85b3fd62ea1a	576	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
NYX	0:85b3fd62ea1a	577
NYX	0:85b3fd62ea1a	578	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
NYX	0:85b3fd62ea1a	579	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	580
NYX	0:85b3fd62ea1a	581	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
NYX	0:85b3fd62ea1a	582	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	583
NYX	0:85b3fd62ea1a	584	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
NYX	0:85b3fd62ea1a	585	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	586
NYX	0:85b3fd62ea1a	587	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
NYX	0:85b3fd62ea1a	588	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
NYX	0:85b3fd62ea1a	589
NYX	0:85b3fd62ea1a	590	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
NYX	0:85b3fd62ea1a	591	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
NYX	0:85b3fd62ea1a	592
NYX	0:85b3fd62ea1a	593	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
NYX	0:85b3fd62ea1a	594	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
NYX	0:85b3fd62ea1a	595
NYX	0:85b3fd62ea1a	596	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
NYX	0:85b3fd62ea1a	597	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
NYX	0:85b3fd62ea1a	598
NYX	0:85b3fd62ea1a	599	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
NYX	0:85b3fd62ea1a	600	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
NYX	0:85b3fd62ea1a	601
NYX	0:85b3fd62ea1a	602	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
NYX	0:85b3fd62ea1a	603	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
NYX	0:85b3fd62ea1a	604
NYX	0:85b3fd62ea1a	605	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
NYX	0:85b3fd62ea1a	606	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
NYX	0:85b3fd62ea1a	607
NYX	0:85b3fd62ea1a	608	/* SCB Configurable Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	609	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
NYX	0:85b3fd62ea1a	610	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
NYX	0:85b3fd62ea1a	611
NYX	0:85b3fd62ea1a	612	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
NYX	0:85b3fd62ea1a	613	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
NYX	0:85b3fd62ea1a	614
NYX	0:85b3fd62ea1a	615	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
NYX	0:85b3fd62ea1a	616	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
NYX	0:85b3fd62ea1a	617
NYX	0:85b3fd62ea1a	618	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	619	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
NYX	0:85b3fd62ea1a	620	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
NYX	0:85b3fd62ea1a	621
NYX	0:85b3fd62ea1a	622	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
NYX	0:85b3fd62ea1a	623	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
NYX	0:85b3fd62ea1a	624
NYX	0:85b3fd62ea1a	625	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
NYX	0:85b3fd62ea1a	626	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
NYX	0:85b3fd62ea1a	627
NYX	0:85b3fd62ea1a	628	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
NYX	0:85b3fd62ea1a	629	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
NYX	0:85b3fd62ea1a	630
NYX	0:85b3fd62ea1a	631	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
NYX	0:85b3fd62ea1a	632	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
NYX	0:85b3fd62ea1a	633
NYX	0:85b3fd62ea1a	634	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
NYX	0:85b3fd62ea1a	635	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
NYX	0:85b3fd62ea1a	636
NYX	0:85b3fd62ea1a	637	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	638	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
NYX	0:85b3fd62ea1a	639	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
NYX	0:85b3fd62ea1a	640
NYX	0:85b3fd62ea1a	641	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
NYX	0:85b3fd62ea1a	642	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
NYX	0:85b3fd62ea1a	643
NYX	0:85b3fd62ea1a	644	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
NYX	0:85b3fd62ea1a	645	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
NYX	0:85b3fd62ea1a	646
NYX	0:85b3fd62ea1a	647	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
NYX	0:85b3fd62ea1a	648	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
NYX	0:85b3fd62ea1a	649
NYX	0:85b3fd62ea1a	650	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
NYX	0:85b3fd62ea1a	651	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
NYX	0:85b3fd62ea1a	652
NYX	0:85b3fd62ea1a	653	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
NYX	0:85b3fd62ea1a	654	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
NYX	0:85b3fd62ea1a	655
NYX	0:85b3fd62ea1a	656	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
NYX	0:85b3fd62ea1a	657	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
NYX	0:85b3fd62ea1a	658
NYX	0:85b3fd62ea1a	659	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	660	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
NYX	0:85b3fd62ea1a	661	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
NYX	0:85b3fd62ea1a	662
NYX	0:85b3fd62ea1a	663	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
NYX	0:85b3fd62ea1a	664	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
NYX	0:85b3fd62ea1a	665
NYX	0:85b3fd62ea1a	666	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
NYX	0:85b3fd62ea1a	667	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
NYX	0:85b3fd62ea1a	668
NYX	0:85b3fd62ea1a	669	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
NYX	0:85b3fd62ea1a	670	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
NYX	0:85b3fd62ea1a	671
NYX	0:85b3fd62ea1a	672	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
NYX	0:85b3fd62ea1a	673	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
NYX	0:85b3fd62ea1a	674
NYX	0:85b3fd62ea1a	675	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
NYX	0:85b3fd62ea1a	676	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
NYX	0:85b3fd62ea1a	677
NYX	0:85b3fd62ea1a	678	/* SCB Hard Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	679	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
NYX	0:85b3fd62ea1a	680	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
NYX	0:85b3fd62ea1a	681
NYX	0:85b3fd62ea1a	682	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
NYX	0:85b3fd62ea1a	683	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
NYX	0:85b3fd62ea1a	684
NYX	0:85b3fd62ea1a	685	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
NYX	0:85b3fd62ea1a	686	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
NYX	0:85b3fd62ea1a	687
NYX	0:85b3fd62ea1a	688	/* SCB Debug Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	689	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
NYX	0:85b3fd62ea1a	690	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
NYX	0:85b3fd62ea1a	691
NYX	0:85b3fd62ea1a	692	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
NYX	0:85b3fd62ea1a	693	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
NYX	0:85b3fd62ea1a	694
NYX	0:85b3fd62ea1a	695	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
NYX	0:85b3fd62ea1a	696	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
NYX	0:85b3fd62ea1a	697
NYX	0:85b3fd62ea1a	698	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
NYX	0:85b3fd62ea1a	699	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
NYX	0:85b3fd62ea1a	700
NYX	0:85b3fd62ea1a	701	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
NYX	0:85b3fd62ea1a	702	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
NYX	0:85b3fd62ea1a	703
NYX	0:85b3fd62ea1a	704	/@} end of group CMSIS_SCB /
NYX	0:85b3fd62ea1a	705
NYX	0:85b3fd62ea1a	706
NYX	0:85b3fd62ea1a	707	/**
NYX	0:85b3fd62ea1a	708	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	709	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
NYX	0:85b3fd62ea1a	710	\brief Type definitions for the System Control and ID Register not in the SCB
NYX	0:85b3fd62ea1a	711	@{
NYX	0:85b3fd62ea1a	712	*/
NYX	0:85b3fd62ea1a	713
NYX	0:85b3fd62ea1a	714	/**
NYX	0:85b3fd62ea1a	715	\brief Structure type to access the System Control and ID Register not in the SCB.
NYX	0:85b3fd62ea1a	716	*/
NYX	0:85b3fd62ea1a	717	typedef struct
NYX	0:85b3fd62ea1a	718	{
NYX	0:85b3fd62ea1a	719	uint32_t RESERVED0[1U];
NYX	0:85b3fd62ea1a	720	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
NYX	0:85b3fd62ea1a	721	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
NYX	0:85b3fd62ea1a	722	} SCnSCB_Type;
NYX	0:85b3fd62ea1a	723
NYX	0:85b3fd62ea1a	724	/* Interrupt Controller Type Register Definitions */
NYX	0:85b3fd62ea1a	725	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
NYX	0:85b3fd62ea1a	726	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
NYX	0:85b3fd62ea1a	727
NYX	0:85b3fd62ea1a	728	/* Auxiliary Control Register Definitions */
NYX	0:85b3fd62ea1a	729	#define SCnSCB_ACTLR_DISOOFP_Pos 9U /!< ACTLR: DISOOFP Position /
NYX	0:85b3fd62ea1a	730	#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /!< ACTLR: DISOOFP Mask /
NYX	0:85b3fd62ea1a	731
NYX	0:85b3fd62ea1a	732	#define SCnSCB_ACTLR_DISFPCA_Pos 8U /!< ACTLR: DISFPCA Position /
NYX	0:85b3fd62ea1a	733	#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /!< ACTLR: DISFPCA Mask /
NYX	0:85b3fd62ea1a	734
NYX	0:85b3fd62ea1a	735	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
NYX	0:85b3fd62ea1a	736	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
NYX	0:85b3fd62ea1a	737
NYX	0:85b3fd62ea1a	738	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
NYX	0:85b3fd62ea1a	739	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
NYX	0:85b3fd62ea1a	740
NYX	0:85b3fd62ea1a	741	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
NYX	0:85b3fd62ea1a	742	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
NYX	0:85b3fd62ea1a	743
NYX	0:85b3fd62ea1a	744	/@} end of group CMSIS_SCnotSCB /
NYX	0:85b3fd62ea1a	745
NYX	0:85b3fd62ea1a	746
NYX	0:85b3fd62ea1a	747	/**
NYX	0:85b3fd62ea1a	748	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	749	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
NYX	0:85b3fd62ea1a	750	\brief Type definitions for the System Timer Registers.
NYX	0:85b3fd62ea1a	751	@{
NYX	0:85b3fd62ea1a	752	*/
NYX	0:85b3fd62ea1a	753
NYX	0:85b3fd62ea1a	754	/**
NYX	0:85b3fd62ea1a	755	\brief Structure type to access the System Timer (SysTick).
NYX	0:85b3fd62ea1a	756	*/
NYX	0:85b3fd62ea1a	757	typedef struct
NYX	0:85b3fd62ea1a	758	{
NYX	0:85b3fd62ea1a	759	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
NYX	0:85b3fd62ea1a	760	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
NYX	0:85b3fd62ea1a	761	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
NYX	0:85b3fd62ea1a	762	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
NYX	0:85b3fd62ea1a	763	} SysTick_Type;
NYX	0:85b3fd62ea1a	764
NYX	0:85b3fd62ea1a	765	/* SysTick Control / Status Register Definitions */
NYX	0:85b3fd62ea1a	766	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
NYX	0:85b3fd62ea1a	767	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
NYX	0:85b3fd62ea1a	768
NYX	0:85b3fd62ea1a	769	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
NYX	0:85b3fd62ea1a	770	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
NYX	0:85b3fd62ea1a	771
NYX	0:85b3fd62ea1a	772	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
NYX	0:85b3fd62ea1a	773	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
NYX	0:85b3fd62ea1a	774
NYX	0:85b3fd62ea1a	775	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
NYX	0:85b3fd62ea1a	776	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
NYX	0:85b3fd62ea1a	777
NYX	0:85b3fd62ea1a	778	/* SysTick Reload Register Definitions */
NYX	0:85b3fd62ea1a	779	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
NYX	0:85b3fd62ea1a	780	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
NYX	0:85b3fd62ea1a	781
NYX	0:85b3fd62ea1a	782	/* SysTick Current Register Definitions */
NYX	0:85b3fd62ea1a	783	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
NYX	0:85b3fd62ea1a	784	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
NYX	0:85b3fd62ea1a	785
NYX	0:85b3fd62ea1a	786	/* SysTick Calibration Register Definitions */
NYX	0:85b3fd62ea1a	787	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
NYX	0:85b3fd62ea1a	788	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
NYX	0:85b3fd62ea1a	789
NYX	0:85b3fd62ea1a	790	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
NYX	0:85b3fd62ea1a	791	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
NYX	0:85b3fd62ea1a	792
NYX	0:85b3fd62ea1a	793	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
NYX	0:85b3fd62ea1a	794	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
NYX	0:85b3fd62ea1a	795
NYX	0:85b3fd62ea1a	796	/@} end of group CMSIS_SysTick /
NYX	0:85b3fd62ea1a	797
NYX	0:85b3fd62ea1a	798
NYX	0:85b3fd62ea1a	799	/**
NYX	0:85b3fd62ea1a	800	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	801	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
NYX	0:85b3fd62ea1a	802	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
NYX	0:85b3fd62ea1a	803	@{
NYX	0:85b3fd62ea1a	804	*/
NYX	0:85b3fd62ea1a	805
NYX	0:85b3fd62ea1a	806	/**
NYX	0:85b3fd62ea1a	807	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
NYX	0:85b3fd62ea1a	808	*/
NYX	0:85b3fd62ea1a	809	typedef struct
NYX	0:85b3fd62ea1a	810	{
NYX	0:85b3fd62ea1a	811	__OM union
NYX	0:85b3fd62ea1a	812	{
NYX	0:85b3fd62ea1a	813	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
NYX	0:85b3fd62ea1a	814	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
NYX	0:85b3fd62ea1a	815	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
NYX	0:85b3fd62ea1a	816	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
NYX	0:85b3fd62ea1a	817	uint32_t RESERVED0[864U];
NYX	0:85b3fd62ea1a	818	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
NYX	0:85b3fd62ea1a	819	uint32_t RESERVED1[15U];
NYX	0:85b3fd62ea1a	820	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
NYX	0:85b3fd62ea1a	821	uint32_t RESERVED2[15U];
NYX	0:85b3fd62ea1a	822	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
NYX	0:85b3fd62ea1a	823	uint32_t RESERVED3[29U];
NYX	0:85b3fd62ea1a	824	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
NYX	0:85b3fd62ea1a	825	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
NYX	0:85b3fd62ea1a	826	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
NYX	0:85b3fd62ea1a	827	uint32_t RESERVED4[43U];
NYX	0:85b3fd62ea1a	828	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
NYX	0:85b3fd62ea1a	829	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
NYX	0:85b3fd62ea1a	830	uint32_t RESERVED5[6U];
NYX	0:85b3fd62ea1a	831	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
NYX	0:85b3fd62ea1a	832	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
NYX	0:85b3fd62ea1a	833	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
NYX	0:85b3fd62ea1a	834	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
NYX	0:85b3fd62ea1a	835	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
NYX	0:85b3fd62ea1a	836	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
NYX	0:85b3fd62ea1a	837	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
NYX	0:85b3fd62ea1a	838	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
NYX	0:85b3fd62ea1a	839	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
NYX	0:85b3fd62ea1a	840	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
NYX	0:85b3fd62ea1a	841	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
NYX	0:85b3fd62ea1a	842	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
NYX	0:85b3fd62ea1a	843	} ITM_Type;
NYX	0:85b3fd62ea1a	844
NYX	0:85b3fd62ea1a	845	/* ITM Trace Privilege Register Definitions */
NYX	0:85b3fd62ea1a	846	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
NYX	0:85b3fd62ea1a	847	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
NYX	0:85b3fd62ea1a	848
NYX	0:85b3fd62ea1a	849	/* ITM Trace Control Register Definitions */
NYX	0:85b3fd62ea1a	850	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
NYX	0:85b3fd62ea1a	851	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
NYX	0:85b3fd62ea1a	852
NYX	0:85b3fd62ea1a	853	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
NYX	0:85b3fd62ea1a	854	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
NYX	0:85b3fd62ea1a	855
NYX	0:85b3fd62ea1a	856	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
NYX	0:85b3fd62ea1a	857	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
NYX	0:85b3fd62ea1a	858
NYX	0:85b3fd62ea1a	859	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
NYX	0:85b3fd62ea1a	860	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
NYX	0:85b3fd62ea1a	861
NYX	0:85b3fd62ea1a	862	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
NYX	0:85b3fd62ea1a	863	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
NYX	0:85b3fd62ea1a	864
NYX	0:85b3fd62ea1a	865	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
NYX	0:85b3fd62ea1a	866	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
NYX	0:85b3fd62ea1a	867
NYX	0:85b3fd62ea1a	868	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
NYX	0:85b3fd62ea1a	869	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
NYX	0:85b3fd62ea1a	870
NYX	0:85b3fd62ea1a	871	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
NYX	0:85b3fd62ea1a	872	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
NYX	0:85b3fd62ea1a	873
NYX	0:85b3fd62ea1a	874	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
NYX	0:85b3fd62ea1a	875	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
NYX	0:85b3fd62ea1a	876
NYX	0:85b3fd62ea1a	877	/* ITM Integration Write Register Definitions */
NYX	0:85b3fd62ea1a	878	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
NYX	0:85b3fd62ea1a	879	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
NYX	0:85b3fd62ea1a	880
NYX	0:85b3fd62ea1a	881	/* ITM Integration Read Register Definitions */
NYX	0:85b3fd62ea1a	882	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
NYX	0:85b3fd62ea1a	883	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
NYX	0:85b3fd62ea1a	884
NYX	0:85b3fd62ea1a	885	/* ITM Integration Mode Control Register Definitions */
NYX	0:85b3fd62ea1a	886	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
NYX	0:85b3fd62ea1a	887	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
NYX	0:85b3fd62ea1a	888
NYX	0:85b3fd62ea1a	889	/* ITM Lock Status Register Definitions */
NYX	0:85b3fd62ea1a	890	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
NYX	0:85b3fd62ea1a	891	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
NYX	0:85b3fd62ea1a	892
NYX	0:85b3fd62ea1a	893	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
NYX	0:85b3fd62ea1a	894	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
NYX	0:85b3fd62ea1a	895
NYX	0:85b3fd62ea1a	896	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
NYX	0:85b3fd62ea1a	897	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
NYX	0:85b3fd62ea1a	898
NYX	0:85b3fd62ea1a	899	/@}/ /* end of group CMSIS_ITM */
NYX	0:85b3fd62ea1a	900
NYX	0:85b3fd62ea1a	901
NYX	0:85b3fd62ea1a	902	/**
NYX	0:85b3fd62ea1a	903	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	904	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
NYX	0:85b3fd62ea1a	905	\brief Type definitions for the Data Watchpoint and Trace (DWT)
NYX	0:85b3fd62ea1a	906	@{
NYX	0:85b3fd62ea1a	907	*/
NYX	0:85b3fd62ea1a	908
NYX	0:85b3fd62ea1a	909	/**
NYX	0:85b3fd62ea1a	910	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
NYX	0:85b3fd62ea1a	911	*/
NYX	0:85b3fd62ea1a	912	typedef struct
NYX	0:85b3fd62ea1a	913	{
NYX	0:85b3fd62ea1a	914	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
NYX	0:85b3fd62ea1a	915	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
NYX	0:85b3fd62ea1a	916	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
NYX	0:85b3fd62ea1a	917	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
NYX	0:85b3fd62ea1a	918	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
NYX	0:85b3fd62ea1a	919	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
NYX	0:85b3fd62ea1a	920	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
NYX	0:85b3fd62ea1a	921	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
NYX	0:85b3fd62ea1a	922	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
NYX	0:85b3fd62ea1a	923	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
NYX	0:85b3fd62ea1a	924	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
NYX	0:85b3fd62ea1a	925	uint32_t RESERVED0[1U];
NYX	0:85b3fd62ea1a	926	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
NYX	0:85b3fd62ea1a	927	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
NYX	0:85b3fd62ea1a	928	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
NYX	0:85b3fd62ea1a	929	uint32_t RESERVED1[1U];
NYX	0:85b3fd62ea1a	930	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
NYX	0:85b3fd62ea1a	931	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
NYX	0:85b3fd62ea1a	932	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
NYX	0:85b3fd62ea1a	933	uint32_t RESERVED2[1U];
NYX	0:85b3fd62ea1a	934	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
NYX	0:85b3fd62ea1a	935	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
NYX	0:85b3fd62ea1a	936	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
NYX	0:85b3fd62ea1a	937	} DWT_Type;
NYX	0:85b3fd62ea1a	938
NYX	0:85b3fd62ea1a	939	/* DWT Control Register Definitions */
NYX	0:85b3fd62ea1a	940	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
NYX	0:85b3fd62ea1a	941	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
NYX	0:85b3fd62ea1a	942
NYX	0:85b3fd62ea1a	943	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
NYX	0:85b3fd62ea1a	944	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
NYX	0:85b3fd62ea1a	945
NYX	0:85b3fd62ea1a	946	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
NYX	0:85b3fd62ea1a	947	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
NYX	0:85b3fd62ea1a	948
NYX	0:85b3fd62ea1a	949	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
NYX	0:85b3fd62ea1a	950	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
NYX	0:85b3fd62ea1a	951
NYX	0:85b3fd62ea1a	952	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
NYX	0:85b3fd62ea1a	953	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
NYX	0:85b3fd62ea1a	954
NYX	0:85b3fd62ea1a	955	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
NYX	0:85b3fd62ea1a	956	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
NYX	0:85b3fd62ea1a	957
NYX	0:85b3fd62ea1a	958	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
NYX	0:85b3fd62ea1a	959	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
NYX	0:85b3fd62ea1a	960
NYX	0:85b3fd62ea1a	961	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
NYX	0:85b3fd62ea1a	962	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
NYX	0:85b3fd62ea1a	963
NYX	0:85b3fd62ea1a	964	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
NYX	0:85b3fd62ea1a	965	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
NYX	0:85b3fd62ea1a	966
NYX	0:85b3fd62ea1a	967	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
NYX	0:85b3fd62ea1a	968	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
NYX	0:85b3fd62ea1a	969
NYX	0:85b3fd62ea1a	970	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
NYX	0:85b3fd62ea1a	971	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
NYX	0:85b3fd62ea1a	972
NYX	0:85b3fd62ea1a	973	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
NYX	0:85b3fd62ea1a	974	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
NYX	0:85b3fd62ea1a	975
NYX	0:85b3fd62ea1a	976	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
NYX	0:85b3fd62ea1a	977	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
NYX	0:85b3fd62ea1a	978
NYX	0:85b3fd62ea1a	979	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
NYX	0:85b3fd62ea1a	980	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
NYX	0:85b3fd62ea1a	981
NYX	0:85b3fd62ea1a	982	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
NYX	0:85b3fd62ea1a	983	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
NYX	0:85b3fd62ea1a	984
NYX	0:85b3fd62ea1a	985	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
NYX	0:85b3fd62ea1a	986	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
NYX	0:85b3fd62ea1a	987
NYX	0:85b3fd62ea1a	988	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
NYX	0:85b3fd62ea1a	989	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
NYX	0:85b3fd62ea1a	990
NYX	0:85b3fd62ea1a	991	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
NYX	0:85b3fd62ea1a	992	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
NYX	0:85b3fd62ea1a	993
NYX	0:85b3fd62ea1a	994	/* DWT CPI Count Register Definitions */
NYX	0:85b3fd62ea1a	995	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
NYX	0:85b3fd62ea1a	996	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
NYX	0:85b3fd62ea1a	997
NYX	0:85b3fd62ea1a	998	/* DWT Exception Overhead Count Register Definitions */
NYX	0:85b3fd62ea1a	999	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
NYX	0:85b3fd62ea1a	1000	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
NYX	0:85b3fd62ea1a	1001
NYX	0:85b3fd62ea1a	1002	/* DWT Sleep Count Register Definitions */
NYX	0:85b3fd62ea1a	1003	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
NYX	0:85b3fd62ea1a	1004	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
NYX	0:85b3fd62ea1a	1005
NYX	0:85b3fd62ea1a	1006	/* DWT LSU Count Register Definitions */
NYX	0:85b3fd62ea1a	1007	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
NYX	0:85b3fd62ea1a	1008	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
NYX	0:85b3fd62ea1a	1009
NYX	0:85b3fd62ea1a	1010	/* DWT Folded-instruction Count Register Definitions */
NYX	0:85b3fd62ea1a	1011	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
NYX	0:85b3fd62ea1a	1012	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
NYX	0:85b3fd62ea1a	1013
NYX	0:85b3fd62ea1a	1014	/* DWT Comparator Mask Register Definitions */
NYX	0:85b3fd62ea1a	1015	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
NYX	0:85b3fd62ea1a	1016	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
NYX	0:85b3fd62ea1a	1017
NYX	0:85b3fd62ea1a	1018	/* DWT Comparator Function Register Definitions */
NYX	0:85b3fd62ea1a	1019	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
NYX	0:85b3fd62ea1a	1020	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
NYX	0:85b3fd62ea1a	1021
NYX	0:85b3fd62ea1a	1022	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
NYX	0:85b3fd62ea1a	1023	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
NYX	0:85b3fd62ea1a	1024
NYX	0:85b3fd62ea1a	1025	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
NYX	0:85b3fd62ea1a	1026	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
NYX	0:85b3fd62ea1a	1027
NYX	0:85b3fd62ea1a	1028	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
NYX	0:85b3fd62ea1a	1029	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
NYX	0:85b3fd62ea1a	1030
NYX	0:85b3fd62ea1a	1031	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
NYX	0:85b3fd62ea1a	1032	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
NYX	0:85b3fd62ea1a	1033
NYX	0:85b3fd62ea1a	1034	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
NYX	0:85b3fd62ea1a	1035	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
NYX	0:85b3fd62ea1a	1036
NYX	0:85b3fd62ea1a	1037	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
NYX	0:85b3fd62ea1a	1038	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
NYX	0:85b3fd62ea1a	1039
NYX	0:85b3fd62ea1a	1040	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
NYX	0:85b3fd62ea1a	1041	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
NYX	0:85b3fd62ea1a	1042
NYX	0:85b3fd62ea1a	1043	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
NYX	0:85b3fd62ea1a	1044	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
NYX	0:85b3fd62ea1a	1045
NYX	0:85b3fd62ea1a	1046	/@}/ /* end of group CMSIS_DWT */
NYX	0:85b3fd62ea1a	1047
NYX	0:85b3fd62ea1a	1048
NYX	0:85b3fd62ea1a	1049	/**
NYX	0:85b3fd62ea1a	1050	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1051	\defgroup CMSIS_TPI Trace Port Interface (TPI)
NYX	0:85b3fd62ea1a	1052	\brief Type definitions for the Trace Port Interface (TPI)
NYX	0:85b3fd62ea1a	1053	@{
NYX	0:85b3fd62ea1a	1054	*/
NYX	0:85b3fd62ea1a	1055
NYX	0:85b3fd62ea1a	1056	/**
NYX	0:85b3fd62ea1a	1057	\brief Structure type to access the Trace Port Interface Register (TPI).
NYX	0:85b3fd62ea1a	1058	*/
NYX	0:85b3fd62ea1a	1059	typedef struct
NYX	0:85b3fd62ea1a	1060	{
NYX	0:85b3fd62ea1a	1061	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
NYX	0:85b3fd62ea1a	1062	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
NYX	0:85b3fd62ea1a	1063	uint32_t RESERVED0[2U];
NYX	0:85b3fd62ea1a	1064	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
NYX	0:85b3fd62ea1a	1065	uint32_t RESERVED1[55U];
NYX	0:85b3fd62ea1a	1066	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
NYX	0:85b3fd62ea1a	1067	uint32_t RESERVED2[131U];
NYX	0:85b3fd62ea1a	1068	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
NYX	0:85b3fd62ea1a	1069	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
NYX	0:85b3fd62ea1a	1070	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
NYX	0:85b3fd62ea1a	1071	uint32_t RESERVED3[759U];
NYX	0:85b3fd62ea1a	1072	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
NYX	0:85b3fd62ea1a	1073	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
NYX	0:85b3fd62ea1a	1074	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
NYX	0:85b3fd62ea1a	1075	uint32_t RESERVED4[1U];
NYX	0:85b3fd62ea1a	1076	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
NYX	0:85b3fd62ea1a	1077	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
NYX	0:85b3fd62ea1a	1078	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
NYX	0:85b3fd62ea1a	1079	uint32_t RESERVED5[39U];
NYX	0:85b3fd62ea1a	1080	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
NYX	0:85b3fd62ea1a	1081	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
NYX	0:85b3fd62ea1a	1082	uint32_t RESERVED7[8U];
NYX	0:85b3fd62ea1a	1083	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
NYX	0:85b3fd62ea1a	1084	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
NYX	0:85b3fd62ea1a	1085	} TPI_Type;
NYX	0:85b3fd62ea1a	1086
NYX	0:85b3fd62ea1a	1087	/* TPI Asynchronous Clock Prescaler Register Definitions */
NYX	0:85b3fd62ea1a	1088	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
NYX	0:85b3fd62ea1a	1089	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
NYX	0:85b3fd62ea1a	1090
NYX	0:85b3fd62ea1a	1091	/* TPI Selected Pin Protocol Register Definitions */
NYX	0:85b3fd62ea1a	1092	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
NYX	0:85b3fd62ea1a	1093	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
NYX	0:85b3fd62ea1a	1094
NYX	0:85b3fd62ea1a	1095	/* TPI Formatter and Flush Status Register Definitions */
NYX	0:85b3fd62ea1a	1096	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
NYX	0:85b3fd62ea1a	1097	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
NYX	0:85b3fd62ea1a	1098
NYX	0:85b3fd62ea1a	1099	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
NYX	0:85b3fd62ea1a	1100	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
NYX	0:85b3fd62ea1a	1101
NYX	0:85b3fd62ea1a	1102	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
NYX	0:85b3fd62ea1a	1103	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
NYX	0:85b3fd62ea1a	1104
NYX	0:85b3fd62ea1a	1105	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
NYX	0:85b3fd62ea1a	1106	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
NYX	0:85b3fd62ea1a	1107
NYX	0:85b3fd62ea1a	1108	/* TPI Formatter and Flush Control Register Definitions */
NYX	0:85b3fd62ea1a	1109	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
NYX	0:85b3fd62ea1a	1110	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
NYX	0:85b3fd62ea1a	1111
NYX	0:85b3fd62ea1a	1112	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
NYX	0:85b3fd62ea1a	1113	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
NYX	0:85b3fd62ea1a	1114
NYX	0:85b3fd62ea1a	1115	/* TPI TRIGGER Register Definitions */
NYX	0:85b3fd62ea1a	1116	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
NYX	0:85b3fd62ea1a	1117	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
NYX	0:85b3fd62ea1a	1118
NYX	0:85b3fd62ea1a	1119	/* TPI Integration ETM Data Register Definitions (FIFO0) */
NYX	0:85b3fd62ea1a	1120	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
NYX	0:85b3fd62ea1a	1121	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1122
NYX	0:85b3fd62ea1a	1123	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
NYX	0:85b3fd62ea1a	1124	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
NYX	0:85b3fd62ea1a	1125
NYX	0:85b3fd62ea1a	1126	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
NYX	0:85b3fd62ea1a	1127	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1128
NYX	0:85b3fd62ea1a	1129	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
NYX	0:85b3fd62ea1a	1130	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
NYX	0:85b3fd62ea1a	1131
NYX	0:85b3fd62ea1a	1132	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
NYX	0:85b3fd62ea1a	1133	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
NYX	0:85b3fd62ea1a	1134
NYX	0:85b3fd62ea1a	1135	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
NYX	0:85b3fd62ea1a	1136	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
NYX	0:85b3fd62ea1a	1137
NYX	0:85b3fd62ea1a	1138	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
NYX	0:85b3fd62ea1a	1139	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
NYX	0:85b3fd62ea1a	1140
NYX	0:85b3fd62ea1a	1141	/* TPI ITATBCTR2 Register Definitions */
NYX	0:85b3fd62ea1a	1142	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
NYX	0:85b3fd62ea1a	1143	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
NYX	0:85b3fd62ea1a	1144
NYX	0:85b3fd62ea1a	1145	/* TPI Integration ITM Data Register Definitions (FIFO1) */
NYX	0:85b3fd62ea1a	1146	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
NYX	0:85b3fd62ea1a	1147	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1148
NYX	0:85b3fd62ea1a	1149	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
NYX	0:85b3fd62ea1a	1150	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
NYX	0:85b3fd62ea1a	1151
NYX	0:85b3fd62ea1a	1152	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
NYX	0:85b3fd62ea1a	1153	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1154
NYX	0:85b3fd62ea1a	1155	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
NYX	0:85b3fd62ea1a	1156	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
NYX	0:85b3fd62ea1a	1157
NYX	0:85b3fd62ea1a	1158	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
NYX	0:85b3fd62ea1a	1159	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
NYX	0:85b3fd62ea1a	1160
NYX	0:85b3fd62ea1a	1161	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
NYX	0:85b3fd62ea1a	1162	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
NYX	0:85b3fd62ea1a	1163
NYX	0:85b3fd62ea1a	1164	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
NYX	0:85b3fd62ea1a	1165	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
NYX	0:85b3fd62ea1a	1166
NYX	0:85b3fd62ea1a	1167	/* TPI ITATBCTR0 Register Definitions */
NYX	0:85b3fd62ea1a	1168	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
NYX	0:85b3fd62ea1a	1169	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
NYX	0:85b3fd62ea1a	1170
NYX	0:85b3fd62ea1a	1171	/* TPI Integration Mode Control Register Definitions */
NYX	0:85b3fd62ea1a	1172	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
NYX	0:85b3fd62ea1a	1173	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
NYX	0:85b3fd62ea1a	1174
NYX	0:85b3fd62ea1a	1175	/* TPI DEVID Register Definitions */
NYX	0:85b3fd62ea1a	1176	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
NYX	0:85b3fd62ea1a	1177	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
NYX	0:85b3fd62ea1a	1178
NYX	0:85b3fd62ea1a	1179	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
NYX	0:85b3fd62ea1a	1180	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
NYX	0:85b3fd62ea1a	1181
NYX	0:85b3fd62ea1a	1182	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
NYX	0:85b3fd62ea1a	1183	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
NYX	0:85b3fd62ea1a	1184
NYX	0:85b3fd62ea1a	1185	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
NYX	0:85b3fd62ea1a	1186	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
NYX	0:85b3fd62ea1a	1187
NYX	0:85b3fd62ea1a	1188	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
NYX	0:85b3fd62ea1a	1189	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
NYX	0:85b3fd62ea1a	1190
NYX	0:85b3fd62ea1a	1191	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
NYX	0:85b3fd62ea1a	1192	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
NYX	0:85b3fd62ea1a	1193
NYX	0:85b3fd62ea1a	1194	/* TPI DEVTYPE Register Definitions */
NYX	0:85b3fd62ea1a	1195	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
NYX	0:85b3fd62ea1a	1196	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
NYX	0:85b3fd62ea1a	1197
NYX	0:85b3fd62ea1a	1198	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
NYX	0:85b3fd62ea1a	1199	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
NYX	0:85b3fd62ea1a	1200
NYX	0:85b3fd62ea1a	1201	/@}/ /* end of group CMSIS_TPI */
NYX	0:85b3fd62ea1a	1202
NYX	0:85b3fd62ea1a	1203
NYX	0:85b3fd62ea1a	1204	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1205	/**
NYX	0:85b3fd62ea1a	1206	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1207	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
NYX	0:85b3fd62ea1a	1208	\brief Type definitions for the Memory Protection Unit (MPU)
NYX	0:85b3fd62ea1a	1209	@{
NYX	0:85b3fd62ea1a	1210	*/
NYX	0:85b3fd62ea1a	1211
NYX	0:85b3fd62ea1a	1212	/**
NYX	0:85b3fd62ea1a	1213	\brief Structure type to access the Memory Protection Unit (MPU).
NYX	0:85b3fd62ea1a	1214	*/
NYX	0:85b3fd62ea1a	1215	typedef struct
NYX	0:85b3fd62ea1a	1216	{
NYX	0:85b3fd62ea1a	1217	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
NYX	0:85b3fd62ea1a	1218	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
NYX	0:85b3fd62ea1a	1219	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
NYX	0:85b3fd62ea1a	1220	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
NYX	0:85b3fd62ea1a	1221	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
NYX	0:85b3fd62ea1a	1222	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
NYX	0:85b3fd62ea1a	1223	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
NYX	0:85b3fd62ea1a	1224	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
NYX	0:85b3fd62ea1a	1225	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
NYX	0:85b3fd62ea1a	1226	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
NYX	0:85b3fd62ea1a	1227	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
NYX	0:85b3fd62ea1a	1228	} MPU_Type;
NYX	0:85b3fd62ea1a	1229
NYX	0:85b3fd62ea1a	1230	/* MPU Type Register Definitions */
NYX	0:85b3fd62ea1a	1231	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
NYX	0:85b3fd62ea1a	1232	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
NYX	0:85b3fd62ea1a	1233
NYX	0:85b3fd62ea1a	1234	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
NYX	0:85b3fd62ea1a	1235	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
NYX	0:85b3fd62ea1a	1236
NYX	0:85b3fd62ea1a	1237	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
NYX	0:85b3fd62ea1a	1238	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
NYX	0:85b3fd62ea1a	1239
NYX	0:85b3fd62ea1a	1240	/* MPU Control Register Definitions */
NYX	0:85b3fd62ea1a	1241	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
NYX	0:85b3fd62ea1a	1242	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
NYX	0:85b3fd62ea1a	1243
NYX	0:85b3fd62ea1a	1244	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
NYX	0:85b3fd62ea1a	1245	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
NYX	0:85b3fd62ea1a	1246
NYX	0:85b3fd62ea1a	1247	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
NYX	0:85b3fd62ea1a	1248	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
NYX	0:85b3fd62ea1a	1249
NYX	0:85b3fd62ea1a	1250	/* MPU Region Number Register Definitions */
NYX	0:85b3fd62ea1a	1251	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
NYX	0:85b3fd62ea1a	1252	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
NYX	0:85b3fd62ea1a	1253
NYX	0:85b3fd62ea1a	1254	/* MPU Region Base Address Register Definitions */
NYX	0:85b3fd62ea1a	1255	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
NYX	0:85b3fd62ea1a	1256	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
NYX	0:85b3fd62ea1a	1257
NYX	0:85b3fd62ea1a	1258	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
NYX	0:85b3fd62ea1a	1259	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
NYX	0:85b3fd62ea1a	1260
NYX	0:85b3fd62ea1a	1261	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
NYX	0:85b3fd62ea1a	1262	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
NYX	0:85b3fd62ea1a	1263
NYX	0:85b3fd62ea1a	1264	/* MPU Region Attribute and Size Register Definitions */
NYX	0:85b3fd62ea1a	1265	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
NYX	0:85b3fd62ea1a	1266	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
NYX	0:85b3fd62ea1a	1267
NYX	0:85b3fd62ea1a	1268	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
NYX	0:85b3fd62ea1a	1269	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
NYX	0:85b3fd62ea1a	1270
NYX	0:85b3fd62ea1a	1271	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
NYX	0:85b3fd62ea1a	1272	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
NYX	0:85b3fd62ea1a	1273
NYX	0:85b3fd62ea1a	1274	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
NYX	0:85b3fd62ea1a	1275	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
NYX	0:85b3fd62ea1a	1276
NYX	0:85b3fd62ea1a	1277	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
NYX	0:85b3fd62ea1a	1278	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
NYX	0:85b3fd62ea1a	1279
NYX	0:85b3fd62ea1a	1280	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
NYX	0:85b3fd62ea1a	1281	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
NYX	0:85b3fd62ea1a	1282
NYX	0:85b3fd62ea1a	1283	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
NYX	0:85b3fd62ea1a	1284	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
NYX	0:85b3fd62ea1a	1285
NYX	0:85b3fd62ea1a	1286	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
NYX	0:85b3fd62ea1a	1287	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
NYX	0:85b3fd62ea1a	1288
NYX	0:85b3fd62ea1a	1289	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
NYX	0:85b3fd62ea1a	1290	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
NYX	0:85b3fd62ea1a	1291
NYX	0:85b3fd62ea1a	1292	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
NYX	0:85b3fd62ea1a	1293	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
NYX	0:85b3fd62ea1a	1294
NYX	0:85b3fd62ea1a	1295	/@} end of group CMSIS_MPU /
NYX	0:85b3fd62ea1a	1296	#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
NYX	0:85b3fd62ea1a	1297
NYX	0:85b3fd62ea1a	1298
NYX	0:85b3fd62ea1a	1299	/**
NYX	0:85b3fd62ea1a	1300	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1301	\defgroup CMSIS_FPU Floating Point Unit (FPU)
NYX	0:85b3fd62ea1a	1302	\brief Type definitions for the Floating Point Unit (FPU)
NYX	0:85b3fd62ea1a	1303	@{
NYX	0:85b3fd62ea1a	1304	*/
NYX	0:85b3fd62ea1a	1305
NYX	0:85b3fd62ea1a	1306	/**
NYX	0:85b3fd62ea1a	1307	\brief Structure type to access the Floating Point Unit (FPU).
NYX	0:85b3fd62ea1a	1308	*/
NYX	0:85b3fd62ea1a	1309	typedef struct
NYX	0:85b3fd62ea1a	1310	{
NYX	0:85b3fd62ea1a	1311	uint32_t RESERVED0[1U];
NYX	0:85b3fd62ea1a	1312	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
NYX	0:85b3fd62ea1a	1313	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
NYX	0:85b3fd62ea1a	1314	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
NYX	0:85b3fd62ea1a	1315	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
NYX	0:85b3fd62ea1a	1316	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
NYX	0:85b3fd62ea1a	1317	} FPU_Type;
NYX	0:85b3fd62ea1a	1318
NYX	0:85b3fd62ea1a	1319	/* Floating-Point Context Control Register Definitions */
NYX	0:85b3fd62ea1a	1320	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
NYX	0:85b3fd62ea1a	1321	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
NYX	0:85b3fd62ea1a	1322
NYX	0:85b3fd62ea1a	1323	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
NYX	0:85b3fd62ea1a	1324	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
NYX	0:85b3fd62ea1a	1325
NYX	0:85b3fd62ea1a	1326	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
NYX	0:85b3fd62ea1a	1327	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
NYX	0:85b3fd62ea1a	1328
NYX	0:85b3fd62ea1a	1329	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
NYX	0:85b3fd62ea1a	1330	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
NYX	0:85b3fd62ea1a	1331
NYX	0:85b3fd62ea1a	1332	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
NYX	0:85b3fd62ea1a	1333	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
NYX	0:85b3fd62ea1a	1334
NYX	0:85b3fd62ea1a	1335	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
NYX	0:85b3fd62ea1a	1336	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
NYX	0:85b3fd62ea1a	1337
NYX	0:85b3fd62ea1a	1338	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
NYX	0:85b3fd62ea1a	1339	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
NYX	0:85b3fd62ea1a	1340
NYX	0:85b3fd62ea1a	1341	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
NYX	0:85b3fd62ea1a	1342	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
NYX	0:85b3fd62ea1a	1343
NYX	0:85b3fd62ea1a	1344	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
NYX	0:85b3fd62ea1a	1345	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
NYX	0:85b3fd62ea1a	1346
NYX	0:85b3fd62ea1a	1347	/* Floating-Point Context Address Register Definitions */
NYX	0:85b3fd62ea1a	1348	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
NYX	0:85b3fd62ea1a	1349	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
NYX	0:85b3fd62ea1a	1350
NYX	0:85b3fd62ea1a	1351	/* Floating-Point Default Status Control Register Definitions */
NYX	0:85b3fd62ea1a	1352	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
NYX	0:85b3fd62ea1a	1353	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
NYX	0:85b3fd62ea1a	1354
NYX	0:85b3fd62ea1a	1355	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
NYX	0:85b3fd62ea1a	1356	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
NYX	0:85b3fd62ea1a	1357
NYX	0:85b3fd62ea1a	1358	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
NYX	0:85b3fd62ea1a	1359	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
NYX	0:85b3fd62ea1a	1360
NYX	0:85b3fd62ea1a	1361	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
NYX	0:85b3fd62ea1a	1362	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
NYX	0:85b3fd62ea1a	1363
NYX	0:85b3fd62ea1a	1364	/* Media and FP Feature Register 0 Definitions */
NYX	0:85b3fd62ea1a	1365	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
NYX	0:85b3fd62ea1a	1366	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
NYX	0:85b3fd62ea1a	1367
NYX	0:85b3fd62ea1a	1368	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
NYX	0:85b3fd62ea1a	1369	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
NYX	0:85b3fd62ea1a	1370
NYX	0:85b3fd62ea1a	1371	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
NYX	0:85b3fd62ea1a	1372	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
NYX	0:85b3fd62ea1a	1373
NYX	0:85b3fd62ea1a	1374	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
NYX	0:85b3fd62ea1a	1375	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
NYX	0:85b3fd62ea1a	1376
NYX	0:85b3fd62ea1a	1377	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
NYX	0:85b3fd62ea1a	1378	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
NYX	0:85b3fd62ea1a	1379
NYX	0:85b3fd62ea1a	1380	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
NYX	0:85b3fd62ea1a	1381	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
NYX	0:85b3fd62ea1a	1382
NYX	0:85b3fd62ea1a	1383	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
NYX	0:85b3fd62ea1a	1384	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
NYX	0:85b3fd62ea1a	1385
NYX	0:85b3fd62ea1a	1386	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
NYX	0:85b3fd62ea1a	1387	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
NYX	0:85b3fd62ea1a	1388
NYX	0:85b3fd62ea1a	1389	/* Media and FP Feature Register 1 Definitions */
NYX	0:85b3fd62ea1a	1390	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
NYX	0:85b3fd62ea1a	1391	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
NYX	0:85b3fd62ea1a	1392
NYX	0:85b3fd62ea1a	1393	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
NYX	0:85b3fd62ea1a	1394	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
NYX	0:85b3fd62ea1a	1395
NYX	0:85b3fd62ea1a	1396	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
NYX	0:85b3fd62ea1a	1397	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
NYX	0:85b3fd62ea1a	1398
NYX	0:85b3fd62ea1a	1399	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
NYX	0:85b3fd62ea1a	1400	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
NYX	0:85b3fd62ea1a	1401
NYX	0:85b3fd62ea1a	1402	/@} end of group CMSIS_FPU /
NYX	0:85b3fd62ea1a	1403
NYX	0:85b3fd62ea1a	1404
NYX	0:85b3fd62ea1a	1405	/**
NYX	0:85b3fd62ea1a	1406	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1407	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
NYX	0:85b3fd62ea1a	1408	\brief Type definitions for the Core Debug Registers
NYX	0:85b3fd62ea1a	1409	@{
NYX	0:85b3fd62ea1a	1410	*/
NYX	0:85b3fd62ea1a	1411
NYX	0:85b3fd62ea1a	1412	/**
NYX	0:85b3fd62ea1a	1413	\brief Structure type to access the Core Debug Register (CoreDebug).
NYX	0:85b3fd62ea1a	1414	*/
NYX	0:85b3fd62ea1a	1415	typedef struct
NYX	0:85b3fd62ea1a	1416	{
NYX	0:85b3fd62ea1a	1417	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
NYX	0:85b3fd62ea1a	1418	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
NYX	0:85b3fd62ea1a	1419	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
NYX	0:85b3fd62ea1a	1420	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
NYX	0:85b3fd62ea1a	1421	} CoreDebug_Type;
NYX	0:85b3fd62ea1a	1422
NYX	0:85b3fd62ea1a	1423	/* Debug Halting Control and Status Register Definitions */
NYX	0:85b3fd62ea1a	1424	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
NYX	0:85b3fd62ea1a	1425	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
NYX	0:85b3fd62ea1a	1426
NYX	0:85b3fd62ea1a	1427	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
NYX	0:85b3fd62ea1a	1428	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
NYX	0:85b3fd62ea1a	1429
NYX	0:85b3fd62ea1a	1430	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
NYX	0:85b3fd62ea1a	1431	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
NYX	0:85b3fd62ea1a	1432
NYX	0:85b3fd62ea1a	1433	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
NYX	0:85b3fd62ea1a	1434	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
NYX	0:85b3fd62ea1a	1435
NYX	0:85b3fd62ea1a	1436	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
NYX	0:85b3fd62ea1a	1437	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
NYX	0:85b3fd62ea1a	1438
NYX	0:85b3fd62ea1a	1439	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
NYX	0:85b3fd62ea1a	1440	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
NYX	0:85b3fd62ea1a	1441
NYX	0:85b3fd62ea1a	1442	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
NYX	0:85b3fd62ea1a	1443	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
NYX	0:85b3fd62ea1a	1444
NYX	0:85b3fd62ea1a	1445	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
NYX	0:85b3fd62ea1a	1446	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
NYX	0:85b3fd62ea1a	1447
NYX	0:85b3fd62ea1a	1448	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
NYX	0:85b3fd62ea1a	1449	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
NYX	0:85b3fd62ea1a	1450
NYX	0:85b3fd62ea1a	1451	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
NYX	0:85b3fd62ea1a	1452	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
NYX	0:85b3fd62ea1a	1453
NYX	0:85b3fd62ea1a	1454	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
NYX	0:85b3fd62ea1a	1455	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
NYX	0:85b3fd62ea1a	1456
NYX	0:85b3fd62ea1a	1457	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
NYX	0:85b3fd62ea1a	1458	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
NYX	0:85b3fd62ea1a	1459
NYX	0:85b3fd62ea1a	1460	/* Debug Core Register Selector Register Definitions */
NYX	0:85b3fd62ea1a	1461	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
NYX	0:85b3fd62ea1a	1462	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
NYX	0:85b3fd62ea1a	1463
NYX	0:85b3fd62ea1a	1464	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
NYX	0:85b3fd62ea1a	1465	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
NYX	0:85b3fd62ea1a	1466
NYX	0:85b3fd62ea1a	1467	/* Debug Exception and Monitor Control Register Definitions */
NYX	0:85b3fd62ea1a	1468	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
NYX	0:85b3fd62ea1a	1469	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
NYX	0:85b3fd62ea1a	1470
NYX	0:85b3fd62ea1a	1471	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
NYX	0:85b3fd62ea1a	1472	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
NYX	0:85b3fd62ea1a	1473
NYX	0:85b3fd62ea1a	1474	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
NYX	0:85b3fd62ea1a	1475	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
NYX	0:85b3fd62ea1a	1476
NYX	0:85b3fd62ea1a	1477	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
NYX	0:85b3fd62ea1a	1478	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
NYX	0:85b3fd62ea1a	1479
NYX	0:85b3fd62ea1a	1480	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
NYX	0:85b3fd62ea1a	1481	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
NYX	0:85b3fd62ea1a	1482
NYX	0:85b3fd62ea1a	1483	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
NYX	0:85b3fd62ea1a	1484	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
NYX	0:85b3fd62ea1a	1485
NYX	0:85b3fd62ea1a	1486	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
NYX	0:85b3fd62ea1a	1487	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
NYX	0:85b3fd62ea1a	1488
NYX	0:85b3fd62ea1a	1489	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
NYX	0:85b3fd62ea1a	1490	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
NYX	0:85b3fd62ea1a	1491
NYX	0:85b3fd62ea1a	1492	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
NYX	0:85b3fd62ea1a	1493	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
NYX	0:85b3fd62ea1a	1494
NYX	0:85b3fd62ea1a	1495	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
NYX	0:85b3fd62ea1a	1496	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
NYX	0:85b3fd62ea1a	1497
NYX	0:85b3fd62ea1a	1498	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
NYX	0:85b3fd62ea1a	1499	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
NYX	0:85b3fd62ea1a	1500
NYX	0:85b3fd62ea1a	1501	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
NYX	0:85b3fd62ea1a	1502	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
NYX	0:85b3fd62ea1a	1503
NYX	0:85b3fd62ea1a	1504	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
NYX	0:85b3fd62ea1a	1505	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
NYX	0:85b3fd62ea1a	1506
NYX	0:85b3fd62ea1a	1507	/@} end of group CMSIS_CoreDebug /
NYX	0:85b3fd62ea1a	1508
NYX	0:85b3fd62ea1a	1509
NYX	0:85b3fd62ea1a	1510	/**
NYX	0:85b3fd62ea1a	1511	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1512	\defgroup CMSIS_core_bitfield Core register bit field macros
NYX	0:85b3fd62ea1a	1513	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
NYX	0:85b3fd62ea1a	1514	@{
NYX	0:85b3fd62ea1a	1515	*/
NYX	0:85b3fd62ea1a	1516
NYX	0:85b3fd62ea1a	1517	/**
NYX	0:85b3fd62ea1a	1518	\brief Mask and shift a bit field value for use in a register bit range.
NYX	0:85b3fd62ea1a	1519	\param[in] field Name of the register bit field.
NYX	0:85b3fd62ea1a	1520	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
NYX	0:85b3fd62ea1a	1521	\return Masked and shifted value.
NYX	0:85b3fd62ea1a	1522	*/
NYX	0:85b3fd62ea1a	1523	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
NYX	0:85b3fd62ea1a	1524
NYX	0:85b3fd62ea1a	1525	/**
NYX	0:85b3fd62ea1a	1526	\brief Mask and shift a register value to extract a bit filed value.
NYX	0:85b3fd62ea1a	1527	\param[in] field Name of the register bit field.
NYX	0:85b3fd62ea1a	1528	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
NYX	0:85b3fd62ea1a	1529	\return Masked and shifted bit field value.
NYX	0:85b3fd62ea1a	1530	*/
NYX	0:85b3fd62ea1a	1531	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
NYX	0:85b3fd62ea1a	1532
NYX	0:85b3fd62ea1a	1533	/@} end of group CMSIS_core_bitfield /
NYX	0:85b3fd62ea1a	1534
NYX	0:85b3fd62ea1a	1535
NYX	0:85b3fd62ea1a	1536	/**
NYX	0:85b3fd62ea1a	1537	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1538	\defgroup CMSIS_core_base Core Definitions
NYX	0:85b3fd62ea1a	1539	\brief Definitions for base addresses, unions, and structures.
NYX	0:85b3fd62ea1a	1540	@{
NYX	0:85b3fd62ea1a	1541	*/
NYX	0:85b3fd62ea1a	1542
NYX	0:85b3fd62ea1a	1543	/* Memory mapping of Core Hardware */
NYX	0:85b3fd62ea1a	1544	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
NYX	0:85b3fd62ea1a	1545	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
NYX	0:85b3fd62ea1a	1546	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
NYX	0:85b3fd62ea1a	1547	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
NYX	0:85b3fd62ea1a	1548	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
NYX	0:85b3fd62ea1a	1549	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
NYX	0:85b3fd62ea1a	1550	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
NYX	0:85b3fd62ea1a	1551	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
NYX	0:85b3fd62ea1a	1552
NYX	0:85b3fd62ea1a	1553	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
NYX	0:85b3fd62ea1a	1554	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
NYX	0:85b3fd62ea1a	1555	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
NYX	0:85b3fd62ea1a	1556	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
NYX	0:85b3fd62ea1a	1557	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
NYX	0:85b3fd62ea1a	1558	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
NYX	0:85b3fd62ea1a	1559	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
NYX	0:85b3fd62ea1a	1560	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
NYX	0:85b3fd62ea1a	1561
NYX	0:85b3fd62ea1a	1562	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1563	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
NYX	0:85b3fd62ea1a	1564	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
NYX	0:85b3fd62ea1a	1565	#endif
NYX	0:85b3fd62ea1a	1566
NYX	0:85b3fd62ea1a	1567	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
NYX	0:85b3fd62ea1a	1568	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
NYX	0:85b3fd62ea1a	1569
NYX	0:85b3fd62ea1a	1570	/@} /
NYX	0:85b3fd62ea1a	1571
NYX	0:85b3fd62ea1a	1572
NYX	0:85b3fd62ea1a	1573
NYX	0:85b3fd62ea1a	1574	/*******************************************************************************
NYX	0:85b3fd62ea1a	1575	* Hardware Abstraction Layer
NYX	0:85b3fd62ea1a	1576	Core Function Interface contains:
NYX	0:85b3fd62ea1a	1577	- Core NVIC Functions
NYX	0:85b3fd62ea1a	1578	- Core SysTick Functions
NYX	0:85b3fd62ea1a	1579	- Core Debug Functions
NYX	0:85b3fd62ea1a	1580	- Core Register Access Functions
NYX	0:85b3fd62ea1a	1581	******************************************************************************/
NYX	0:85b3fd62ea1a	1582	/**
NYX	0:85b3fd62ea1a	1583	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
NYX	0:85b3fd62ea1a	1584	*/
NYX	0:85b3fd62ea1a	1585
NYX	0:85b3fd62ea1a	1586
NYX	0:85b3fd62ea1a	1587
NYX	0:85b3fd62ea1a	1588	/* ########################## NVIC functions #################################### */
NYX	0:85b3fd62ea1a	1589	/**
NYX	0:85b3fd62ea1a	1590	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	1591	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
NYX	0:85b3fd62ea1a	1592	\brief Functions that manage interrupts and exceptions via the NVIC.
NYX	0:85b3fd62ea1a	1593	@{
NYX	0:85b3fd62ea1a	1594	*/
NYX	0:85b3fd62ea1a	1595
NYX	0:85b3fd62ea1a	1596	#ifdef CMSIS_NVIC_VIRTUAL
NYX	0:85b3fd62ea1a	1597	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	1598	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
NYX	0:85b3fd62ea1a	1599	#endif
NYX	0:85b3fd62ea1a	1600	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	1601	#else
NYX	0:85b3fd62ea1a	1602	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
NYX	0:85b3fd62ea1a	1603	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
NYX	0:85b3fd62ea1a	1604	#define NVIC_EnableIRQ __NVIC_EnableIRQ
NYX	0:85b3fd62ea1a	1605	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
NYX	0:85b3fd62ea1a	1606	#define NVIC_DisableIRQ __NVIC_DisableIRQ
NYX	0:85b3fd62ea1a	1607	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
NYX	0:85b3fd62ea1a	1608	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
NYX	0:85b3fd62ea1a	1609	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
NYX	0:85b3fd62ea1a	1610	#define NVIC_GetActive __NVIC_GetActive
NYX	0:85b3fd62ea1a	1611	#define NVIC_SetPriority __NVIC_SetPriority
NYX	0:85b3fd62ea1a	1612	#define NVIC_GetPriority __NVIC_GetPriority
NYX	0:85b3fd62ea1a	1613	#define NVIC_SystemReset __NVIC_SystemReset
NYX	0:85b3fd62ea1a	1614	#endif /* CMSIS_NVIC_VIRTUAL */
NYX	0:85b3fd62ea1a	1615
NYX	0:85b3fd62ea1a	1616	#ifdef CMSIS_VECTAB_VIRTUAL
NYX	0:85b3fd62ea1a	1617	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	1618	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
NYX	0:85b3fd62ea1a	1619	#endif
NYX	0:85b3fd62ea1a	1620	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	1621	#else
NYX	0:85b3fd62ea1a	1622	#define NVIC_SetVector __NVIC_SetVector
NYX	0:85b3fd62ea1a	1623	#define NVIC_GetVector __NVIC_GetVector
NYX	0:85b3fd62ea1a	1624	#endif /* (CMSIS_VECTAB_VIRTUAL) */
NYX	0:85b3fd62ea1a	1625
NYX	0:85b3fd62ea1a	1626	#define NVIC_USER_IRQ_OFFSET 16
NYX	0:85b3fd62ea1a	1627
NYX	0:85b3fd62ea1a	1628
NYX	0:85b3fd62ea1a	1629
NYX	0:85b3fd62ea1a	1630	/**
NYX	0:85b3fd62ea1a	1631	\brief Set Priority Grouping
NYX	0:85b3fd62ea1a	1632	\details Sets the priority grouping field using the required unlock sequence.
NYX	0:85b3fd62ea1a	1633	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
NYX	0:85b3fd62ea1a	1634	Only values from 0..7 are used.
NYX	0:85b3fd62ea1a	1635	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	1636	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	1637	\param [in] PriorityGroup Priority grouping field.
NYX	0:85b3fd62ea1a	1638	*/
NYX	0:85b3fd62ea1a	1639	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
NYX	0:85b3fd62ea1a	1640	{
NYX	0:85b3fd62ea1a	1641	uint32_t reg_value;
NYX	0:85b3fd62ea1a	1642	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	1643
NYX	0:85b3fd62ea1a	1644	reg_value = SCB->AIRCR; /* read old register configuration */
NYX	0:85b3fd62ea1a	1645	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
NYX	0:85b3fd62ea1a	1646	reg_value = (reg_value \|
NYX	0:85b3fd62ea1a	1647	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
NYX	0:85b3fd62ea1a	1648	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
NYX	0:85b3fd62ea1a	1649	SCB->AIRCR = reg_value;
NYX	0:85b3fd62ea1a	1650	}
NYX	0:85b3fd62ea1a	1651
NYX	0:85b3fd62ea1a	1652
NYX	0:85b3fd62ea1a	1653	/**
NYX	0:85b3fd62ea1a	1654	\brief Get Priority Grouping
NYX	0:85b3fd62ea1a	1655	\details Reads the priority grouping field from the NVIC Interrupt Controller.
NYX	0:85b3fd62ea1a	1656	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
NYX	0:85b3fd62ea1a	1657	*/
NYX	0:85b3fd62ea1a	1658	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
NYX	0:85b3fd62ea1a	1659	{
NYX	0:85b3fd62ea1a	1660	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
NYX	0:85b3fd62ea1a	1661	}
NYX	0:85b3fd62ea1a	1662
NYX	0:85b3fd62ea1a	1663
NYX	0:85b3fd62ea1a	1664	/**
NYX	0:85b3fd62ea1a	1665	\brief Enable Interrupt
NYX	0:85b3fd62ea1a	1666	\details Enables a device specific interrupt in the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	1667	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1668	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1669	*/
NYX	0:85b3fd62ea1a	1670	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1671	{
NYX	0:85b3fd62ea1a	1672	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1673	{
NYX	0:85b3fd62ea1a	1674	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	1675	}
NYX	0:85b3fd62ea1a	1676	}
NYX	0:85b3fd62ea1a	1677
NYX	0:85b3fd62ea1a	1678
NYX	0:85b3fd62ea1a	1679	/**
NYX	0:85b3fd62ea1a	1680	\brief Get Interrupt Enable status
NYX	0:85b3fd62ea1a	1681	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	1682	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1683	\return 0 Interrupt is not enabled.
NYX	0:85b3fd62ea1a	1684	\return 1 Interrupt is enabled.
NYX	0:85b3fd62ea1a	1685	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1686	*/
NYX	0:85b3fd62ea1a	1687	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1688	{
NYX	0:85b3fd62ea1a	1689	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1690	{
NYX	0:85b3fd62ea1a	1691	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	1692	}
NYX	0:85b3fd62ea1a	1693	else
NYX	0:85b3fd62ea1a	1694	{
NYX	0:85b3fd62ea1a	1695	return(0U);
NYX	0:85b3fd62ea1a	1696	}
NYX	0:85b3fd62ea1a	1697	}
NYX	0:85b3fd62ea1a	1698
NYX	0:85b3fd62ea1a	1699
NYX	0:85b3fd62ea1a	1700	/**
NYX	0:85b3fd62ea1a	1701	\brief Disable Interrupt
NYX	0:85b3fd62ea1a	1702	\details Disables a device specific interrupt in the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	1703	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1704	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1705	*/
NYX	0:85b3fd62ea1a	1706	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1707	{
NYX	0:85b3fd62ea1a	1708	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1709	{
NYX	0:85b3fd62ea1a	1710	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	1711	__DSB();
NYX	0:85b3fd62ea1a	1712	__ISB();
NYX	0:85b3fd62ea1a	1713	}
NYX	0:85b3fd62ea1a	1714	}
NYX	0:85b3fd62ea1a	1715
NYX	0:85b3fd62ea1a	1716
NYX	0:85b3fd62ea1a	1717	/**
NYX	0:85b3fd62ea1a	1718	\brief Get Pending Interrupt
NYX	0:85b3fd62ea1a	1719	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
NYX	0:85b3fd62ea1a	1720	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1721	\return 0 Interrupt status is not pending.
NYX	0:85b3fd62ea1a	1722	\return 1 Interrupt status is pending.
NYX	0:85b3fd62ea1a	1723	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1724	*/
NYX	0:85b3fd62ea1a	1725	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1726	{
NYX	0:85b3fd62ea1a	1727	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1728	{
NYX	0:85b3fd62ea1a	1729	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	1730	}
NYX	0:85b3fd62ea1a	1731	else
NYX	0:85b3fd62ea1a	1732	{
NYX	0:85b3fd62ea1a	1733	return(0U);
NYX	0:85b3fd62ea1a	1734	}
NYX	0:85b3fd62ea1a	1735	}
NYX	0:85b3fd62ea1a	1736
NYX	0:85b3fd62ea1a	1737
NYX	0:85b3fd62ea1a	1738	/**
NYX	0:85b3fd62ea1a	1739	\brief Set Pending Interrupt
NYX	0:85b3fd62ea1a	1740	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
NYX	0:85b3fd62ea1a	1741	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1742	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1743	*/
NYX	0:85b3fd62ea1a	1744	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1745	{
NYX	0:85b3fd62ea1a	1746	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1747	{
NYX	0:85b3fd62ea1a	1748	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	1749	}
NYX	0:85b3fd62ea1a	1750	}
NYX	0:85b3fd62ea1a	1751
NYX	0:85b3fd62ea1a	1752
NYX	0:85b3fd62ea1a	1753	/**
NYX	0:85b3fd62ea1a	1754	\brief Clear Pending Interrupt
NYX	0:85b3fd62ea1a	1755	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
NYX	0:85b3fd62ea1a	1756	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1757	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1758	*/
NYX	0:85b3fd62ea1a	1759	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1760	{
NYX	0:85b3fd62ea1a	1761	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1762	{
NYX	0:85b3fd62ea1a	1763	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	1764	}
NYX	0:85b3fd62ea1a	1765	}
NYX	0:85b3fd62ea1a	1766
NYX	0:85b3fd62ea1a	1767
NYX	0:85b3fd62ea1a	1768	/**
NYX	0:85b3fd62ea1a	1769	\brief Get Active Interrupt
NYX	0:85b3fd62ea1a	1770	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
NYX	0:85b3fd62ea1a	1771	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1772	\return 0 Interrupt status is not active.
NYX	0:85b3fd62ea1a	1773	\return 1 Interrupt status is active.
NYX	0:85b3fd62ea1a	1774	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1775	*/
NYX	0:85b3fd62ea1a	1776	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1777	{
NYX	0:85b3fd62ea1a	1778	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1779	{
NYX	0:85b3fd62ea1a	1780	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	1781	}
NYX	0:85b3fd62ea1a	1782	else
NYX	0:85b3fd62ea1a	1783	{
NYX	0:85b3fd62ea1a	1784	return(0U);
NYX	0:85b3fd62ea1a	1785	}
NYX	0:85b3fd62ea1a	1786	}
NYX	0:85b3fd62ea1a	1787
NYX	0:85b3fd62ea1a	1788
NYX	0:85b3fd62ea1a	1789	/**
NYX	0:85b3fd62ea1a	1790	\brief Set Interrupt Priority
NYX	0:85b3fd62ea1a	1791	\details Sets the priority of a device specific interrupt or a processor exception.
NYX	0:85b3fd62ea1a	1792	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	1793	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	1794	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	1795	\param [in] priority Priority to set.
NYX	0:85b3fd62ea1a	1796	\note The priority cannot be set for every processor exception.
NYX	0:85b3fd62ea1a	1797	*/
NYX	0:85b3fd62ea1a	1798	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
NYX	0:85b3fd62ea1a	1799	{
NYX	0:85b3fd62ea1a	1800	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1801	{
NYX	0:85b3fd62ea1a	1802	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
NYX	0:85b3fd62ea1a	1803	}
NYX	0:85b3fd62ea1a	1804	else
NYX	0:85b3fd62ea1a	1805	{
NYX	0:85b3fd62ea1a	1806	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
NYX	0:85b3fd62ea1a	1807	}
NYX	0:85b3fd62ea1a	1808	}
NYX	0:85b3fd62ea1a	1809
NYX	0:85b3fd62ea1a	1810
NYX	0:85b3fd62ea1a	1811	/**
NYX	0:85b3fd62ea1a	1812	\brief Get Interrupt Priority
NYX	0:85b3fd62ea1a	1813	\details Reads the priority of a device specific interrupt or a processor exception.
NYX	0:85b3fd62ea1a	1814	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	1815	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	1816	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	1817	\return Interrupt Priority.
NYX	0:85b3fd62ea1a	1818	Value is aligned automatically to the implemented priority bits of the microcontroller.
NYX	0:85b3fd62ea1a	1819	*/
NYX	0:85b3fd62ea1a	1820	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1821	{
NYX	0:85b3fd62ea1a	1822
NYX	0:85b3fd62ea1a	1823	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1824	{
NYX	0:85b3fd62ea1a	1825	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
NYX	0:85b3fd62ea1a	1826	}
NYX	0:85b3fd62ea1a	1827	else
NYX	0:85b3fd62ea1a	1828	{
NYX	0:85b3fd62ea1a	1829	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
NYX	0:85b3fd62ea1a	1830	}
NYX	0:85b3fd62ea1a	1831	}
NYX	0:85b3fd62ea1a	1832
NYX	0:85b3fd62ea1a	1833
NYX	0:85b3fd62ea1a	1834	/**
NYX	0:85b3fd62ea1a	1835	\brief Encode Priority
NYX	0:85b3fd62ea1a	1836	\details Encodes the priority for an interrupt with the given priority group,
NYX	0:85b3fd62ea1a	1837	preemptive priority value, and subpriority value.
NYX	0:85b3fd62ea1a	1838	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	1839	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	1840	\param [in] PriorityGroup Used priority group.
NYX	0:85b3fd62ea1a	1841	\param [in] PreemptPriority Preemptive priority value (starting from 0).
NYX	0:85b3fd62ea1a	1842	\param [in] SubPriority Subpriority value (starting from 0).
NYX	0:85b3fd62ea1a	1843	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
NYX	0:85b3fd62ea1a	1844	*/
NYX	0:85b3fd62ea1a	1845	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
NYX	0:85b3fd62ea1a	1846	{
NYX	0:85b3fd62ea1a	1847	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	1848	uint32_t PreemptPriorityBits;
NYX	0:85b3fd62ea1a	1849	uint32_t SubPriorityBits;
NYX	0:85b3fd62ea1a	1850
NYX	0:85b3fd62ea1a	1851	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
NYX	0:85b3fd62ea1a	1852	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
NYX	0:85b3fd62ea1a	1853
NYX	0:85b3fd62ea1a	1854	return (
NYX	0:85b3fd62ea1a	1855	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
NYX	0:85b3fd62ea1a	1856	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
NYX	0:85b3fd62ea1a	1857	);
NYX	0:85b3fd62ea1a	1858	}
NYX	0:85b3fd62ea1a	1859
NYX	0:85b3fd62ea1a	1860
NYX	0:85b3fd62ea1a	1861	/**
NYX	0:85b3fd62ea1a	1862	\brief Decode Priority
NYX	0:85b3fd62ea1a	1863	\details Decodes an interrupt priority value with a given priority group to
NYX	0:85b3fd62ea1a	1864	preemptive priority value and subpriority value.
NYX	0:85b3fd62ea1a	1865	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	1866	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	1867	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
NYX	0:85b3fd62ea1a	1868	\param [in] PriorityGroup Used priority group.
NYX	0:85b3fd62ea1a	1869	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
NYX	0:85b3fd62ea1a	1870	\param [out] pSubPriority Subpriority value (starting from 0).
NYX	0:85b3fd62ea1a	1871	*/
NYX	0:85b3fd62ea1a	1872	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
NYX	0:85b3fd62ea1a	1873	{
NYX	0:85b3fd62ea1a	1874	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	1875	uint32_t PreemptPriorityBits;
NYX	0:85b3fd62ea1a	1876	uint32_t SubPriorityBits;
NYX	0:85b3fd62ea1a	1877
NYX	0:85b3fd62ea1a	1878	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
NYX	0:85b3fd62ea1a	1879	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
NYX	0:85b3fd62ea1a	1880
NYX	0:85b3fd62ea1a	1881	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
NYX	0:85b3fd62ea1a	1882	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
NYX	0:85b3fd62ea1a	1883	}
NYX	0:85b3fd62ea1a	1884
NYX	0:85b3fd62ea1a	1885
NYX	0:85b3fd62ea1a	1886	/**
NYX	0:85b3fd62ea1a	1887	\brief Set Interrupt Vector
NYX	0:85b3fd62ea1a	1888	\details Sets an interrupt vector in SRAM based interrupt vector table.
NYX	0:85b3fd62ea1a	1889	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	1890	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	1891	VTOR must been relocated to SRAM before.
NYX	0:85b3fd62ea1a	1892	\param [in] IRQn Interrupt number
NYX	0:85b3fd62ea1a	1893	\param [in] vector Address of interrupt handler function
NYX	0:85b3fd62ea1a	1894	*/
NYX	0:85b3fd62ea1a	1895	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
NYX	0:85b3fd62ea1a	1896	{
NYX	0:85b3fd62ea1a	1897	uint32_t vectors = (uint32_t )SCB->VTOR;
NYX	0:85b3fd62ea1a	1898	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
NYX	0:85b3fd62ea1a	1899	}
NYX	0:85b3fd62ea1a	1900
NYX	0:85b3fd62ea1a	1901
NYX	0:85b3fd62ea1a	1902	/**
NYX	0:85b3fd62ea1a	1903	\brief Get Interrupt Vector
NYX	0:85b3fd62ea1a	1904	\details Reads an interrupt vector from interrupt vector table.
NYX	0:85b3fd62ea1a	1905	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	1906	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	1907	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	1908	\return Address of interrupt handler function
NYX	0:85b3fd62ea1a	1909	*/
NYX	0:85b3fd62ea1a	1910	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1911	{
NYX	0:85b3fd62ea1a	1912	uint32_t vectors = (uint32_t )SCB->VTOR;
NYX	0:85b3fd62ea1a	1913	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
NYX	0:85b3fd62ea1a	1914	}
NYX	0:85b3fd62ea1a	1915
NYX	0:85b3fd62ea1a	1916
NYX	0:85b3fd62ea1a	1917	/**
NYX	0:85b3fd62ea1a	1918	\brief System Reset
NYX	0:85b3fd62ea1a	1919	\details Initiates a system reset request to reset the MCU.
NYX	0:85b3fd62ea1a	1920	*/
NYX	0:85b3fd62ea1a	1921	__STATIC_INLINE void __NVIC_SystemReset(void)
NYX	0:85b3fd62ea1a	1922	{
NYX	0:85b3fd62ea1a	1923	__DSB(); /* Ensure all outstanding memory accesses included
NYX	0:85b3fd62ea1a	1924	buffered write are completed before reset */
NYX	0:85b3fd62ea1a	1925	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
NYX	0:85b3fd62ea1a	1926	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
NYX	0:85b3fd62ea1a	1927	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
NYX	0:85b3fd62ea1a	1928	__DSB(); /* Ensure completion of memory access */
NYX	0:85b3fd62ea1a	1929
NYX	0:85b3fd62ea1a	1930	for(;;) /* wait until reset */
NYX	0:85b3fd62ea1a	1931	{
NYX	0:85b3fd62ea1a	1932	__NOP();
NYX	0:85b3fd62ea1a	1933	}
NYX	0:85b3fd62ea1a	1934	}
NYX	0:85b3fd62ea1a	1935
NYX	0:85b3fd62ea1a	1936	/@} end of CMSIS_Core_NVICFunctions /
NYX	0:85b3fd62ea1a	1937
NYX	0:85b3fd62ea1a	1938
NYX	0:85b3fd62ea1a	1939	/* ########################## FPU functions #################################### */
NYX	0:85b3fd62ea1a	1940	/**
NYX	0:85b3fd62ea1a	1941	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	1942	\defgroup CMSIS_Core_FpuFunctions FPU Functions
NYX	0:85b3fd62ea1a	1943	\brief Function that provides FPU type.
NYX	0:85b3fd62ea1a	1944	@{
NYX	0:85b3fd62ea1a	1945	*/
NYX	0:85b3fd62ea1a	1946
NYX	0:85b3fd62ea1a	1947	/**
NYX	0:85b3fd62ea1a	1948	\brief get FPU type
NYX	0:85b3fd62ea1a	1949	\details returns the FPU type
NYX	0:85b3fd62ea1a	1950	\returns
NYX	0:85b3fd62ea1a	1951	- \b 0: No FPU
NYX	0:85b3fd62ea1a	1952	- \b 1: Single precision FPU
NYX	0:85b3fd62ea1a	1953	- \b 2: Double + Single precision FPU
NYX	0:85b3fd62ea1a	1954	*/
NYX	0:85b3fd62ea1a	1955	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
NYX	0:85b3fd62ea1a	1956	{
NYX	0:85b3fd62ea1a	1957	uint32_t mvfr0;
NYX	0:85b3fd62ea1a	1958
NYX	0:85b3fd62ea1a	1959	mvfr0 = FPU->MVFR0;
NYX	0:85b3fd62ea1a	1960	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
NYX	0:85b3fd62ea1a	1961	{
NYX	0:85b3fd62ea1a	1962	return 1U; /* Single precision FPU */
NYX	0:85b3fd62ea1a	1963	}
NYX	0:85b3fd62ea1a	1964	else
NYX	0:85b3fd62ea1a	1965	{
NYX	0:85b3fd62ea1a	1966	return 0U; /* No FPU */
NYX	0:85b3fd62ea1a	1967	}
NYX	0:85b3fd62ea1a	1968	}
NYX	0:85b3fd62ea1a	1969
NYX	0:85b3fd62ea1a	1970
NYX	0:85b3fd62ea1a	1971	/@} end of CMSIS_Core_FpuFunctions /
NYX	0:85b3fd62ea1a	1972
NYX	0:85b3fd62ea1a	1973
NYX	0:85b3fd62ea1a	1974
NYX	0:85b3fd62ea1a	1975	/* ################################## SysTick function ############################################ */
NYX	0:85b3fd62ea1a	1976	/**
NYX	0:85b3fd62ea1a	1977	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	1978	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
NYX	0:85b3fd62ea1a	1979	\brief Functions that configure the System.
NYX	0:85b3fd62ea1a	1980	@{
NYX	0:85b3fd62ea1a	1981	*/
NYX	0:85b3fd62ea1a	1982
NYX	0:85b3fd62ea1a	1983	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
NYX	0:85b3fd62ea1a	1984
NYX	0:85b3fd62ea1a	1985	/**
NYX	0:85b3fd62ea1a	1986	\brief System Tick Configuration
NYX	0:85b3fd62ea1a	1987	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
NYX	0:85b3fd62ea1a	1988	Counter is in free running mode to generate periodic interrupts.
NYX	0:85b3fd62ea1a	1989	\param [in] ticks Number of ticks between two interrupts.
NYX	0:85b3fd62ea1a	1990	\return 0 Function succeeded.
NYX	0:85b3fd62ea1a	1991	\return 1 Function failed.
NYX	0:85b3fd62ea1a	1992	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
NYX	0:85b3fd62ea1a	1993	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
NYX	0:85b3fd62ea1a	1994	must contain a vendor-specific implementation of this function.
NYX	0:85b3fd62ea1a	1995	*/
NYX	0:85b3fd62ea1a	1996	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
NYX	0:85b3fd62ea1a	1997	{
NYX	0:85b3fd62ea1a	1998	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
NYX	0:85b3fd62ea1a	1999	{
NYX	0:85b3fd62ea1a	2000	return (1UL); /* Reload value impossible */
NYX	0:85b3fd62ea1a	2001	}
NYX	0:85b3fd62ea1a	2002
NYX	0:85b3fd62ea1a	2003	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NYX	0:85b3fd62ea1a	2004	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
NYX	0:85b3fd62ea1a	2005	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NYX	0:85b3fd62ea1a	2006	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
NYX	0:85b3fd62ea1a	2007	SysTick_CTRL_TICKINT_Msk \|
NYX	0:85b3fd62ea1a	2008	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
NYX	0:85b3fd62ea1a	2009	return (0UL); /* Function successful */
NYX	0:85b3fd62ea1a	2010	}
NYX	0:85b3fd62ea1a	2011
NYX	0:85b3fd62ea1a	2012	#endif
NYX	0:85b3fd62ea1a	2013
NYX	0:85b3fd62ea1a	2014	/@} end of CMSIS_Core_SysTickFunctions /
NYX	0:85b3fd62ea1a	2015
NYX	0:85b3fd62ea1a	2016
NYX	0:85b3fd62ea1a	2017
NYX	0:85b3fd62ea1a	2018	/* ##################################### Debug In/Output function ########################################### */
NYX	0:85b3fd62ea1a	2019	/**
NYX	0:85b3fd62ea1a	2020	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	2021	\defgroup CMSIS_core_DebugFunctions ITM Functions
NYX	0:85b3fd62ea1a	2022	\brief Functions that access the ITM debug interface.
NYX	0:85b3fd62ea1a	2023	@{
NYX	0:85b3fd62ea1a	2024	*/
NYX	0:85b3fd62ea1a	2025
NYX	0:85b3fd62ea1a	2026	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
NYX	0:85b3fd62ea1a	2027	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
NYX	0:85b3fd62ea1a	2028
NYX	0:85b3fd62ea1a	2029
NYX	0:85b3fd62ea1a	2030	/**
NYX	0:85b3fd62ea1a	2031	\brief ITM Send Character
NYX	0:85b3fd62ea1a	2032	\details Transmits a character via the ITM channel 0, and
NYX	0:85b3fd62ea1a	2033	\li Just returns when no debugger is connected that has booked the output.
NYX	0:85b3fd62ea1a	2034	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
NYX	0:85b3fd62ea1a	2035	\param [in] ch Character to transmit.
NYX	0:85b3fd62ea1a	2036	\returns Character to transmit.
NYX	0:85b3fd62ea1a	2037	*/
NYX	0:85b3fd62ea1a	2038	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
NYX	0:85b3fd62ea1a	2039	{
NYX	0:85b3fd62ea1a	2040	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
NYX	0:85b3fd62ea1a	2041	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
NYX	0:85b3fd62ea1a	2042	{
NYX	0:85b3fd62ea1a	2043	while (ITM->PORT[0U].u32 == 0UL)
NYX	0:85b3fd62ea1a	2044	{
NYX	0:85b3fd62ea1a	2045	__NOP();
NYX	0:85b3fd62ea1a	2046	}
NYX	0:85b3fd62ea1a	2047	ITM->PORT[0U].u8 = (uint8_t)ch;
NYX	0:85b3fd62ea1a	2048	}
NYX	0:85b3fd62ea1a	2049	return (ch);
NYX	0:85b3fd62ea1a	2050	}
NYX	0:85b3fd62ea1a	2051
NYX	0:85b3fd62ea1a	2052
NYX	0:85b3fd62ea1a	2053	/**
NYX	0:85b3fd62ea1a	2054	\brief ITM Receive Character
NYX	0:85b3fd62ea1a	2055	\details Inputs a character via the external variable \ref ITM_RxBuffer.
NYX	0:85b3fd62ea1a	2056	\return Received character.
NYX	0:85b3fd62ea1a	2057	\return -1 No character pending.
NYX	0:85b3fd62ea1a	2058	*/
NYX	0:85b3fd62ea1a	2059	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
NYX	0:85b3fd62ea1a	2060	{
NYX	0:85b3fd62ea1a	2061	int32_t ch = -1; /* no character available */
NYX	0:85b3fd62ea1a	2062
NYX	0:85b3fd62ea1a	2063	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
NYX	0:85b3fd62ea1a	2064	{
NYX	0:85b3fd62ea1a	2065	ch = ITM_RxBuffer;
NYX	0:85b3fd62ea1a	2066	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
NYX	0:85b3fd62ea1a	2067	}
NYX	0:85b3fd62ea1a	2068
NYX	0:85b3fd62ea1a	2069	return (ch);
NYX	0:85b3fd62ea1a	2070	}
NYX	0:85b3fd62ea1a	2071
NYX	0:85b3fd62ea1a	2072
NYX	0:85b3fd62ea1a	2073	/**
NYX	0:85b3fd62ea1a	2074	\brief ITM Check Character
NYX	0:85b3fd62ea1a	2075	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
NYX	0:85b3fd62ea1a	2076	\return 0 No character available.
NYX	0:85b3fd62ea1a	2077	\return 1 Character available.
NYX	0:85b3fd62ea1a	2078	*/
NYX	0:85b3fd62ea1a	2079	__STATIC_INLINE int32_t ITM_CheckChar (void)
NYX	0:85b3fd62ea1a	2080	{
NYX	0:85b3fd62ea1a	2081
NYX	0:85b3fd62ea1a	2082	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
NYX	0:85b3fd62ea1a	2083	{
NYX	0:85b3fd62ea1a	2084	return (0); /* no character available */
NYX	0:85b3fd62ea1a	2085	}
NYX	0:85b3fd62ea1a	2086	else
NYX	0:85b3fd62ea1a	2087	{
NYX	0:85b3fd62ea1a	2088	return (1); /* character available */
NYX	0:85b3fd62ea1a	2089	}
NYX	0:85b3fd62ea1a	2090	}
NYX	0:85b3fd62ea1a	2091
NYX	0:85b3fd62ea1a	2092	/@} end of CMSIS_core_DebugFunctions /
NYX	0:85b3fd62ea1a	2093
NYX	0:85b3fd62ea1a	2094
NYX	0:85b3fd62ea1a	2095
NYX	0:85b3fd62ea1a	2096
NYX	0:85b3fd62ea1a	2097	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	2098	}
NYX	0:85b3fd62ea1a	2099	#endif
NYX	0:85b3fd62ea1a	2100
NYX	0:85b3fd62ea1a	2101	#endif /* __CORE_CM4_H_DEPENDANT */
NYX	0:85b3fd62ea1a	2102
NYX	0:85b3fd62ea1a	2103	#endif /* __CMSIS_GENERIC */

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Created:	16 Mar 2020
Imports:	73
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cmsis/core_cm4.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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