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cmsis/core_cm33.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/************************************************************************//
NYX	0:85b3fd62ea1a	2	* @file core_cm33.h
NYX	0:85b3fd62ea1a	3	* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
NYX	0:85b3fd62ea1a	4	* @version V5.0.2
NYX	0:85b3fd62ea1a	5	* @date 13. February 2017
NYX	0:85b3fd62ea1a	6	******************************************************************************/
NYX	0:85b3fd62ea1a	7	/*
NYX	0:85b3fd62ea1a	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
NYX	0:85b3fd62ea1a	9	*
NYX	0:85b3fd62ea1a	10	* SPDX-License-Identifier: Apache-2.0
NYX	0:85b3fd62ea1a	11	*
NYX	0:85b3fd62ea1a	12	* Licensed under the Apache License, Version 2.0 (the License); you may
NYX	0:85b3fd62ea1a	13	* not use this file except in compliance with the License.
NYX	0:85b3fd62ea1a	14	* You may obtain a copy of the License at
NYX	0:85b3fd62ea1a	15	*
NYX	0:85b3fd62ea1a	16	* www.apache.org/licenses/LICENSE-2.0
NYX	0:85b3fd62ea1a	17	*
NYX	0:85b3fd62ea1a	18	* Unless required by applicable law or agreed to in writing, software
NYX	0:85b3fd62ea1a	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
NYX	0:85b3fd62ea1a	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX	0:85b3fd62ea1a	21	* See the License for the specific language governing permissions and
NYX	0:85b3fd62ea1a	22	* limitations under the License.
NYX	0:85b3fd62ea1a	23	*/
NYX	0:85b3fd62ea1a	24
NYX	0:85b3fd62ea1a	25	#if defined ( __ICCARM__ )
NYX	0:85b3fd62ea1a	26	#pragma system_include /* treat file as system include file for MISRA check */
NYX	0:85b3fd62ea1a	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX	0:85b3fd62ea1a	28	#pragma clang system_header /* treat file as system include file */
NYX	0:85b3fd62ea1a	29	#endif
NYX	0:85b3fd62ea1a	30
NYX	0:85b3fd62ea1a	31	#ifndef __CORE_CM33_H_GENERIC
NYX	0:85b3fd62ea1a	32	#define __CORE_CM33_H_GENERIC
NYX	0:85b3fd62ea1a	33
NYX	0:85b3fd62ea1a	34	#include <stdint.h>
NYX	0:85b3fd62ea1a	35
NYX	0:85b3fd62ea1a	36	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	37	extern "C" {
NYX	0:85b3fd62ea1a	38	#endif
NYX	0:85b3fd62ea1a	39
NYX	0:85b3fd62ea1a	40	/**
NYX	0:85b3fd62ea1a	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
NYX	0:85b3fd62ea1a	42	CMSIS violates the following MISRA-C:2004 rules:
NYX	0:85b3fd62ea1a	43
NYX	0:85b3fd62ea1a	44	\li Required Rule 8.5, object/function definition in header file.<br>
NYX	0:85b3fd62ea1a	45	Function definitions in header files are used to allow 'inlining'.
NYX	0:85b3fd62ea1a	46
NYX	0:85b3fd62ea1a	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
NYX	0:85b3fd62ea1a	48	Unions are used for effective representation of core registers.
NYX	0:85b3fd62ea1a	49
NYX	0:85b3fd62ea1a	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
NYX	0:85b3fd62ea1a	51	Function-like macros are used to allow more efficient code.
NYX	0:85b3fd62ea1a	52	*/
NYX	0:85b3fd62ea1a	53
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/*******************************************************************************
NYX	0:85b3fd62ea1a	56	* CMSIS definitions
NYX	0:85b3fd62ea1a	57	******************************************************************************/
NYX	0:85b3fd62ea1a	58	/**
NYX	0:85b3fd62ea1a	59	\ingroup Cortex_M33
NYX	0:85b3fd62ea1a	60	@{
NYX	0:85b3fd62ea1a	61	*/
NYX	0:85b3fd62ea1a	62
NYX	0:85b3fd62ea1a	63	/* CMSIS CM33 definitions */
NYX	0:85b3fd62ea1a	64	#define __CM33_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
NYX	0:85b3fd62ea1a	65	#define __CM33_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
NYX	0:85b3fd62ea1a	66	#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) \| \
NYX	0:85b3fd62ea1a	67	__CM33_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
NYX	0:85b3fd62ea1a	68
NYX	0:85b3fd62ea1a	69	#define __CORTEX_M (33U) /!< Cortex-M Core /
NYX	0:85b3fd62ea1a	70
NYX	0:85b3fd62ea1a	71	/** __FPU_USED indicates whether an FPU is used or not.
NYX	0:85b3fd62ea1a	72	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
NYX	0:85b3fd62ea1a	73	*/
NYX	0:85b3fd62ea1a	74	#if defined ( __CC_ARM )
NYX	0:85b3fd62ea1a	75	#if defined __TARGET_FPU_VFP
NYX	0:85b3fd62ea1a	76	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	77	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	78	#else
NYX	0:85b3fd62ea1a	79	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	80	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	81	#endif
NYX	0:85b3fd62ea1a	82	#else
NYX	0:85b3fd62ea1a	83	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	84	#endif
NYX	0:85b3fd62ea1a	85
NYX	0:85b3fd62ea1a	86	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX	0:85b3fd62ea1a	87	#if defined __ARM_PCS_VFP
NYX	0:85b3fd62ea1a	88	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	89	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	90	#else
NYX	0:85b3fd62ea1a	91	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	92	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	93	#endif
NYX	0:85b3fd62ea1a	94	#else
NYX	0:85b3fd62ea1a	95	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	96	#endif
NYX	0:85b3fd62ea1a	97
NYX	0:85b3fd62ea1a	98	#elif defined ( __GNUC__ )
NYX	0:85b3fd62ea1a	99	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
NYX	0:85b3fd62ea1a	100	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	101	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	102	#else
NYX	0:85b3fd62ea1a	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	104	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	105	#endif
NYX	0:85b3fd62ea1a	106	#else
NYX	0:85b3fd62ea1a	107	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	108	#endif
NYX	0:85b3fd62ea1a	109
NYX	0:85b3fd62ea1a	110	#elif defined ( __ICCARM__ )
NYX	0:85b3fd62ea1a	111	#if defined __ARMVFP__
NYX	0:85b3fd62ea1a	112	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	113	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	114	#else
NYX	0:85b3fd62ea1a	115	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	116	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	117	#endif
NYX	0:85b3fd62ea1a	118	#else
NYX	0:85b3fd62ea1a	119	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	120	#endif
NYX	0:85b3fd62ea1a	121
NYX	0:85b3fd62ea1a	122	#elif defined ( __TI_ARM__ )
NYX	0:85b3fd62ea1a	123	#if defined __TI_VFP_SUPPORT__
NYX	0:85b3fd62ea1a	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	125	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	126	#else
NYX	0:85b3fd62ea1a	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	128	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	129	#endif
NYX	0:85b3fd62ea1a	130	#else
NYX	0:85b3fd62ea1a	131	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	132	#endif
NYX	0:85b3fd62ea1a	133
NYX	0:85b3fd62ea1a	134	#elif defined ( __TASKING__ )
NYX	0:85b3fd62ea1a	135	#if defined __FPU_VFP__
NYX	0:85b3fd62ea1a	136	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	137	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	138	#else
NYX	0:85b3fd62ea1a	139	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	140	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	141	#endif
NYX	0:85b3fd62ea1a	142	#else
NYX	0:85b3fd62ea1a	143	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	144	#endif
NYX	0:85b3fd62ea1a	145
NYX	0:85b3fd62ea1a	146	#elif defined ( __CSMC__ )
NYX	0:85b3fd62ea1a	147	#if ( __CSMC__ & 0x400U)
NYX	0:85b3fd62ea1a	148	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	149	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	150	#else
NYX	0:85b3fd62ea1a	151	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	152	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	153	#endif
NYX	0:85b3fd62ea1a	154	#else
NYX	0:85b3fd62ea1a	155	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	156	#endif
NYX	0:85b3fd62ea1a	157
NYX	0:85b3fd62ea1a	158	#endif
NYX	0:85b3fd62ea1a	159
NYX	0:85b3fd62ea1a	160	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
NYX	0:85b3fd62ea1a	161
NYX	0:85b3fd62ea1a	162
NYX	0:85b3fd62ea1a	163	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	164	}
NYX	0:85b3fd62ea1a	165	#endif
NYX	0:85b3fd62ea1a	166
NYX	0:85b3fd62ea1a	167	#endif /* __CORE_CM33_H_GENERIC */
NYX	0:85b3fd62ea1a	168
NYX	0:85b3fd62ea1a	169	#ifndef __CMSIS_GENERIC
NYX	0:85b3fd62ea1a	170
NYX	0:85b3fd62ea1a	171	#ifndef __CORE_CM33_H_DEPENDANT
NYX	0:85b3fd62ea1a	172	#define __CORE_CM33_H_DEPENDANT
NYX	0:85b3fd62ea1a	173
NYX	0:85b3fd62ea1a	174	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	175	extern "C" {
NYX	0:85b3fd62ea1a	176	#endif
NYX	0:85b3fd62ea1a	177
NYX	0:85b3fd62ea1a	178	/* check device defines and use defaults */
NYX	0:85b3fd62ea1a	179	#if defined __CHECK_DEVICE_DEFINES
NYX	0:85b3fd62ea1a	180	#ifndef __CM33_REV
NYX	0:85b3fd62ea1a	181	#define __CM33_REV 0x0000U
NYX	0:85b3fd62ea1a	182	#warning "__CM33_REV not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	183	#endif
NYX	0:85b3fd62ea1a	184
NYX	0:85b3fd62ea1a	185	#ifndef __FPU_PRESENT
NYX	0:85b3fd62ea1a	186	#define __FPU_PRESENT 0U
NYX	0:85b3fd62ea1a	187	#warning "__FPU_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	188	#endif
NYX	0:85b3fd62ea1a	189
NYX	0:85b3fd62ea1a	190	#ifndef __MPU_PRESENT
NYX	0:85b3fd62ea1a	191	#define __MPU_PRESENT 0U
NYX	0:85b3fd62ea1a	192	#warning "__MPU_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	193	#endif
NYX	0:85b3fd62ea1a	194
NYX	0:85b3fd62ea1a	195	#ifndef __SAUREGION_PRESENT
NYX	0:85b3fd62ea1a	196	#define __SAUREGION_PRESENT 0U
NYX	0:85b3fd62ea1a	197	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	198	#endif
NYX	0:85b3fd62ea1a	199
NYX	0:85b3fd62ea1a	200	#ifndef __DSP_PRESENT
NYX	0:85b3fd62ea1a	201	#define __DSP_PRESENT 0U
NYX	0:85b3fd62ea1a	202	#warning "__DSP_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	203	#endif
NYX	0:85b3fd62ea1a	204
NYX	0:85b3fd62ea1a	205	#ifndef __NVIC_PRIO_BITS
NYX	0:85b3fd62ea1a	206	#define __NVIC_PRIO_BITS 3U
NYX	0:85b3fd62ea1a	207	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	208	#endif
NYX	0:85b3fd62ea1a	209
NYX	0:85b3fd62ea1a	210	#ifndef __Vendor_SysTickConfig
NYX	0:85b3fd62ea1a	211	#define __Vendor_SysTickConfig 0U
NYX	0:85b3fd62ea1a	212	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	213	#endif
NYX	0:85b3fd62ea1a	214	#endif
NYX	0:85b3fd62ea1a	215
NYX	0:85b3fd62ea1a	216	/* IO definitions (access restrictions to peripheral registers) */
NYX	0:85b3fd62ea1a	217	/**
NYX	0:85b3fd62ea1a	218	\defgroup CMSIS_glob_defs CMSIS Global Defines
NYX	0:85b3fd62ea1a	219
NYX	0:85b3fd62ea1a	220	<strong>IO Type Qualifiers</strong> are used
NYX	0:85b3fd62ea1a	221	\li to specify the access to peripheral variables.
NYX	0:85b3fd62ea1a	222	\li for automatic generation of peripheral register debug information.
NYX	0:85b3fd62ea1a	223	*/
NYX	0:85b3fd62ea1a	224	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	225	#define __I volatile /!< Defines 'read only' permissions /
NYX	0:85b3fd62ea1a	226	#else
NYX	0:85b3fd62ea1a	227	#define __I volatile const /!< Defines 'read only' permissions /
NYX	0:85b3fd62ea1a	228	#endif
NYX	0:85b3fd62ea1a	229	#define __O volatile /!< Defines 'write only' permissions /
NYX	0:85b3fd62ea1a	230	#define __IO volatile /!< Defines 'read / write' permissions /
NYX	0:85b3fd62ea1a	231
NYX	0:85b3fd62ea1a	232	/* following defines should be used for structure members */
NYX	0:85b3fd62ea1a	233	#define __IM volatile const /! Defines 'read only' structure member permissions /
NYX	0:85b3fd62ea1a	234	#define __OM volatile /! Defines 'write only' structure member permissions /
NYX	0:85b3fd62ea1a	235	#define __IOM volatile /! Defines 'read / write' structure member permissions /
NYX	0:85b3fd62ea1a	236
NYX	0:85b3fd62ea1a	237	/@} end of group Cortex_M33 /
NYX	0:85b3fd62ea1a	238
NYX	0:85b3fd62ea1a	239
NYX	0:85b3fd62ea1a	240
NYX	0:85b3fd62ea1a	241	/*******************************************************************************
NYX	0:85b3fd62ea1a	242	* Register Abstraction
NYX	0:85b3fd62ea1a	243	Core Register contain:
NYX	0:85b3fd62ea1a	244	- Core Register
NYX	0:85b3fd62ea1a	245	- Core NVIC Register
NYX	0:85b3fd62ea1a	246	- Core SCB Register
NYX	0:85b3fd62ea1a	247	- Core SysTick Register
NYX	0:85b3fd62ea1a	248	- Core Debug Register
NYX	0:85b3fd62ea1a	249	- Core MPU Register
NYX	0:85b3fd62ea1a	250	- Core SAU Register
NYX	0:85b3fd62ea1a	251	- Core FPU Register
NYX	0:85b3fd62ea1a	252	******************************************************************************/
NYX	0:85b3fd62ea1a	253	/**
NYX	0:85b3fd62ea1a	254	\defgroup CMSIS_core_register Defines and Type Definitions
NYX	0:85b3fd62ea1a	255	\brief Type definitions and defines for Cortex-M processor based devices.
NYX	0:85b3fd62ea1a	256	*/
NYX	0:85b3fd62ea1a	257
NYX	0:85b3fd62ea1a	258	/**
NYX	0:85b3fd62ea1a	259	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	260	\defgroup CMSIS_CORE Status and Control Registers
NYX	0:85b3fd62ea1a	261	\brief Core Register type definitions.
NYX	0:85b3fd62ea1a	262	@{
NYX	0:85b3fd62ea1a	263	*/
NYX	0:85b3fd62ea1a	264
NYX	0:85b3fd62ea1a	265	/**
NYX	0:85b3fd62ea1a	266	\brief Union type to access the Application Program Status Register (APSR).
NYX	0:85b3fd62ea1a	267	*/
NYX	0:85b3fd62ea1a	268	typedef union
NYX	0:85b3fd62ea1a	269	{
NYX	0:85b3fd62ea1a	270	struct
NYX	0:85b3fd62ea1a	271	{
NYX	0:85b3fd62ea1a	272	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
NYX	0:85b3fd62ea1a	273	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
NYX	0:85b3fd62ea1a	274	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
NYX	0:85b3fd62ea1a	275	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
NYX	0:85b3fd62ea1a	276	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
NYX	0:85b3fd62ea1a	277	uint32_t C:1; /!< bit: 29 Carry condition code flag /
NYX	0:85b3fd62ea1a	278	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
NYX	0:85b3fd62ea1a	279	uint32_t N:1; /!< bit: 31 Negative condition code flag /
NYX	0:85b3fd62ea1a	280	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	281	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	282	} APSR_Type;
NYX	0:85b3fd62ea1a	283
NYX	0:85b3fd62ea1a	284	/* APSR Register Definitions */
NYX	0:85b3fd62ea1a	285	#define APSR_N_Pos 31U /!< APSR: N Position /
NYX	0:85b3fd62ea1a	286	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
NYX	0:85b3fd62ea1a	287
NYX	0:85b3fd62ea1a	288	#define APSR_Z_Pos 30U /!< APSR: Z Position /
NYX	0:85b3fd62ea1a	289	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
NYX	0:85b3fd62ea1a	290
NYX	0:85b3fd62ea1a	291	#define APSR_C_Pos 29U /!< APSR: C Position /
NYX	0:85b3fd62ea1a	292	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
NYX	0:85b3fd62ea1a	293
NYX	0:85b3fd62ea1a	294	#define APSR_V_Pos 28U /!< APSR: V Position /
NYX	0:85b3fd62ea1a	295	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
NYX	0:85b3fd62ea1a	296
NYX	0:85b3fd62ea1a	297	#define APSR_Q_Pos 27U /!< APSR: Q Position /
NYX	0:85b3fd62ea1a	298	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
NYX	0:85b3fd62ea1a	299
NYX	0:85b3fd62ea1a	300	#define APSR_GE_Pos 16U /!< APSR: GE Position /
NYX	0:85b3fd62ea1a	301	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
NYX	0:85b3fd62ea1a	302
NYX	0:85b3fd62ea1a	303
NYX	0:85b3fd62ea1a	304	/**
NYX	0:85b3fd62ea1a	305	\brief Union type to access the Interrupt Program Status Register (IPSR).
NYX	0:85b3fd62ea1a	306	*/
NYX	0:85b3fd62ea1a	307	typedef union
NYX	0:85b3fd62ea1a	308	{
NYX	0:85b3fd62ea1a	309	struct
NYX	0:85b3fd62ea1a	310	{
NYX	0:85b3fd62ea1a	311	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
NYX	0:85b3fd62ea1a	312	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
NYX	0:85b3fd62ea1a	313	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	314	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	315	} IPSR_Type;
NYX	0:85b3fd62ea1a	316
NYX	0:85b3fd62ea1a	317	/* IPSR Register Definitions */
NYX	0:85b3fd62ea1a	318	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
NYX	0:85b3fd62ea1a	319	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
NYX	0:85b3fd62ea1a	320
NYX	0:85b3fd62ea1a	321
NYX	0:85b3fd62ea1a	322	/**
NYX	0:85b3fd62ea1a	323	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
NYX	0:85b3fd62ea1a	324	*/
NYX	0:85b3fd62ea1a	325	typedef union
NYX	0:85b3fd62ea1a	326	{
NYX	0:85b3fd62ea1a	327	struct
NYX	0:85b3fd62ea1a	328	{
NYX	0:85b3fd62ea1a	329	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
NYX	0:85b3fd62ea1a	330	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
NYX	0:85b3fd62ea1a	331	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
NYX	0:85b3fd62ea1a	332	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
NYX	0:85b3fd62ea1a	333	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
NYX	0:85b3fd62ea1a	334	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
NYX	0:85b3fd62ea1a	335	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
NYX	0:85b3fd62ea1a	336	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
NYX	0:85b3fd62ea1a	337	uint32_t C:1; /!< bit: 29 Carry condition code flag /
NYX	0:85b3fd62ea1a	338	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
NYX	0:85b3fd62ea1a	339	uint32_t N:1; /!< bit: 31 Negative condition code flag /
NYX	0:85b3fd62ea1a	340	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	341	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	342	} xPSR_Type;
NYX	0:85b3fd62ea1a	343
NYX	0:85b3fd62ea1a	344	/* xPSR Register Definitions */
NYX	0:85b3fd62ea1a	345	#define xPSR_N_Pos 31U /!< xPSR: N Position /
NYX	0:85b3fd62ea1a	346	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
NYX	0:85b3fd62ea1a	347
NYX	0:85b3fd62ea1a	348	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
NYX	0:85b3fd62ea1a	349	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
NYX	0:85b3fd62ea1a	350
NYX	0:85b3fd62ea1a	351	#define xPSR_C_Pos 29U /!< xPSR: C Position /
NYX	0:85b3fd62ea1a	352	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
NYX	0:85b3fd62ea1a	353
NYX	0:85b3fd62ea1a	354	#define xPSR_V_Pos 28U /!< xPSR: V Position /
NYX	0:85b3fd62ea1a	355	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
NYX	0:85b3fd62ea1a	356
NYX	0:85b3fd62ea1a	357	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
NYX	0:85b3fd62ea1a	358	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
NYX	0:85b3fd62ea1a	359
NYX	0:85b3fd62ea1a	360	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
NYX	0:85b3fd62ea1a	361	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
NYX	0:85b3fd62ea1a	362
NYX	0:85b3fd62ea1a	363	#define xPSR_T_Pos 24U /!< xPSR: T Position /
NYX	0:85b3fd62ea1a	364	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
NYX	0:85b3fd62ea1a	365
NYX	0:85b3fd62ea1a	366	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
NYX	0:85b3fd62ea1a	367	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
NYX	0:85b3fd62ea1a	368
NYX	0:85b3fd62ea1a	369	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
NYX	0:85b3fd62ea1a	370	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
NYX	0:85b3fd62ea1a	371
NYX	0:85b3fd62ea1a	372
NYX	0:85b3fd62ea1a	373	/**
NYX	0:85b3fd62ea1a	374	\brief Union type to access the Control Registers (CONTROL).
NYX	0:85b3fd62ea1a	375	*/
NYX	0:85b3fd62ea1a	376	typedef union
NYX	0:85b3fd62ea1a	377	{
NYX	0:85b3fd62ea1a	378	struct
NYX	0:85b3fd62ea1a	379	{
NYX	0:85b3fd62ea1a	380	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
NYX	0:85b3fd62ea1a	381	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
NYX	0:85b3fd62ea1a	382	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
NYX	0:85b3fd62ea1a	383	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
NYX	0:85b3fd62ea1a	384	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
NYX	0:85b3fd62ea1a	385	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	386	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	387	} CONTROL_Type;
NYX	0:85b3fd62ea1a	388
NYX	0:85b3fd62ea1a	389	/* CONTROL Register Definitions */
NYX	0:85b3fd62ea1a	390	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
NYX	0:85b3fd62ea1a	391	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
NYX	0:85b3fd62ea1a	392
NYX	0:85b3fd62ea1a	393	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
NYX	0:85b3fd62ea1a	394	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
NYX	0:85b3fd62ea1a	395
NYX	0:85b3fd62ea1a	396	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
NYX	0:85b3fd62ea1a	397	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
NYX	0:85b3fd62ea1a	398
NYX	0:85b3fd62ea1a	399	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
NYX	0:85b3fd62ea1a	400	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
NYX	0:85b3fd62ea1a	401
NYX	0:85b3fd62ea1a	402	/@} end of group CMSIS_CORE /
NYX	0:85b3fd62ea1a	403
NYX	0:85b3fd62ea1a	404
NYX	0:85b3fd62ea1a	405	/**
NYX	0:85b3fd62ea1a	406	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	407	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
NYX	0:85b3fd62ea1a	408	\brief Type definitions for the NVIC Registers
NYX	0:85b3fd62ea1a	409	@{
NYX	0:85b3fd62ea1a	410	*/
NYX	0:85b3fd62ea1a	411
NYX	0:85b3fd62ea1a	412	/**
NYX	0:85b3fd62ea1a	413	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
NYX	0:85b3fd62ea1a	414	*/
NYX	0:85b3fd62ea1a	415	typedef struct
NYX	0:85b3fd62ea1a	416	{
NYX	0:85b3fd62ea1a	417	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
NYX	0:85b3fd62ea1a	418	uint32_t RESERVED0[16U];
NYX	0:85b3fd62ea1a	419	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
NYX	0:85b3fd62ea1a	420	uint32_t RSERVED1[16U];
NYX	0:85b3fd62ea1a	421	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
NYX	0:85b3fd62ea1a	422	uint32_t RESERVED2[16U];
NYX	0:85b3fd62ea1a	423	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
NYX	0:85b3fd62ea1a	424	uint32_t RESERVED3[16U];
NYX	0:85b3fd62ea1a	425	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
NYX	0:85b3fd62ea1a	426	uint32_t RESERVED4[16U];
NYX	0:85b3fd62ea1a	427	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
NYX	0:85b3fd62ea1a	428	uint32_t RESERVED5[16U];
NYX	0:85b3fd62ea1a	429	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
NYX	0:85b3fd62ea1a	430	uint32_t RESERVED6[580U];
NYX	0:85b3fd62ea1a	431	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
NYX	0:85b3fd62ea1a	432	} NVIC_Type;
NYX	0:85b3fd62ea1a	433
NYX	0:85b3fd62ea1a	434	/* Software Triggered Interrupt Register Definitions */
NYX	0:85b3fd62ea1a	435	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
NYX	0:85b3fd62ea1a	436	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
NYX	0:85b3fd62ea1a	437
NYX	0:85b3fd62ea1a	438	/@} end of group CMSIS_NVIC /
NYX	0:85b3fd62ea1a	439
NYX	0:85b3fd62ea1a	440
NYX	0:85b3fd62ea1a	441	/**
NYX	0:85b3fd62ea1a	442	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	443	\defgroup CMSIS_SCB System Control Block (SCB)
NYX	0:85b3fd62ea1a	444	\brief Type definitions for the System Control Block Registers
NYX	0:85b3fd62ea1a	445	@{
NYX	0:85b3fd62ea1a	446	*/
NYX	0:85b3fd62ea1a	447
NYX	0:85b3fd62ea1a	448	/**
NYX	0:85b3fd62ea1a	449	\brief Structure type to access the System Control Block (SCB).
NYX	0:85b3fd62ea1a	450	*/
NYX	0:85b3fd62ea1a	451	typedef struct
NYX	0:85b3fd62ea1a	452	{
NYX	0:85b3fd62ea1a	453	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
NYX	0:85b3fd62ea1a	454	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
NYX	0:85b3fd62ea1a	455	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
NYX	0:85b3fd62ea1a	456	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
NYX	0:85b3fd62ea1a	457	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
NYX	0:85b3fd62ea1a	458	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
NYX	0:85b3fd62ea1a	459	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
NYX	0:85b3fd62ea1a	460	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
NYX	0:85b3fd62ea1a	461	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
NYX	0:85b3fd62ea1a	462	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
NYX	0:85b3fd62ea1a	463	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
NYX	0:85b3fd62ea1a	464	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
NYX	0:85b3fd62ea1a	465	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
NYX	0:85b3fd62ea1a	466	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
NYX	0:85b3fd62ea1a	467	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
NYX	0:85b3fd62ea1a	468	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
NYX	0:85b3fd62ea1a	469	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
NYX	0:85b3fd62ea1a	470	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
NYX	0:85b3fd62ea1a	471	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
NYX	0:85b3fd62ea1a	472	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
NYX	0:85b3fd62ea1a	473	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
NYX	0:85b3fd62ea1a	474	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
NYX	0:85b3fd62ea1a	475	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
NYX	0:85b3fd62ea1a	476	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
NYX	0:85b3fd62ea1a	477	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
NYX	0:85b3fd62ea1a	478	uint32_t RESERVED3[92U];
NYX	0:85b3fd62ea1a	479	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
NYX	0:85b3fd62ea1a	480	uint32_t RESERVED4[15U];
NYX	0:85b3fd62ea1a	481	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
NYX	0:85b3fd62ea1a	482	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
NYX	0:85b3fd62ea1a	483	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
NYX	0:85b3fd62ea1a	484	uint32_t RESERVED5[1U];
NYX	0:85b3fd62ea1a	485	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
NYX	0:85b3fd62ea1a	486	uint32_t RESERVED6[1U];
NYX	0:85b3fd62ea1a	487	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
NYX	0:85b3fd62ea1a	488	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
NYX	0:85b3fd62ea1a	489	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
NYX	0:85b3fd62ea1a	490	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
NYX	0:85b3fd62ea1a	491	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
NYX	0:85b3fd62ea1a	492	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
NYX	0:85b3fd62ea1a	493	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
NYX	0:85b3fd62ea1a	494	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
NYX	0:85b3fd62ea1a	495	uint32_t RESERVED7[6U];
NYX	0:85b3fd62ea1a	496	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
NYX	0:85b3fd62ea1a	497	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
NYX	0:85b3fd62ea1a	498	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
NYX	0:85b3fd62ea1a	499	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
NYX	0:85b3fd62ea1a	500	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
NYX	0:85b3fd62ea1a	501	uint32_t RESERVED8[1U];
NYX	0:85b3fd62ea1a	502	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
NYX	0:85b3fd62ea1a	503	} SCB_Type;
NYX	0:85b3fd62ea1a	504
NYX	0:85b3fd62ea1a	505	/* SCB CPUID Register Definitions */
NYX	0:85b3fd62ea1a	506	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
NYX	0:85b3fd62ea1a	507	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
NYX	0:85b3fd62ea1a	508
NYX	0:85b3fd62ea1a	509	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
NYX	0:85b3fd62ea1a	510	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
NYX	0:85b3fd62ea1a	511
NYX	0:85b3fd62ea1a	512	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
NYX	0:85b3fd62ea1a	513	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
NYX	0:85b3fd62ea1a	514
NYX	0:85b3fd62ea1a	515	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
NYX	0:85b3fd62ea1a	516	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
NYX	0:85b3fd62ea1a	517
NYX	0:85b3fd62ea1a	518	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
NYX	0:85b3fd62ea1a	519	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
NYX	0:85b3fd62ea1a	520
NYX	0:85b3fd62ea1a	521	/* SCB Interrupt Control State Register Definitions */
NYX	0:85b3fd62ea1a	522	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
NYX	0:85b3fd62ea1a	523	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
NYX	0:85b3fd62ea1a	524
NYX	0:85b3fd62ea1a	525	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
NYX	0:85b3fd62ea1a	526	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
NYX	0:85b3fd62ea1a	527
NYX	0:85b3fd62ea1a	528	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
NYX	0:85b3fd62ea1a	529	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
NYX	0:85b3fd62ea1a	530
NYX	0:85b3fd62ea1a	531	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
NYX	0:85b3fd62ea1a	532	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
NYX	0:85b3fd62ea1a	533
NYX	0:85b3fd62ea1a	534	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
NYX	0:85b3fd62ea1a	535	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
NYX	0:85b3fd62ea1a	536
NYX	0:85b3fd62ea1a	537	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
NYX	0:85b3fd62ea1a	538	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
NYX	0:85b3fd62ea1a	539
NYX	0:85b3fd62ea1a	540	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
NYX	0:85b3fd62ea1a	541	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
NYX	0:85b3fd62ea1a	542
NYX	0:85b3fd62ea1a	543	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
NYX	0:85b3fd62ea1a	544	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
NYX	0:85b3fd62ea1a	545
NYX	0:85b3fd62ea1a	546	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
NYX	0:85b3fd62ea1a	547	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
NYX	0:85b3fd62ea1a	548
NYX	0:85b3fd62ea1a	549	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
NYX	0:85b3fd62ea1a	550	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
NYX	0:85b3fd62ea1a	551
NYX	0:85b3fd62ea1a	552	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
NYX	0:85b3fd62ea1a	553	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
NYX	0:85b3fd62ea1a	554
NYX	0:85b3fd62ea1a	555	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
NYX	0:85b3fd62ea1a	556	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
NYX	0:85b3fd62ea1a	557
NYX	0:85b3fd62ea1a	558	/* SCB Vector Table Offset Register Definitions */
NYX	0:85b3fd62ea1a	559	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
NYX	0:85b3fd62ea1a	560	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
NYX	0:85b3fd62ea1a	561
NYX	0:85b3fd62ea1a	562	/* SCB Application Interrupt and Reset Control Register Definitions */
NYX	0:85b3fd62ea1a	563	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
NYX	0:85b3fd62ea1a	564	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
NYX	0:85b3fd62ea1a	565
NYX	0:85b3fd62ea1a	566	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
NYX	0:85b3fd62ea1a	567	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
NYX	0:85b3fd62ea1a	568
NYX	0:85b3fd62ea1a	569	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
NYX	0:85b3fd62ea1a	570	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
NYX	0:85b3fd62ea1a	571
NYX	0:85b3fd62ea1a	572	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
NYX	0:85b3fd62ea1a	573	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
NYX	0:85b3fd62ea1a	574
NYX	0:85b3fd62ea1a	575	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
NYX	0:85b3fd62ea1a	576	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
NYX	0:85b3fd62ea1a	577
NYX	0:85b3fd62ea1a	578	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
NYX	0:85b3fd62ea1a	579	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
NYX	0:85b3fd62ea1a	580
NYX	0:85b3fd62ea1a	581	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
NYX	0:85b3fd62ea1a	582	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
NYX	0:85b3fd62ea1a	583
NYX	0:85b3fd62ea1a	584	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
NYX	0:85b3fd62ea1a	585	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
NYX	0:85b3fd62ea1a	586
NYX	0:85b3fd62ea1a	587	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
NYX	0:85b3fd62ea1a	588	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
NYX	0:85b3fd62ea1a	589
NYX	0:85b3fd62ea1a	590	/* SCB System Control Register Definitions */
NYX	0:85b3fd62ea1a	591	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
NYX	0:85b3fd62ea1a	592	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
NYX	0:85b3fd62ea1a	593
NYX	0:85b3fd62ea1a	594	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
NYX	0:85b3fd62ea1a	595	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
NYX	0:85b3fd62ea1a	596
NYX	0:85b3fd62ea1a	597	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
NYX	0:85b3fd62ea1a	598	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
NYX	0:85b3fd62ea1a	599
NYX	0:85b3fd62ea1a	600	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
NYX	0:85b3fd62ea1a	601	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
NYX	0:85b3fd62ea1a	602
NYX	0:85b3fd62ea1a	603	/* SCB Configuration Control Register Definitions */
NYX	0:85b3fd62ea1a	604	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
NYX	0:85b3fd62ea1a	605	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
NYX	0:85b3fd62ea1a	606
NYX	0:85b3fd62ea1a	607	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
NYX	0:85b3fd62ea1a	608	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
NYX	0:85b3fd62ea1a	609
NYX	0:85b3fd62ea1a	610	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
NYX	0:85b3fd62ea1a	611	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
NYX	0:85b3fd62ea1a	612
NYX	0:85b3fd62ea1a	613	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
NYX	0:85b3fd62ea1a	614	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
NYX	0:85b3fd62ea1a	615
NYX	0:85b3fd62ea1a	616	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
NYX	0:85b3fd62ea1a	617	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
NYX	0:85b3fd62ea1a	618
NYX	0:85b3fd62ea1a	619	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
NYX	0:85b3fd62ea1a	620	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
NYX	0:85b3fd62ea1a	621
NYX	0:85b3fd62ea1a	622	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
NYX	0:85b3fd62ea1a	623	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
NYX	0:85b3fd62ea1a	624
NYX	0:85b3fd62ea1a	625	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
NYX	0:85b3fd62ea1a	626	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
NYX	0:85b3fd62ea1a	627
NYX	0:85b3fd62ea1a	628	/* SCB System Handler Control and State Register Definitions */
NYX	0:85b3fd62ea1a	629	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
NYX	0:85b3fd62ea1a	630	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	631
NYX	0:85b3fd62ea1a	632	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
NYX	0:85b3fd62ea1a	633	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	634
NYX	0:85b3fd62ea1a	635	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
NYX	0:85b3fd62ea1a	636	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
NYX	0:85b3fd62ea1a	637
NYX	0:85b3fd62ea1a	638	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
NYX	0:85b3fd62ea1a	639	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
NYX	0:85b3fd62ea1a	640
NYX	0:85b3fd62ea1a	641	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
NYX	0:85b3fd62ea1a	642	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
NYX	0:85b3fd62ea1a	643
NYX	0:85b3fd62ea1a	644	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
NYX	0:85b3fd62ea1a	645	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
NYX	0:85b3fd62ea1a	646
NYX	0:85b3fd62ea1a	647	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
NYX	0:85b3fd62ea1a	648	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
NYX	0:85b3fd62ea1a	649
NYX	0:85b3fd62ea1a	650	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
NYX	0:85b3fd62ea1a	651	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	652
NYX	0:85b3fd62ea1a	653	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
NYX	0:85b3fd62ea1a	654	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	655
NYX	0:85b3fd62ea1a	656	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
NYX	0:85b3fd62ea1a	657	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	658
NYX	0:85b3fd62ea1a	659	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
NYX	0:85b3fd62ea1a	660	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
NYX	0:85b3fd62ea1a	661
NYX	0:85b3fd62ea1a	662	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
NYX	0:85b3fd62ea1a	663	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
NYX	0:85b3fd62ea1a	664
NYX	0:85b3fd62ea1a	665	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
NYX	0:85b3fd62ea1a	666	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
NYX	0:85b3fd62ea1a	667
NYX	0:85b3fd62ea1a	668	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
NYX	0:85b3fd62ea1a	669	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
NYX	0:85b3fd62ea1a	670
NYX	0:85b3fd62ea1a	671	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
NYX	0:85b3fd62ea1a	672	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
NYX	0:85b3fd62ea1a	673
NYX	0:85b3fd62ea1a	674	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
NYX	0:85b3fd62ea1a	675	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
NYX	0:85b3fd62ea1a	676
NYX	0:85b3fd62ea1a	677	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
NYX	0:85b3fd62ea1a	678	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
NYX	0:85b3fd62ea1a	679
NYX	0:85b3fd62ea1a	680	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
NYX	0:85b3fd62ea1a	681	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
NYX	0:85b3fd62ea1a	682
NYX	0:85b3fd62ea1a	683	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
NYX	0:85b3fd62ea1a	684	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
NYX	0:85b3fd62ea1a	685
NYX	0:85b3fd62ea1a	686	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
NYX	0:85b3fd62ea1a	687	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
NYX	0:85b3fd62ea1a	688
NYX	0:85b3fd62ea1a	689	/* SCB Configurable Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	690	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
NYX	0:85b3fd62ea1a	691	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
NYX	0:85b3fd62ea1a	692
NYX	0:85b3fd62ea1a	693	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
NYX	0:85b3fd62ea1a	694	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
NYX	0:85b3fd62ea1a	695
NYX	0:85b3fd62ea1a	696	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
NYX	0:85b3fd62ea1a	697	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
NYX	0:85b3fd62ea1a	698
NYX	0:85b3fd62ea1a	699	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	700	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
NYX	0:85b3fd62ea1a	701	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
NYX	0:85b3fd62ea1a	702
NYX	0:85b3fd62ea1a	703	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
NYX	0:85b3fd62ea1a	704	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
NYX	0:85b3fd62ea1a	705
NYX	0:85b3fd62ea1a	706	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
NYX	0:85b3fd62ea1a	707	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
NYX	0:85b3fd62ea1a	708
NYX	0:85b3fd62ea1a	709	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
NYX	0:85b3fd62ea1a	710	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
NYX	0:85b3fd62ea1a	711
NYX	0:85b3fd62ea1a	712	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
NYX	0:85b3fd62ea1a	713	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
NYX	0:85b3fd62ea1a	714
NYX	0:85b3fd62ea1a	715	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
NYX	0:85b3fd62ea1a	716	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
NYX	0:85b3fd62ea1a	717
NYX	0:85b3fd62ea1a	718	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	719	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
NYX	0:85b3fd62ea1a	720	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
NYX	0:85b3fd62ea1a	721
NYX	0:85b3fd62ea1a	722	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
NYX	0:85b3fd62ea1a	723	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
NYX	0:85b3fd62ea1a	724
NYX	0:85b3fd62ea1a	725	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
NYX	0:85b3fd62ea1a	726	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
NYX	0:85b3fd62ea1a	727
NYX	0:85b3fd62ea1a	728	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
NYX	0:85b3fd62ea1a	729	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
NYX	0:85b3fd62ea1a	730
NYX	0:85b3fd62ea1a	731	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
NYX	0:85b3fd62ea1a	732	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
NYX	0:85b3fd62ea1a	733
NYX	0:85b3fd62ea1a	734	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
NYX	0:85b3fd62ea1a	735	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
NYX	0:85b3fd62ea1a	736
NYX	0:85b3fd62ea1a	737	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
NYX	0:85b3fd62ea1a	738	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
NYX	0:85b3fd62ea1a	739
NYX	0:85b3fd62ea1a	740	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	741	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
NYX	0:85b3fd62ea1a	742	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
NYX	0:85b3fd62ea1a	743
NYX	0:85b3fd62ea1a	744	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
NYX	0:85b3fd62ea1a	745	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
NYX	0:85b3fd62ea1a	746
NYX	0:85b3fd62ea1a	747	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
NYX	0:85b3fd62ea1a	748	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
NYX	0:85b3fd62ea1a	749
NYX	0:85b3fd62ea1a	750	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
NYX	0:85b3fd62ea1a	751	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
NYX	0:85b3fd62ea1a	752
NYX	0:85b3fd62ea1a	753	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
NYX	0:85b3fd62ea1a	754	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
NYX	0:85b3fd62ea1a	755
NYX	0:85b3fd62ea1a	756	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
NYX	0:85b3fd62ea1a	757	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
NYX	0:85b3fd62ea1a	758
NYX	0:85b3fd62ea1a	759	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
NYX	0:85b3fd62ea1a	760	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
NYX	0:85b3fd62ea1a	761
NYX	0:85b3fd62ea1a	762	/* SCB Hard Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	763	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
NYX	0:85b3fd62ea1a	764	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
NYX	0:85b3fd62ea1a	765
NYX	0:85b3fd62ea1a	766	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
NYX	0:85b3fd62ea1a	767	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
NYX	0:85b3fd62ea1a	768
NYX	0:85b3fd62ea1a	769	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
NYX	0:85b3fd62ea1a	770	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
NYX	0:85b3fd62ea1a	771
NYX	0:85b3fd62ea1a	772	/* SCB Debug Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	773	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
NYX	0:85b3fd62ea1a	774	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
NYX	0:85b3fd62ea1a	775
NYX	0:85b3fd62ea1a	776	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
NYX	0:85b3fd62ea1a	777	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
NYX	0:85b3fd62ea1a	778
NYX	0:85b3fd62ea1a	779	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
NYX	0:85b3fd62ea1a	780	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
NYX	0:85b3fd62ea1a	781
NYX	0:85b3fd62ea1a	782	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
NYX	0:85b3fd62ea1a	783	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
NYX	0:85b3fd62ea1a	784
NYX	0:85b3fd62ea1a	785	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
NYX	0:85b3fd62ea1a	786	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
NYX	0:85b3fd62ea1a	787
NYX	0:85b3fd62ea1a	788	/* SCB Non-Secure Access Control Register Definitions */
NYX	0:85b3fd62ea1a	789	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
NYX	0:85b3fd62ea1a	790	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
NYX	0:85b3fd62ea1a	791
NYX	0:85b3fd62ea1a	792	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
NYX	0:85b3fd62ea1a	793	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
NYX	0:85b3fd62ea1a	794
NYX	0:85b3fd62ea1a	795	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
NYX	0:85b3fd62ea1a	796	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
NYX	0:85b3fd62ea1a	797
NYX	0:85b3fd62ea1a	798	/* SCB Cache Level ID Register Definitions */
NYX	0:85b3fd62ea1a	799	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
NYX	0:85b3fd62ea1a	800	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
NYX	0:85b3fd62ea1a	801
NYX	0:85b3fd62ea1a	802	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
NYX	0:85b3fd62ea1a	803	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
NYX	0:85b3fd62ea1a	804
NYX	0:85b3fd62ea1a	805	/* SCB Cache Type Register Definitions */
NYX	0:85b3fd62ea1a	806	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
NYX	0:85b3fd62ea1a	807	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
NYX	0:85b3fd62ea1a	808
NYX	0:85b3fd62ea1a	809	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
NYX	0:85b3fd62ea1a	810	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
NYX	0:85b3fd62ea1a	811
NYX	0:85b3fd62ea1a	812	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
NYX	0:85b3fd62ea1a	813	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
NYX	0:85b3fd62ea1a	814
NYX	0:85b3fd62ea1a	815	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
NYX	0:85b3fd62ea1a	816	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
NYX	0:85b3fd62ea1a	817
NYX	0:85b3fd62ea1a	818	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
NYX	0:85b3fd62ea1a	819	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
NYX	0:85b3fd62ea1a	820
NYX	0:85b3fd62ea1a	821	/* SCB Cache Size ID Register Definitions */
NYX	0:85b3fd62ea1a	822	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
NYX	0:85b3fd62ea1a	823	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
NYX	0:85b3fd62ea1a	824
NYX	0:85b3fd62ea1a	825	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
NYX	0:85b3fd62ea1a	826	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
NYX	0:85b3fd62ea1a	827
NYX	0:85b3fd62ea1a	828	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
NYX	0:85b3fd62ea1a	829	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
NYX	0:85b3fd62ea1a	830
NYX	0:85b3fd62ea1a	831	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
NYX	0:85b3fd62ea1a	832	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
NYX	0:85b3fd62ea1a	833
NYX	0:85b3fd62ea1a	834	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
NYX	0:85b3fd62ea1a	835	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
NYX	0:85b3fd62ea1a	836
NYX	0:85b3fd62ea1a	837	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
NYX	0:85b3fd62ea1a	838	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
NYX	0:85b3fd62ea1a	839
NYX	0:85b3fd62ea1a	840	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
NYX	0:85b3fd62ea1a	841	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
NYX	0:85b3fd62ea1a	842
NYX	0:85b3fd62ea1a	843	/* SCB Cache Size Selection Register Definitions */
NYX	0:85b3fd62ea1a	844	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
NYX	0:85b3fd62ea1a	845	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
NYX	0:85b3fd62ea1a	846
NYX	0:85b3fd62ea1a	847	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
NYX	0:85b3fd62ea1a	848	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
NYX	0:85b3fd62ea1a	849
NYX	0:85b3fd62ea1a	850	/* SCB Software Triggered Interrupt Register Definitions */
NYX	0:85b3fd62ea1a	851	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
NYX	0:85b3fd62ea1a	852	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
NYX	0:85b3fd62ea1a	853
NYX	0:85b3fd62ea1a	854	/* SCB D-Cache Invalidate by Set-way Register Definitions */
NYX	0:85b3fd62ea1a	855	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
NYX	0:85b3fd62ea1a	856	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
NYX	0:85b3fd62ea1a	857
NYX	0:85b3fd62ea1a	858	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
NYX	0:85b3fd62ea1a	859	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
NYX	0:85b3fd62ea1a	860
NYX	0:85b3fd62ea1a	861	/* SCB D-Cache Clean by Set-way Register Definitions */
NYX	0:85b3fd62ea1a	862	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
NYX	0:85b3fd62ea1a	863	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
NYX	0:85b3fd62ea1a	864
NYX	0:85b3fd62ea1a	865	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
NYX	0:85b3fd62ea1a	866	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
NYX	0:85b3fd62ea1a	867
NYX	0:85b3fd62ea1a	868	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
NYX	0:85b3fd62ea1a	869	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
NYX	0:85b3fd62ea1a	870	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
NYX	0:85b3fd62ea1a	871
NYX	0:85b3fd62ea1a	872	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
NYX	0:85b3fd62ea1a	873	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
NYX	0:85b3fd62ea1a	874
NYX	0:85b3fd62ea1a	875	/* Instruction Tightly-Coupled Memory Control Register Definitions */
NYX	0:85b3fd62ea1a	876	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
NYX	0:85b3fd62ea1a	877	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
NYX	0:85b3fd62ea1a	878
NYX	0:85b3fd62ea1a	879	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
NYX	0:85b3fd62ea1a	880	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
NYX	0:85b3fd62ea1a	881
NYX	0:85b3fd62ea1a	882	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
NYX	0:85b3fd62ea1a	883	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
NYX	0:85b3fd62ea1a	884
NYX	0:85b3fd62ea1a	885	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
NYX	0:85b3fd62ea1a	886	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
NYX	0:85b3fd62ea1a	887
NYX	0:85b3fd62ea1a	888	/* Data Tightly-Coupled Memory Control Register Definitions */
NYX	0:85b3fd62ea1a	889	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
NYX	0:85b3fd62ea1a	890	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
NYX	0:85b3fd62ea1a	891
NYX	0:85b3fd62ea1a	892	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
NYX	0:85b3fd62ea1a	893	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
NYX	0:85b3fd62ea1a	894
NYX	0:85b3fd62ea1a	895	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
NYX	0:85b3fd62ea1a	896	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
NYX	0:85b3fd62ea1a	897
NYX	0:85b3fd62ea1a	898	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
NYX	0:85b3fd62ea1a	899	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
NYX	0:85b3fd62ea1a	900
NYX	0:85b3fd62ea1a	901	/* AHBP Control Register Definitions */
NYX	0:85b3fd62ea1a	902	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
NYX	0:85b3fd62ea1a	903	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
NYX	0:85b3fd62ea1a	904
NYX	0:85b3fd62ea1a	905	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
NYX	0:85b3fd62ea1a	906	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
NYX	0:85b3fd62ea1a	907
NYX	0:85b3fd62ea1a	908	/* L1 Cache Control Register Definitions */
NYX	0:85b3fd62ea1a	909	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
NYX	0:85b3fd62ea1a	910	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
NYX	0:85b3fd62ea1a	911
NYX	0:85b3fd62ea1a	912	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
NYX	0:85b3fd62ea1a	913	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
NYX	0:85b3fd62ea1a	914
NYX	0:85b3fd62ea1a	915	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
NYX	0:85b3fd62ea1a	916	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
NYX	0:85b3fd62ea1a	917
NYX	0:85b3fd62ea1a	918	/* AHBS Control Register Definitions */
NYX	0:85b3fd62ea1a	919	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
NYX	0:85b3fd62ea1a	920	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
NYX	0:85b3fd62ea1a	921
NYX	0:85b3fd62ea1a	922	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
NYX	0:85b3fd62ea1a	923	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
NYX	0:85b3fd62ea1a	924
NYX	0:85b3fd62ea1a	925	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
NYX	0:85b3fd62ea1a	926	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
NYX	0:85b3fd62ea1a	927
NYX	0:85b3fd62ea1a	928	/* Auxiliary Bus Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	929	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
NYX	0:85b3fd62ea1a	930	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
NYX	0:85b3fd62ea1a	931
NYX	0:85b3fd62ea1a	932	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
NYX	0:85b3fd62ea1a	933	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
NYX	0:85b3fd62ea1a	934
NYX	0:85b3fd62ea1a	935	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
NYX	0:85b3fd62ea1a	936	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
NYX	0:85b3fd62ea1a	937
NYX	0:85b3fd62ea1a	938	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
NYX	0:85b3fd62ea1a	939	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
NYX	0:85b3fd62ea1a	940
NYX	0:85b3fd62ea1a	941	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
NYX	0:85b3fd62ea1a	942	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
NYX	0:85b3fd62ea1a	943
NYX	0:85b3fd62ea1a	944	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
NYX	0:85b3fd62ea1a	945	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
NYX	0:85b3fd62ea1a	946
NYX	0:85b3fd62ea1a	947	/@} end of group CMSIS_SCB /
NYX	0:85b3fd62ea1a	948
NYX	0:85b3fd62ea1a	949
NYX	0:85b3fd62ea1a	950	/**
NYX	0:85b3fd62ea1a	951	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	952	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
NYX	0:85b3fd62ea1a	953	\brief Type definitions for the System Control and ID Register not in the SCB
NYX	0:85b3fd62ea1a	954	@{
NYX	0:85b3fd62ea1a	955	*/
NYX	0:85b3fd62ea1a	956
NYX	0:85b3fd62ea1a	957	/**
NYX	0:85b3fd62ea1a	958	\brief Structure type to access the System Control and ID Register not in the SCB.
NYX	0:85b3fd62ea1a	959	*/
NYX	0:85b3fd62ea1a	960	typedef struct
NYX	0:85b3fd62ea1a	961	{
NYX	0:85b3fd62ea1a	962	uint32_t RESERVED0[1U];
NYX	0:85b3fd62ea1a	963	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
NYX	0:85b3fd62ea1a	964	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
NYX	0:85b3fd62ea1a	965	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
NYX	0:85b3fd62ea1a	966	} SCnSCB_Type;
NYX	0:85b3fd62ea1a	967
NYX	0:85b3fd62ea1a	968	/* Interrupt Controller Type Register Definitions */
NYX	0:85b3fd62ea1a	969	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
NYX	0:85b3fd62ea1a	970	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
NYX	0:85b3fd62ea1a	971
NYX	0:85b3fd62ea1a	972	/@} end of group CMSIS_SCnotSCB /
NYX	0:85b3fd62ea1a	973
NYX	0:85b3fd62ea1a	974
NYX	0:85b3fd62ea1a	975	/**
NYX	0:85b3fd62ea1a	976	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	977	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
NYX	0:85b3fd62ea1a	978	\brief Type definitions for the System Timer Registers.
NYX	0:85b3fd62ea1a	979	@{
NYX	0:85b3fd62ea1a	980	*/
NYX	0:85b3fd62ea1a	981
NYX	0:85b3fd62ea1a	982	/**
NYX	0:85b3fd62ea1a	983	\brief Structure type to access the System Timer (SysTick).
NYX	0:85b3fd62ea1a	984	*/
NYX	0:85b3fd62ea1a	985	typedef struct
NYX	0:85b3fd62ea1a	986	{
NYX	0:85b3fd62ea1a	987	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
NYX	0:85b3fd62ea1a	988	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
NYX	0:85b3fd62ea1a	989	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
NYX	0:85b3fd62ea1a	990	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
NYX	0:85b3fd62ea1a	991	} SysTick_Type;
NYX	0:85b3fd62ea1a	992
NYX	0:85b3fd62ea1a	993	/* SysTick Control / Status Register Definitions */
NYX	0:85b3fd62ea1a	994	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
NYX	0:85b3fd62ea1a	995	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
NYX	0:85b3fd62ea1a	996
NYX	0:85b3fd62ea1a	997	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
NYX	0:85b3fd62ea1a	998	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
NYX	0:85b3fd62ea1a	999
NYX	0:85b3fd62ea1a	1000	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
NYX	0:85b3fd62ea1a	1001	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
NYX	0:85b3fd62ea1a	1002
NYX	0:85b3fd62ea1a	1003	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
NYX	0:85b3fd62ea1a	1004	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
NYX	0:85b3fd62ea1a	1005
NYX	0:85b3fd62ea1a	1006	/* SysTick Reload Register Definitions */
NYX	0:85b3fd62ea1a	1007	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
NYX	0:85b3fd62ea1a	1008	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
NYX	0:85b3fd62ea1a	1009
NYX	0:85b3fd62ea1a	1010	/* SysTick Current Register Definitions */
NYX	0:85b3fd62ea1a	1011	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
NYX	0:85b3fd62ea1a	1012	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
NYX	0:85b3fd62ea1a	1013
NYX	0:85b3fd62ea1a	1014	/* SysTick Calibration Register Definitions */
NYX	0:85b3fd62ea1a	1015	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
NYX	0:85b3fd62ea1a	1016	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
NYX	0:85b3fd62ea1a	1017
NYX	0:85b3fd62ea1a	1018	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
NYX	0:85b3fd62ea1a	1019	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
NYX	0:85b3fd62ea1a	1020
NYX	0:85b3fd62ea1a	1021	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
NYX	0:85b3fd62ea1a	1022	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
NYX	0:85b3fd62ea1a	1023
NYX	0:85b3fd62ea1a	1024	/@} end of group CMSIS_SysTick /
NYX	0:85b3fd62ea1a	1025
NYX	0:85b3fd62ea1a	1026
NYX	0:85b3fd62ea1a	1027	/**
NYX	0:85b3fd62ea1a	1028	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1029	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
NYX	0:85b3fd62ea1a	1030	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
NYX	0:85b3fd62ea1a	1031	@{
NYX	0:85b3fd62ea1a	1032	*/
NYX	0:85b3fd62ea1a	1033
NYX	0:85b3fd62ea1a	1034	/**
NYX	0:85b3fd62ea1a	1035	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
NYX	0:85b3fd62ea1a	1036	*/
NYX	0:85b3fd62ea1a	1037	typedef struct
NYX	0:85b3fd62ea1a	1038	{
NYX	0:85b3fd62ea1a	1039	__OM union
NYX	0:85b3fd62ea1a	1040	{
NYX	0:85b3fd62ea1a	1041	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
NYX	0:85b3fd62ea1a	1042	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
NYX	0:85b3fd62ea1a	1043	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
NYX	0:85b3fd62ea1a	1044	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
NYX	0:85b3fd62ea1a	1045	uint32_t RESERVED0[864U];
NYX	0:85b3fd62ea1a	1046	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
NYX	0:85b3fd62ea1a	1047	uint32_t RESERVED1[15U];
NYX	0:85b3fd62ea1a	1048	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
NYX	0:85b3fd62ea1a	1049	uint32_t RESERVED2[15U];
NYX	0:85b3fd62ea1a	1050	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
NYX	0:85b3fd62ea1a	1051	uint32_t RESERVED3[29U];
NYX	0:85b3fd62ea1a	1052	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
NYX	0:85b3fd62ea1a	1053	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
NYX	0:85b3fd62ea1a	1054	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
NYX	0:85b3fd62ea1a	1055	uint32_t RESERVED4[43U];
NYX	0:85b3fd62ea1a	1056	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
NYX	0:85b3fd62ea1a	1057	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
NYX	0:85b3fd62ea1a	1058	uint32_t RESERVED5[1U];
NYX	0:85b3fd62ea1a	1059	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
NYX	0:85b3fd62ea1a	1060	uint32_t RESERVED6[4U];
NYX	0:85b3fd62ea1a	1061	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
NYX	0:85b3fd62ea1a	1062	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
NYX	0:85b3fd62ea1a	1063	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
NYX	0:85b3fd62ea1a	1064	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
NYX	0:85b3fd62ea1a	1065	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
NYX	0:85b3fd62ea1a	1066	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
NYX	0:85b3fd62ea1a	1067	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
NYX	0:85b3fd62ea1a	1068	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
NYX	0:85b3fd62ea1a	1069	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
NYX	0:85b3fd62ea1a	1070	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
NYX	0:85b3fd62ea1a	1071	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
NYX	0:85b3fd62ea1a	1072	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
NYX	0:85b3fd62ea1a	1073	} ITM_Type;
NYX	0:85b3fd62ea1a	1074
NYX	0:85b3fd62ea1a	1075	/* ITM Stimulus Port Register Definitions */
NYX	0:85b3fd62ea1a	1076	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
NYX	0:85b3fd62ea1a	1077	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
NYX	0:85b3fd62ea1a	1078
NYX	0:85b3fd62ea1a	1079	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
NYX	0:85b3fd62ea1a	1080	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
NYX	0:85b3fd62ea1a	1081
NYX	0:85b3fd62ea1a	1082	/* ITM Trace Privilege Register Definitions */
NYX	0:85b3fd62ea1a	1083	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
NYX	0:85b3fd62ea1a	1084	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
NYX	0:85b3fd62ea1a	1085
NYX	0:85b3fd62ea1a	1086	/* ITM Trace Control Register Definitions */
NYX	0:85b3fd62ea1a	1087	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
NYX	0:85b3fd62ea1a	1088	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
NYX	0:85b3fd62ea1a	1089
NYX	0:85b3fd62ea1a	1090	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
NYX	0:85b3fd62ea1a	1091	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
NYX	0:85b3fd62ea1a	1092
NYX	0:85b3fd62ea1a	1093	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
NYX	0:85b3fd62ea1a	1094	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
NYX	0:85b3fd62ea1a	1095
NYX	0:85b3fd62ea1a	1096	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
NYX	0:85b3fd62ea1a	1097	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
NYX	0:85b3fd62ea1a	1098
NYX	0:85b3fd62ea1a	1099	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
NYX	0:85b3fd62ea1a	1100	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
NYX	0:85b3fd62ea1a	1101
NYX	0:85b3fd62ea1a	1102	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
NYX	0:85b3fd62ea1a	1103	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
NYX	0:85b3fd62ea1a	1104
NYX	0:85b3fd62ea1a	1105	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
NYX	0:85b3fd62ea1a	1106	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
NYX	0:85b3fd62ea1a	1107
NYX	0:85b3fd62ea1a	1108	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
NYX	0:85b3fd62ea1a	1109	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
NYX	0:85b3fd62ea1a	1110
NYX	0:85b3fd62ea1a	1111	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
NYX	0:85b3fd62ea1a	1112	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
NYX	0:85b3fd62ea1a	1113
NYX	0:85b3fd62ea1a	1114	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
NYX	0:85b3fd62ea1a	1115	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
NYX	0:85b3fd62ea1a	1116
NYX	0:85b3fd62ea1a	1117	/* ITM Integration Write Register Definitions */
NYX	0:85b3fd62ea1a	1118	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
NYX	0:85b3fd62ea1a	1119	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
NYX	0:85b3fd62ea1a	1120
NYX	0:85b3fd62ea1a	1121	/* ITM Integration Read Register Definitions */
NYX	0:85b3fd62ea1a	1122	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
NYX	0:85b3fd62ea1a	1123	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
NYX	0:85b3fd62ea1a	1124
NYX	0:85b3fd62ea1a	1125	/* ITM Integration Mode Control Register Definitions */
NYX	0:85b3fd62ea1a	1126	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
NYX	0:85b3fd62ea1a	1127	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
NYX	0:85b3fd62ea1a	1128
NYX	0:85b3fd62ea1a	1129	/* ITM Lock Status Register Definitions */
NYX	0:85b3fd62ea1a	1130	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
NYX	0:85b3fd62ea1a	1131	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
NYX	0:85b3fd62ea1a	1132
NYX	0:85b3fd62ea1a	1133	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
NYX	0:85b3fd62ea1a	1134	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
NYX	0:85b3fd62ea1a	1135
NYX	0:85b3fd62ea1a	1136	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
NYX	0:85b3fd62ea1a	1137	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
NYX	0:85b3fd62ea1a	1138
NYX	0:85b3fd62ea1a	1139	/@}/ /* end of group CMSIS_ITM */
NYX	0:85b3fd62ea1a	1140
NYX	0:85b3fd62ea1a	1141
NYX	0:85b3fd62ea1a	1142	/**
NYX	0:85b3fd62ea1a	1143	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1144	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
NYX	0:85b3fd62ea1a	1145	\brief Type definitions for the Data Watchpoint and Trace (DWT)
NYX	0:85b3fd62ea1a	1146	@{
NYX	0:85b3fd62ea1a	1147	*/
NYX	0:85b3fd62ea1a	1148
NYX	0:85b3fd62ea1a	1149	/**
NYX	0:85b3fd62ea1a	1150	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
NYX	0:85b3fd62ea1a	1151	*/
NYX	0:85b3fd62ea1a	1152	typedef struct
NYX	0:85b3fd62ea1a	1153	{
NYX	0:85b3fd62ea1a	1154	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
NYX	0:85b3fd62ea1a	1155	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
NYX	0:85b3fd62ea1a	1156	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
NYX	0:85b3fd62ea1a	1157	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
NYX	0:85b3fd62ea1a	1158	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
NYX	0:85b3fd62ea1a	1159	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
NYX	0:85b3fd62ea1a	1160	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
NYX	0:85b3fd62ea1a	1161	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
NYX	0:85b3fd62ea1a	1162	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
NYX	0:85b3fd62ea1a	1163	uint32_t RESERVED1[1U];
NYX	0:85b3fd62ea1a	1164	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
NYX	0:85b3fd62ea1a	1165	uint32_t RESERVED2[1U];
NYX	0:85b3fd62ea1a	1166	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
NYX	0:85b3fd62ea1a	1167	uint32_t RESERVED3[1U];
NYX	0:85b3fd62ea1a	1168	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
NYX	0:85b3fd62ea1a	1169	uint32_t RESERVED4[1U];
NYX	0:85b3fd62ea1a	1170	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
NYX	0:85b3fd62ea1a	1171	uint32_t RESERVED5[1U];
NYX	0:85b3fd62ea1a	1172	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
NYX	0:85b3fd62ea1a	1173	uint32_t RESERVED6[1U];
NYX	0:85b3fd62ea1a	1174	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
NYX	0:85b3fd62ea1a	1175	uint32_t RESERVED7[1U];
NYX	0:85b3fd62ea1a	1176	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
NYX	0:85b3fd62ea1a	1177	uint32_t RESERVED8[1U];
NYX	0:85b3fd62ea1a	1178	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
NYX	0:85b3fd62ea1a	1179	uint32_t RESERVED9[1U];
NYX	0:85b3fd62ea1a	1180	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
NYX	0:85b3fd62ea1a	1181	uint32_t RESERVED10[1U];
NYX	0:85b3fd62ea1a	1182	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
NYX	0:85b3fd62ea1a	1183	uint32_t RESERVED11[1U];
NYX	0:85b3fd62ea1a	1184	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
NYX	0:85b3fd62ea1a	1185	uint32_t RESERVED12[1U];
NYX	0:85b3fd62ea1a	1186	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
NYX	0:85b3fd62ea1a	1187	uint32_t RESERVED13[1U];
NYX	0:85b3fd62ea1a	1188	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
NYX	0:85b3fd62ea1a	1189	uint32_t RESERVED14[1U];
NYX	0:85b3fd62ea1a	1190	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
NYX	0:85b3fd62ea1a	1191	uint32_t RESERVED15[1U];
NYX	0:85b3fd62ea1a	1192	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
NYX	0:85b3fd62ea1a	1193	uint32_t RESERVED16[1U];
NYX	0:85b3fd62ea1a	1194	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
NYX	0:85b3fd62ea1a	1195	uint32_t RESERVED17[1U];
NYX	0:85b3fd62ea1a	1196	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
NYX	0:85b3fd62ea1a	1197	uint32_t RESERVED18[1U];
NYX	0:85b3fd62ea1a	1198	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
NYX	0:85b3fd62ea1a	1199	uint32_t RESERVED19[1U];
NYX	0:85b3fd62ea1a	1200	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
NYX	0:85b3fd62ea1a	1201	uint32_t RESERVED20[1U];
NYX	0:85b3fd62ea1a	1202	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
NYX	0:85b3fd62ea1a	1203	uint32_t RESERVED21[1U];
NYX	0:85b3fd62ea1a	1204	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
NYX	0:85b3fd62ea1a	1205	uint32_t RESERVED22[1U];
NYX	0:85b3fd62ea1a	1206	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
NYX	0:85b3fd62ea1a	1207	uint32_t RESERVED23[1U];
NYX	0:85b3fd62ea1a	1208	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
NYX	0:85b3fd62ea1a	1209	uint32_t RESERVED24[1U];
NYX	0:85b3fd62ea1a	1210	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
NYX	0:85b3fd62ea1a	1211	uint32_t RESERVED25[1U];
NYX	0:85b3fd62ea1a	1212	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
NYX	0:85b3fd62ea1a	1213	uint32_t RESERVED26[1U];
NYX	0:85b3fd62ea1a	1214	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
NYX	0:85b3fd62ea1a	1215	uint32_t RESERVED27[1U];
NYX	0:85b3fd62ea1a	1216	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
NYX	0:85b3fd62ea1a	1217	uint32_t RESERVED28[1U];
NYX	0:85b3fd62ea1a	1218	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
NYX	0:85b3fd62ea1a	1219	uint32_t RESERVED29[1U];
NYX	0:85b3fd62ea1a	1220	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
NYX	0:85b3fd62ea1a	1221	uint32_t RESERVED30[1U];
NYX	0:85b3fd62ea1a	1222	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
NYX	0:85b3fd62ea1a	1223	uint32_t RESERVED31[1U];
NYX	0:85b3fd62ea1a	1224	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
NYX	0:85b3fd62ea1a	1225	uint32_t RESERVED32[934U];
NYX	0:85b3fd62ea1a	1226	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
NYX	0:85b3fd62ea1a	1227	uint32_t RESERVED33[1U];
NYX	0:85b3fd62ea1a	1228	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
NYX	0:85b3fd62ea1a	1229	} DWT_Type;
NYX	0:85b3fd62ea1a	1230
NYX	0:85b3fd62ea1a	1231	/* DWT Control Register Definitions */
NYX	0:85b3fd62ea1a	1232	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
NYX	0:85b3fd62ea1a	1233	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
NYX	0:85b3fd62ea1a	1234
NYX	0:85b3fd62ea1a	1235	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
NYX	0:85b3fd62ea1a	1236	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
NYX	0:85b3fd62ea1a	1237
NYX	0:85b3fd62ea1a	1238	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
NYX	0:85b3fd62ea1a	1239	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
NYX	0:85b3fd62ea1a	1240
NYX	0:85b3fd62ea1a	1241	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
NYX	0:85b3fd62ea1a	1242	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
NYX	0:85b3fd62ea1a	1243
NYX	0:85b3fd62ea1a	1244	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
NYX	0:85b3fd62ea1a	1245	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
NYX	0:85b3fd62ea1a	1246
NYX	0:85b3fd62ea1a	1247	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
NYX	0:85b3fd62ea1a	1248	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
NYX	0:85b3fd62ea1a	1249
NYX	0:85b3fd62ea1a	1250	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
NYX	0:85b3fd62ea1a	1251	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
NYX	0:85b3fd62ea1a	1252
NYX	0:85b3fd62ea1a	1253	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
NYX	0:85b3fd62ea1a	1254	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
NYX	0:85b3fd62ea1a	1255
NYX	0:85b3fd62ea1a	1256	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
NYX	0:85b3fd62ea1a	1257	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
NYX	0:85b3fd62ea1a	1258
NYX	0:85b3fd62ea1a	1259	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
NYX	0:85b3fd62ea1a	1260	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
NYX	0:85b3fd62ea1a	1261
NYX	0:85b3fd62ea1a	1262	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
NYX	0:85b3fd62ea1a	1263	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
NYX	0:85b3fd62ea1a	1264
NYX	0:85b3fd62ea1a	1265	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
NYX	0:85b3fd62ea1a	1266	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
NYX	0:85b3fd62ea1a	1267
NYX	0:85b3fd62ea1a	1268	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
NYX	0:85b3fd62ea1a	1269	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
NYX	0:85b3fd62ea1a	1270
NYX	0:85b3fd62ea1a	1271	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
NYX	0:85b3fd62ea1a	1272	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
NYX	0:85b3fd62ea1a	1273
NYX	0:85b3fd62ea1a	1274	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
NYX	0:85b3fd62ea1a	1275	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
NYX	0:85b3fd62ea1a	1276
NYX	0:85b3fd62ea1a	1277	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
NYX	0:85b3fd62ea1a	1278	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
NYX	0:85b3fd62ea1a	1279
NYX	0:85b3fd62ea1a	1280	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
NYX	0:85b3fd62ea1a	1281	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
NYX	0:85b3fd62ea1a	1282
NYX	0:85b3fd62ea1a	1283	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
NYX	0:85b3fd62ea1a	1284	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
NYX	0:85b3fd62ea1a	1285
NYX	0:85b3fd62ea1a	1286	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
NYX	0:85b3fd62ea1a	1287	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
NYX	0:85b3fd62ea1a	1288
NYX	0:85b3fd62ea1a	1289	/* DWT CPI Count Register Definitions */
NYX	0:85b3fd62ea1a	1290	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
NYX	0:85b3fd62ea1a	1291	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
NYX	0:85b3fd62ea1a	1292
NYX	0:85b3fd62ea1a	1293	/* DWT Exception Overhead Count Register Definitions */
NYX	0:85b3fd62ea1a	1294	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
NYX	0:85b3fd62ea1a	1295	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
NYX	0:85b3fd62ea1a	1296
NYX	0:85b3fd62ea1a	1297	/* DWT Sleep Count Register Definitions */
NYX	0:85b3fd62ea1a	1298	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
NYX	0:85b3fd62ea1a	1299	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
NYX	0:85b3fd62ea1a	1300
NYX	0:85b3fd62ea1a	1301	/* DWT LSU Count Register Definitions */
NYX	0:85b3fd62ea1a	1302	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
NYX	0:85b3fd62ea1a	1303	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
NYX	0:85b3fd62ea1a	1304
NYX	0:85b3fd62ea1a	1305	/* DWT Folded-instruction Count Register Definitions */
NYX	0:85b3fd62ea1a	1306	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
NYX	0:85b3fd62ea1a	1307	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
NYX	0:85b3fd62ea1a	1308
NYX	0:85b3fd62ea1a	1309	/* DWT Comparator Function Register Definitions */
NYX	0:85b3fd62ea1a	1310	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
NYX	0:85b3fd62ea1a	1311	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
NYX	0:85b3fd62ea1a	1312
NYX	0:85b3fd62ea1a	1313	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
NYX	0:85b3fd62ea1a	1314	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
NYX	0:85b3fd62ea1a	1315
NYX	0:85b3fd62ea1a	1316	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
NYX	0:85b3fd62ea1a	1317	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
NYX	0:85b3fd62ea1a	1318
NYX	0:85b3fd62ea1a	1319	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
NYX	0:85b3fd62ea1a	1320	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
NYX	0:85b3fd62ea1a	1321
NYX	0:85b3fd62ea1a	1322	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
NYX	0:85b3fd62ea1a	1323	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
NYX	0:85b3fd62ea1a	1324
NYX	0:85b3fd62ea1a	1325	/@}/ /* end of group CMSIS_DWT */
NYX	0:85b3fd62ea1a	1326
NYX	0:85b3fd62ea1a	1327
NYX	0:85b3fd62ea1a	1328	/**
NYX	0:85b3fd62ea1a	1329	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1330	\defgroup CMSIS_TPI Trace Port Interface (TPI)
NYX	0:85b3fd62ea1a	1331	\brief Type definitions for the Trace Port Interface (TPI)
NYX	0:85b3fd62ea1a	1332	@{
NYX	0:85b3fd62ea1a	1333	*/
NYX	0:85b3fd62ea1a	1334
NYX	0:85b3fd62ea1a	1335	/**
NYX	0:85b3fd62ea1a	1336	\brief Structure type to access the Trace Port Interface Register (TPI).
NYX	0:85b3fd62ea1a	1337	*/
NYX	0:85b3fd62ea1a	1338	typedef struct
NYX	0:85b3fd62ea1a	1339	{
NYX	0:85b3fd62ea1a	1340	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
NYX	0:85b3fd62ea1a	1341	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
NYX	0:85b3fd62ea1a	1342	uint32_t RESERVED0[2U];
NYX	0:85b3fd62ea1a	1343	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
NYX	0:85b3fd62ea1a	1344	uint32_t RESERVED1[55U];
NYX	0:85b3fd62ea1a	1345	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
NYX	0:85b3fd62ea1a	1346	uint32_t RESERVED2[131U];
NYX	0:85b3fd62ea1a	1347	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
NYX	0:85b3fd62ea1a	1348	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
NYX	0:85b3fd62ea1a	1349	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
NYX	0:85b3fd62ea1a	1350	uint32_t RESERVED3[759U];
NYX	0:85b3fd62ea1a	1351	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
NYX	0:85b3fd62ea1a	1352	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
NYX	0:85b3fd62ea1a	1353	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
NYX	0:85b3fd62ea1a	1354	uint32_t RESERVED4[1U];
NYX	0:85b3fd62ea1a	1355	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
NYX	0:85b3fd62ea1a	1356	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
NYX	0:85b3fd62ea1a	1357	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
NYX	0:85b3fd62ea1a	1358	uint32_t RESERVED5[39U];
NYX	0:85b3fd62ea1a	1359	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
NYX	0:85b3fd62ea1a	1360	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
NYX	0:85b3fd62ea1a	1361	uint32_t RESERVED7[8U];
NYX	0:85b3fd62ea1a	1362	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
NYX	0:85b3fd62ea1a	1363	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
NYX	0:85b3fd62ea1a	1364	} TPI_Type;
NYX	0:85b3fd62ea1a	1365
NYX	0:85b3fd62ea1a	1366	/* TPI Asynchronous Clock Prescaler Register Definitions */
NYX	0:85b3fd62ea1a	1367	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
NYX	0:85b3fd62ea1a	1368	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
NYX	0:85b3fd62ea1a	1369
NYX	0:85b3fd62ea1a	1370	/* TPI Selected Pin Protocol Register Definitions */
NYX	0:85b3fd62ea1a	1371	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
NYX	0:85b3fd62ea1a	1372	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
NYX	0:85b3fd62ea1a	1373
NYX	0:85b3fd62ea1a	1374	/* TPI Formatter and Flush Status Register Definitions */
NYX	0:85b3fd62ea1a	1375	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
NYX	0:85b3fd62ea1a	1376	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
NYX	0:85b3fd62ea1a	1377
NYX	0:85b3fd62ea1a	1378	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
NYX	0:85b3fd62ea1a	1379	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
NYX	0:85b3fd62ea1a	1380
NYX	0:85b3fd62ea1a	1381	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
NYX	0:85b3fd62ea1a	1382	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
NYX	0:85b3fd62ea1a	1383
NYX	0:85b3fd62ea1a	1384	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
NYX	0:85b3fd62ea1a	1385	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
NYX	0:85b3fd62ea1a	1386
NYX	0:85b3fd62ea1a	1387	/* TPI Formatter and Flush Control Register Definitions */
NYX	0:85b3fd62ea1a	1388	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
NYX	0:85b3fd62ea1a	1389	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
NYX	0:85b3fd62ea1a	1390
NYX	0:85b3fd62ea1a	1391	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
NYX	0:85b3fd62ea1a	1392	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
NYX	0:85b3fd62ea1a	1393
NYX	0:85b3fd62ea1a	1394	/* TPI TRIGGER Register Definitions */
NYX	0:85b3fd62ea1a	1395	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
NYX	0:85b3fd62ea1a	1396	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
NYX	0:85b3fd62ea1a	1397
NYX	0:85b3fd62ea1a	1398	/* TPI Integration ETM Data Register Definitions (FIFO0) */
NYX	0:85b3fd62ea1a	1399	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
NYX	0:85b3fd62ea1a	1400	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1401
NYX	0:85b3fd62ea1a	1402	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
NYX	0:85b3fd62ea1a	1403	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
NYX	0:85b3fd62ea1a	1404
NYX	0:85b3fd62ea1a	1405	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
NYX	0:85b3fd62ea1a	1406	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1407
NYX	0:85b3fd62ea1a	1408	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
NYX	0:85b3fd62ea1a	1409	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
NYX	0:85b3fd62ea1a	1410
NYX	0:85b3fd62ea1a	1411	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
NYX	0:85b3fd62ea1a	1412	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
NYX	0:85b3fd62ea1a	1413
NYX	0:85b3fd62ea1a	1414	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
NYX	0:85b3fd62ea1a	1415	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
NYX	0:85b3fd62ea1a	1416
NYX	0:85b3fd62ea1a	1417	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
NYX	0:85b3fd62ea1a	1418	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
NYX	0:85b3fd62ea1a	1419
NYX	0:85b3fd62ea1a	1420	/* TPI ITATBCTR2 Register Definitions */
NYX	0:85b3fd62ea1a	1421	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
NYX	0:85b3fd62ea1a	1422	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
NYX	0:85b3fd62ea1a	1423
NYX	0:85b3fd62ea1a	1424	/* TPI Integration ITM Data Register Definitions (FIFO1) */
NYX	0:85b3fd62ea1a	1425	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
NYX	0:85b3fd62ea1a	1426	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1427
NYX	0:85b3fd62ea1a	1428	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
NYX	0:85b3fd62ea1a	1429	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
NYX	0:85b3fd62ea1a	1430
NYX	0:85b3fd62ea1a	1431	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
NYX	0:85b3fd62ea1a	1432	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1433
NYX	0:85b3fd62ea1a	1434	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
NYX	0:85b3fd62ea1a	1435	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
NYX	0:85b3fd62ea1a	1436
NYX	0:85b3fd62ea1a	1437	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
NYX	0:85b3fd62ea1a	1438	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
NYX	0:85b3fd62ea1a	1439
NYX	0:85b3fd62ea1a	1440	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
NYX	0:85b3fd62ea1a	1441	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
NYX	0:85b3fd62ea1a	1442
NYX	0:85b3fd62ea1a	1443	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
NYX	0:85b3fd62ea1a	1444	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
NYX	0:85b3fd62ea1a	1445
NYX	0:85b3fd62ea1a	1446	/* TPI ITATBCTR0 Register Definitions */
NYX	0:85b3fd62ea1a	1447	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
NYX	0:85b3fd62ea1a	1448	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
NYX	0:85b3fd62ea1a	1449
NYX	0:85b3fd62ea1a	1450	/* TPI Integration Mode Control Register Definitions */
NYX	0:85b3fd62ea1a	1451	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
NYX	0:85b3fd62ea1a	1452	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
NYX	0:85b3fd62ea1a	1453
NYX	0:85b3fd62ea1a	1454	/* TPI DEVID Register Definitions */
NYX	0:85b3fd62ea1a	1455	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
NYX	0:85b3fd62ea1a	1456	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
NYX	0:85b3fd62ea1a	1457
NYX	0:85b3fd62ea1a	1458	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
NYX	0:85b3fd62ea1a	1459	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
NYX	0:85b3fd62ea1a	1460
NYX	0:85b3fd62ea1a	1461	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
NYX	0:85b3fd62ea1a	1462	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
NYX	0:85b3fd62ea1a	1463
NYX	0:85b3fd62ea1a	1464	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
NYX	0:85b3fd62ea1a	1465	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
NYX	0:85b3fd62ea1a	1466
NYX	0:85b3fd62ea1a	1467	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
NYX	0:85b3fd62ea1a	1468	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
NYX	0:85b3fd62ea1a	1469
NYX	0:85b3fd62ea1a	1470	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
NYX	0:85b3fd62ea1a	1471	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
NYX	0:85b3fd62ea1a	1472
NYX	0:85b3fd62ea1a	1473	/* TPI DEVTYPE Register Definitions */
NYX	0:85b3fd62ea1a	1474	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
NYX	0:85b3fd62ea1a	1475	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
NYX	0:85b3fd62ea1a	1476
NYX	0:85b3fd62ea1a	1477	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
NYX	0:85b3fd62ea1a	1478	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
NYX	0:85b3fd62ea1a	1479
NYX	0:85b3fd62ea1a	1480	/@}/ /* end of group CMSIS_TPI */
NYX	0:85b3fd62ea1a	1481
NYX	0:85b3fd62ea1a	1482
NYX	0:85b3fd62ea1a	1483	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1484	/**
NYX	0:85b3fd62ea1a	1485	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1486	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
NYX	0:85b3fd62ea1a	1487	\brief Type definitions for the Memory Protection Unit (MPU)
NYX	0:85b3fd62ea1a	1488	@{
NYX	0:85b3fd62ea1a	1489	*/
NYX	0:85b3fd62ea1a	1490
NYX	0:85b3fd62ea1a	1491	/**
NYX	0:85b3fd62ea1a	1492	\brief Structure type to access the Memory Protection Unit (MPU).
NYX	0:85b3fd62ea1a	1493	*/
NYX	0:85b3fd62ea1a	1494	typedef struct
NYX	0:85b3fd62ea1a	1495	{
NYX	0:85b3fd62ea1a	1496	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
NYX	0:85b3fd62ea1a	1497	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
NYX	0:85b3fd62ea1a	1498	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
NYX	0:85b3fd62ea1a	1499	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
NYX	0:85b3fd62ea1a	1500	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
NYX	0:85b3fd62ea1a	1501	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
NYX	0:85b3fd62ea1a	1502	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
NYX	0:85b3fd62ea1a	1503	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
NYX	0:85b3fd62ea1a	1504	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
NYX	0:85b3fd62ea1a	1505	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
NYX	0:85b3fd62ea1a	1506	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
NYX	0:85b3fd62ea1a	1507	uint32_t RESERVED0[1];
NYX	0:85b3fd62ea1a	1508	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
NYX	0:85b3fd62ea1a	1509	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
NYX	0:85b3fd62ea1a	1510	} MPU_Type;
NYX	0:85b3fd62ea1a	1511
NYX	0:85b3fd62ea1a	1512	/* MPU Type Register Definitions */
NYX	0:85b3fd62ea1a	1513	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
NYX	0:85b3fd62ea1a	1514	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
NYX	0:85b3fd62ea1a	1515
NYX	0:85b3fd62ea1a	1516	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
NYX	0:85b3fd62ea1a	1517	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
NYX	0:85b3fd62ea1a	1518
NYX	0:85b3fd62ea1a	1519	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
NYX	0:85b3fd62ea1a	1520	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
NYX	0:85b3fd62ea1a	1521
NYX	0:85b3fd62ea1a	1522	/* MPU Control Register Definitions */
NYX	0:85b3fd62ea1a	1523	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
NYX	0:85b3fd62ea1a	1524	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
NYX	0:85b3fd62ea1a	1525
NYX	0:85b3fd62ea1a	1526	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
NYX	0:85b3fd62ea1a	1527	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
NYX	0:85b3fd62ea1a	1528
NYX	0:85b3fd62ea1a	1529	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
NYX	0:85b3fd62ea1a	1530	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
NYX	0:85b3fd62ea1a	1531
NYX	0:85b3fd62ea1a	1532	/* MPU Region Number Register Definitions */
NYX	0:85b3fd62ea1a	1533	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
NYX	0:85b3fd62ea1a	1534	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
NYX	0:85b3fd62ea1a	1535
NYX	0:85b3fd62ea1a	1536	/* MPU Region Base Address Register Definitions */
NYX	0:85b3fd62ea1a	1537	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
NYX	0:85b3fd62ea1a	1538	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
NYX	0:85b3fd62ea1a	1539
NYX	0:85b3fd62ea1a	1540	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
NYX	0:85b3fd62ea1a	1541	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
NYX	0:85b3fd62ea1a	1542
NYX	0:85b3fd62ea1a	1543	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
NYX	0:85b3fd62ea1a	1544	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
NYX	0:85b3fd62ea1a	1545
NYX	0:85b3fd62ea1a	1546	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
NYX	0:85b3fd62ea1a	1547	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
NYX	0:85b3fd62ea1a	1548
NYX	0:85b3fd62ea1a	1549	/* MPU Region Limit Address Register Definitions */
NYX	0:85b3fd62ea1a	1550	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
NYX	0:85b3fd62ea1a	1551	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
NYX	0:85b3fd62ea1a	1552
NYX	0:85b3fd62ea1a	1553	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
NYX	0:85b3fd62ea1a	1554	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
NYX	0:85b3fd62ea1a	1555
NYX	0:85b3fd62ea1a	1556	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
NYX	0:85b3fd62ea1a	1557	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
NYX	0:85b3fd62ea1a	1558
NYX	0:85b3fd62ea1a	1559	/* MPU Memory Attribute Indirection Register 0 Definitions */
NYX	0:85b3fd62ea1a	1560	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
NYX	0:85b3fd62ea1a	1561	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
NYX	0:85b3fd62ea1a	1562
NYX	0:85b3fd62ea1a	1563	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
NYX	0:85b3fd62ea1a	1564	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
NYX	0:85b3fd62ea1a	1565
NYX	0:85b3fd62ea1a	1566	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
NYX	0:85b3fd62ea1a	1567	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
NYX	0:85b3fd62ea1a	1568
NYX	0:85b3fd62ea1a	1569	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
NYX	0:85b3fd62ea1a	1570	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
NYX	0:85b3fd62ea1a	1571
NYX	0:85b3fd62ea1a	1572	/* MPU Memory Attribute Indirection Register 1 Definitions */
NYX	0:85b3fd62ea1a	1573	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
NYX	0:85b3fd62ea1a	1574	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
NYX	0:85b3fd62ea1a	1575
NYX	0:85b3fd62ea1a	1576	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
NYX	0:85b3fd62ea1a	1577	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
NYX	0:85b3fd62ea1a	1578
NYX	0:85b3fd62ea1a	1579	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
NYX	0:85b3fd62ea1a	1580	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
NYX	0:85b3fd62ea1a	1581
NYX	0:85b3fd62ea1a	1582	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
NYX	0:85b3fd62ea1a	1583	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
NYX	0:85b3fd62ea1a	1584
NYX	0:85b3fd62ea1a	1585	/@} end of group CMSIS_MPU /
NYX	0:85b3fd62ea1a	1586	#endif
NYX	0:85b3fd62ea1a	1587
NYX	0:85b3fd62ea1a	1588
NYX	0:85b3fd62ea1a	1589	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX	0:85b3fd62ea1a	1590	/**
NYX	0:85b3fd62ea1a	1591	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1592	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
NYX	0:85b3fd62ea1a	1593	\brief Type definitions for the Security Attribution Unit (SAU)
NYX	0:85b3fd62ea1a	1594	@{
NYX	0:85b3fd62ea1a	1595	*/
NYX	0:85b3fd62ea1a	1596
NYX	0:85b3fd62ea1a	1597	/**
NYX	0:85b3fd62ea1a	1598	\brief Structure type to access the Security Attribution Unit (SAU).
NYX	0:85b3fd62ea1a	1599	*/
NYX	0:85b3fd62ea1a	1600	typedef struct
NYX	0:85b3fd62ea1a	1601	{
NYX	0:85b3fd62ea1a	1602	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
NYX	0:85b3fd62ea1a	1603	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
NYX	0:85b3fd62ea1a	1604	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1605	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
NYX	0:85b3fd62ea1a	1606	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
NYX	0:85b3fd62ea1a	1607	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
NYX	0:85b3fd62ea1a	1608	#else
NYX	0:85b3fd62ea1a	1609	uint32_t RESERVED0[3];
NYX	0:85b3fd62ea1a	1610	#endif
NYX	0:85b3fd62ea1a	1611	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
NYX	0:85b3fd62ea1a	1612	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
NYX	0:85b3fd62ea1a	1613	} SAU_Type;
NYX	0:85b3fd62ea1a	1614
NYX	0:85b3fd62ea1a	1615	/* SAU Control Register Definitions */
NYX	0:85b3fd62ea1a	1616	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
NYX	0:85b3fd62ea1a	1617	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
NYX	0:85b3fd62ea1a	1618
NYX	0:85b3fd62ea1a	1619	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
NYX	0:85b3fd62ea1a	1620	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
NYX	0:85b3fd62ea1a	1621
NYX	0:85b3fd62ea1a	1622	/* SAU Type Register Definitions */
NYX	0:85b3fd62ea1a	1623	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
NYX	0:85b3fd62ea1a	1624	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
NYX	0:85b3fd62ea1a	1625
NYX	0:85b3fd62ea1a	1626	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1627	/* SAU Region Number Register Definitions */
NYX	0:85b3fd62ea1a	1628	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
NYX	0:85b3fd62ea1a	1629	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
NYX	0:85b3fd62ea1a	1630
NYX	0:85b3fd62ea1a	1631	/* SAU Region Base Address Register Definitions */
NYX	0:85b3fd62ea1a	1632	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
NYX	0:85b3fd62ea1a	1633	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
NYX	0:85b3fd62ea1a	1634
NYX	0:85b3fd62ea1a	1635	/* SAU Region Limit Address Register Definitions */
NYX	0:85b3fd62ea1a	1636	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
NYX	0:85b3fd62ea1a	1637	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
NYX	0:85b3fd62ea1a	1638
NYX	0:85b3fd62ea1a	1639	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
NYX	0:85b3fd62ea1a	1640	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
NYX	0:85b3fd62ea1a	1641
NYX	0:85b3fd62ea1a	1642	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
NYX	0:85b3fd62ea1a	1643	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
NYX	0:85b3fd62ea1a	1644
NYX	0:85b3fd62ea1a	1645	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
NYX	0:85b3fd62ea1a	1646
NYX	0:85b3fd62ea1a	1647	/* Secure Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	1648	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
NYX	0:85b3fd62ea1a	1649	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
NYX	0:85b3fd62ea1a	1650
NYX	0:85b3fd62ea1a	1651	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
NYX	0:85b3fd62ea1a	1652	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
NYX	0:85b3fd62ea1a	1653
NYX	0:85b3fd62ea1a	1654	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
NYX	0:85b3fd62ea1a	1655	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
NYX	0:85b3fd62ea1a	1656
NYX	0:85b3fd62ea1a	1657	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
NYX	0:85b3fd62ea1a	1658	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
NYX	0:85b3fd62ea1a	1659
NYX	0:85b3fd62ea1a	1660	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
NYX	0:85b3fd62ea1a	1661	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
NYX	0:85b3fd62ea1a	1662
NYX	0:85b3fd62ea1a	1663	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
NYX	0:85b3fd62ea1a	1664	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
NYX	0:85b3fd62ea1a	1665
NYX	0:85b3fd62ea1a	1666	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
NYX	0:85b3fd62ea1a	1667	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
NYX	0:85b3fd62ea1a	1668
NYX	0:85b3fd62ea1a	1669	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
NYX	0:85b3fd62ea1a	1670	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
NYX	0:85b3fd62ea1a	1671
NYX	0:85b3fd62ea1a	1672	/@} end of group CMSIS_SAU /
NYX	0:85b3fd62ea1a	1673	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX	0:85b3fd62ea1a	1674
NYX	0:85b3fd62ea1a	1675
NYX	0:85b3fd62ea1a	1676	/**
NYX	0:85b3fd62ea1a	1677	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1678	\defgroup CMSIS_FPU Floating Point Unit (FPU)
NYX	0:85b3fd62ea1a	1679	\brief Type definitions for the Floating Point Unit (FPU)
NYX	0:85b3fd62ea1a	1680	@{
NYX	0:85b3fd62ea1a	1681	*/
NYX	0:85b3fd62ea1a	1682
NYX	0:85b3fd62ea1a	1683	/**
NYX	0:85b3fd62ea1a	1684	\brief Structure type to access the Floating Point Unit (FPU).
NYX	0:85b3fd62ea1a	1685	*/
NYX	0:85b3fd62ea1a	1686	typedef struct
NYX	0:85b3fd62ea1a	1687	{
NYX	0:85b3fd62ea1a	1688	uint32_t RESERVED0[1U];
NYX	0:85b3fd62ea1a	1689	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
NYX	0:85b3fd62ea1a	1690	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
NYX	0:85b3fd62ea1a	1691	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
NYX	0:85b3fd62ea1a	1692	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
NYX	0:85b3fd62ea1a	1693	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
NYX	0:85b3fd62ea1a	1694	} FPU_Type;
NYX	0:85b3fd62ea1a	1695
NYX	0:85b3fd62ea1a	1696	/* Floating-Point Context Control Register Definitions */
NYX	0:85b3fd62ea1a	1697	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
NYX	0:85b3fd62ea1a	1698	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
NYX	0:85b3fd62ea1a	1699
NYX	0:85b3fd62ea1a	1700	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
NYX	0:85b3fd62ea1a	1701	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
NYX	0:85b3fd62ea1a	1702
NYX	0:85b3fd62ea1a	1703	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
NYX	0:85b3fd62ea1a	1704	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
NYX	0:85b3fd62ea1a	1705
NYX	0:85b3fd62ea1a	1706	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
NYX	0:85b3fd62ea1a	1707	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
NYX	0:85b3fd62ea1a	1708
NYX	0:85b3fd62ea1a	1709	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
NYX	0:85b3fd62ea1a	1710	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
NYX	0:85b3fd62ea1a	1711
NYX	0:85b3fd62ea1a	1712	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
NYX	0:85b3fd62ea1a	1713	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
NYX	0:85b3fd62ea1a	1714
NYX	0:85b3fd62ea1a	1715	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
NYX	0:85b3fd62ea1a	1716	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
NYX	0:85b3fd62ea1a	1717
NYX	0:85b3fd62ea1a	1718	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
NYX	0:85b3fd62ea1a	1719	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
NYX	0:85b3fd62ea1a	1720
NYX	0:85b3fd62ea1a	1721	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
NYX	0:85b3fd62ea1a	1722	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
NYX	0:85b3fd62ea1a	1723
NYX	0:85b3fd62ea1a	1724	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
NYX	0:85b3fd62ea1a	1725	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
NYX	0:85b3fd62ea1a	1726
NYX	0:85b3fd62ea1a	1727	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
NYX	0:85b3fd62ea1a	1728	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
NYX	0:85b3fd62ea1a	1729
NYX	0:85b3fd62ea1a	1730	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
NYX	0:85b3fd62ea1a	1731	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
NYX	0:85b3fd62ea1a	1732
NYX	0:85b3fd62ea1a	1733	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
NYX	0:85b3fd62ea1a	1734	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
NYX	0:85b3fd62ea1a	1735
NYX	0:85b3fd62ea1a	1736	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
NYX	0:85b3fd62ea1a	1737	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
NYX	0:85b3fd62ea1a	1738
NYX	0:85b3fd62ea1a	1739	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
NYX	0:85b3fd62ea1a	1740	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
NYX	0:85b3fd62ea1a	1741
NYX	0:85b3fd62ea1a	1742	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
NYX	0:85b3fd62ea1a	1743	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
NYX	0:85b3fd62ea1a	1744
NYX	0:85b3fd62ea1a	1745	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
NYX	0:85b3fd62ea1a	1746	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
NYX	0:85b3fd62ea1a	1747
NYX	0:85b3fd62ea1a	1748	/* Floating-Point Context Address Register Definitions */
NYX	0:85b3fd62ea1a	1749	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
NYX	0:85b3fd62ea1a	1750	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
NYX	0:85b3fd62ea1a	1751
NYX	0:85b3fd62ea1a	1752	/* Floating-Point Default Status Control Register Definitions */
NYX	0:85b3fd62ea1a	1753	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
NYX	0:85b3fd62ea1a	1754	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
NYX	0:85b3fd62ea1a	1755
NYX	0:85b3fd62ea1a	1756	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
NYX	0:85b3fd62ea1a	1757	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
NYX	0:85b3fd62ea1a	1758
NYX	0:85b3fd62ea1a	1759	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
NYX	0:85b3fd62ea1a	1760	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
NYX	0:85b3fd62ea1a	1761
NYX	0:85b3fd62ea1a	1762	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
NYX	0:85b3fd62ea1a	1763	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
NYX	0:85b3fd62ea1a	1764
NYX	0:85b3fd62ea1a	1765	/* Media and FP Feature Register 0 Definitions */
NYX	0:85b3fd62ea1a	1766	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
NYX	0:85b3fd62ea1a	1767	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
NYX	0:85b3fd62ea1a	1768
NYX	0:85b3fd62ea1a	1769	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
NYX	0:85b3fd62ea1a	1770	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
NYX	0:85b3fd62ea1a	1771
NYX	0:85b3fd62ea1a	1772	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
NYX	0:85b3fd62ea1a	1773	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
NYX	0:85b3fd62ea1a	1774
NYX	0:85b3fd62ea1a	1775	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
NYX	0:85b3fd62ea1a	1776	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
NYX	0:85b3fd62ea1a	1777
NYX	0:85b3fd62ea1a	1778	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
NYX	0:85b3fd62ea1a	1779	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
NYX	0:85b3fd62ea1a	1780
NYX	0:85b3fd62ea1a	1781	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
NYX	0:85b3fd62ea1a	1782	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
NYX	0:85b3fd62ea1a	1783
NYX	0:85b3fd62ea1a	1784	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
NYX	0:85b3fd62ea1a	1785	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
NYX	0:85b3fd62ea1a	1786
NYX	0:85b3fd62ea1a	1787	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
NYX	0:85b3fd62ea1a	1788	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
NYX	0:85b3fd62ea1a	1789
NYX	0:85b3fd62ea1a	1790	/* Media and FP Feature Register 1 Definitions */
NYX	0:85b3fd62ea1a	1791	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
NYX	0:85b3fd62ea1a	1792	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
NYX	0:85b3fd62ea1a	1793
NYX	0:85b3fd62ea1a	1794	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
NYX	0:85b3fd62ea1a	1795	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
NYX	0:85b3fd62ea1a	1796
NYX	0:85b3fd62ea1a	1797	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
NYX	0:85b3fd62ea1a	1798	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
NYX	0:85b3fd62ea1a	1799
NYX	0:85b3fd62ea1a	1800	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
NYX	0:85b3fd62ea1a	1801	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
NYX	0:85b3fd62ea1a	1802
NYX	0:85b3fd62ea1a	1803	/@} end of group CMSIS_FPU /
NYX	0:85b3fd62ea1a	1804
NYX	0:85b3fd62ea1a	1805
NYX	0:85b3fd62ea1a	1806	/**
NYX	0:85b3fd62ea1a	1807	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1808	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
NYX	0:85b3fd62ea1a	1809	\brief Type definitions for the Core Debug Registers
NYX	0:85b3fd62ea1a	1810	@{
NYX	0:85b3fd62ea1a	1811	*/
NYX	0:85b3fd62ea1a	1812
NYX	0:85b3fd62ea1a	1813	/**
NYX	0:85b3fd62ea1a	1814	\brief Structure type to access the Core Debug Register (CoreDebug).
NYX	0:85b3fd62ea1a	1815	*/
NYX	0:85b3fd62ea1a	1816	typedef struct
NYX	0:85b3fd62ea1a	1817	{
NYX	0:85b3fd62ea1a	1818	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
NYX	0:85b3fd62ea1a	1819	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
NYX	0:85b3fd62ea1a	1820	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
NYX	0:85b3fd62ea1a	1821	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
NYX	0:85b3fd62ea1a	1822	uint32_t RESERVED4[1U];
NYX	0:85b3fd62ea1a	1823	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
NYX	0:85b3fd62ea1a	1824	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
NYX	0:85b3fd62ea1a	1825	} CoreDebug_Type;
NYX	0:85b3fd62ea1a	1826
NYX	0:85b3fd62ea1a	1827	/* Debug Halting Control and Status Register Definitions */
NYX	0:85b3fd62ea1a	1828	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
NYX	0:85b3fd62ea1a	1829	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
NYX	0:85b3fd62ea1a	1830
NYX	0:85b3fd62ea1a	1831	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
NYX	0:85b3fd62ea1a	1832	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
NYX	0:85b3fd62ea1a	1833
NYX	0:85b3fd62ea1a	1834	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
NYX	0:85b3fd62ea1a	1835	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
NYX	0:85b3fd62ea1a	1836
NYX	0:85b3fd62ea1a	1837	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
NYX	0:85b3fd62ea1a	1838	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
NYX	0:85b3fd62ea1a	1839
NYX	0:85b3fd62ea1a	1840	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
NYX	0:85b3fd62ea1a	1841	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
NYX	0:85b3fd62ea1a	1842
NYX	0:85b3fd62ea1a	1843	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
NYX	0:85b3fd62ea1a	1844	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
NYX	0:85b3fd62ea1a	1845
NYX	0:85b3fd62ea1a	1846	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
NYX	0:85b3fd62ea1a	1847	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
NYX	0:85b3fd62ea1a	1848
NYX	0:85b3fd62ea1a	1849	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
NYX	0:85b3fd62ea1a	1850	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
NYX	0:85b3fd62ea1a	1851
NYX	0:85b3fd62ea1a	1852	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
NYX	0:85b3fd62ea1a	1853	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
NYX	0:85b3fd62ea1a	1854
NYX	0:85b3fd62ea1a	1855	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
NYX	0:85b3fd62ea1a	1856	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
NYX	0:85b3fd62ea1a	1857
NYX	0:85b3fd62ea1a	1858	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
NYX	0:85b3fd62ea1a	1859	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
NYX	0:85b3fd62ea1a	1860
NYX	0:85b3fd62ea1a	1861	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
NYX	0:85b3fd62ea1a	1862	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
NYX	0:85b3fd62ea1a	1863
NYX	0:85b3fd62ea1a	1864	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
NYX	0:85b3fd62ea1a	1865	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
NYX	0:85b3fd62ea1a	1866
NYX	0:85b3fd62ea1a	1867	/* Debug Core Register Selector Register Definitions */
NYX	0:85b3fd62ea1a	1868	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
NYX	0:85b3fd62ea1a	1869	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
NYX	0:85b3fd62ea1a	1870
NYX	0:85b3fd62ea1a	1871	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
NYX	0:85b3fd62ea1a	1872	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
NYX	0:85b3fd62ea1a	1873
NYX	0:85b3fd62ea1a	1874	/* Debug Exception and Monitor Control Register Definitions */
NYX	0:85b3fd62ea1a	1875	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
NYX	0:85b3fd62ea1a	1876	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
NYX	0:85b3fd62ea1a	1877
NYX	0:85b3fd62ea1a	1878	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
NYX	0:85b3fd62ea1a	1879	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
NYX	0:85b3fd62ea1a	1880
NYX	0:85b3fd62ea1a	1881	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
NYX	0:85b3fd62ea1a	1882	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
NYX	0:85b3fd62ea1a	1883
NYX	0:85b3fd62ea1a	1884	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
NYX	0:85b3fd62ea1a	1885	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
NYX	0:85b3fd62ea1a	1886
NYX	0:85b3fd62ea1a	1887	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
NYX	0:85b3fd62ea1a	1888	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
NYX	0:85b3fd62ea1a	1889
NYX	0:85b3fd62ea1a	1890	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
NYX	0:85b3fd62ea1a	1891	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
NYX	0:85b3fd62ea1a	1892
NYX	0:85b3fd62ea1a	1893	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
NYX	0:85b3fd62ea1a	1894	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
NYX	0:85b3fd62ea1a	1895
NYX	0:85b3fd62ea1a	1896	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
NYX	0:85b3fd62ea1a	1897	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
NYX	0:85b3fd62ea1a	1898
NYX	0:85b3fd62ea1a	1899	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
NYX	0:85b3fd62ea1a	1900	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
NYX	0:85b3fd62ea1a	1901
NYX	0:85b3fd62ea1a	1902	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
NYX	0:85b3fd62ea1a	1903	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
NYX	0:85b3fd62ea1a	1904
NYX	0:85b3fd62ea1a	1905	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
NYX	0:85b3fd62ea1a	1906	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
NYX	0:85b3fd62ea1a	1907
NYX	0:85b3fd62ea1a	1908	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
NYX	0:85b3fd62ea1a	1909	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
NYX	0:85b3fd62ea1a	1910
NYX	0:85b3fd62ea1a	1911	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
NYX	0:85b3fd62ea1a	1912	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
NYX	0:85b3fd62ea1a	1913
NYX	0:85b3fd62ea1a	1914	/* Debug Authentication Control Register Definitions */
NYX	0:85b3fd62ea1a	1915	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
NYX	0:85b3fd62ea1a	1916	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
NYX	0:85b3fd62ea1a	1917
NYX	0:85b3fd62ea1a	1918	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
NYX	0:85b3fd62ea1a	1919	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
NYX	0:85b3fd62ea1a	1920
NYX	0:85b3fd62ea1a	1921	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
NYX	0:85b3fd62ea1a	1922	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
NYX	0:85b3fd62ea1a	1923
NYX	0:85b3fd62ea1a	1924	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
NYX	0:85b3fd62ea1a	1925	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
NYX	0:85b3fd62ea1a	1926
NYX	0:85b3fd62ea1a	1927	/* Debug Security Control and Status Register Definitions */
NYX	0:85b3fd62ea1a	1928	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
NYX	0:85b3fd62ea1a	1929	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
NYX	0:85b3fd62ea1a	1930
NYX	0:85b3fd62ea1a	1931	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
NYX	0:85b3fd62ea1a	1932	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
NYX	0:85b3fd62ea1a	1933
NYX	0:85b3fd62ea1a	1934	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
NYX	0:85b3fd62ea1a	1935	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
NYX	0:85b3fd62ea1a	1936
NYX	0:85b3fd62ea1a	1937	/@} end of group CMSIS_CoreDebug /
NYX	0:85b3fd62ea1a	1938
NYX	0:85b3fd62ea1a	1939
NYX	0:85b3fd62ea1a	1940	/**
NYX	0:85b3fd62ea1a	1941	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1942	\defgroup CMSIS_core_bitfield Core register bit field macros
NYX	0:85b3fd62ea1a	1943	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
NYX	0:85b3fd62ea1a	1944	@{
NYX	0:85b3fd62ea1a	1945	*/
NYX	0:85b3fd62ea1a	1946
NYX	0:85b3fd62ea1a	1947	/**
NYX	0:85b3fd62ea1a	1948	\brief Mask and shift a bit field value for use in a register bit range.
NYX	0:85b3fd62ea1a	1949	\param[in] field Name of the register bit field.
NYX	0:85b3fd62ea1a	1950	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
NYX	0:85b3fd62ea1a	1951	\return Masked and shifted value.
NYX	0:85b3fd62ea1a	1952	*/
NYX	0:85b3fd62ea1a	1953	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
NYX	0:85b3fd62ea1a	1954
NYX	0:85b3fd62ea1a	1955	/**
NYX	0:85b3fd62ea1a	1956	\brief Mask and shift a register value to extract a bit filed value.
NYX	0:85b3fd62ea1a	1957	\param[in] field Name of the register bit field.
NYX	0:85b3fd62ea1a	1958	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
NYX	0:85b3fd62ea1a	1959	\return Masked and shifted bit field value.
NYX	0:85b3fd62ea1a	1960	*/
NYX	0:85b3fd62ea1a	1961	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
NYX	0:85b3fd62ea1a	1962
NYX	0:85b3fd62ea1a	1963	/@} end of group CMSIS_core_bitfield /
NYX	0:85b3fd62ea1a	1964
NYX	0:85b3fd62ea1a	1965
NYX	0:85b3fd62ea1a	1966	/**
NYX	0:85b3fd62ea1a	1967	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1968	\defgroup CMSIS_core_base Core Definitions
NYX	0:85b3fd62ea1a	1969	\brief Definitions for base addresses, unions, and structures.
NYX	0:85b3fd62ea1a	1970	@{
NYX	0:85b3fd62ea1a	1971	*/
NYX	0:85b3fd62ea1a	1972
NYX	0:85b3fd62ea1a	1973	/* Memory mapping of Core Hardware */
NYX	0:85b3fd62ea1a	1974	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
NYX	0:85b3fd62ea1a	1975	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
NYX	0:85b3fd62ea1a	1976	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
NYX	0:85b3fd62ea1a	1977	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
NYX	0:85b3fd62ea1a	1978	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
NYX	0:85b3fd62ea1a	1979	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
NYX	0:85b3fd62ea1a	1980	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
NYX	0:85b3fd62ea1a	1981	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
NYX	0:85b3fd62ea1a	1982
NYX	0:85b3fd62ea1a	1983	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
NYX	0:85b3fd62ea1a	1984	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
NYX	0:85b3fd62ea1a	1985	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
NYX	0:85b3fd62ea1a	1986	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
NYX	0:85b3fd62ea1a	1987	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
NYX	0:85b3fd62ea1a	1988	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
NYX	0:85b3fd62ea1a	1989	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
NYX	0:85b3fd62ea1a	1990	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
NYX	0:85b3fd62ea1a	1991
NYX	0:85b3fd62ea1a	1992	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1993	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
NYX	0:85b3fd62ea1a	1994	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
NYX	0:85b3fd62ea1a	1995	#endif
NYX	0:85b3fd62ea1a	1996
NYX	0:85b3fd62ea1a	1997	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX	0:85b3fd62ea1a	1998	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
NYX	0:85b3fd62ea1a	1999	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
NYX	0:85b3fd62ea1a	2000	#endif
NYX	0:85b3fd62ea1a	2001
NYX	0:85b3fd62ea1a	2002	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
NYX	0:85b3fd62ea1a	2003	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
NYX	0:85b3fd62ea1a	2004
NYX	0:85b3fd62ea1a	2005	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX	0:85b3fd62ea1a	2006	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
NYX	0:85b3fd62ea1a	2007	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
NYX	0:85b3fd62ea1a	2008	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
NYX	0:85b3fd62ea1a	2009	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
NYX	0:85b3fd62ea1a	2010	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
NYX	0:85b3fd62ea1a	2011
NYX	0:85b3fd62ea1a	2012	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
NYX	0:85b3fd62ea1a	2013	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
NYX	0:85b3fd62ea1a	2014	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
NYX	0:85b3fd62ea1a	2015	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
NYX	0:85b3fd62ea1a	2016	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
NYX	0:85b3fd62ea1a	2017
NYX	0:85b3fd62ea1a	2018	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	2019	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
NYX	0:85b3fd62ea1a	2020	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
NYX	0:85b3fd62ea1a	2021	#endif
NYX	0:85b3fd62ea1a	2022
NYX	0:85b3fd62ea1a	2023	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
NYX	0:85b3fd62ea1a	2024	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
NYX	0:85b3fd62ea1a	2025
NYX	0:85b3fd62ea1a	2026	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX	0:85b3fd62ea1a	2027	/@} /
NYX	0:85b3fd62ea1a	2028
NYX	0:85b3fd62ea1a	2029
NYX	0:85b3fd62ea1a	2030
NYX	0:85b3fd62ea1a	2031	/*******************************************************************************
NYX	0:85b3fd62ea1a	2032	* Hardware Abstraction Layer
NYX	0:85b3fd62ea1a	2033	Core Function Interface contains:
NYX	0:85b3fd62ea1a	2034	- Core NVIC Functions
NYX	0:85b3fd62ea1a	2035	- Core SysTick Functions
NYX	0:85b3fd62ea1a	2036	- Core Debug Functions
NYX	0:85b3fd62ea1a	2037	- Core Register Access Functions
NYX	0:85b3fd62ea1a	2038	******************************************************************************/
NYX	0:85b3fd62ea1a	2039	/**
NYX	0:85b3fd62ea1a	2040	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
NYX	0:85b3fd62ea1a	2041	*/
NYX	0:85b3fd62ea1a	2042
NYX	0:85b3fd62ea1a	2043
NYX	0:85b3fd62ea1a	2044
NYX	0:85b3fd62ea1a	2045	/* ########################## NVIC functions #################################### */
NYX	0:85b3fd62ea1a	2046	/**
NYX	0:85b3fd62ea1a	2047	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	2048	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
NYX	0:85b3fd62ea1a	2049	\brief Functions that manage interrupts and exceptions via the NVIC.
NYX	0:85b3fd62ea1a	2050	@{
NYX	0:85b3fd62ea1a	2051	*/
NYX	0:85b3fd62ea1a	2052
NYX	0:85b3fd62ea1a	2053	#ifdef CMSIS_NVIC_VIRTUAL
NYX	0:85b3fd62ea1a	2054	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	2055	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
NYX	0:85b3fd62ea1a	2056	#endif
NYX	0:85b3fd62ea1a	2057	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	2058	#else
NYX	0:85b3fd62ea1a	2059	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
NYX	0:85b3fd62ea1a	2060	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
NYX	0:85b3fd62ea1a	2061	#define NVIC_EnableIRQ __NVIC_EnableIRQ
NYX	0:85b3fd62ea1a	2062	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
NYX	0:85b3fd62ea1a	2063	#define NVIC_DisableIRQ __NVIC_DisableIRQ
NYX	0:85b3fd62ea1a	2064	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
NYX	0:85b3fd62ea1a	2065	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
NYX	0:85b3fd62ea1a	2066	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
NYX	0:85b3fd62ea1a	2067	#define NVIC_GetActive __NVIC_GetActive
NYX	0:85b3fd62ea1a	2068	#define NVIC_SetPriority __NVIC_SetPriority
NYX	0:85b3fd62ea1a	2069	#define NVIC_GetPriority __NVIC_GetPriority
NYX	0:85b3fd62ea1a	2070	#define NVIC_SystemReset __NVIC_SystemReset
NYX	0:85b3fd62ea1a	2071	#endif /* CMSIS_NVIC_VIRTUAL */
NYX	0:85b3fd62ea1a	2072
NYX	0:85b3fd62ea1a	2073	#ifdef CMSIS_VECTAB_VIRTUAL
NYX	0:85b3fd62ea1a	2074	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	2075	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
NYX	0:85b3fd62ea1a	2076	#endif
NYX	0:85b3fd62ea1a	2077	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	2078	#else
NYX	0:85b3fd62ea1a	2079	#define NVIC_SetVector __NVIC_SetVector
NYX	0:85b3fd62ea1a	2080	#define NVIC_GetVector __NVIC_GetVector
NYX	0:85b3fd62ea1a	2081	#endif /* (CMSIS_VECTAB_VIRTUAL) */
NYX	0:85b3fd62ea1a	2082
NYX	0:85b3fd62ea1a	2083	#define NVIC_USER_IRQ_OFFSET 16
NYX	0:85b3fd62ea1a	2084
NYX	0:85b3fd62ea1a	2085
NYX	0:85b3fd62ea1a	2086
NYX	0:85b3fd62ea1a	2087	/**
NYX	0:85b3fd62ea1a	2088	\brief Set Priority Grouping
NYX	0:85b3fd62ea1a	2089	\details Sets the priority grouping field using the required unlock sequence.
NYX	0:85b3fd62ea1a	2090	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
NYX	0:85b3fd62ea1a	2091	Only values from 0..7 are used.
NYX	0:85b3fd62ea1a	2092	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	2093	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	2094	\param [in] PriorityGroup Priority grouping field.
NYX	0:85b3fd62ea1a	2095	*/
NYX	0:85b3fd62ea1a	2096	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
NYX	0:85b3fd62ea1a	2097	{
NYX	0:85b3fd62ea1a	2098	uint32_t reg_value;
NYX	0:85b3fd62ea1a	2099	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	2100
NYX	0:85b3fd62ea1a	2101	reg_value = SCB->AIRCR; /* read old register configuration */
NYX	0:85b3fd62ea1a	2102	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
NYX	0:85b3fd62ea1a	2103	reg_value = (reg_value \|
NYX	0:85b3fd62ea1a	2104	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
NYX	0:85b3fd62ea1a	2105	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
NYX	0:85b3fd62ea1a	2106	SCB->AIRCR = reg_value;
NYX	0:85b3fd62ea1a	2107	}
NYX	0:85b3fd62ea1a	2108
NYX	0:85b3fd62ea1a	2109
NYX	0:85b3fd62ea1a	2110	/**
NYX	0:85b3fd62ea1a	2111	\brief Get Priority Grouping
NYX	0:85b3fd62ea1a	2112	\details Reads the priority grouping field from the NVIC Interrupt Controller.
NYX	0:85b3fd62ea1a	2113	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
NYX	0:85b3fd62ea1a	2114	*/
NYX	0:85b3fd62ea1a	2115	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
NYX	0:85b3fd62ea1a	2116	{
NYX	0:85b3fd62ea1a	2117	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
NYX	0:85b3fd62ea1a	2118	}
NYX	0:85b3fd62ea1a	2119
NYX	0:85b3fd62ea1a	2120
NYX	0:85b3fd62ea1a	2121	/**
NYX	0:85b3fd62ea1a	2122	\brief Enable Interrupt
NYX	0:85b3fd62ea1a	2123	\details Enables a device specific interrupt in the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	2124	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2125	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2126	*/
NYX	0:85b3fd62ea1a	2127	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2128	{
NYX	0:85b3fd62ea1a	2129	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2130	{
NYX	0:85b3fd62ea1a	2131	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	2132	}
NYX	0:85b3fd62ea1a	2133	}
NYX	0:85b3fd62ea1a	2134
NYX	0:85b3fd62ea1a	2135
NYX	0:85b3fd62ea1a	2136	/**
NYX	0:85b3fd62ea1a	2137	\brief Get Interrupt Enable status
NYX	0:85b3fd62ea1a	2138	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	2139	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2140	\return 0 Interrupt is not enabled.
NYX	0:85b3fd62ea1a	2141	\return 1 Interrupt is enabled.
NYX	0:85b3fd62ea1a	2142	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2143	*/
NYX	0:85b3fd62ea1a	2144	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2145	{
NYX	0:85b3fd62ea1a	2146	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2147	{
NYX	0:85b3fd62ea1a	2148	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2149	}
NYX	0:85b3fd62ea1a	2150	else
NYX	0:85b3fd62ea1a	2151	{
NYX	0:85b3fd62ea1a	2152	return(0U);
NYX	0:85b3fd62ea1a	2153	}
NYX	0:85b3fd62ea1a	2154	}
NYX	0:85b3fd62ea1a	2155
NYX	0:85b3fd62ea1a	2156
NYX	0:85b3fd62ea1a	2157	/**
NYX	0:85b3fd62ea1a	2158	\brief Disable Interrupt
NYX	0:85b3fd62ea1a	2159	\details Disables a device specific interrupt in the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	2160	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2161	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2162	*/
NYX	0:85b3fd62ea1a	2163	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2164	{
NYX	0:85b3fd62ea1a	2165	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2166	{
NYX	0:85b3fd62ea1a	2167	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	2168	__DSB();
NYX	0:85b3fd62ea1a	2169	__ISB();
NYX	0:85b3fd62ea1a	2170	}
NYX	0:85b3fd62ea1a	2171	}
NYX	0:85b3fd62ea1a	2172
NYX	0:85b3fd62ea1a	2173
NYX	0:85b3fd62ea1a	2174	/**
NYX	0:85b3fd62ea1a	2175	\brief Get Pending Interrupt
NYX	0:85b3fd62ea1a	2176	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
NYX	0:85b3fd62ea1a	2177	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2178	\return 0 Interrupt status is not pending.
NYX	0:85b3fd62ea1a	2179	\return 1 Interrupt status is pending.
NYX	0:85b3fd62ea1a	2180	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2181	*/
NYX	0:85b3fd62ea1a	2182	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2183	{
NYX	0:85b3fd62ea1a	2184	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2185	{
NYX	0:85b3fd62ea1a	2186	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2187	}
NYX	0:85b3fd62ea1a	2188	else
NYX	0:85b3fd62ea1a	2189	{
NYX	0:85b3fd62ea1a	2190	return(0U);
NYX	0:85b3fd62ea1a	2191	}
NYX	0:85b3fd62ea1a	2192	}
NYX	0:85b3fd62ea1a	2193
NYX	0:85b3fd62ea1a	2194
NYX	0:85b3fd62ea1a	2195	/**
NYX	0:85b3fd62ea1a	2196	\brief Set Pending Interrupt
NYX	0:85b3fd62ea1a	2197	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
NYX	0:85b3fd62ea1a	2198	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2199	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2200	*/
NYX	0:85b3fd62ea1a	2201	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2202	{
NYX	0:85b3fd62ea1a	2203	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2204	{
NYX	0:85b3fd62ea1a	2205	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	2206	}
NYX	0:85b3fd62ea1a	2207	}
NYX	0:85b3fd62ea1a	2208
NYX	0:85b3fd62ea1a	2209
NYX	0:85b3fd62ea1a	2210	/**
NYX	0:85b3fd62ea1a	2211	\brief Clear Pending Interrupt
NYX	0:85b3fd62ea1a	2212	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
NYX	0:85b3fd62ea1a	2213	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2214	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2215	*/
NYX	0:85b3fd62ea1a	2216	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2217	{
NYX	0:85b3fd62ea1a	2218	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2219	{
NYX	0:85b3fd62ea1a	2220	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	2221	}
NYX	0:85b3fd62ea1a	2222	}
NYX	0:85b3fd62ea1a	2223
NYX	0:85b3fd62ea1a	2224
NYX	0:85b3fd62ea1a	2225	/**
NYX	0:85b3fd62ea1a	2226	\brief Get Active Interrupt
NYX	0:85b3fd62ea1a	2227	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
NYX	0:85b3fd62ea1a	2228	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2229	\return 0 Interrupt status is not active.
NYX	0:85b3fd62ea1a	2230	\return 1 Interrupt status is active.
NYX	0:85b3fd62ea1a	2231	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2232	*/
NYX	0:85b3fd62ea1a	2233	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2234	{
NYX	0:85b3fd62ea1a	2235	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2236	{
NYX	0:85b3fd62ea1a	2237	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2238	}
NYX	0:85b3fd62ea1a	2239	else
NYX	0:85b3fd62ea1a	2240	{
NYX	0:85b3fd62ea1a	2241	return(0U);
NYX	0:85b3fd62ea1a	2242	}
NYX	0:85b3fd62ea1a	2243	}
NYX	0:85b3fd62ea1a	2244
NYX	0:85b3fd62ea1a	2245
NYX	0:85b3fd62ea1a	2246	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX	0:85b3fd62ea1a	2247	/**
NYX	0:85b3fd62ea1a	2248	\brief Get Interrupt Target State
NYX	0:85b3fd62ea1a	2249	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
NYX	0:85b3fd62ea1a	2250	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2251	\return 0 if interrupt is assigned to Secure
NYX	0:85b3fd62ea1a	2252	\return 1 if interrupt is assigned to Non Secure
NYX	0:85b3fd62ea1a	2253	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2254	*/
NYX	0:85b3fd62ea1a	2255	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2256	{
NYX	0:85b3fd62ea1a	2257	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2258	{
NYX	0:85b3fd62ea1a	2259	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2260	}
NYX	0:85b3fd62ea1a	2261	else
NYX	0:85b3fd62ea1a	2262	{
NYX	0:85b3fd62ea1a	2263	return(0U);
NYX	0:85b3fd62ea1a	2264	}
NYX	0:85b3fd62ea1a	2265	}
NYX	0:85b3fd62ea1a	2266
NYX	0:85b3fd62ea1a	2267
NYX	0:85b3fd62ea1a	2268	/**
NYX	0:85b3fd62ea1a	2269	\brief Set Interrupt Target State
NYX	0:85b3fd62ea1a	2270	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
NYX	0:85b3fd62ea1a	2271	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2272	\return 0 if interrupt is assigned to Secure
NYX	0:85b3fd62ea1a	2273	1 if interrupt is assigned to Non Secure
NYX	0:85b3fd62ea1a	2274	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2275	*/
NYX	0:85b3fd62ea1a	2276	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2277	{
NYX	0:85b3fd62ea1a	2278	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2279	{
NYX	0:85b3fd62ea1a	2280	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
NYX	0:85b3fd62ea1a	2281	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2282	}
NYX	0:85b3fd62ea1a	2283	else
NYX	0:85b3fd62ea1a	2284	{
NYX	0:85b3fd62ea1a	2285	return(0U);
NYX	0:85b3fd62ea1a	2286	}
NYX	0:85b3fd62ea1a	2287	}
NYX	0:85b3fd62ea1a	2288
NYX	0:85b3fd62ea1a	2289
NYX	0:85b3fd62ea1a	2290	/**
NYX	0:85b3fd62ea1a	2291	\brief Clear Interrupt Target State
NYX	0:85b3fd62ea1a	2292	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
NYX	0:85b3fd62ea1a	2293	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2294	\return 0 if interrupt is assigned to Secure
NYX	0:85b3fd62ea1a	2295	1 if interrupt is assigned to Non Secure
NYX	0:85b3fd62ea1a	2296	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2297	*/
NYX	0:85b3fd62ea1a	2298	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2299	{
NYX	0:85b3fd62ea1a	2300	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2301	{
NYX	0:85b3fd62ea1a	2302	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
NYX	0:85b3fd62ea1a	2303	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2304	}
NYX	0:85b3fd62ea1a	2305	else
NYX	0:85b3fd62ea1a	2306	{
NYX	0:85b3fd62ea1a	2307	return(0U);
NYX	0:85b3fd62ea1a	2308	}
NYX	0:85b3fd62ea1a	2309	}
NYX	0:85b3fd62ea1a	2310	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX	0:85b3fd62ea1a	2311
NYX	0:85b3fd62ea1a	2312
NYX	0:85b3fd62ea1a	2313	/**
NYX	0:85b3fd62ea1a	2314	\brief Set Interrupt Priority
NYX	0:85b3fd62ea1a	2315	\details Sets the priority of a device specific interrupt or a processor exception.
NYX	0:85b3fd62ea1a	2316	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	2317	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	2318	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	2319	\param [in] priority Priority to set.
NYX	0:85b3fd62ea1a	2320	\note The priority cannot be set for every processor exception.
NYX	0:85b3fd62ea1a	2321	*/
NYX	0:85b3fd62ea1a	2322	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
NYX	0:85b3fd62ea1a	2323	{
NYX	0:85b3fd62ea1a	2324	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2325	{
NYX	0:85b3fd62ea1a	2326	NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
NYX	0:85b3fd62ea1a	2327	}
NYX	0:85b3fd62ea1a	2328	else
NYX	0:85b3fd62ea1a	2329	{
NYX	0:85b3fd62ea1a	2330	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
NYX	0:85b3fd62ea1a	2331	}
NYX	0:85b3fd62ea1a	2332	}
NYX	0:85b3fd62ea1a	2333
NYX	0:85b3fd62ea1a	2334
NYX	0:85b3fd62ea1a	2335	/**
NYX	0:85b3fd62ea1a	2336	\brief Get Interrupt Priority
NYX	0:85b3fd62ea1a	2337	\details Reads the priority of a device specific interrupt or a processor exception.
NYX	0:85b3fd62ea1a	2338	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	2339	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	2340	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	2341	\return Interrupt Priority.
NYX	0:85b3fd62ea1a	2342	Value is aligned automatically to the implemented priority bits of the microcontroller.
NYX	0:85b3fd62ea1a	2343	*/
NYX	0:85b3fd62ea1a	2344	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2345	{
NYX	0:85b3fd62ea1a	2346
NYX	0:85b3fd62ea1a	2347	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2348	{
NYX	0:85b3fd62ea1a	2349	return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
NYX	0:85b3fd62ea1a	2350	}
NYX	0:85b3fd62ea1a	2351	else
NYX	0:85b3fd62ea1a	2352	{
NYX	0:85b3fd62ea1a	2353	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
NYX	0:85b3fd62ea1a	2354	}
NYX	0:85b3fd62ea1a	2355	}
NYX	0:85b3fd62ea1a	2356
NYX	0:85b3fd62ea1a	2357
NYX	0:85b3fd62ea1a	2358	/**
NYX	0:85b3fd62ea1a	2359	\brief Encode Priority
NYX	0:85b3fd62ea1a	2360	\details Encodes the priority for an interrupt with the given priority group,
NYX	0:85b3fd62ea1a	2361	preemptive priority value, and subpriority value.
NYX	0:85b3fd62ea1a	2362	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	2363	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	2364	\param [in] PriorityGroup Used priority group.
NYX	0:85b3fd62ea1a	2365	\param [in] PreemptPriority Preemptive priority value (starting from 0).
NYX	0:85b3fd62ea1a	2366	\param [in] SubPriority Subpriority value (starting from 0).
NYX	0:85b3fd62ea1a	2367	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
NYX	0:85b3fd62ea1a	2368	*/
NYX	0:85b3fd62ea1a	2369	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
NYX	0:85b3fd62ea1a	2370	{
NYX	0:85b3fd62ea1a	2371	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	2372	uint32_t PreemptPriorityBits;
NYX	0:85b3fd62ea1a	2373	uint32_t SubPriorityBits;
NYX	0:85b3fd62ea1a	2374
NYX	0:85b3fd62ea1a	2375	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
NYX	0:85b3fd62ea1a	2376	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
NYX	0:85b3fd62ea1a	2377
NYX	0:85b3fd62ea1a	2378	return (
NYX	0:85b3fd62ea1a	2379	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
NYX	0:85b3fd62ea1a	2380	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
NYX	0:85b3fd62ea1a	2381	);
NYX	0:85b3fd62ea1a	2382	}
NYX	0:85b3fd62ea1a	2383
NYX	0:85b3fd62ea1a	2384
NYX	0:85b3fd62ea1a	2385	/**
NYX	0:85b3fd62ea1a	2386	\brief Decode Priority
NYX	0:85b3fd62ea1a	2387	\details Decodes an interrupt priority value with a given priority group to
NYX	0:85b3fd62ea1a	2388	preemptive priority value and subpriority value.
NYX	0:85b3fd62ea1a	2389	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	2390	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	2391	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
NYX	0:85b3fd62ea1a	2392	\param [in] PriorityGroup Used priority group.
NYX	0:85b3fd62ea1a	2393	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
NYX	0:85b3fd62ea1a	2394	\param [out] pSubPriority Subpriority value (starting from 0).
NYX	0:85b3fd62ea1a	2395	*/
NYX	0:85b3fd62ea1a	2396	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
NYX	0:85b3fd62ea1a	2397	{
NYX	0:85b3fd62ea1a	2398	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	2399	uint32_t PreemptPriorityBits;
NYX	0:85b3fd62ea1a	2400	uint32_t SubPriorityBits;
NYX	0:85b3fd62ea1a	2401
NYX	0:85b3fd62ea1a	2402	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
NYX	0:85b3fd62ea1a	2403	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
NYX	0:85b3fd62ea1a	2404
NYX	0:85b3fd62ea1a	2405	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
NYX	0:85b3fd62ea1a	2406	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
NYX	0:85b3fd62ea1a	2407	}
NYX	0:85b3fd62ea1a	2408
NYX	0:85b3fd62ea1a	2409
NYX	0:85b3fd62ea1a	2410	/**
NYX	0:85b3fd62ea1a	2411	\brief Set Interrupt Vector
NYX	0:85b3fd62ea1a	2412	\details Sets an interrupt vector in SRAM based interrupt vector table.
NYX	0:85b3fd62ea1a	2413	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	2414	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	2415	VTOR must been relocated to SRAM before.
NYX	0:85b3fd62ea1a	2416	\param [in] IRQn Interrupt number
NYX	0:85b3fd62ea1a	2417	\param [in] vector Address of interrupt handler function
NYX	0:85b3fd62ea1a	2418	*/
NYX	0:85b3fd62ea1a	2419	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
NYX	0:85b3fd62ea1a	2420	{
NYX	0:85b3fd62ea1a	2421	uint32_t vectors = (uint32_t )SCB->VTOR;
NYX	0:85b3fd62ea1a	2422	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
NYX	0:85b3fd62ea1a	2423	}
NYX	0:85b3fd62ea1a	2424
NYX	0:85b3fd62ea1a	2425
NYX	0:85b3fd62ea1a	2426	/**
NYX	0:85b3fd62ea1a	2427	\brief Get Interrupt Vector
NYX	0:85b3fd62ea1a	2428	\details Reads an interrupt vector from interrupt vector table.
NYX	0:85b3fd62ea1a	2429	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	2430	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	2431	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	2432	\return Address of interrupt handler function
NYX	0:85b3fd62ea1a	2433	*/
NYX	0:85b3fd62ea1a	2434	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2435	{
NYX	0:85b3fd62ea1a	2436	uint32_t vectors = (uint32_t )SCB->VTOR;
NYX	0:85b3fd62ea1a	2437	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
NYX	0:85b3fd62ea1a	2438	}
NYX	0:85b3fd62ea1a	2439
NYX	0:85b3fd62ea1a	2440
NYX	0:85b3fd62ea1a	2441	/**
NYX	0:85b3fd62ea1a	2442	\brief System Reset
NYX	0:85b3fd62ea1a	2443	\details Initiates a system reset request to reset the MCU.
NYX	0:85b3fd62ea1a	2444	*/
NYX	0:85b3fd62ea1a	2445	__STATIC_INLINE void __NVIC_SystemReset(void)
NYX	0:85b3fd62ea1a	2446	{
NYX	0:85b3fd62ea1a	2447	__DSB(); /* Ensure all outstanding memory accesses included
NYX	0:85b3fd62ea1a	2448	buffered write are completed before reset */
NYX	0:85b3fd62ea1a	2449	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
NYX	0:85b3fd62ea1a	2450	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
NYX	0:85b3fd62ea1a	2451	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
NYX	0:85b3fd62ea1a	2452	__DSB(); /* Ensure completion of memory access */
NYX	0:85b3fd62ea1a	2453
NYX	0:85b3fd62ea1a	2454	for(;;) /* wait until reset */
NYX	0:85b3fd62ea1a	2455	{
NYX	0:85b3fd62ea1a	2456	__NOP();
NYX	0:85b3fd62ea1a	2457	}
NYX	0:85b3fd62ea1a	2458	}
NYX	0:85b3fd62ea1a	2459
NYX	0:85b3fd62ea1a	2460	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX	0:85b3fd62ea1a	2461	/**
NYX	0:85b3fd62ea1a	2462	\brief Set Priority Grouping (non-secure)
NYX	0:85b3fd62ea1a	2463	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
NYX	0:85b3fd62ea1a	2464	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
NYX	0:85b3fd62ea1a	2465	Only values from 0..7 are used.
NYX	0:85b3fd62ea1a	2466	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	2467	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	2468	\param [in] PriorityGroup Priority grouping field.
NYX	0:85b3fd62ea1a	2469	*/
NYX	0:85b3fd62ea1a	2470	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
NYX	0:85b3fd62ea1a	2471	{
NYX	0:85b3fd62ea1a	2472	uint32_t reg_value;
NYX	0:85b3fd62ea1a	2473	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	2474
NYX	0:85b3fd62ea1a	2475	reg_value = SCB_NS->AIRCR; /* read old register configuration */
NYX	0:85b3fd62ea1a	2476	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
NYX	0:85b3fd62ea1a	2477	reg_value = (reg_value \|
NYX	0:85b3fd62ea1a	2478	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
NYX	0:85b3fd62ea1a	2479	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
NYX	0:85b3fd62ea1a	2480	SCB_NS->AIRCR = reg_value;
NYX	0:85b3fd62ea1a	2481	}
NYX	0:85b3fd62ea1a	2482
NYX	0:85b3fd62ea1a	2483
NYX	0:85b3fd62ea1a	2484	/**
NYX	0:85b3fd62ea1a	2485	\brief Get Priority Grouping (non-secure)
NYX	0:85b3fd62ea1a	2486	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
NYX	0:85b3fd62ea1a	2487	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
NYX	0:85b3fd62ea1a	2488	*/
NYX	0:85b3fd62ea1a	2489	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
NYX	0:85b3fd62ea1a	2490	{
NYX	0:85b3fd62ea1a	2491	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
NYX	0:85b3fd62ea1a	2492	}
NYX	0:85b3fd62ea1a	2493
NYX	0:85b3fd62ea1a	2494
NYX	0:85b3fd62ea1a	2495	/**
NYX	0:85b3fd62ea1a	2496	\brief Enable Interrupt (non-secure)
NYX	0:85b3fd62ea1a	2497	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
NYX	0:85b3fd62ea1a	2498	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2499	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2500	*/
NYX	0:85b3fd62ea1a	2501	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2502	{
NYX	0:85b3fd62ea1a	2503	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2504	{
NYX	0:85b3fd62ea1a	2505	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	2506	}
NYX	0:85b3fd62ea1a	2507	}
NYX	0:85b3fd62ea1a	2508
NYX	0:85b3fd62ea1a	2509
NYX	0:85b3fd62ea1a	2510	/**
NYX	0:85b3fd62ea1a	2511	\brief Get Interrupt Enable status (non-secure)
NYX	0:85b3fd62ea1a	2512	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
NYX	0:85b3fd62ea1a	2513	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2514	\return 0 Interrupt is not enabled.
NYX	0:85b3fd62ea1a	2515	\return 1 Interrupt is enabled.
NYX	0:85b3fd62ea1a	2516	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2517	*/
NYX	0:85b3fd62ea1a	2518	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2519	{
NYX	0:85b3fd62ea1a	2520	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2521	{
NYX	0:85b3fd62ea1a	2522	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2523	}
NYX	0:85b3fd62ea1a	2524	else
NYX	0:85b3fd62ea1a	2525	{
NYX	0:85b3fd62ea1a	2526	return(0U);
NYX	0:85b3fd62ea1a	2527	}
NYX	0:85b3fd62ea1a	2528	}
NYX	0:85b3fd62ea1a	2529
NYX	0:85b3fd62ea1a	2530
NYX	0:85b3fd62ea1a	2531	/**
NYX	0:85b3fd62ea1a	2532	\brief Disable Interrupt (non-secure)
NYX	0:85b3fd62ea1a	2533	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
NYX	0:85b3fd62ea1a	2534	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2535	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2536	*/
NYX	0:85b3fd62ea1a	2537	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2538	{
NYX	0:85b3fd62ea1a	2539	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2540	{
NYX	0:85b3fd62ea1a	2541	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	2542	}
NYX	0:85b3fd62ea1a	2543	}
NYX	0:85b3fd62ea1a	2544
NYX	0:85b3fd62ea1a	2545
NYX	0:85b3fd62ea1a	2546	/**
NYX	0:85b3fd62ea1a	2547	\brief Get Pending Interrupt (non-secure)
NYX	0:85b3fd62ea1a	2548	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
NYX	0:85b3fd62ea1a	2549	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2550	\return 0 Interrupt status is not pending.
NYX	0:85b3fd62ea1a	2551	\return 1 Interrupt status is pending.
NYX	0:85b3fd62ea1a	2552	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2553	*/
NYX	0:85b3fd62ea1a	2554	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2555	{
NYX	0:85b3fd62ea1a	2556	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2557	{
NYX	0:85b3fd62ea1a	2558	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2559	}
NYX	0:85b3fd62ea1a	2560	}
NYX	0:85b3fd62ea1a	2561
NYX	0:85b3fd62ea1a	2562
NYX	0:85b3fd62ea1a	2563	/**
NYX	0:85b3fd62ea1a	2564	\brief Set Pending Interrupt (non-secure)
NYX	0:85b3fd62ea1a	2565	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
NYX	0:85b3fd62ea1a	2566	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2567	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2568	*/
NYX	0:85b3fd62ea1a	2569	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2570	{
NYX	0:85b3fd62ea1a	2571	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2572	{
NYX	0:85b3fd62ea1a	2573	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	2574	}
NYX	0:85b3fd62ea1a	2575	}
NYX	0:85b3fd62ea1a	2576
NYX	0:85b3fd62ea1a	2577
NYX	0:85b3fd62ea1a	2578	/**
NYX	0:85b3fd62ea1a	2579	\brief Clear Pending Interrupt (non-secure)
NYX	0:85b3fd62ea1a	2580	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
NYX	0:85b3fd62ea1a	2581	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2582	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2583	*/
NYX	0:85b3fd62ea1a	2584	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2585	{
NYX	0:85b3fd62ea1a	2586	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2587	{
NYX	0:85b3fd62ea1a	2588	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	2589	}
NYX	0:85b3fd62ea1a	2590	}
NYX	0:85b3fd62ea1a	2591
NYX	0:85b3fd62ea1a	2592
NYX	0:85b3fd62ea1a	2593	/**
NYX	0:85b3fd62ea1a	2594	\brief Get Active Interrupt (non-secure)
NYX	0:85b3fd62ea1a	2595	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
NYX	0:85b3fd62ea1a	2596	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	2597	\return 0 Interrupt status is not active.
NYX	0:85b3fd62ea1a	2598	\return 1 Interrupt status is active.
NYX	0:85b3fd62ea1a	2599	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	2600	*/
NYX	0:85b3fd62ea1a	2601	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2602	{
NYX	0:85b3fd62ea1a	2603	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2604	{
NYX	0:85b3fd62ea1a	2605	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	2606	}
NYX	0:85b3fd62ea1a	2607	else
NYX	0:85b3fd62ea1a	2608	{
NYX	0:85b3fd62ea1a	2609	return(0U);
NYX	0:85b3fd62ea1a	2610	}
NYX	0:85b3fd62ea1a	2611	}
NYX	0:85b3fd62ea1a	2612
NYX	0:85b3fd62ea1a	2613
NYX	0:85b3fd62ea1a	2614	/**
NYX	0:85b3fd62ea1a	2615	\brief Set Interrupt Priority (non-secure)
NYX	0:85b3fd62ea1a	2616	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
NYX	0:85b3fd62ea1a	2617	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	2618	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	2619	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	2620	\param [in] priority Priority to set.
NYX	0:85b3fd62ea1a	2621	\note The priority cannot be set for every non-secure processor exception.
NYX	0:85b3fd62ea1a	2622	*/
NYX	0:85b3fd62ea1a	2623	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
NYX	0:85b3fd62ea1a	2624	{
NYX	0:85b3fd62ea1a	2625	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2626	{
NYX	0:85b3fd62ea1a	2627	NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
NYX	0:85b3fd62ea1a	2628	}
NYX	0:85b3fd62ea1a	2629	else
NYX	0:85b3fd62ea1a	2630	{
NYX	0:85b3fd62ea1a	2631	SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
NYX	0:85b3fd62ea1a	2632	}
NYX	0:85b3fd62ea1a	2633	}
NYX	0:85b3fd62ea1a	2634
NYX	0:85b3fd62ea1a	2635
NYX	0:85b3fd62ea1a	2636	/**
NYX	0:85b3fd62ea1a	2637	\brief Get Interrupt Priority (non-secure)
NYX	0:85b3fd62ea1a	2638	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
NYX	0:85b3fd62ea1a	2639	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	2640	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	2641	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	2642	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
NYX	0:85b3fd62ea1a	2643	*/
NYX	0:85b3fd62ea1a	2644	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	2645	{
NYX	0:85b3fd62ea1a	2646
NYX	0:85b3fd62ea1a	2647	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	2648	{
NYX	0:85b3fd62ea1a	2649	return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
NYX	0:85b3fd62ea1a	2650	}
NYX	0:85b3fd62ea1a	2651	else
NYX	0:85b3fd62ea1a	2652	{
NYX	0:85b3fd62ea1a	2653	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
NYX	0:85b3fd62ea1a	2654	}
NYX	0:85b3fd62ea1a	2655	}
NYX	0:85b3fd62ea1a	2656	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
NYX	0:85b3fd62ea1a	2657
NYX	0:85b3fd62ea1a	2658	/@} end of CMSIS_Core_NVICFunctions /
NYX	0:85b3fd62ea1a	2659
NYX	0:85b3fd62ea1a	2660
NYX	0:85b3fd62ea1a	2661	/* ########################## FPU functions #################################### */
NYX	0:85b3fd62ea1a	2662	/**
NYX	0:85b3fd62ea1a	2663	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	2664	\defgroup CMSIS_Core_FpuFunctions FPU Functions
NYX	0:85b3fd62ea1a	2665	\brief Function that provides FPU type.
NYX	0:85b3fd62ea1a	2666	@{
NYX	0:85b3fd62ea1a	2667	*/
NYX	0:85b3fd62ea1a	2668
NYX	0:85b3fd62ea1a	2669	/**
NYX	0:85b3fd62ea1a	2670	\brief get FPU type
NYX	0:85b3fd62ea1a	2671	\details returns the FPU type
NYX	0:85b3fd62ea1a	2672	\returns
NYX	0:85b3fd62ea1a	2673	- \b 0: No FPU
NYX	0:85b3fd62ea1a	2674	- \b 1: Single precision FPU
NYX	0:85b3fd62ea1a	2675	- \b 2: Double + Single precision FPU
NYX	0:85b3fd62ea1a	2676	*/
NYX	0:85b3fd62ea1a	2677	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
NYX	0:85b3fd62ea1a	2678	{
NYX	0:85b3fd62ea1a	2679	uint32_t mvfr0;
NYX	0:85b3fd62ea1a	2680
NYX	0:85b3fd62ea1a	2681	mvfr0 = FPU->MVFR0;
NYX	0:85b3fd62ea1a	2682	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
NYX	0:85b3fd62ea1a	2683	{
NYX	0:85b3fd62ea1a	2684	return 2U; /* Double + Single precision FPU */
NYX	0:85b3fd62ea1a	2685	}
NYX	0:85b3fd62ea1a	2686	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
NYX	0:85b3fd62ea1a	2687	{
NYX	0:85b3fd62ea1a	2688	return 1U; /* Single precision FPU */
NYX	0:85b3fd62ea1a	2689	}
NYX	0:85b3fd62ea1a	2690	else
NYX	0:85b3fd62ea1a	2691	{
NYX	0:85b3fd62ea1a	2692	return 0U; /* No FPU */
NYX	0:85b3fd62ea1a	2693	}
NYX	0:85b3fd62ea1a	2694	}
NYX	0:85b3fd62ea1a	2695
NYX	0:85b3fd62ea1a	2696
NYX	0:85b3fd62ea1a	2697	/@} end of CMSIS_Core_FpuFunctions /
NYX	0:85b3fd62ea1a	2698
NYX	0:85b3fd62ea1a	2699
NYX	0:85b3fd62ea1a	2700
NYX	0:85b3fd62ea1a	2701	/* ########################## SAU functions #################################### */
NYX	0:85b3fd62ea1a	2702	/**
NYX	0:85b3fd62ea1a	2703	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	2704	\defgroup CMSIS_Core_SAUFunctions SAU Functions
NYX	0:85b3fd62ea1a	2705	\brief Functions that configure the SAU.
NYX	0:85b3fd62ea1a	2706	@{
NYX	0:85b3fd62ea1a	2707	*/
NYX	0:85b3fd62ea1a	2708
NYX	0:85b3fd62ea1a	2709	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX	0:85b3fd62ea1a	2710
NYX	0:85b3fd62ea1a	2711	/**
NYX	0:85b3fd62ea1a	2712	\brief Enable SAU
NYX	0:85b3fd62ea1a	2713	\details Enables the Security Attribution Unit (SAU).
NYX	0:85b3fd62ea1a	2714	*/
NYX	0:85b3fd62ea1a	2715	__STATIC_INLINE void TZ_SAU_Enable(void)
NYX	0:85b3fd62ea1a	2716	{
NYX	0:85b3fd62ea1a	2717	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
NYX	0:85b3fd62ea1a	2718	}
NYX	0:85b3fd62ea1a	2719
NYX	0:85b3fd62ea1a	2720
NYX	0:85b3fd62ea1a	2721
NYX	0:85b3fd62ea1a	2722	/**
NYX	0:85b3fd62ea1a	2723	\brief Disable SAU
NYX	0:85b3fd62ea1a	2724	\details Disables the Security Attribution Unit (SAU).
NYX	0:85b3fd62ea1a	2725	*/
NYX	0:85b3fd62ea1a	2726	__STATIC_INLINE void TZ_SAU_Disable(void)
NYX	0:85b3fd62ea1a	2727	{
NYX	0:85b3fd62ea1a	2728	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
NYX	0:85b3fd62ea1a	2729	}
NYX	0:85b3fd62ea1a	2730
NYX	0:85b3fd62ea1a	2731	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX	0:85b3fd62ea1a	2732
NYX	0:85b3fd62ea1a	2733	/@} end of CMSIS_Core_SAUFunctions /
NYX	0:85b3fd62ea1a	2734
NYX	0:85b3fd62ea1a	2735
NYX	0:85b3fd62ea1a	2736
NYX	0:85b3fd62ea1a	2737
NYX	0:85b3fd62ea1a	2738	/* ################################## SysTick function ############################################ */
NYX	0:85b3fd62ea1a	2739	/**
NYX	0:85b3fd62ea1a	2740	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	2741	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
NYX	0:85b3fd62ea1a	2742	\brief Functions that configure the System.
NYX	0:85b3fd62ea1a	2743	@{
NYX	0:85b3fd62ea1a	2744	*/
NYX	0:85b3fd62ea1a	2745
NYX	0:85b3fd62ea1a	2746	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
NYX	0:85b3fd62ea1a	2747
NYX	0:85b3fd62ea1a	2748	/**
NYX	0:85b3fd62ea1a	2749	\brief System Tick Configuration
NYX	0:85b3fd62ea1a	2750	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
NYX	0:85b3fd62ea1a	2751	Counter is in free running mode to generate periodic interrupts.
NYX	0:85b3fd62ea1a	2752	\param [in] ticks Number of ticks between two interrupts.
NYX	0:85b3fd62ea1a	2753	\return 0 Function succeeded.
NYX	0:85b3fd62ea1a	2754	\return 1 Function failed.
NYX	0:85b3fd62ea1a	2755	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
NYX	0:85b3fd62ea1a	2756	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
NYX	0:85b3fd62ea1a	2757	must contain a vendor-specific implementation of this function.
NYX	0:85b3fd62ea1a	2758	*/
NYX	0:85b3fd62ea1a	2759	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
NYX	0:85b3fd62ea1a	2760	{
NYX	0:85b3fd62ea1a	2761	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
NYX	0:85b3fd62ea1a	2762	{
NYX	0:85b3fd62ea1a	2763	return (1UL); /* Reload value impossible */
NYX	0:85b3fd62ea1a	2764	}
NYX	0:85b3fd62ea1a	2765
NYX	0:85b3fd62ea1a	2766	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NYX	0:85b3fd62ea1a	2767	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
NYX	0:85b3fd62ea1a	2768	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NYX	0:85b3fd62ea1a	2769	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
NYX	0:85b3fd62ea1a	2770	SysTick_CTRL_TICKINT_Msk \|
NYX	0:85b3fd62ea1a	2771	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
NYX	0:85b3fd62ea1a	2772	return (0UL); /* Function successful */
NYX	0:85b3fd62ea1a	2773	}
NYX	0:85b3fd62ea1a	2774
NYX	0:85b3fd62ea1a	2775	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX	0:85b3fd62ea1a	2776	/**
NYX	0:85b3fd62ea1a	2777	\brief System Tick Configuration (non-secure)
NYX	0:85b3fd62ea1a	2778	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
NYX	0:85b3fd62ea1a	2779	Counter is in free running mode to generate periodic interrupts.
NYX	0:85b3fd62ea1a	2780	\param [in] ticks Number of ticks between two interrupts.
NYX	0:85b3fd62ea1a	2781	\return 0 Function succeeded.
NYX	0:85b3fd62ea1a	2782	\return 1 Function failed.
NYX	0:85b3fd62ea1a	2783	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
NYX	0:85b3fd62ea1a	2784	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
NYX	0:85b3fd62ea1a	2785	must contain a vendor-specific implementation of this function.
NYX	0:85b3fd62ea1a	2786
NYX	0:85b3fd62ea1a	2787	*/
NYX	0:85b3fd62ea1a	2788	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
NYX	0:85b3fd62ea1a	2789	{
NYX	0:85b3fd62ea1a	2790	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
NYX	0:85b3fd62ea1a	2791	{
NYX	0:85b3fd62ea1a	2792	return (1UL); /* Reload value impossible */
NYX	0:85b3fd62ea1a	2793	}
NYX	0:85b3fd62ea1a	2794
NYX	0:85b3fd62ea1a	2795	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NYX	0:85b3fd62ea1a	2796	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
NYX	0:85b3fd62ea1a	2797	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
NYX	0:85b3fd62ea1a	2798	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
NYX	0:85b3fd62ea1a	2799	SysTick_CTRL_TICKINT_Msk \|
NYX	0:85b3fd62ea1a	2800	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
NYX	0:85b3fd62ea1a	2801	return (0UL); /* Function successful */
NYX	0:85b3fd62ea1a	2802	}
NYX	0:85b3fd62ea1a	2803	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX	0:85b3fd62ea1a	2804
NYX	0:85b3fd62ea1a	2805	#endif
NYX	0:85b3fd62ea1a	2806
NYX	0:85b3fd62ea1a	2807	/@} end of CMSIS_Core_SysTickFunctions /
NYX	0:85b3fd62ea1a	2808
NYX	0:85b3fd62ea1a	2809
NYX	0:85b3fd62ea1a	2810
NYX	0:85b3fd62ea1a	2811	/* ##################################### Debug In/Output function ########################################### */
NYX	0:85b3fd62ea1a	2812	/**
NYX	0:85b3fd62ea1a	2813	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	2814	\defgroup CMSIS_core_DebugFunctions ITM Functions
NYX	0:85b3fd62ea1a	2815	\brief Functions that access the ITM debug interface.
NYX	0:85b3fd62ea1a	2816	@{
NYX	0:85b3fd62ea1a	2817	*/
NYX	0:85b3fd62ea1a	2818
NYX	0:85b3fd62ea1a	2819	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
NYX	0:85b3fd62ea1a	2820	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
NYX	0:85b3fd62ea1a	2821
NYX	0:85b3fd62ea1a	2822
NYX	0:85b3fd62ea1a	2823	/**
NYX	0:85b3fd62ea1a	2824	\brief ITM Send Character
NYX	0:85b3fd62ea1a	2825	\details Transmits a character via the ITM channel 0, and
NYX	0:85b3fd62ea1a	2826	\li Just returns when no debugger is connected that has booked the output.
NYX	0:85b3fd62ea1a	2827	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
NYX	0:85b3fd62ea1a	2828	\param [in] ch Character to transmit.
NYX	0:85b3fd62ea1a	2829	\returns Character to transmit.
NYX	0:85b3fd62ea1a	2830	*/
NYX	0:85b3fd62ea1a	2831	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
NYX	0:85b3fd62ea1a	2832	{
NYX	0:85b3fd62ea1a	2833	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
NYX	0:85b3fd62ea1a	2834	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
NYX	0:85b3fd62ea1a	2835	{
NYX	0:85b3fd62ea1a	2836	while (ITM->PORT[0U].u32 == 0UL)
NYX	0:85b3fd62ea1a	2837	{
NYX	0:85b3fd62ea1a	2838	__NOP();
NYX	0:85b3fd62ea1a	2839	}
NYX	0:85b3fd62ea1a	2840	ITM->PORT[0U].u8 = (uint8_t)ch;
NYX	0:85b3fd62ea1a	2841	}
NYX	0:85b3fd62ea1a	2842	return (ch);
NYX	0:85b3fd62ea1a	2843	}
NYX	0:85b3fd62ea1a	2844
NYX	0:85b3fd62ea1a	2845
NYX	0:85b3fd62ea1a	2846	/**
NYX	0:85b3fd62ea1a	2847	\brief ITM Receive Character
NYX	0:85b3fd62ea1a	2848	\details Inputs a character via the external variable \ref ITM_RxBuffer.
NYX	0:85b3fd62ea1a	2849	\return Received character.
NYX	0:85b3fd62ea1a	2850	\return -1 No character pending.
NYX	0:85b3fd62ea1a	2851	*/
NYX	0:85b3fd62ea1a	2852	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
NYX	0:85b3fd62ea1a	2853	{
NYX	0:85b3fd62ea1a	2854	int32_t ch = -1; /* no character available */
NYX	0:85b3fd62ea1a	2855
NYX	0:85b3fd62ea1a	2856	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
NYX	0:85b3fd62ea1a	2857	{
NYX	0:85b3fd62ea1a	2858	ch = ITM_RxBuffer;
NYX	0:85b3fd62ea1a	2859	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
NYX	0:85b3fd62ea1a	2860	}
NYX	0:85b3fd62ea1a	2861
NYX	0:85b3fd62ea1a	2862	return (ch);
NYX	0:85b3fd62ea1a	2863	}
NYX	0:85b3fd62ea1a	2864
NYX	0:85b3fd62ea1a	2865
NYX	0:85b3fd62ea1a	2866	/**
NYX	0:85b3fd62ea1a	2867	\brief ITM Check Character
NYX	0:85b3fd62ea1a	2868	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
NYX	0:85b3fd62ea1a	2869	\return 0 No character available.
NYX	0:85b3fd62ea1a	2870	\return 1 Character available.
NYX	0:85b3fd62ea1a	2871	*/
NYX	0:85b3fd62ea1a	2872	__STATIC_INLINE int32_t ITM_CheckChar (void)
NYX	0:85b3fd62ea1a	2873	{
NYX	0:85b3fd62ea1a	2874
NYX	0:85b3fd62ea1a	2875	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
NYX	0:85b3fd62ea1a	2876	{
NYX	0:85b3fd62ea1a	2877	return (0); /* no character available */
NYX	0:85b3fd62ea1a	2878	}
NYX	0:85b3fd62ea1a	2879	else
NYX	0:85b3fd62ea1a	2880	{
NYX	0:85b3fd62ea1a	2881	return (1); /* character available */
NYX	0:85b3fd62ea1a	2882	}
NYX	0:85b3fd62ea1a	2883	}
NYX	0:85b3fd62ea1a	2884
NYX	0:85b3fd62ea1a	2885	/@} end of CMSIS_core_DebugFunctions /
NYX	0:85b3fd62ea1a	2886
NYX	0:85b3fd62ea1a	2887
NYX	0:85b3fd62ea1a	2888
NYX	0:85b3fd62ea1a	2889
NYX	0:85b3fd62ea1a	2890	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	2891	}
NYX	0:85b3fd62ea1a	2892	#endif
NYX	0:85b3fd62ea1a	2893
NYX	0:85b3fd62ea1a	2894	#endif /* __CORE_CM33_H_DEPENDANT */
NYX	0:85b3fd62ea1a	2895
NYX	0:85b3fd62ea1a	2896	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
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Followers:	2

cmsis/core_cm33.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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