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cmsis/core_cm3.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/************************************************************************//
NYX	0:85b3fd62ea1a	2	* @file core_cm3.h
NYX	0:85b3fd62ea1a	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
NYX	0:85b3fd62ea1a	4	* @version V5.0.2
NYX	0:85b3fd62ea1a	5	* @date 13. February 2017
NYX	0:85b3fd62ea1a	6	******************************************************************************/
NYX	0:85b3fd62ea1a	7	/*
NYX	0:85b3fd62ea1a	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
NYX	0:85b3fd62ea1a	9	*
NYX	0:85b3fd62ea1a	10	* SPDX-License-Identifier: Apache-2.0
NYX	0:85b3fd62ea1a	11	*
NYX	0:85b3fd62ea1a	12	* Licensed under the Apache License, Version 2.0 (the License); you may
NYX	0:85b3fd62ea1a	13	* not use this file except in compliance with the License.
NYX	0:85b3fd62ea1a	14	* You may obtain a copy of the License at
NYX	0:85b3fd62ea1a	15	*
NYX	0:85b3fd62ea1a	16	* www.apache.org/licenses/LICENSE-2.0
NYX	0:85b3fd62ea1a	17	*
NYX	0:85b3fd62ea1a	18	* Unless required by applicable law or agreed to in writing, software
NYX	0:85b3fd62ea1a	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
NYX	0:85b3fd62ea1a	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX	0:85b3fd62ea1a	21	* See the License for the specific language governing permissions and
NYX	0:85b3fd62ea1a	22	* limitations under the License.
NYX	0:85b3fd62ea1a	23	*/
NYX	0:85b3fd62ea1a	24
NYX	0:85b3fd62ea1a	25	#if defined ( __ICCARM__ )
NYX	0:85b3fd62ea1a	26	#pragma system_include /* treat file as system include file for MISRA check */
NYX	0:85b3fd62ea1a	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX	0:85b3fd62ea1a	28	#pragma clang system_header /* treat file as system include file */
NYX	0:85b3fd62ea1a	29	#endif
NYX	0:85b3fd62ea1a	30
NYX	0:85b3fd62ea1a	31	#ifndef __CORE_CM3_H_GENERIC
NYX	0:85b3fd62ea1a	32	#define __CORE_CM3_H_GENERIC
NYX	0:85b3fd62ea1a	33
NYX	0:85b3fd62ea1a	34	#include <stdint.h>
NYX	0:85b3fd62ea1a	35
NYX	0:85b3fd62ea1a	36	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	37	extern "C" {
NYX	0:85b3fd62ea1a	38	#endif
NYX	0:85b3fd62ea1a	39
NYX	0:85b3fd62ea1a	40	/**
NYX	0:85b3fd62ea1a	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
NYX	0:85b3fd62ea1a	42	CMSIS violates the following MISRA-C:2004 rules:
NYX	0:85b3fd62ea1a	43
NYX	0:85b3fd62ea1a	44	\li Required Rule 8.5, object/function definition in header file.<br>
NYX	0:85b3fd62ea1a	45	Function definitions in header files are used to allow 'inlining'.
NYX	0:85b3fd62ea1a	46
NYX	0:85b3fd62ea1a	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
NYX	0:85b3fd62ea1a	48	Unions are used for effective representation of core registers.
NYX	0:85b3fd62ea1a	49
NYX	0:85b3fd62ea1a	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
NYX	0:85b3fd62ea1a	51	Function-like macros are used to allow more efficient code.
NYX	0:85b3fd62ea1a	52	*/
NYX	0:85b3fd62ea1a	53
NYX	0:85b3fd62ea1a	54
NYX	0:85b3fd62ea1a	55	/*******************************************************************************
NYX	0:85b3fd62ea1a	56	* CMSIS definitions
NYX	0:85b3fd62ea1a	57	******************************************************************************/
NYX	0:85b3fd62ea1a	58	/**
NYX	0:85b3fd62ea1a	59	\ingroup Cortex_M3
NYX	0:85b3fd62ea1a	60	@{
NYX	0:85b3fd62ea1a	61	*/
NYX	0:85b3fd62ea1a	62
NYX	0:85b3fd62ea1a	63	/* CMSIS CM3 definitions */
NYX	0:85b3fd62ea1a	64	#define __CM3_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
NYX	0:85b3fd62ea1a	65	#define __CM3_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
NYX	0:85b3fd62ea1a	66	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) \| \
NYX	0:85b3fd62ea1a	67	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
NYX	0:85b3fd62ea1a	68
NYX	0:85b3fd62ea1a	69	#define __CORTEX_M (3U) /!< Cortex-M Core /
NYX	0:85b3fd62ea1a	70
NYX	0:85b3fd62ea1a	71	/** __FPU_USED indicates whether an FPU is used or not.
NYX	0:85b3fd62ea1a	72	This core does not support an FPU at all
NYX	0:85b3fd62ea1a	73	*/
NYX	0:85b3fd62ea1a	74	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	75
NYX	0:85b3fd62ea1a	76	#if defined ( __CC_ARM )
NYX	0:85b3fd62ea1a	77	#if defined __TARGET_FPU_VFP
NYX	0:85b3fd62ea1a	78	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	79	#endif
NYX	0:85b3fd62ea1a	80
NYX	0:85b3fd62ea1a	81	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX	0:85b3fd62ea1a	82	#if defined __ARM_PCS_VFP
NYX	0:85b3fd62ea1a	83	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	84	#endif
NYX	0:85b3fd62ea1a	85
NYX	0:85b3fd62ea1a	86	#elif defined ( __GNUC__ )
NYX	0:85b3fd62ea1a	87	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
NYX	0:85b3fd62ea1a	88	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	89	#endif
NYX	0:85b3fd62ea1a	90
NYX	0:85b3fd62ea1a	91	#elif defined ( __ICCARM__ )
NYX	0:85b3fd62ea1a	92	#if defined __ARMVFP__
NYX	0:85b3fd62ea1a	93	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	94	#endif
NYX	0:85b3fd62ea1a	95
NYX	0:85b3fd62ea1a	96	#elif defined ( __TI_ARM__ )
NYX	0:85b3fd62ea1a	97	#if defined __TI_VFP_SUPPORT__
NYX	0:85b3fd62ea1a	98	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	99	#endif
NYX	0:85b3fd62ea1a	100
NYX	0:85b3fd62ea1a	101	#elif defined ( __TASKING__ )
NYX	0:85b3fd62ea1a	102	#if defined __FPU_VFP__
NYX	0:85b3fd62ea1a	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	104	#endif
NYX	0:85b3fd62ea1a	105
NYX	0:85b3fd62ea1a	106	#elif defined ( __CSMC__ )
NYX	0:85b3fd62ea1a	107	#if ( __CSMC__ & 0x400U)
NYX	0:85b3fd62ea1a	108	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	109	#endif
NYX	0:85b3fd62ea1a	110
NYX	0:85b3fd62ea1a	111	#endif
NYX	0:85b3fd62ea1a	112
NYX	0:85b3fd62ea1a	113	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
NYX	0:85b3fd62ea1a	114
NYX	0:85b3fd62ea1a	115
NYX	0:85b3fd62ea1a	116	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	117	}
NYX	0:85b3fd62ea1a	118	#endif
NYX	0:85b3fd62ea1a	119
NYX	0:85b3fd62ea1a	120	#endif /* __CORE_CM3_H_GENERIC */
NYX	0:85b3fd62ea1a	121
NYX	0:85b3fd62ea1a	122	#ifndef __CMSIS_GENERIC
NYX	0:85b3fd62ea1a	123
NYX	0:85b3fd62ea1a	124	#ifndef __CORE_CM3_H_DEPENDANT
NYX	0:85b3fd62ea1a	125	#define __CORE_CM3_H_DEPENDANT
NYX	0:85b3fd62ea1a	126
NYX	0:85b3fd62ea1a	127	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	128	extern "C" {
NYX	0:85b3fd62ea1a	129	#endif
NYX	0:85b3fd62ea1a	130
NYX	0:85b3fd62ea1a	131	/* check device defines and use defaults */
NYX	0:85b3fd62ea1a	132	#if defined __CHECK_DEVICE_DEFINES
NYX	0:85b3fd62ea1a	133	#ifndef __CM3_REV
NYX	0:85b3fd62ea1a	134	#define __CM3_REV 0x0200U
NYX	0:85b3fd62ea1a	135	#warning "__CM3_REV not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	136	#endif
NYX	0:85b3fd62ea1a	137
NYX	0:85b3fd62ea1a	138	#ifndef __MPU_PRESENT
NYX	0:85b3fd62ea1a	139	#define __MPU_PRESENT 0U
NYX	0:85b3fd62ea1a	140	#warning "__MPU_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	141	#endif
NYX	0:85b3fd62ea1a	142
NYX	0:85b3fd62ea1a	143	#ifndef __NVIC_PRIO_BITS
NYX	0:85b3fd62ea1a	144	#define __NVIC_PRIO_BITS 3U
NYX	0:85b3fd62ea1a	145	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	146	#endif
NYX	0:85b3fd62ea1a	147
NYX	0:85b3fd62ea1a	148	#ifndef __Vendor_SysTickConfig
NYX	0:85b3fd62ea1a	149	#define __Vendor_SysTickConfig 0U
NYX	0:85b3fd62ea1a	150	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	151	#endif
NYX	0:85b3fd62ea1a	152	#endif
NYX	0:85b3fd62ea1a	153
NYX	0:85b3fd62ea1a	154	/* IO definitions (access restrictions to peripheral registers) */
NYX	0:85b3fd62ea1a	155	/**
NYX	0:85b3fd62ea1a	156	\defgroup CMSIS_glob_defs CMSIS Global Defines
NYX	0:85b3fd62ea1a	157
NYX	0:85b3fd62ea1a	158	<strong>IO Type Qualifiers</strong> are used
NYX	0:85b3fd62ea1a	159	\li to specify the access to peripheral variables.
NYX	0:85b3fd62ea1a	160	\li for automatic generation of peripheral register debug information.
NYX	0:85b3fd62ea1a	161	*/
NYX	0:85b3fd62ea1a	162	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	163	#define __I volatile /!< Defines 'read only' permissions /
NYX	0:85b3fd62ea1a	164	#else
NYX	0:85b3fd62ea1a	165	#define __I volatile const /!< Defines 'read only' permissions /
NYX	0:85b3fd62ea1a	166	#endif
NYX	0:85b3fd62ea1a	167	#define __O volatile /!< Defines 'write only' permissions /
NYX	0:85b3fd62ea1a	168	#define __IO volatile /!< Defines 'read / write' permissions /
NYX	0:85b3fd62ea1a	169
NYX	0:85b3fd62ea1a	170	/* following defines should be used for structure members */
NYX	0:85b3fd62ea1a	171	#define __IM volatile const /! Defines 'read only' structure member permissions /
NYX	0:85b3fd62ea1a	172	#define __OM volatile /! Defines 'write only' structure member permissions /
NYX	0:85b3fd62ea1a	173	#define __IOM volatile /! Defines 'read / write' structure member permissions /
NYX	0:85b3fd62ea1a	174
NYX	0:85b3fd62ea1a	175	/@} end of group Cortex_M3 /
NYX	0:85b3fd62ea1a	176
NYX	0:85b3fd62ea1a	177
NYX	0:85b3fd62ea1a	178
NYX	0:85b3fd62ea1a	179	/*******************************************************************************
NYX	0:85b3fd62ea1a	180	* Register Abstraction
NYX	0:85b3fd62ea1a	181	Core Register contain:
NYX	0:85b3fd62ea1a	182	- Core Register
NYX	0:85b3fd62ea1a	183	- Core NVIC Register
NYX	0:85b3fd62ea1a	184	- Core SCB Register
NYX	0:85b3fd62ea1a	185	- Core SysTick Register
NYX	0:85b3fd62ea1a	186	- Core Debug Register
NYX	0:85b3fd62ea1a	187	- Core MPU Register
NYX	0:85b3fd62ea1a	188	******************************************************************************/
NYX	0:85b3fd62ea1a	189	/**
NYX	0:85b3fd62ea1a	190	\defgroup CMSIS_core_register Defines and Type Definitions
NYX	0:85b3fd62ea1a	191	\brief Type definitions and defines for Cortex-M processor based devices.
NYX	0:85b3fd62ea1a	192	*/
NYX	0:85b3fd62ea1a	193
NYX	0:85b3fd62ea1a	194	/**
NYX	0:85b3fd62ea1a	195	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	196	\defgroup CMSIS_CORE Status and Control Registers
NYX	0:85b3fd62ea1a	197	\brief Core Register type definitions.
NYX	0:85b3fd62ea1a	198	@{
NYX	0:85b3fd62ea1a	199	*/
NYX	0:85b3fd62ea1a	200
NYX	0:85b3fd62ea1a	201	/**
NYX	0:85b3fd62ea1a	202	\brief Union type to access the Application Program Status Register (APSR).
NYX	0:85b3fd62ea1a	203	*/
NYX	0:85b3fd62ea1a	204	typedef union
NYX	0:85b3fd62ea1a	205	{
NYX	0:85b3fd62ea1a	206	struct
NYX	0:85b3fd62ea1a	207	{
NYX	0:85b3fd62ea1a	208	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
NYX	0:85b3fd62ea1a	209	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
NYX	0:85b3fd62ea1a	210	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
NYX	0:85b3fd62ea1a	211	uint32_t C:1; /!< bit: 29 Carry condition code flag /
NYX	0:85b3fd62ea1a	212	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
NYX	0:85b3fd62ea1a	213	uint32_t N:1; /!< bit: 31 Negative condition code flag /
NYX	0:85b3fd62ea1a	214	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	215	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	216	} APSR_Type;
NYX	0:85b3fd62ea1a	217
NYX	0:85b3fd62ea1a	218	/* APSR Register Definitions */
NYX	0:85b3fd62ea1a	219	#define APSR_N_Pos 31U /!< APSR: N Position /
NYX	0:85b3fd62ea1a	220	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
NYX	0:85b3fd62ea1a	221
NYX	0:85b3fd62ea1a	222	#define APSR_Z_Pos 30U /!< APSR: Z Position /
NYX	0:85b3fd62ea1a	223	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
NYX	0:85b3fd62ea1a	224
NYX	0:85b3fd62ea1a	225	#define APSR_C_Pos 29U /!< APSR: C Position /
NYX	0:85b3fd62ea1a	226	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
NYX	0:85b3fd62ea1a	227
NYX	0:85b3fd62ea1a	228	#define APSR_V_Pos 28U /!< APSR: V Position /
NYX	0:85b3fd62ea1a	229	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
NYX	0:85b3fd62ea1a	230
NYX	0:85b3fd62ea1a	231	#define APSR_Q_Pos 27U /!< APSR: Q Position /
NYX	0:85b3fd62ea1a	232	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
NYX	0:85b3fd62ea1a	233
NYX	0:85b3fd62ea1a	234
NYX	0:85b3fd62ea1a	235	/**
NYX	0:85b3fd62ea1a	236	\brief Union type to access the Interrupt Program Status Register (IPSR).
NYX	0:85b3fd62ea1a	237	*/
NYX	0:85b3fd62ea1a	238	typedef union
NYX	0:85b3fd62ea1a	239	{
NYX	0:85b3fd62ea1a	240	struct
NYX	0:85b3fd62ea1a	241	{
NYX	0:85b3fd62ea1a	242	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
NYX	0:85b3fd62ea1a	243	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
NYX	0:85b3fd62ea1a	244	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	245	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	246	} IPSR_Type;
NYX	0:85b3fd62ea1a	247
NYX	0:85b3fd62ea1a	248	/* IPSR Register Definitions */
NYX	0:85b3fd62ea1a	249	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
NYX	0:85b3fd62ea1a	250	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
NYX	0:85b3fd62ea1a	251
NYX	0:85b3fd62ea1a	252
NYX	0:85b3fd62ea1a	253	/**
NYX	0:85b3fd62ea1a	254	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
NYX	0:85b3fd62ea1a	255	*/
NYX	0:85b3fd62ea1a	256	typedef union
NYX	0:85b3fd62ea1a	257	{
NYX	0:85b3fd62ea1a	258	struct
NYX	0:85b3fd62ea1a	259	{
NYX	0:85b3fd62ea1a	260	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
NYX	0:85b3fd62ea1a	261	uint32_t _reserved0:1; /!< bit: 9 Reserved /
NYX	0:85b3fd62ea1a	262	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
NYX	0:85b3fd62ea1a	263	uint32_t _reserved1:8; /!< bit: 16..23 Reserved /
NYX	0:85b3fd62ea1a	264	uint32_t T:1; /!< bit: 24 Thumb bit /
NYX	0:85b3fd62ea1a	265	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
NYX	0:85b3fd62ea1a	266	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
NYX	0:85b3fd62ea1a	267	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
NYX	0:85b3fd62ea1a	268	uint32_t C:1; /!< bit: 29 Carry condition code flag /
NYX	0:85b3fd62ea1a	269	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
NYX	0:85b3fd62ea1a	270	uint32_t N:1; /!< bit: 31 Negative condition code flag /
NYX	0:85b3fd62ea1a	271	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	272	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	273	} xPSR_Type;
NYX	0:85b3fd62ea1a	274
NYX	0:85b3fd62ea1a	275	/* xPSR Register Definitions */
NYX	0:85b3fd62ea1a	276	#define xPSR_N_Pos 31U /!< xPSR: N Position /
NYX	0:85b3fd62ea1a	277	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
NYX	0:85b3fd62ea1a	278
NYX	0:85b3fd62ea1a	279	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
NYX	0:85b3fd62ea1a	280	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
NYX	0:85b3fd62ea1a	281
NYX	0:85b3fd62ea1a	282	#define xPSR_C_Pos 29U /!< xPSR: C Position /
NYX	0:85b3fd62ea1a	283	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
NYX	0:85b3fd62ea1a	284
NYX	0:85b3fd62ea1a	285	#define xPSR_V_Pos 28U /!< xPSR: V Position /
NYX	0:85b3fd62ea1a	286	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
NYX	0:85b3fd62ea1a	287
NYX	0:85b3fd62ea1a	288	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
NYX	0:85b3fd62ea1a	289	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
NYX	0:85b3fd62ea1a	290
NYX	0:85b3fd62ea1a	291	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
NYX	0:85b3fd62ea1a	292	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
NYX	0:85b3fd62ea1a	293
NYX	0:85b3fd62ea1a	294	#define xPSR_T_Pos 24U /!< xPSR: T Position /
NYX	0:85b3fd62ea1a	295	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
NYX	0:85b3fd62ea1a	296
NYX	0:85b3fd62ea1a	297	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
NYX	0:85b3fd62ea1a	298	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
NYX	0:85b3fd62ea1a	299
NYX	0:85b3fd62ea1a	300	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
NYX	0:85b3fd62ea1a	301	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
NYX	0:85b3fd62ea1a	302
NYX	0:85b3fd62ea1a	303
NYX	0:85b3fd62ea1a	304	/**
NYX	0:85b3fd62ea1a	305	\brief Union type to access the Control Registers (CONTROL).
NYX	0:85b3fd62ea1a	306	*/
NYX	0:85b3fd62ea1a	307	typedef union
NYX	0:85b3fd62ea1a	308	{
NYX	0:85b3fd62ea1a	309	struct
NYX	0:85b3fd62ea1a	310	{
NYX	0:85b3fd62ea1a	311	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
NYX	0:85b3fd62ea1a	312	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
NYX	0:85b3fd62ea1a	313	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
NYX	0:85b3fd62ea1a	314	} b; /!< Structure used for bit access /
NYX	0:85b3fd62ea1a	315	uint32_t w; /!< Type used for word access /
NYX	0:85b3fd62ea1a	316	} CONTROL_Type;
NYX	0:85b3fd62ea1a	317
NYX	0:85b3fd62ea1a	318	/* CONTROL Register Definitions */
NYX	0:85b3fd62ea1a	319	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
NYX	0:85b3fd62ea1a	320	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
NYX	0:85b3fd62ea1a	321
NYX	0:85b3fd62ea1a	322	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
NYX	0:85b3fd62ea1a	323	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
NYX	0:85b3fd62ea1a	324
NYX	0:85b3fd62ea1a	325	/@} end of group CMSIS_CORE /
NYX	0:85b3fd62ea1a	326
NYX	0:85b3fd62ea1a	327
NYX	0:85b3fd62ea1a	328	/**
NYX	0:85b3fd62ea1a	329	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	330	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
NYX	0:85b3fd62ea1a	331	\brief Type definitions for the NVIC Registers
NYX	0:85b3fd62ea1a	332	@{
NYX	0:85b3fd62ea1a	333	*/
NYX	0:85b3fd62ea1a	334
NYX	0:85b3fd62ea1a	335	/**
NYX	0:85b3fd62ea1a	336	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
NYX	0:85b3fd62ea1a	337	*/
NYX	0:85b3fd62ea1a	338	typedef struct
NYX	0:85b3fd62ea1a	339	{
NYX	0:85b3fd62ea1a	340	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
NYX	0:85b3fd62ea1a	341	uint32_t RESERVED0[24U];
NYX	0:85b3fd62ea1a	342	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
NYX	0:85b3fd62ea1a	343	uint32_t RSERVED1[24U];
NYX	0:85b3fd62ea1a	344	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
NYX	0:85b3fd62ea1a	345	uint32_t RESERVED2[24U];
NYX	0:85b3fd62ea1a	346	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
NYX	0:85b3fd62ea1a	347	uint32_t RESERVED3[24U];
NYX	0:85b3fd62ea1a	348	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
NYX	0:85b3fd62ea1a	349	uint32_t RESERVED4[56U];
NYX	0:85b3fd62ea1a	350	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
NYX	0:85b3fd62ea1a	351	uint32_t RESERVED5[644U];
NYX	0:85b3fd62ea1a	352	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
NYX	0:85b3fd62ea1a	353	} NVIC_Type;
NYX	0:85b3fd62ea1a	354
NYX	0:85b3fd62ea1a	355	/* Software Triggered Interrupt Register Definitions */
NYX	0:85b3fd62ea1a	356	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
NYX	0:85b3fd62ea1a	357	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
NYX	0:85b3fd62ea1a	358
NYX	0:85b3fd62ea1a	359	/@} end of group CMSIS_NVIC /
NYX	0:85b3fd62ea1a	360
NYX	0:85b3fd62ea1a	361
NYX	0:85b3fd62ea1a	362	/**
NYX	0:85b3fd62ea1a	363	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	364	\defgroup CMSIS_SCB System Control Block (SCB)
NYX	0:85b3fd62ea1a	365	\brief Type definitions for the System Control Block Registers
NYX	0:85b3fd62ea1a	366	@{
NYX	0:85b3fd62ea1a	367	*/
NYX	0:85b3fd62ea1a	368
NYX	0:85b3fd62ea1a	369	/**
NYX	0:85b3fd62ea1a	370	\brief Structure type to access the System Control Block (SCB).
NYX	0:85b3fd62ea1a	371	*/
NYX	0:85b3fd62ea1a	372	typedef struct
NYX	0:85b3fd62ea1a	373	{
NYX	0:85b3fd62ea1a	374	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
NYX	0:85b3fd62ea1a	375	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
NYX	0:85b3fd62ea1a	376	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
NYX	0:85b3fd62ea1a	377	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
NYX	0:85b3fd62ea1a	378	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
NYX	0:85b3fd62ea1a	379	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
NYX	0:85b3fd62ea1a	380	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
NYX	0:85b3fd62ea1a	381	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
NYX	0:85b3fd62ea1a	382	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
NYX	0:85b3fd62ea1a	383	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
NYX	0:85b3fd62ea1a	384	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
NYX	0:85b3fd62ea1a	385	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
NYX	0:85b3fd62ea1a	386	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
NYX	0:85b3fd62ea1a	387	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
NYX	0:85b3fd62ea1a	388	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
NYX	0:85b3fd62ea1a	389	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
NYX	0:85b3fd62ea1a	390	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
NYX	0:85b3fd62ea1a	391	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
NYX	0:85b3fd62ea1a	392	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
NYX	0:85b3fd62ea1a	393	uint32_t RESERVED0[5U];
NYX	0:85b3fd62ea1a	394	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
NYX	0:85b3fd62ea1a	395	} SCB_Type;
NYX	0:85b3fd62ea1a	396
NYX	0:85b3fd62ea1a	397	/* SCB CPUID Register Definitions */
NYX	0:85b3fd62ea1a	398	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
NYX	0:85b3fd62ea1a	399	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
NYX	0:85b3fd62ea1a	400
NYX	0:85b3fd62ea1a	401	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
NYX	0:85b3fd62ea1a	402	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
NYX	0:85b3fd62ea1a	403
NYX	0:85b3fd62ea1a	404	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
NYX	0:85b3fd62ea1a	405	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
NYX	0:85b3fd62ea1a	406
NYX	0:85b3fd62ea1a	407	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
NYX	0:85b3fd62ea1a	408	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
NYX	0:85b3fd62ea1a	409
NYX	0:85b3fd62ea1a	410	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
NYX	0:85b3fd62ea1a	411	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
NYX	0:85b3fd62ea1a	412
NYX	0:85b3fd62ea1a	413	/* SCB Interrupt Control State Register Definitions */
NYX	0:85b3fd62ea1a	414	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
NYX	0:85b3fd62ea1a	415	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
NYX	0:85b3fd62ea1a	416
NYX	0:85b3fd62ea1a	417	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
NYX	0:85b3fd62ea1a	418	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
NYX	0:85b3fd62ea1a	419
NYX	0:85b3fd62ea1a	420	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
NYX	0:85b3fd62ea1a	421	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
NYX	0:85b3fd62ea1a	422
NYX	0:85b3fd62ea1a	423	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
NYX	0:85b3fd62ea1a	424	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
NYX	0:85b3fd62ea1a	425
NYX	0:85b3fd62ea1a	426	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
NYX	0:85b3fd62ea1a	427	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
NYX	0:85b3fd62ea1a	428
NYX	0:85b3fd62ea1a	429	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
NYX	0:85b3fd62ea1a	430	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
NYX	0:85b3fd62ea1a	431
NYX	0:85b3fd62ea1a	432	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
NYX	0:85b3fd62ea1a	433	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
NYX	0:85b3fd62ea1a	434
NYX	0:85b3fd62ea1a	435	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
NYX	0:85b3fd62ea1a	436	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
NYX	0:85b3fd62ea1a	437
NYX	0:85b3fd62ea1a	438	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
NYX	0:85b3fd62ea1a	439	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
NYX	0:85b3fd62ea1a	440
NYX	0:85b3fd62ea1a	441	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
NYX	0:85b3fd62ea1a	442	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
NYX	0:85b3fd62ea1a	443
NYX	0:85b3fd62ea1a	444	/* SCB Vector Table Offset Register Definitions */
NYX	0:85b3fd62ea1a	445	#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
NYX	0:85b3fd62ea1a	446	#define SCB_VTOR_TBLBASE_Pos 29U /!< SCB VTOR: TBLBASE Position /
NYX	0:85b3fd62ea1a	447	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
NYX	0:85b3fd62ea1a	448
NYX	0:85b3fd62ea1a	449	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
NYX	0:85b3fd62ea1a	450	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
NYX	0:85b3fd62ea1a	451	#else
NYX	0:85b3fd62ea1a	452	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
NYX	0:85b3fd62ea1a	453	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
NYX	0:85b3fd62ea1a	454	#endif
NYX	0:85b3fd62ea1a	455
NYX	0:85b3fd62ea1a	456	/* SCB Application Interrupt and Reset Control Register Definitions */
NYX	0:85b3fd62ea1a	457	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
NYX	0:85b3fd62ea1a	458	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
NYX	0:85b3fd62ea1a	459
NYX	0:85b3fd62ea1a	460	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
NYX	0:85b3fd62ea1a	461	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
NYX	0:85b3fd62ea1a	462
NYX	0:85b3fd62ea1a	463	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
NYX	0:85b3fd62ea1a	464	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
NYX	0:85b3fd62ea1a	465
NYX	0:85b3fd62ea1a	466	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
NYX	0:85b3fd62ea1a	467	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
NYX	0:85b3fd62ea1a	468
NYX	0:85b3fd62ea1a	469	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
NYX	0:85b3fd62ea1a	470	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
NYX	0:85b3fd62ea1a	471
NYX	0:85b3fd62ea1a	472	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
NYX	0:85b3fd62ea1a	473	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
NYX	0:85b3fd62ea1a	474
NYX	0:85b3fd62ea1a	475	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
NYX	0:85b3fd62ea1a	476	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
NYX	0:85b3fd62ea1a	477
NYX	0:85b3fd62ea1a	478	/* SCB System Control Register Definitions */
NYX	0:85b3fd62ea1a	479	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
NYX	0:85b3fd62ea1a	480	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
NYX	0:85b3fd62ea1a	481
NYX	0:85b3fd62ea1a	482	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
NYX	0:85b3fd62ea1a	483	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
NYX	0:85b3fd62ea1a	484
NYX	0:85b3fd62ea1a	485	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
NYX	0:85b3fd62ea1a	486	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
NYX	0:85b3fd62ea1a	487
NYX	0:85b3fd62ea1a	488	/* SCB Configuration Control Register Definitions */
NYX	0:85b3fd62ea1a	489	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
NYX	0:85b3fd62ea1a	490	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
NYX	0:85b3fd62ea1a	491
NYX	0:85b3fd62ea1a	492	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
NYX	0:85b3fd62ea1a	493	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
NYX	0:85b3fd62ea1a	494
NYX	0:85b3fd62ea1a	495	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
NYX	0:85b3fd62ea1a	496	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
NYX	0:85b3fd62ea1a	497
NYX	0:85b3fd62ea1a	498	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
NYX	0:85b3fd62ea1a	499	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
NYX	0:85b3fd62ea1a	500
NYX	0:85b3fd62ea1a	501	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
NYX	0:85b3fd62ea1a	502	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
NYX	0:85b3fd62ea1a	503
NYX	0:85b3fd62ea1a	504	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
NYX	0:85b3fd62ea1a	505	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
NYX	0:85b3fd62ea1a	506
NYX	0:85b3fd62ea1a	507	/* SCB System Handler Control and State Register Definitions */
NYX	0:85b3fd62ea1a	508	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
NYX	0:85b3fd62ea1a	509	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
NYX	0:85b3fd62ea1a	510
NYX	0:85b3fd62ea1a	511	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
NYX	0:85b3fd62ea1a	512	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
NYX	0:85b3fd62ea1a	513
NYX	0:85b3fd62ea1a	514	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
NYX	0:85b3fd62ea1a	515	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
NYX	0:85b3fd62ea1a	516
NYX	0:85b3fd62ea1a	517	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
NYX	0:85b3fd62ea1a	518	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
NYX	0:85b3fd62ea1a	519
NYX	0:85b3fd62ea1a	520	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
NYX	0:85b3fd62ea1a	521	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	522
NYX	0:85b3fd62ea1a	523	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
NYX	0:85b3fd62ea1a	524	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	525
NYX	0:85b3fd62ea1a	526	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
NYX	0:85b3fd62ea1a	527	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
NYX	0:85b3fd62ea1a	528
NYX	0:85b3fd62ea1a	529	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
NYX	0:85b3fd62ea1a	530	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
NYX	0:85b3fd62ea1a	531
NYX	0:85b3fd62ea1a	532	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
NYX	0:85b3fd62ea1a	533	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
NYX	0:85b3fd62ea1a	534
NYX	0:85b3fd62ea1a	535	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
NYX	0:85b3fd62ea1a	536	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
NYX	0:85b3fd62ea1a	537
NYX	0:85b3fd62ea1a	538	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
NYX	0:85b3fd62ea1a	539	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
NYX	0:85b3fd62ea1a	540
NYX	0:85b3fd62ea1a	541	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
NYX	0:85b3fd62ea1a	542	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
NYX	0:85b3fd62ea1a	543
NYX	0:85b3fd62ea1a	544	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
NYX	0:85b3fd62ea1a	545	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
NYX	0:85b3fd62ea1a	546
NYX	0:85b3fd62ea1a	547	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
NYX	0:85b3fd62ea1a	548	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
NYX	0:85b3fd62ea1a	549
NYX	0:85b3fd62ea1a	550	/* SCB Configurable Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	551	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
NYX	0:85b3fd62ea1a	552	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
NYX	0:85b3fd62ea1a	553
NYX	0:85b3fd62ea1a	554	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
NYX	0:85b3fd62ea1a	555	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
NYX	0:85b3fd62ea1a	556
NYX	0:85b3fd62ea1a	557	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
NYX	0:85b3fd62ea1a	558	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
NYX	0:85b3fd62ea1a	559
NYX	0:85b3fd62ea1a	560	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	561	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
NYX	0:85b3fd62ea1a	562	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
NYX	0:85b3fd62ea1a	563
NYX	0:85b3fd62ea1a	564	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
NYX	0:85b3fd62ea1a	565	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
NYX	0:85b3fd62ea1a	566
NYX	0:85b3fd62ea1a	567	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
NYX	0:85b3fd62ea1a	568	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
NYX	0:85b3fd62ea1a	569
NYX	0:85b3fd62ea1a	570	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
NYX	0:85b3fd62ea1a	571	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
NYX	0:85b3fd62ea1a	572
NYX	0:85b3fd62ea1a	573	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
NYX	0:85b3fd62ea1a	574	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
NYX	0:85b3fd62ea1a	575
NYX	0:85b3fd62ea1a	576	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	577	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
NYX	0:85b3fd62ea1a	578	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
NYX	0:85b3fd62ea1a	579
NYX	0:85b3fd62ea1a	580	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
NYX	0:85b3fd62ea1a	581	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
NYX	0:85b3fd62ea1a	582
NYX	0:85b3fd62ea1a	583	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
NYX	0:85b3fd62ea1a	584	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
NYX	0:85b3fd62ea1a	585
NYX	0:85b3fd62ea1a	586	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
NYX	0:85b3fd62ea1a	587	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
NYX	0:85b3fd62ea1a	588
NYX	0:85b3fd62ea1a	589	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
NYX	0:85b3fd62ea1a	590	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
NYX	0:85b3fd62ea1a	591
NYX	0:85b3fd62ea1a	592	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
NYX	0:85b3fd62ea1a	593	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
NYX	0:85b3fd62ea1a	594
NYX	0:85b3fd62ea1a	595	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
NYX	0:85b3fd62ea1a	596	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
NYX	0:85b3fd62ea1a	597	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
NYX	0:85b3fd62ea1a	598
NYX	0:85b3fd62ea1a	599	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
NYX	0:85b3fd62ea1a	600	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
NYX	0:85b3fd62ea1a	601
NYX	0:85b3fd62ea1a	602	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
NYX	0:85b3fd62ea1a	603	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
NYX	0:85b3fd62ea1a	604
NYX	0:85b3fd62ea1a	605	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
NYX	0:85b3fd62ea1a	606	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
NYX	0:85b3fd62ea1a	607
NYX	0:85b3fd62ea1a	608	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
NYX	0:85b3fd62ea1a	609	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
NYX	0:85b3fd62ea1a	610
NYX	0:85b3fd62ea1a	611	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
NYX	0:85b3fd62ea1a	612	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
NYX	0:85b3fd62ea1a	613
NYX	0:85b3fd62ea1a	614	/* SCB Hard Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	615	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
NYX	0:85b3fd62ea1a	616	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
NYX	0:85b3fd62ea1a	617
NYX	0:85b3fd62ea1a	618	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
NYX	0:85b3fd62ea1a	619	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
NYX	0:85b3fd62ea1a	620
NYX	0:85b3fd62ea1a	621	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
NYX	0:85b3fd62ea1a	622	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
NYX	0:85b3fd62ea1a	623
NYX	0:85b3fd62ea1a	624	/* SCB Debug Fault Status Register Definitions */
NYX	0:85b3fd62ea1a	625	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
NYX	0:85b3fd62ea1a	626	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
NYX	0:85b3fd62ea1a	627
NYX	0:85b3fd62ea1a	628	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
NYX	0:85b3fd62ea1a	629	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
NYX	0:85b3fd62ea1a	630
NYX	0:85b3fd62ea1a	631	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
NYX	0:85b3fd62ea1a	632	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
NYX	0:85b3fd62ea1a	633
NYX	0:85b3fd62ea1a	634	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
NYX	0:85b3fd62ea1a	635	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
NYX	0:85b3fd62ea1a	636
NYX	0:85b3fd62ea1a	637	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
NYX	0:85b3fd62ea1a	638	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
NYX	0:85b3fd62ea1a	639
NYX	0:85b3fd62ea1a	640	/@} end of group CMSIS_SCB /
NYX	0:85b3fd62ea1a	641
NYX	0:85b3fd62ea1a	642
NYX	0:85b3fd62ea1a	643	/**
NYX	0:85b3fd62ea1a	644	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	645	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
NYX	0:85b3fd62ea1a	646	\brief Type definitions for the System Control and ID Register not in the SCB
NYX	0:85b3fd62ea1a	647	@{
NYX	0:85b3fd62ea1a	648	*/
NYX	0:85b3fd62ea1a	649
NYX	0:85b3fd62ea1a	650	/**
NYX	0:85b3fd62ea1a	651	\brief Structure type to access the System Control and ID Register not in the SCB.
NYX	0:85b3fd62ea1a	652	*/
NYX	0:85b3fd62ea1a	653	typedef struct
NYX	0:85b3fd62ea1a	654	{
NYX	0:85b3fd62ea1a	655	uint32_t RESERVED0[1U];
NYX	0:85b3fd62ea1a	656	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
NYX	0:85b3fd62ea1a	657	#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
NYX	0:85b3fd62ea1a	658	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
NYX	0:85b3fd62ea1a	659	#else
NYX	0:85b3fd62ea1a	660	uint32_t RESERVED1[1U];
NYX	0:85b3fd62ea1a	661	#endif
NYX	0:85b3fd62ea1a	662	} SCnSCB_Type;
NYX	0:85b3fd62ea1a	663
NYX	0:85b3fd62ea1a	664	/* Interrupt Controller Type Register Definitions */
NYX	0:85b3fd62ea1a	665	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
NYX	0:85b3fd62ea1a	666	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
NYX	0:85b3fd62ea1a	667
NYX	0:85b3fd62ea1a	668	/* Auxiliary Control Register Definitions */
NYX	0:85b3fd62ea1a	669
NYX	0:85b3fd62ea1a	670	#define SCnSCB_ACTLR_DISFOLD_Pos 2U /!< ACTLR: DISFOLD Position /
NYX	0:85b3fd62ea1a	671	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
NYX	0:85b3fd62ea1a	672
NYX	0:85b3fd62ea1a	673	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /!< ACTLR: DISDEFWBUF Position /
NYX	0:85b3fd62ea1a	674	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
NYX	0:85b3fd62ea1a	675
NYX	0:85b3fd62ea1a	676	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /!< ACTLR: DISMCYCINT Position /
NYX	0:85b3fd62ea1a	677	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
NYX	0:85b3fd62ea1a	678
NYX	0:85b3fd62ea1a	679	/@} end of group CMSIS_SCnotSCB /
NYX	0:85b3fd62ea1a	680
NYX	0:85b3fd62ea1a	681
NYX	0:85b3fd62ea1a	682	/**
NYX	0:85b3fd62ea1a	683	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	684	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
NYX	0:85b3fd62ea1a	685	\brief Type definitions for the System Timer Registers.
NYX	0:85b3fd62ea1a	686	@{
NYX	0:85b3fd62ea1a	687	*/
NYX	0:85b3fd62ea1a	688
NYX	0:85b3fd62ea1a	689	/**
NYX	0:85b3fd62ea1a	690	\brief Structure type to access the System Timer (SysTick).
NYX	0:85b3fd62ea1a	691	*/
NYX	0:85b3fd62ea1a	692	typedef struct
NYX	0:85b3fd62ea1a	693	{
NYX	0:85b3fd62ea1a	694	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
NYX	0:85b3fd62ea1a	695	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
NYX	0:85b3fd62ea1a	696	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
NYX	0:85b3fd62ea1a	697	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
NYX	0:85b3fd62ea1a	698	} SysTick_Type;
NYX	0:85b3fd62ea1a	699
NYX	0:85b3fd62ea1a	700	/* SysTick Control / Status Register Definitions */
NYX	0:85b3fd62ea1a	701	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
NYX	0:85b3fd62ea1a	702	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
NYX	0:85b3fd62ea1a	703
NYX	0:85b3fd62ea1a	704	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
NYX	0:85b3fd62ea1a	705	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
NYX	0:85b3fd62ea1a	706
NYX	0:85b3fd62ea1a	707	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
NYX	0:85b3fd62ea1a	708	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
NYX	0:85b3fd62ea1a	709
NYX	0:85b3fd62ea1a	710	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
NYX	0:85b3fd62ea1a	711	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
NYX	0:85b3fd62ea1a	712
NYX	0:85b3fd62ea1a	713	/* SysTick Reload Register Definitions */
NYX	0:85b3fd62ea1a	714	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
NYX	0:85b3fd62ea1a	715	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
NYX	0:85b3fd62ea1a	716
NYX	0:85b3fd62ea1a	717	/* SysTick Current Register Definitions */
NYX	0:85b3fd62ea1a	718	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
NYX	0:85b3fd62ea1a	719	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
NYX	0:85b3fd62ea1a	720
NYX	0:85b3fd62ea1a	721	/* SysTick Calibration Register Definitions */
NYX	0:85b3fd62ea1a	722	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
NYX	0:85b3fd62ea1a	723	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
NYX	0:85b3fd62ea1a	724
NYX	0:85b3fd62ea1a	725	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
NYX	0:85b3fd62ea1a	726	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
NYX	0:85b3fd62ea1a	727
NYX	0:85b3fd62ea1a	728	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
NYX	0:85b3fd62ea1a	729	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
NYX	0:85b3fd62ea1a	730
NYX	0:85b3fd62ea1a	731	/@} end of group CMSIS_SysTick /
NYX	0:85b3fd62ea1a	732
NYX	0:85b3fd62ea1a	733
NYX	0:85b3fd62ea1a	734	/**
NYX	0:85b3fd62ea1a	735	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	736	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
NYX	0:85b3fd62ea1a	737	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
NYX	0:85b3fd62ea1a	738	@{
NYX	0:85b3fd62ea1a	739	*/
NYX	0:85b3fd62ea1a	740
NYX	0:85b3fd62ea1a	741	/**
NYX	0:85b3fd62ea1a	742	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
NYX	0:85b3fd62ea1a	743	*/
NYX	0:85b3fd62ea1a	744	typedef struct
NYX	0:85b3fd62ea1a	745	{
NYX	0:85b3fd62ea1a	746	__OM union
NYX	0:85b3fd62ea1a	747	{
NYX	0:85b3fd62ea1a	748	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
NYX	0:85b3fd62ea1a	749	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
NYX	0:85b3fd62ea1a	750	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
NYX	0:85b3fd62ea1a	751	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
NYX	0:85b3fd62ea1a	752	uint32_t RESERVED0[864U];
NYX	0:85b3fd62ea1a	753	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
NYX	0:85b3fd62ea1a	754	uint32_t RESERVED1[15U];
NYX	0:85b3fd62ea1a	755	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
NYX	0:85b3fd62ea1a	756	uint32_t RESERVED2[15U];
NYX	0:85b3fd62ea1a	757	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
NYX	0:85b3fd62ea1a	758	uint32_t RESERVED3[29U];
NYX	0:85b3fd62ea1a	759	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
NYX	0:85b3fd62ea1a	760	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
NYX	0:85b3fd62ea1a	761	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
NYX	0:85b3fd62ea1a	762	uint32_t RESERVED4[43U];
NYX	0:85b3fd62ea1a	763	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
NYX	0:85b3fd62ea1a	764	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
NYX	0:85b3fd62ea1a	765	uint32_t RESERVED5[6U];
NYX	0:85b3fd62ea1a	766	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
NYX	0:85b3fd62ea1a	767	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
NYX	0:85b3fd62ea1a	768	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
NYX	0:85b3fd62ea1a	769	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
NYX	0:85b3fd62ea1a	770	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
NYX	0:85b3fd62ea1a	771	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
NYX	0:85b3fd62ea1a	772	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
NYX	0:85b3fd62ea1a	773	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
NYX	0:85b3fd62ea1a	774	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
NYX	0:85b3fd62ea1a	775	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
NYX	0:85b3fd62ea1a	776	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
NYX	0:85b3fd62ea1a	777	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
NYX	0:85b3fd62ea1a	778	} ITM_Type;
NYX	0:85b3fd62ea1a	779
NYX	0:85b3fd62ea1a	780	/* ITM Trace Privilege Register Definitions */
NYX	0:85b3fd62ea1a	781	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
NYX	0:85b3fd62ea1a	782	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
NYX	0:85b3fd62ea1a	783
NYX	0:85b3fd62ea1a	784	/* ITM Trace Control Register Definitions */
NYX	0:85b3fd62ea1a	785	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
NYX	0:85b3fd62ea1a	786	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
NYX	0:85b3fd62ea1a	787
NYX	0:85b3fd62ea1a	788	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
NYX	0:85b3fd62ea1a	789	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
NYX	0:85b3fd62ea1a	790
NYX	0:85b3fd62ea1a	791	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
NYX	0:85b3fd62ea1a	792	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
NYX	0:85b3fd62ea1a	793
NYX	0:85b3fd62ea1a	794	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
NYX	0:85b3fd62ea1a	795	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
NYX	0:85b3fd62ea1a	796
NYX	0:85b3fd62ea1a	797	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
NYX	0:85b3fd62ea1a	798	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
NYX	0:85b3fd62ea1a	799
NYX	0:85b3fd62ea1a	800	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
NYX	0:85b3fd62ea1a	801	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
NYX	0:85b3fd62ea1a	802
NYX	0:85b3fd62ea1a	803	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
NYX	0:85b3fd62ea1a	804	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
NYX	0:85b3fd62ea1a	805
NYX	0:85b3fd62ea1a	806	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
NYX	0:85b3fd62ea1a	807	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
NYX	0:85b3fd62ea1a	808
NYX	0:85b3fd62ea1a	809	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
NYX	0:85b3fd62ea1a	810	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
NYX	0:85b3fd62ea1a	811
NYX	0:85b3fd62ea1a	812	/* ITM Integration Write Register Definitions */
NYX	0:85b3fd62ea1a	813	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
NYX	0:85b3fd62ea1a	814	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
NYX	0:85b3fd62ea1a	815
NYX	0:85b3fd62ea1a	816	/* ITM Integration Read Register Definitions */
NYX	0:85b3fd62ea1a	817	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
NYX	0:85b3fd62ea1a	818	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
NYX	0:85b3fd62ea1a	819
NYX	0:85b3fd62ea1a	820	/* ITM Integration Mode Control Register Definitions */
NYX	0:85b3fd62ea1a	821	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
NYX	0:85b3fd62ea1a	822	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
NYX	0:85b3fd62ea1a	823
NYX	0:85b3fd62ea1a	824	/* ITM Lock Status Register Definitions */
NYX	0:85b3fd62ea1a	825	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
NYX	0:85b3fd62ea1a	826	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
NYX	0:85b3fd62ea1a	827
NYX	0:85b3fd62ea1a	828	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
NYX	0:85b3fd62ea1a	829	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
NYX	0:85b3fd62ea1a	830
NYX	0:85b3fd62ea1a	831	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
NYX	0:85b3fd62ea1a	832	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
NYX	0:85b3fd62ea1a	833
NYX	0:85b3fd62ea1a	834	/@}/ /* end of group CMSIS_ITM */
NYX	0:85b3fd62ea1a	835
NYX	0:85b3fd62ea1a	836
NYX	0:85b3fd62ea1a	837	/**
NYX	0:85b3fd62ea1a	838	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	839	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
NYX	0:85b3fd62ea1a	840	\brief Type definitions for the Data Watchpoint and Trace (DWT)
NYX	0:85b3fd62ea1a	841	@{
NYX	0:85b3fd62ea1a	842	*/
NYX	0:85b3fd62ea1a	843
NYX	0:85b3fd62ea1a	844	/**
NYX	0:85b3fd62ea1a	845	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
NYX	0:85b3fd62ea1a	846	*/
NYX	0:85b3fd62ea1a	847	typedef struct
NYX	0:85b3fd62ea1a	848	{
NYX	0:85b3fd62ea1a	849	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
NYX	0:85b3fd62ea1a	850	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
NYX	0:85b3fd62ea1a	851	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
NYX	0:85b3fd62ea1a	852	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
NYX	0:85b3fd62ea1a	853	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
NYX	0:85b3fd62ea1a	854	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
NYX	0:85b3fd62ea1a	855	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
NYX	0:85b3fd62ea1a	856	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
NYX	0:85b3fd62ea1a	857	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
NYX	0:85b3fd62ea1a	858	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
NYX	0:85b3fd62ea1a	859	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
NYX	0:85b3fd62ea1a	860	uint32_t RESERVED0[1U];
NYX	0:85b3fd62ea1a	861	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
NYX	0:85b3fd62ea1a	862	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
NYX	0:85b3fd62ea1a	863	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
NYX	0:85b3fd62ea1a	864	uint32_t RESERVED1[1U];
NYX	0:85b3fd62ea1a	865	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
NYX	0:85b3fd62ea1a	866	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
NYX	0:85b3fd62ea1a	867	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
NYX	0:85b3fd62ea1a	868	uint32_t RESERVED2[1U];
NYX	0:85b3fd62ea1a	869	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
NYX	0:85b3fd62ea1a	870	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
NYX	0:85b3fd62ea1a	871	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
NYX	0:85b3fd62ea1a	872	} DWT_Type;
NYX	0:85b3fd62ea1a	873
NYX	0:85b3fd62ea1a	874	/* DWT Control Register Definitions */
NYX	0:85b3fd62ea1a	875	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
NYX	0:85b3fd62ea1a	876	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
NYX	0:85b3fd62ea1a	877
NYX	0:85b3fd62ea1a	878	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
NYX	0:85b3fd62ea1a	879	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
NYX	0:85b3fd62ea1a	880
NYX	0:85b3fd62ea1a	881	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
NYX	0:85b3fd62ea1a	882	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
NYX	0:85b3fd62ea1a	883
NYX	0:85b3fd62ea1a	884	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
NYX	0:85b3fd62ea1a	885	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
NYX	0:85b3fd62ea1a	886
NYX	0:85b3fd62ea1a	887	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
NYX	0:85b3fd62ea1a	888	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
NYX	0:85b3fd62ea1a	889
NYX	0:85b3fd62ea1a	890	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
NYX	0:85b3fd62ea1a	891	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
NYX	0:85b3fd62ea1a	892
NYX	0:85b3fd62ea1a	893	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
NYX	0:85b3fd62ea1a	894	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
NYX	0:85b3fd62ea1a	895
NYX	0:85b3fd62ea1a	896	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
NYX	0:85b3fd62ea1a	897	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
NYX	0:85b3fd62ea1a	898
NYX	0:85b3fd62ea1a	899	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
NYX	0:85b3fd62ea1a	900	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
NYX	0:85b3fd62ea1a	901
NYX	0:85b3fd62ea1a	902	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
NYX	0:85b3fd62ea1a	903	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
NYX	0:85b3fd62ea1a	904
NYX	0:85b3fd62ea1a	905	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
NYX	0:85b3fd62ea1a	906	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
NYX	0:85b3fd62ea1a	907
NYX	0:85b3fd62ea1a	908	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
NYX	0:85b3fd62ea1a	909	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
NYX	0:85b3fd62ea1a	910
NYX	0:85b3fd62ea1a	911	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
NYX	0:85b3fd62ea1a	912	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
NYX	0:85b3fd62ea1a	913
NYX	0:85b3fd62ea1a	914	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
NYX	0:85b3fd62ea1a	915	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
NYX	0:85b3fd62ea1a	916
NYX	0:85b3fd62ea1a	917	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
NYX	0:85b3fd62ea1a	918	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
NYX	0:85b3fd62ea1a	919
NYX	0:85b3fd62ea1a	920	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
NYX	0:85b3fd62ea1a	921	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
NYX	0:85b3fd62ea1a	922
NYX	0:85b3fd62ea1a	923	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
NYX	0:85b3fd62ea1a	924	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
NYX	0:85b3fd62ea1a	925
NYX	0:85b3fd62ea1a	926	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
NYX	0:85b3fd62ea1a	927	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
NYX	0:85b3fd62ea1a	928
NYX	0:85b3fd62ea1a	929	/* DWT CPI Count Register Definitions */
NYX	0:85b3fd62ea1a	930	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
NYX	0:85b3fd62ea1a	931	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
NYX	0:85b3fd62ea1a	932
NYX	0:85b3fd62ea1a	933	/* DWT Exception Overhead Count Register Definitions */
NYX	0:85b3fd62ea1a	934	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
NYX	0:85b3fd62ea1a	935	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
NYX	0:85b3fd62ea1a	936
NYX	0:85b3fd62ea1a	937	/* DWT Sleep Count Register Definitions */
NYX	0:85b3fd62ea1a	938	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
NYX	0:85b3fd62ea1a	939	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
NYX	0:85b3fd62ea1a	940
NYX	0:85b3fd62ea1a	941	/* DWT LSU Count Register Definitions */
NYX	0:85b3fd62ea1a	942	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
NYX	0:85b3fd62ea1a	943	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
NYX	0:85b3fd62ea1a	944
NYX	0:85b3fd62ea1a	945	/* DWT Folded-instruction Count Register Definitions */
NYX	0:85b3fd62ea1a	946	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
NYX	0:85b3fd62ea1a	947	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
NYX	0:85b3fd62ea1a	948
NYX	0:85b3fd62ea1a	949	/* DWT Comparator Mask Register Definitions */
NYX	0:85b3fd62ea1a	950	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
NYX	0:85b3fd62ea1a	951	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
NYX	0:85b3fd62ea1a	952
NYX	0:85b3fd62ea1a	953	/* DWT Comparator Function Register Definitions */
NYX	0:85b3fd62ea1a	954	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
NYX	0:85b3fd62ea1a	955	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
NYX	0:85b3fd62ea1a	956
NYX	0:85b3fd62ea1a	957	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
NYX	0:85b3fd62ea1a	958	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
NYX	0:85b3fd62ea1a	959
NYX	0:85b3fd62ea1a	960	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
NYX	0:85b3fd62ea1a	961	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
NYX	0:85b3fd62ea1a	962
NYX	0:85b3fd62ea1a	963	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
NYX	0:85b3fd62ea1a	964	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
NYX	0:85b3fd62ea1a	965
NYX	0:85b3fd62ea1a	966	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
NYX	0:85b3fd62ea1a	967	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
NYX	0:85b3fd62ea1a	968
NYX	0:85b3fd62ea1a	969	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
NYX	0:85b3fd62ea1a	970	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
NYX	0:85b3fd62ea1a	971
NYX	0:85b3fd62ea1a	972	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
NYX	0:85b3fd62ea1a	973	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
NYX	0:85b3fd62ea1a	974
NYX	0:85b3fd62ea1a	975	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
NYX	0:85b3fd62ea1a	976	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
NYX	0:85b3fd62ea1a	977
NYX	0:85b3fd62ea1a	978	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
NYX	0:85b3fd62ea1a	979	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
NYX	0:85b3fd62ea1a	980
NYX	0:85b3fd62ea1a	981	/@}/ /* end of group CMSIS_DWT */
NYX	0:85b3fd62ea1a	982
NYX	0:85b3fd62ea1a	983
NYX	0:85b3fd62ea1a	984	/**
NYX	0:85b3fd62ea1a	985	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	986	\defgroup CMSIS_TPI Trace Port Interface (TPI)
NYX	0:85b3fd62ea1a	987	\brief Type definitions for the Trace Port Interface (TPI)
NYX	0:85b3fd62ea1a	988	@{
NYX	0:85b3fd62ea1a	989	*/
NYX	0:85b3fd62ea1a	990
NYX	0:85b3fd62ea1a	991	/**
NYX	0:85b3fd62ea1a	992	\brief Structure type to access the Trace Port Interface Register (TPI).
NYX	0:85b3fd62ea1a	993	*/
NYX	0:85b3fd62ea1a	994	typedef struct
NYX	0:85b3fd62ea1a	995	{
NYX	0:85b3fd62ea1a	996	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
NYX	0:85b3fd62ea1a	997	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
NYX	0:85b3fd62ea1a	998	uint32_t RESERVED0[2U];
NYX	0:85b3fd62ea1a	999	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
NYX	0:85b3fd62ea1a	1000	uint32_t RESERVED1[55U];
NYX	0:85b3fd62ea1a	1001	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
NYX	0:85b3fd62ea1a	1002	uint32_t RESERVED2[131U];
NYX	0:85b3fd62ea1a	1003	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
NYX	0:85b3fd62ea1a	1004	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
NYX	0:85b3fd62ea1a	1005	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
NYX	0:85b3fd62ea1a	1006	uint32_t RESERVED3[759U];
NYX	0:85b3fd62ea1a	1007	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
NYX	0:85b3fd62ea1a	1008	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
NYX	0:85b3fd62ea1a	1009	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
NYX	0:85b3fd62ea1a	1010	uint32_t RESERVED4[1U];
NYX	0:85b3fd62ea1a	1011	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
NYX	0:85b3fd62ea1a	1012	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
NYX	0:85b3fd62ea1a	1013	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
NYX	0:85b3fd62ea1a	1014	uint32_t RESERVED5[39U];
NYX	0:85b3fd62ea1a	1015	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
NYX	0:85b3fd62ea1a	1016	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
NYX	0:85b3fd62ea1a	1017	uint32_t RESERVED7[8U];
NYX	0:85b3fd62ea1a	1018	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
NYX	0:85b3fd62ea1a	1019	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
NYX	0:85b3fd62ea1a	1020	} TPI_Type;
NYX	0:85b3fd62ea1a	1021
NYX	0:85b3fd62ea1a	1022	/* TPI Asynchronous Clock Prescaler Register Definitions */
NYX	0:85b3fd62ea1a	1023	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
NYX	0:85b3fd62ea1a	1024	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
NYX	0:85b3fd62ea1a	1025
NYX	0:85b3fd62ea1a	1026	/* TPI Selected Pin Protocol Register Definitions */
NYX	0:85b3fd62ea1a	1027	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
NYX	0:85b3fd62ea1a	1028	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
NYX	0:85b3fd62ea1a	1029
NYX	0:85b3fd62ea1a	1030	/* TPI Formatter and Flush Status Register Definitions */
NYX	0:85b3fd62ea1a	1031	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
NYX	0:85b3fd62ea1a	1032	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
NYX	0:85b3fd62ea1a	1033
NYX	0:85b3fd62ea1a	1034	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
NYX	0:85b3fd62ea1a	1035	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
NYX	0:85b3fd62ea1a	1036
NYX	0:85b3fd62ea1a	1037	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
NYX	0:85b3fd62ea1a	1038	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
NYX	0:85b3fd62ea1a	1039
NYX	0:85b3fd62ea1a	1040	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
NYX	0:85b3fd62ea1a	1041	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
NYX	0:85b3fd62ea1a	1042
NYX	0:85b3fd62ea1a	1043	/* TPI Formatter and Flush Control Register Definitions */
NYX	0:85b3fd62ea1a	1044	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
NYX	0:85b3fd62ea1a	1045	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
NYX	0:85b3fd62ea1a	1046
NYX	0:85b3fd62ea1a	1047	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
NYX	0:85b3fd62ea1a	1048	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
NYX	0:85b3fd62ea1a	1049
NYX	0:85b3fd62ea1a	1050	/* TPI TRIGGER Register Definitions */
NYX	0:85b3fd62ea1a	1051	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
NYX	0:85b3fd62ea1a	1052	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
NYX	0:85b3fd62ea1a	1053
NYX	0:85b3fd62ea1a	1054	/* TPI Integration ETM Data Register Definitions (FIFO0) */
NYX	0:85b3fd62ea1a	1055	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
NYX	0:85b3fd62ea1a	1056	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1057
NYX	0:85b3fd62ea1a	1058	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
NYX	0:85b3fd62ea1a	1059	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
NYX	0:85b3fd62ea1a	1060
NYX	0:85b3fd62ea1a	1061	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
NYX	0:85b3fd62ea1a	1062	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1063
NYX	0:85b3fd62ea1a	1064	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
NYX	0:85b3fd62ea1a	1065	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
NYX	0:85b3fd62ea1a	1066
NYX	0:85b3fd62ea1a	1067	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
NYX	0:85b3fd62ea1a	1068	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
NYX	0:85b3fd62ea1a	1069
NYX	0:85b3fd62ea1a	1070	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
NYX	0:85b3fd62ea1a	1071	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
NYX	0:85b3fd62ea1a	1072
NYX	0:85b3fd62ea1a	1073	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
NYX	0:85b3fd62ea1a	1074	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
NYX	0:85b3fd62ea1a	1075
NYX	0:85b3fd62ea1a	1076	/* TPI ITATBCTR2 Register Definitions */
NYX	0:85b3fd62ea1a	1077	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
NYX	0:85b3fd62ea1a	1078	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
NYX	0:85b3fd62ea1a	1079
NYX	0:85b3fd62ea1a	1080	/* TPI Integration ITM Data Register Definitions (FIFO1) */
NYX	0:85b3fd62ea1a	1081	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
NYX	0:85b3fd62ea1a	1082	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1083
NYX	0:85b3fd62ea1a	1084	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
NYX	0:85b3fd62ea1a	1085	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
NYX	0:85b3fd62ea1a	1086
NYX	0:85b3fd62ea1a	1087	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
NYX	0:85b3fd62ea1a	1088	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
NYX	0:85b3fd62ea1a	1089
NYX	0:85b3fd62ea1a	1090	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
NYX	0:85b3fd62ea1a	1091	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
NYX	0:85b3fd62ea1a	1092
NYX	0:85b3fd62ea1a	1093	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
NYX	0:85b3fd62ea1a	1094	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
NYX	0:85b3fd62ea1a	1095
NYX	0:85b3fd62ea1a	1096	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
NYX	0:85b3fd62ea1a	1097	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
NYX	0:85b3fd62ea1a	1098
NYX	0:85b3fd62ea1a	1099	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
NYX	0:85b3fd62ea1a	1100	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
NYX	0:85b3fd62ea1a	1101
NYX	0:85b3fd62ea1a	1102	/* TPI ITATBCTR0 Register Definitions */
NYX	0:85b3fd62ea1a	1103	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
NYX	0:85b3fd62ea1a	1104	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
NYX	0:85b3fd62ea1a	1105
NYX	0:85b3fd62ea1a	1106	/* TPI Integration Mode Control Register Definitions */
NYX	0:85b3fd62ea1a	1107	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
NYX	0:85b3fd62ea1a	1108	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
NYX	0:85b3fd62ea1a	1109
NYX	0:85b3fd62ea1a	1110	/* TPI DEVID Register Definitions */
NYX	0:85b3fd62ea1a	1111	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
NYX	0:85b3fd62ea1a	1112	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
NYX	0:85b3fd62ea1a	1113
NYX	0:85b3fd62ea1a	1114	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
NYX	0:85b3fd62ea1a	1115	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
NYX	0:85b3fd62ea1a	1116
NYX	0:85b3fd62ea1a	1117	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
NYX	0:85b3fd62ea1a	1118	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
NYX	0:85b3fd62ea1a	1119
NYX	0:85b3fd62ea1a	1120	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
NYX	0:85b3fd62ea1a	1121	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
NYX	0:85b3fd62ea1a	1122
NYX	0:85b3fd62ea1a	1123	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
NYX	0:85b3fd62ea1a	1124	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
NYX	0:85b3fd62ea1a	1125
NYX	0:85b3fd62ea1a	1126	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
NYX	0:85b3fd62ea1a	1127	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
NYX	0:85b3fd62ea1a	1128
NYX	0:85b3fd62ea1a	1129	/* TPI DEVTYPE Register Definitions */
NYX	0:85b3fd62ea1a	1130	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
NYX	0:85b3fd62ea1a	1131	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
NYX	0:85b3fd62ea1a	1132
NYX	0:85b3fd62ea1a	1133	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
NYX	0:85b3fd62ea1a	1134	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
NYX	0:85b3fd62ea1a	1135
NYX	0:85b3fd62ea1a	1136	/@}/ /* end of group CMSIS_TPI */
NYX	0:85b3fd62ea1a	1137
NYX	0:85b3fd62ea1a	1138
NYX	0:85b3fd62ea1a	1139	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1140	/**
NYX	0:85b3fd62ea1a	1141	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1142	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
NYX	0:85b3fd62ea1a	1143	\brief Type definitions for the Memory Protection Unit (MPU)
NYX	0:85b3fd62ea1a	1144	@{
NYX	0:85b3fd62ea1a	1145	*/
NYX	0:85b3fd62ea1a	1146
NYX	0:85b3fd62ea1a	1147	/**
NYX	0:85b3fd62ea1a	1148	\brief Structure type to access the Memory Protection Unit (MPU).
NYX	0:85b3fd62ea1a	1149	*/
NYX	0:85b3fd62ea1a	1150	typedef struct
NYX	0:85b3fd62ea1a	1151	{
NYX	0:85b3fd62ea1a	1152	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
NYX	0:85b3fd62ea1a	1153	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
NYX	0:85b3fd62ea1a	1154	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
NYX	0:85b3fd62ea1a	1155	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
NYX	0:85b3fd62ea1a	1156	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
NYX	0:85b3fd62ea1a	1157	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
NYX	0:85b3fd62ea1a	1158	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
NYX	0:85b3fd62ea1a	1159	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
NYX	0:85b3fd62ea1a	1160	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
NYX	0:85b3fd62ea1a	1161	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
NYX	0:85b3fd62ea1a	1162	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
NYX	0:85b3fd62ea1a	1163	} MPU_Type;
NYX	0:85b3fd62ea1a	1164
NYX	0:85b3fd62ea1a	1165	/* MPU Type Register Definitions */
NYX	0:85b3fd62ea1a	1166	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
NYX	0:85b3fd62ea1a	1167	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
NYX	0:85b3fd62ea1a	1168
NYX	0:85b3fd62ea1a	1169	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
NYX	0:85b3fd62ea1a	1170	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
NYX	0:85b3fd62ea1a	1171
NYX	0:85b3fd62ea1a	1172	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
NYX	0:85b3fd62ea1a	1173	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
NYX	0:85b3fd62ea1a	1174
NYX	0:85b3fd62ea1a	1175	/* MPU Control Register Definitions */
NYX	0:85b3fd62ea1a	1176	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
NYX	0:85b3fd62ea1a	1177	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
NYX	0:85b3fd62ea1a	1178
NYX	0:85b3fd62ea1a	1179	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
NYX	0:85b3fd62ea1a	1180	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
NYX	0:85b3fd62ea1a	1181
NYX	0:85b3fd62ea1a	1182	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
NYX	0:85b3fd62ea1a	1183	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
NYX	0:85b3fd62ea1a	1184
NYX	0:85b3fd62ea1a	1185	/* MPU Region Number Register Definitions */
NYX	0:85b3fd62ea1a	1186	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
NYX	0:85b3fd62ea1a	1187	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
NYX	0:85b3fd62ea1a	1188
NYX	0:85b3fd62ea1a	1189	/* MPU Region Base Address Register Definitions */
NYX	0:85b3fd62ea1a	1190	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
NYX	0:85b3fd62ea1a	1191	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
NYX	0:85b3fd62ea1a	1192
NYX	0:85b3fd62ea1a	1193	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
NYX	0:85b3fd62ea1a	1194	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
NYX	0:85b3fd62ea1a	1195
NYX	0:85b3fd62ea1a	1196	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
NYX	0:85b3fd62ea1a	1197	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
NYX	0:85b3fd62ea1a	1198
NYX	0:85b3fd62ea1a	1199	/* MPU Region Attribute and Size Register Definitions */
NYX	0:85b3fd62ea1a	1200	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
NYX	0:85b3fd62ea1a	1201	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
NYX	0:85b3fd62ea1a	1202
NYX	0:85b3fd62ea1a	1203	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
NYX	0:85b3fd62ea1a	1204	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
NYX	0:85b3fd62ea1a	1205
NYX	0:85b3fd62ea1a	1206	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
NYX	0:85b3fd62ea1a	1207	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
NYX	0:85b3fd62ea1a	1208
NYX	0:85b3fd62ea1a	1209	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
NYX	0:85b3fd62ea1a	1210	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
NYX	0:85b3fd62ea1a	1211
NYX	0:85b3fd62ea1a	1212	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
NYX	0:85b3fd62ea1a	1213	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
NYX	0:85b3fd62ea1a	1214
NYX	0:85b3fd62ea1a	1215	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
NYX	0:85b3fd62ea1a	1216	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
NYX	0:85b3fd62ea1a	1217
NYX	0:85b3fd62ea1a	1218	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
NYX	0:85b3fd62ea1a	1219	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
NYX	0:85b3fd62ea1a	1220
NYX	0:85b3fd62ea1a	1221	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
NYX	0:85b3fd62ea1a	1222	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
NYX	0:85b3fd62ea1a	1223
NYX	0:85b3fd62ea1a	1224	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
NYX	0:85b3fd62ea1a	1225	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
NYX	0:85b3fd62ea1a	1226
NYX	0:85b3fd62ea1a	1227	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
NYX	0:85b3fd62ea1a	1228	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
NYX	0:85b3fd62ea1a	1229
NYX	0:85b3fd62ea1a	1230	/@} end of group CMSIS_MPU /
NYX	0:85b3fd62ea1a	1231	#endif
NYX	0:85b3fd62ea1a	1232
NYX	0:85b3fd62ea1a	1233
NYX	0:85b3fd62ea1a	1234	/**
NYX	0:85b3fd62ea1a	1235	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1236	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
NYX	0:85b3fd62ea1a	1237	\brief Type definitions for the Core Debug Registers
NYX	0:85b3fd62ea1a	1238	@{
NYX	0:85b3fd62ea1a	1239	*/
NYX	0:85b3fd62ea1a	1240
NYX	0:85b3fd62ea1a	1241	/**
NYX	0:85b3fd62ea1a	1242	\brief Structure type to access the Core Debug Register (CoreDebug).
NYX	0:85b3fd62ea1a	1243	*/
NYX	0:85b3fd62ea1a	1244	typedef struct
NYX	0:85b3fd62ea1a	1245	{
NYX	0:85b3fd62ea1a	1246	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
NYX	0:85b3fd62ea1a	1247	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
NYX	0:85b3fd62ea1a	1248	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
NYX	0:85b3fd62ea1a	1249	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
NYX	0:85b3fd62ea1a	1250	} CoreDebug_Type;
NYX	0:85b3fd62ea1a	1251
NYX	0:85b3fd62ea1a	1252	/* Debug Halting Control and Status Register Definitions */
NYX	0:85b3fd62ea1a	1253	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
NYX	0:85b3fd62ea1a	1254	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
NYX	0:85b3fd62ea1a	1255
NYX	0:85b3fd62ea1a	1256	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
NYX	0:85b3fd62ea1a	1257	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
NYX	0:85b3fd62ea1a	1258
NYX	0:85b3fd62ea1a	1259	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
NYX	0:85b3fd62ea1a	1260	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
NYX	0:85b3fd62ea1a	1261
NYX	0:85b3fd62ea1a	1262	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
NYX	0:85b3fd62ea1a	1263	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
NYX	0:85b3fd62ea1a	1264
NYX	0:85b3fd62ea1a	1265	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
NYX	0:85b3fd62ea1a	1266	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
NYX	0:85b3fd62ea1a	1267
NYX	0:85b3fd62ea1a	1268	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
NYX	0:85b3fd62ea1a	1269	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
NYX	0:85b3fd62ea1a	1270
NYX	0:85b3fd62ea1a	1271	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
NYX	0:85b3fd62ea1a	1272	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
NYX	0:85b3fd62ea1a	1273
NYX	0:85b3fd62ea1a	1274	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
NYX	0:85b3fd62ea1a	1275	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
NYX	0:85b3fd62ea1a	1276
NYX	0:85b3fd62ea1a	1277	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
NYX	0:85b3fd62ea1a	1278	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
NYX	0:85b3fd62ea1a	1279
NYX	0:85b3fd62ea1a	1280	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
NYX	0:85b3fd62ea1a	1281	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
NYX	0:85b3fd62ea1a	1282
NYX	0:85b3fd62ea1a	1283	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
NYX	0:85b3fd62ea1a	1284	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
NYX	0:85b3fd62ea1a	1285
NYX	0:85b3fd62ea1a	1286	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
NYX	0:85b3fd62ea1a	1287	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
NYX	0:85b3fd62ea1a	1288
NYX	0:85b3fd62ea1a	1289	/* Debug Core Register Selector Register Definitions */
NYX	0:85b3fd62ea1a	1290	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
NYX	0:85b3fd62ea1a	1291	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
NYX	0:85b3fd62ea1a	1292
NYX	0:85b3fd62ea1a	1293	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
NYX	0:85b3fd62ea1a	1294	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
NYX	0:85b3fd62ea1a	1295
NYX	0:85b3fd62ea1a	1296	/* Debug Exception and Monitor Control Register Definitions */
NYX	0:85b3fd62ea1a	1297	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
NYX	0:85b3fd62ea1a	1298	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
NYX	0:85b3fd62ea1a	1299
NYX	0:85b3fd62ea1a	1300	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
NYX	0:85b3fd62ea1a	1301	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
NYX	0:85b3fd62ea1a	1302
NYX	0:85b3fd62ea1a	1303	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
NYX	0:85b3fd62ea1a	1304	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
NYX	0:85b3fd62ea1a	1305
NYX	0:85b3fd62ea1a	1306	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
NYX	0:85b3fd62ea1a	1307	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
NYX	0:85b3fd62ea1a	1308
NYX	0:85b3fd62ea1a	1309	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
NYX	0:85b3fd62ea1a	1310	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
NYX	0:85b3fd62ea1a	1311
NYX	0:85b3fd62ea1a	1312	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
NYX	0:85b3fd62ea1a	1313	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
NYX	0:85b3fd62ea1a	1314
NYX	0:85b3fd62ea1a	1315	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
NYX	0:85b3fd62ea1a	1316	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
NYX	0:85b3fd62ea1a	1317
NYX	0:85b3fd62ea1a	1318	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
NYX	0:85b3fd62ea1a	1319	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
NYX	0:85b3fd62ea1a	1320
NYX	0:85b3fd62ea1a	1321	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
NYX	0:85b3fd62ea1a	1322	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
NYX	0:85b3fd62ea1a	1323
NYX	0:85b3fd62ea1a	1324	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
NYX	0:85b3fd62ea1a	1325	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
NYX	0:85b3fd62ea1a	1326
NYX	0:85b3fd62ea1a	1327	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
NYX	0:85b3fd62ea1a	1328	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
NYX	0:85b3fd62ea1a	1329
NYX	0:85b3fd62ea1a	1330	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
NYX	0:85b3fd62ea1a	1331	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
NYX	0:85b3fd62ea1a	1332
NYX	0:85b3fd62ea1a	1333	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
NYX	0:85b3fd62ea1a	1334	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
NYX	0:85b3fd62ea1a	1335
NYX	0:85b3fd62ea1a	1336	/@} end of group CMSIS_CoreDebug /
NYX	0:85b3fd62ea1a	1337
NYX	0:85b3fd62ea1a	1338
NYX	0:85b3fd62ea1a	1339	/**
NYX	0:85b3fd62ea1a	1340	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1341	\defgroup CMSIS_core_bitfield Core register bit field macros
NYX	0:85b3fd62ea1a	1342	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
NYX	0:85b3fd62ea1a	1343	@{
NYX	0:85b3fd62ea1a	1344	*/
NYX	0:85b3fd62ea1a	1345
NYX	0:85b3fd62ea1a	1346	/**
NYX	0:85b3fd62ea1a	1347	\brief Mask and shift a bit field value for use in a register bit range.
NYX	0:85b3fd62ea1a	1348	\param[in] field Name of the register bit field.
NYX	0:85b3fd62ea1a	1349	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
NYX	0:85b3fd62ea1a	1350	\return Masked and shifted value.
NYX	0:85b3fd62ea1a	1351	*/
NYX	0:85b3fd62ea1a	1352	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
NYX	0:85b3fd62ea1a	1353
NYX	0:85b3fd62ea1a	1354	/**
NYX	0:85b3fd62ea1a	1355	\brief Mask and shift a register value to extract a bit filed value.
NYX	0:85b3fd62ea1a	1356	\param[in] field Name of the register bit field.
NYX	0:85b3fd62ea1a	1357	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
NYX	0:85b3fd62ea1a	1358	\return Masked and shifted bit field value.
NYX	0:85b3fd62ea1a	1359	*/
NYX	0:85b3fd62ea1a	1360	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
NYX	0:85b3fd62ea1a	1361
NYX	0:85b3fd62ea1a	1362	/@} end of group CMSIS_core_bitfield /
NYX	0:85b3fd62ea1a	1363
NYX	0:85b3fd62ea1a	1364
NYX	0:85b3fd62ea1a	1365	/**
NYX	0:85b3fd62ea1a	1366	\ingroup CMSIS_core_register
NYX	0:85b3fd62ea1a	1367	\defgroup CMSIS_core_base Core Definitions
NYX	0:85b3fd62ea1a	1368	\brief Definitions for base addresses, unions, and structures.
NYX	0:85b3fd62ea1a	1369	@{
NYX	0:85b3fd62ea1a	1370	*/
NYX	0:85b3fd62ea1a	1371
NYX	0:85b3fd62ea1a	1372	/* Memory mapping of Core Hardware */
NYX	0:85b3fd62ea1a	1373	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
NYX	0:85b3fd62ea1a	1374	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
NYX	0:85b3fd62ea1a	1375	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
NYX	0:85b3fd62ea1a	1376	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
NYX	0:85b3fd62ea1a	1377	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
NYX	0:85b3fd62ea1a	1378	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
NYX	0:85b3fd62ea1a	1379	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
NYX	0:85b3fd62ea1a	1380	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
NYX	0:85b3fd62ea1a	1381
NYX	0:85b3fd62ea1a	1382	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
NYX	0:85b3fd62ea1a	1383	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
NYX	0:85b3fd62ea1a	1384	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
NYX	0:85b3fd62ea1a	1385	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
NYX	0:85b3fd62ea1a	1386	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
NYX	0:85b3fd62ea1a	1387	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
NYX	0:85b3fd62ea1a	1388	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
NYX	0:85b3fd62ea1a	1389	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
NYX	0:85b3fd62ea1a	1390
NYX	0:85b3fd62ea1a	1391	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1392	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
NYX	0:85b3fd62ea1a	1393	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
NYX	0:85b3fd62ea1a	1394	#endif
NYX	0:85b3fd62ea1a	1395
NYX	0:85b3fd62ea1a	1396	/@} /
NYX	0:85b3fd62ea1a	1397
NYX	0:85b3fd62ea1a	1398
NYX	0:85b3fd62ea1a	1399
NYX	0:85b3fd62ea1a	1400	/*******************************************************************************
NYX	0:85b3fd62ea1a	1401	* Hardware Abstraction Layer
NYX	0:85b3fd62ea1a	1402	Core Function Interface contains:
NYX	0:85b3fd62ea1a	1403	- Core NVIC Functions
NYX	0:85b3fd62ea1a	1404	- Core SysTick Functions
NYX	0:85b3fd62ea1a	1405	- Core Debug Functions
NYX	0:85b3fd62ea1a	1406	- Core Register Access Functions
NYX	0:85b3fd62ea1a	1407	******************************************************************************/
NYX	0:85b3fd62ea1a	1408	/**
NYX	0:85b3fd62ea1a	1409	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
NYX	0:85b3fd62ea1a	1410	*/
NYX	0:85b3fd62ea1a	1411
NYX	0:85b3fd62ea1a	1412
NYX	0:85b3fd62ea1a	1413
NYX	0:85b3fd62ea1a	1414	/* ########################## NVIC functions #################################### */
NYX	0:85b3fd62ea1a	1415	/**
NYX	0:85b3fd62ea1a	1416	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	1417	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
NYX	0:85b3fd62ea1a	1418	\brief Functions that manage interrupts and exceptions via the NVIC.
NYX	0:85b3fd62ea1a	1419	@{
NYX	0:85b3fd62ea1a	1420	*/
NYX	0:85b3fd62ea1a	1421
NYX	0:85b3fd62ea1a	1422	#ifdef CMSIS_NVIC_VIRTUAL
NYX	0:85b3fd62ea1a	1423	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	1424	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
NYX	0:85b3fd62ea1a	1425	#endif
NYX	0:85b3fd62ea1a	1426	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	1427	#else
NYX	0:85b3fd62ea1a	1428	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
NYX	0:85b3fd62ea1a	1429	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
NYX	0:85b3fd62ea1a	1430	#define NVIC_EnableIRQ __NVIC_EnableIRQ
NYX	0:85b3fd62ea1a	1431	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
NYX	0:85b3fd62ea1a	1432	#define NVIC_DisableIRQ __NVIC_DisableIRQ
NYX	0:85b3fd62ea1a	1433	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
NYX	0:85b3fd62ea1a	1434	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
NYX	0:85b3fd62ea1a	1435	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
NYX	0:85b3fd62ea1a	1436	#define NVIC_GetActive __NVIC_GetActive
NYX	0:85b3fd62ea1a	1437	#define NVIC_SetPriority __NVIC_SetPriority
NYX	0:85b3fd62ea1a	1438	#define NVIC_GetPriority __NVIC_GetPriority
NYX	0:85b3fd62ea1a	1439	#define NVIC_SystemReset __NVIC_SystemReset
NYX	0:85b3fd62ea1a	1440	#endif /* CMSIS_NVIC_VIRTUAL */
NYX	0:85b3fd62ea1a	1441
NYX	0:85b3fd62ea1a	1442	#ifdef CMSIS_VECTAB_VIRTUAL
NYX	0:85b3fd62ea1a	1443	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	1444	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
NYX	0:85b3fd62ea1a	1445	#endif
NYX	0:85b3fd62ea1a	1446	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX	0:85b3fd62ea1a	1447	#else
NYX	0:85b3fd62ea1a	1448	#define NVIC_SetVector __NVIC_SetVector
NYX	0:85b3fd62ea1a	1449	#define NVIC_GetVector __NVIC_GetVector
NYX	0:85b3fd62ea1a	1450	#endif /* (CMSIS_VECTAB_VIRTUAL) */
NYX	0:85b3fd62ea1a	1451
NYX	0:85b3fd62ea1a	1452	#define NVIC_USER_IRQ_OFFSET 16
NYX	0:85b3fd62ea1a	1453
NYX	0:85b3fd62ea1a	1454
NYX	0:85b3fd62ea1a	1455
NYX	0:85b3fd62ea1a	1456	/**
NYX	0:85b3fd62ea1a	1457	\brief Set Priority Grouping
NYX	0:85b3fd62ea1a	1458	\details Sets the priority grouping field using the required unlock sequence.
NYX	0:85b3fd62ea1a	1459	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
NYX	0:85b3fd62ea1a	1460	Only values from 0..7 are used.
NYX	0:85b3fd62ea1a	1461	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	1462	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	1463	\param [in] PriorityGroup Priority grouping field.
NYX	0:85b3fd62ea1a	1464	*/
NYX	0:85b3fd62ea1a	1465	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
NYX	0:85b3fd62ea1a	1466	{
NYX	0:85b3fd62ea1a	1467	uint32_t reg_value;
NYX	0:85b3fd62ea1a	1468	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	1469
NYX	0:85b3fd62ea1a	1470	reg_value = SCB->AIRCR; /* read old register configuration */
NYX	0:85b3fd62ea1a	1471	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
NYX	0:85b3fd62ea1a	1472	reg_value = (reg_value \|
NYX	0:85b3fd62ea1a	1473	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
NYX	0:85b3fd62ea1a	1474	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
NYX	0:85b3fd62ea1a	1475	SCB->AIRCR = reg_value;
NYX	0:85b3fd62ea1a	1476	}
NYX	0:85b3fd62ea1a	1477
NYX	0:85b3fd62ea1a	1478
NYX	0:85b3fd62ea1a	1479	/**
NYX	0:85b3fd62ea1a	1480	\brief Get Priority Grouping
NYX	0:85b3fd62ea1a	1481	\details Reads the priority grouping field from the NVIC Interrupt Controller.
NYX	0:85b3fd62ea1a	1482	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
NYX	0:85b3fd62ea1a	1483	*/
NYX	0:85b3fd62ea1a	1484	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
NYX	0:85b3fd62ea1a	1485	{
NYX	0:85b3fd62ea1a	1486	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
NYX	0:85b3fd62ea1a	1487	}
NYX	0:85b3fd62ea1a	1488
NYX	0:85b3fd62ea1a	1489
NYX	0:85b3fd62ea1a	1490	/**
NYX	0:85b3fd62ea1a	1491	\brief Enable Interrupt
NYX	0:85b3fd62ea1a	1492	\details Enables a device specific interrupt in the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	1493	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1494	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1495	*/
NYX	0:85b3fd62ea1a	1496	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1497	{
NYX	0:85b3fd62ea1a	1498	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1499	{
NYX	0:85b3fd62ea1a	1500	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	1501	}
NYX	0:85b3fd62ea1a	1502	}
NYX	0:85b3fd62ea1a	1503
NYX	0:85b3fd62ea1a	1504
NYX	0:85b3fd62ea1a	1505	/**
NYX	0:85b3fd62ea1a	1506	\brief Get Interrupt Enable status
NYX	0:85b3fd62ea1a	1507	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	1508	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1509	\return 0 Interrupt is not enabled.
NYX	0:85b3fd62ea1a	1510	\return 1 Interrupt is enabled.
NYX	0:85b3fd62ea1a	1511	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1512	*/
NYX	0:85b3fd62ea1a	1513	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1514	{
NYX	0:85b3fd62ea1a	1515	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1516	{
NYX	0:85b3fd62ea1a	1517	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	1518	}
NYX	0:85b3fd62ea1a	1519	else
NYX	0:85b3fd62ea1a	1520	{
NYX	0:85b3fd62ea1a	1521	return(0U);
NYX	0:85b3fd62ea1a	1522	}
NYX	0:85b3fd62ea1a	1523	}
NYX	0:85b3fd62ea1a	1524
NYX	0:85b3fd62ea1a	1525
NYX	0:85b3fd62ea1a	1526	/**
NYX	0:85b3fd62ea1a	1527	\brief Disable Interrupt
NYX	0:85b3fd62ea1a	1528	\details Disables a device specific interrupt in the NVIC interrupt controller.
NYX	0:85b3fd62ea1a	1529	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1530	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1531	*/
NYX	0:85b3fd62ea1a	1532	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1533	{
NYX	0:85b3fd62ea1a	1534	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1535	{
NYX	0:85b3fd62ea1a	1536	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	1537	__DSB();
NYX	0:85b3fd62ea1a	1538	__ISB();
NYX	0:85b3fd62ea1a	1539	}
NYX	0:85b3fd62ea1a	1540	}
NYX	0:85b3fd62ea1a	1541
NYX	0:85b3fd62ea1a	1542
NYX	0:85b3fd62ea1a	1543	/**
NYX	0:85b3fd62ea1a	1544	\brief Get Pending Interrupt
NYX	0:85b3fd62ea1a	1545	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
NYX	0:85b3fd62ea1a	1546	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1547	\return 0 Interrupt status is not pending.
NYX	0:85b3fd62ea1a	1548	\return 1 Interrupt status is pending.
NYX	0:85b3fd62ea1a	1549	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1550	*/
NYX	0:85b3fd62ea1a	1551	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1552	{
NYX	0:85b3fd62ea1a	1553	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1554	{
NYX	0:85b3fd62ea1a	1555	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	1556	}
NYX	0:85b3fd62ea1a	1557	else
NYX	0:85b3fd62ea1a	1558	{
NYX	0:85b3fd62ea1a	1559	return(0U);
NYX	0:85b3fd62ea1a	1560	}
NYX	0:85b3fd62ea1a	1561	}
NYX	0:85b3fd62ea1a	1562
NYX	0:85b3fd62ea1a	1563
NYX	0:85b3fd62ea1a	1564	/**
NYX	0:85b3fd62ea1a	1565	\brief Set Pending Interrupt
NYX	0:85b3fd62ea1a	1566	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
NYX	0:85b3fd62ea1a	1567	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1568	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1569	*/
NYX	0:85b3fd62ea1a	1570	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1571	{
NYX	0:85b3fd62ea1a	1572	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1573	{
NYX	0:85b3fd62ea1a	1574	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	1575	}
NYX	0:85b3fd62ea1a	1576	}
NYX	0:85b3fd62ea1a	1577
NYX	0:85b3fd62ea1a	1578
NYX	0:85b3fd62ea1a	1579	/**
NYX	0:85b3fd62ea1a	1580	\brief Clear Pending Interrupt
NYX	0:85b3fd62ea1a	1581	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
NYX	0:85b3fd62ea1a	1582	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1583	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1584	*/
NYX	0:85b3fd62ea1a	1585	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1586	{
NYX	0:85b3fd62ea1a	1587	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1588	{
NYX	0:85b3fd62ea1a	1589	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX	0:85b3fd62ea1a	1590	}
NYX	0:85b3fd62ea1a	1591	}
NYX	0:85b3fd62ea1a	1592
NYX	0:85b3fd62ea1a	1593
NYX	0:85b3fd62ea1a	1594	/**
NYX	0:85b3fd62ea1a	1595	\brief Get Active Interrupt
NYX	0:85b3fd62ea1a	1596	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
NYX	0:85b3fd62ea1a	1597	\param [in] IRQn Device specific interrupt number.
NYX	0:85b3fd62ea1a	1598	\return 0 Interrupt status is not active.
NYX	0:85b3fd62ea1a	1599	\return 1 Interrupt status is active.
NYX	0:85b3fd62ea1a	1600	\note IRQn must not be negative.
NYX	0:85b3fd62ea1a	1601	*/
NYX	0:85b3fd62ea1a	1602	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1603	{
NYX	0:85b3fd62ea1a	1604	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1605	{
NYX	0:85b3fd62ea1a	1606	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX	0:85b3fd62ea1a	1607	}
NYX	0:85b3fd62ea1a	1608	else
NYX	0:85b3fd62ea1a	1609	{
NYX	0:85b3fd62ea1a	1610	return(0U);
NYX	0:85b3fd62ea1a	1611	}
NYX	0:85b3fd62ea1a	1612	}
NYX	0:85b3fd62ea1a	1613
NYX	0:85b3fd62ea1a	1614
NYX	0:85b3fd62ea1a	1615	/**
NYX	0:85b3fd62ea1a	1616	\brief Set Interrupt Priority
NYX	0:85b3fd62ea1a	1617	\details Sets the priority of a device specific interrupt or a processor exception.
NYX	0:85b3fd62ea1a	1618	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	1619	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	1620	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	1621	\param [in] priority Priority to set.
NYX	0:85b3fd62ea1a	1622	\note The priority cannot be set for every processor exception.
NYX	0:85b3fd62ea1a	1623	*/
NYX	0:85b3fd62ea1a	1624	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
NYX	0:85b3fd62ea1a	1625	{
NYX	0:85b3fd62ea1a	1626	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1627	{
NYX	0:85b3fd62ea1a	1628	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
NYX	0:85b3fd62ea1a	1629	}
NYX	0:85b3fd62ea1a	1630	else
NYX	0:85b3fd62ea1a	1631	{
NYX	0:85b3fd62ea1a	1632	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
NYX	0:85b3fd62ea1a	1633	}
NYX	0:85b3fd62ea1a	1634	}
NYX	0:85b3fd62ea1a	1635
NYX	0:85b3fd62ea1a	1636
NYX	0:85b3fd62ea1a	1637	/**
NYX	0:85b3fd62ea1a	1638	\brief Get Interrupt Priority
NYX	0:85b3fd62ea1a	1639	\details Reads the priority of a device specific interrupt or a processor exception.
NYX	0:85b3fd62ea1a	1640	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	1641	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	1642	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	1643	\return Interrupt Priority.
NYX	0:85b3fd62ea1a	1644	Value is aligned automatically to the implemented priority bits of the microcontroller.
NYX	0:85b3fd62ea1a	1645	*/
NYX	0:85b3fd62ea1a	1646	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1647	{
NYX	0:85b3fd62ea1a	1648
NYX	0:85b3fd62ea1a	1649	if ((int32_t)(IRQn) >= 0)
NYX	0:85b3fd62ea1a	1650	{
NYX	0:85b3fd62ea1a	1651	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
NYX	0:85b3fd62ea1a	1652	}
NYX	0:85b3fd62ea1a	1653	else
NYX	0:85b3fd62ea1a	1654	{
NYX	0:85b3fd62ea1a	1655	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
NYX	0:85b3fd62ea1a	1656	}
NYX	0:85b3fd62ea1a	1657	}
NYX	0:85b3fd62ea1a	1658
NYX	0:85b3fd62ea1a	1659
NYX	0:85b3fd62ea1a	1660	/**
NYX	0:85b3fd62ea1a	1661	\brief Encode Priority
NYX	0:85b3fd62ea1a	1662	\details Encodes the priority for an interrupt with the given priority group,
NYX	0:85b3fd62ea1a	1663	preemptive priority value, and subpriority value.
NYX	0:85b3fd62ea1a	1664	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	1665	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	1666	\param [in] PriorityGroup Used priority group.
NYX	0:85b3fd62ea1a	1667	\param [in] PreemptPriority Preemptive priority value (starting from 0).
NYX	0:85b3fd62ea1a	1668	\param [in] SubPriority Subpriority value (starting from 0).
NYX	0:85b3fd62ea1a	1669	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
NYX	0:85b3fd62ea1a	1670	*/
NYX	0:85b3fd62ea1a	1671	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
NYX	0:85b3fd62ea1a	1672	{
NYX	0:85b3fd62ea1a	1673	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	1674	uint32_t PreemptPriorityBits;
NYX	0:85b3fd62ea1a	1675	uint32_t SubPriorityBits;
NYX	0:85b3fd62ea1a	1676
NYX	0:85b3fd62ea1a	1677	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
NYX	0:85b3fd62ea1a	1678	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
NYX	0:85b3fd62ea1a	1679
NYX	0:85b3fd62ea1a	1680	return (
NYX	0:85b3fd62ea1a	1681	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
NYX	0:85b3fd62ea1a	1682	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
NYX	0:85b3fd62ea1a	1683	);
NYX	0:85b3fd62ea1a	1684	}
NYX	0:85b3fd62ea1a	1685
NYX	0:85b3fd62ea1a	1686
NYX	0:85b3fd62ea1a	1687	/**
NYX	0:85b3fd62ea1a	1688	\brief Decode Priority
NYX	0:85b3fd62ea1a	1689	\details Decodes an interrupt priority value with a given priority group to
NYX	0:85b3fd62ea1a	1690	preemptive priority value and subpriority value.
NYX	0:85b3fd62ea1a	1691	In case of a conflict between priority grouping and available
NYX	0:85b3fd62ea1a	1692	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
NYX	0:85b3fd62ea1a	1693	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
NYX	0:85b3fd62ea1a	1694	\param [in] PriorityGroup Used priority group.
NYX	0:85b3fd62ea1a	1695	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
NYX	0:85b3fd62ea1a	1696	\param [out] pSubPriority Subpriority value (starting from 0).
NYX	0:85b3fd62ea1a	1697	*/
NYX	0:85b3fd62ea1a	1698	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
NYX	0:85b3fd62ea1a	1699	{
NYX	0:85b3fd62ea1a	1700	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
NYX	0:85b3fd62ea1a	1701	uint32_t PreemptPriorityBits;
NYX	0:85b3fd62ea1a	1702	uint32_t SubPriorityBits;
NYX	0:85b3fd62ea1a	1703
NYX	0:85b3fd62ea1a	1704	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
NYX	0:85b3fd62ea1a	1705	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
NYX	0:85b3fd62ea1a	1706
NYX	0:85b3fd62ea1a	1707	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
NYX	0:85b3fd62ea1a	1708	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
NYX	0:85b3fd62ea1a	1709	}
NYX	0:85b3fd62ea1a	1710
NYX	0:85b3fd62ea1a	1711
NYX	0:85b3fd62ea1a	1712	/**
NYX	0:85b3fd62ea1a	1713	\brief Set Interrupt Vector
NYX	0:85b3fd62ea1a	1714	\details Sets an interrupt vector in SRAM based interrupt vector table.
NYX	0:85b3fd62ea1a	1715	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	1716	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	1717	VTOR must been relocated to SRAM before.
NYX	0:85b3fd62ea1a	1718	\param [in] IRQn Interrupt number
NYX	0:85b3fd62ea1a	1719	\param [in] vector Address of interrupt handler function
NYX	0:85b3fd62ea1a	1720	*/
NYX	0:85b3fd62ea1a	1721	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
NYX	0:85b3fd62ea1a	1722	{
NYX	0:85b3fd62ea1a	1723	uint32_t vectors = (uint32_t )SCB->VTOR;
NYX	0:85b3fd62ea1a	1724	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
NYX	0:85b3fd62ea1a	1725	}
NYX	0:85b3fd62ea1a	1726
NYX	0:85b3fd62ea1a	1727
NYX	0:85b3fd62ea1a	1728	/**
NYX	0:85b3fd62ea1a	1729	\brief Get Interrupt Vector
NYX	0:85b3fd62ea1a	1730	\details Reads an interrupt vector from interrupt vector table.
NYX	0:85b3fd62ea1a	1731	The interrupt number can be positive to specify a device specific interrupt,
NYX	0:85b3fd62ea1a	1732	or negative to specify a processor exception.
NYX	0:85b3fd62ea1a	1733	\param [in] IRQn Interrupt number.
NYX	0:85b3fd62ea1a	1734	\return Address of interrupt handler function
NYX	0:85b3fd62ea1a	1735	*/
NYX	0:85b3fd62ea1a	1736	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	1737	{
NYX	0:85b3fd62ea1a	1738	uint32_t vectors = (uint32_t )SCB->VTOR;
NYX	0:85b3fd62ea1a	1739	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
NYX	0:85b3fd62ea1a	1740	}
NYX	0:85b3fd62ea1a	1741
NYX	0:85b3fd62ea1a	1742
NYX	0:85b3fd62ea1a	1743	/**
NYX	0:85b3fd62ea1a	1744	\brief System Reset
NYX	0:85b3fd62ea1a	1745	\details Initiates a system reset request to reset the MCU.
NYX	0:85b3fd62ea1a	1746	*/
NYX	0:85b3fd62ea1a	1747	__STATIC_INLINE void __NVIC_SystemReset(void)
NYX	0:85b3fd62ea1a	1748	{
NYX	0:85b3fd62ea1a	1749	__DSB(); /* Ensure all outstanding memory accesses included
NYX	0:85b3fd62ea1a	1750	buffered write are completed before reset */
NYX	0:85b3fd62ea1a	1751	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
NYX	0:85b3fd62ea1a	1752	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
NYX	0:85b3fd62ea1a	1753	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
NYX	0:85b3fd62ea1a	1754	__DSB(); /* Ensure completion of memory access */
NYX	0:85b3fd62ea1a	1755
NYX	0:85b3fd62ea1a	1756	for(;;) /* wait until reset */
NYX	0:85b3fd62ea1a	1757	{
NYX	0:85b3fd62ea1a	1758	__NOP();
NYX	0:85b3fd62ea1a	1759	}
NYX	0:85b3fd62ea1a	1760	}
NYX	0:85b3fd62ea1a	1761
NYX	0:85b3fd62ea1a	1762	/@} end of CMSIS_Core_NVICFunctions /
NYX	0:85b3fd62ea1a	1763
NYX	0:85b3fd62ea1a	1764
NYX	0:85b3fd62ea1a	1765	/* ########################## FPU functions #################################### */
NYX	0:85b3fd62ea1a	1766	/**
NYX	0:85b3fd62ea1a	1767	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	1768	\defgroup CMSIS_Core_FpuFunctions FPU Functions
NYX	0:85b3fd62ea1a	1769	\brief Function that provides FPU type.
NYX	0:85b3fd62ea1a	1770	@{
NYX	0:85b3fd62ea1a	1771	*/
NYX	0:85b3fd62ea1a	1772
NYX	0:85b3fd62ea1a	1773	/**
NYX	0:85b3fd62ea1a	1774	\brief get FPU type
NYX	0:85b3fd62ea1a	1775	\details returns the FPU type
NYX	0:85b3fd62ea1a	1776	\returns
NYX	0:85b3fd62ea1a	1777	- \b 0: No FPU
NYX	0:85b3fd62ea1a	1778	- \b 1: Single precision FPU
NYX	0:85b3fd62ea1a	1779	- \b 2: Double + Single precision FPU
NYX	0:85b3fd62ea1a	1780	*/
NYX	0:85b3fd62ea1a	1781	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
NYX	0:85b3fd62ea1a	1782	{
NYX	0:85b3fd62ea1a	1783	return 0U; /* No FPU */
NYX	0:85b3fd62ea1a	1784	}
NYX	0:85b3fd62ea1a	1785
NYX	0:85b3fd62ea1a	1786
NYX	0:85b3fd62ea1a	1787	/@} end of CMSIS_Core_FpuFunctions /
NYX	0:85b3fd62ea1a	1788
NYX	0:85b3fd62ea1a	1789
NYX	0:85b3fd62ea1a	1790
NYX	0:85b3fd62ea1a	1791	/* ################################## SysTick function ############################################ */
NYX	0:85b3fd62ea1a	1792	/**
NYX	0:85b3fd62ea1a	1793	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	1794	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
NYX	0:85b3fd62ea1a	1795	\brief Functions that configure the System.
NYX	0:85b3fd62ea1a	1796	@{
NYX	0:85b3fd62ea1a	1797	*/
NYX	0:85b3fd62ea1a	1798
NYX	0:85b3fd62ea1a	1799	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
NYX	0:85b3fd62ea1a	1800
NYX	0:85b3fd62ea1a	1801	/**
NYX	0:85b3fd62ea1a	1802	\brief System Tick Configuration
NYX	0:85b3fd62ea1a	1803	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
NYX	0:85b3fd62ea1a	1804	Counter is in free running mode to generate periodic interrupts.
NYX	0:85b3fd62ea1a	1805	\param [in] ticks Number of ticks between two interrupts.
NYX	0:85b3fd62ea1a	1806	\return 0 Function succeeded.
NYX	0:85b3fd62ea1a	1807	\return 1 Function failed.
NYX	0:85b3fd62ea1a	1808	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
NYX	0:85b3fd62ea1a	1809	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
NYX	0:85b3fd62ea1a	1810	must contain a vendor-specific implementation of this function.
NYX	0:85b3fd62ea1a	1811	*/
NYX	0:85b3fd62ea1a	1812	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
NYX	0:85b3fd62ea1a	1813	{
NYX	0:85b3fd62ea1a	1814	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
NYX	0:85b3fd62ea1a	1815	{
NYX	0:85b3fd62ea1a	1816	return (1UL); /* Reload value impossible */
NYX	0:85b3fd62ea1a	1817	}
NYX	0:85b3fd62ea1a	1818
NYX	0:85b3fd62ea1a	1819	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NYX	0:85b3fd62ea1a	1820	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
NYX	0:85b3fd62ea1a	1821	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NYX	0:85b3fd62ea1a	1822	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
NYX	0:85b3fd62ea1a	1823	SysTick_CTRL_TICKINT_Msk \|
NYX	0:85b3fd62ea1a	1824	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
NYX	0:85b3fd62ea1a	1825	return (0UL); /* Function successful */
NYX	0:85b3fd62ea1a	1826	}
NYX	0:85b3fd62ea1a	1827
NYX	0:85b3fd62ea1a	1828	#endif
NYX	0:85b3fd62ea1a	1829
NYX	0:85b3fd62ea1a	1830	/@} end of CMSIS_Core_SysTickFunctions /
NYX	0:85b3fd62ea1a	1831
NYX	0:85b3fd62ea1a	1832
NYX	0:85b3fd62ea1a	1833
NYX	0:85b3fd62ea1a	1834	/* ##################################### Debug In/Output function ########################################### */
NYX	0:85b3fd62ea1a	1835	/**
NYX	0:85b3fd62ea1a	1836	\ingroup CMSIS_Core_FunctionInterface
NYX	0:85b3fd62ea1a	1837	\defgroup CMSIS_core_DebugFunctions ITM Functions
NYX	0:85b3fd62ea1a	1838	\brief Functions that access the ITM debug interface.
NYX	0:85b3fd62ea1a	1839	@{
NYX	0:85b3fd62ea1a	1840	*/
NYX	0:85b3fd62ea1a	1841
NYX	0:85b3fd62ea1a	1842	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
NYX	0:85b3fd62ea1a	1843	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
NYX	0:85b3fd62ea1a	1844
NYX	0:85b3fd62ea1a	1845
NYX	0:85b3fd62ea1a	1846	/**
NYX	0:85b3fd62ea1a	1847	\brief ITM Send Character
NYX	0:85b3fd62ea1a	1848	\details Transmits a character via the ITM channel 0, and
NYX	0:85b3fd62ea1a	1849	\li Just returns when no debugger is connected that has booked the output.
NYX	0:85b3fd62ea1a	1850	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
NYX	0:85b3fd62ea1a	1851	\param [in] ch Character to transmit.
NYX	0:85b3fd62ea1a	1852	\returns Character to transmit.
NYX	0:85b3fd62ea1a	1853	*/
NYX	0:85b3fd62ea1a	1854	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
NYX	0:85b3fd62ea1a	1855	{
NYX	0:85b3fd62ea1a	1856	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
NYX	0:85b3fd62ea1a	1857	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
NYX	0:85b3fd62ea1a	1858	{
NYX	0:85b3fd62ea1a	1859	while (ITM->PORT[0U].u32 == 0UL)
NYX	0:85b3fd62ea1a	1860	{
NYX	0:85b3fd62ea1a	1861	__NOP();
NYX	0:85b3fd62ea1a	1862	}
NYX	0:85b3fd62ea1a	1863	ITM->PORT[0U].u8 = (uint8_t)ch;
NYX	0:85b3fd62ea1a	1864	}
NYX	0:85b3fd62ea1a	1865	return (ch);
NYX	0:85b3fd62ea1a	1866	}
NYX	0:85b3fd62ea1a	1867
NYX	0:85b3fd62ea1a	1868
NYX	0:85b3fd62ea1a	1869	/**
NYX	0:85b3fd62ea1a	1870	\brief ITM Receive Character
NYX	0:85b3fd62ea1a	1871	\details Inputs a character via the external variable \ref ITM_RxBuffer.
NYX	0:85b3fd62ea1a	1872	\return Received character.
NYX	0:85b3fd62ea1a	1873	\return -1 No character pending.
NYX	0:85b3fd62ea1a	1874	*/
NYX	0:85b3fd62ea1a	1875	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
NYX	0:85b3fd62ea1a	1876	{
NYX	0:85b3fd62ea1a	1877	int32_t ch = -1; /* no character available */
NYX	0:85b3fd62ea1a	1878
NYX	0:85b3fd62ea1a	1879	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
NYX	0:85b3fd62ea1a	1880	{
NYX	0:85b3fd62ea1a	1881	ch = ITM_RxBuffer;
NYX	0:85b3fd62ea1a	1882	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
NYX	0:85b3fd62ea1a	1883	}
NYX	0:85b3fd62ea1a	1884
NYX	0:85b3fd62ea1a	1885	return (ch);
NYX	0:85b3fd62ea1a	1886	}
NYX	0:85b3fd62ea1a	1887
NYX	0:85b3fd62ea1a	1888
NYX	0:85b3fd62ea1a	1889	/**
NYX	0:85b3fd62ea1a	1890	\brief ITM Check Character
NYX	0:85b3fd62ea1a	1891	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
NYX	0:85b3fd62ea1a	1892	\return 0 No character available.
NYX	0:85b3fd62ea1a	1893	\return 1 Character available.
NYX	0:85b3fd62ea1a	1894	*/
NYX	0:85b3fd62ea1a	1895	__STATIC_INLINE int32_t ITM_CheckChar (void)
NYX	0:85b3fd62ea1a	1896	{
NYX	0:85b3fd62ea1a	1897
NYX	0:85b3fd62ea1a	1898	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
NYX	0:85b3fd62ea1a	1899	{
NYX	0:85b3fd62ea1a	1900	return (0); /* no character available */
NYX	0:85b3fd62ea1a	1901	}
NYX	0:85b3fd62ea1a	1902	else
NYX	0:85b3fd62ea1a	1903	{
NYX	0:85b3fd62ea1a	1904	return (1); /* character available */
NYX	0:85b3fd62ea1a	1905	}
NYX	0:85b3fd62ea1a	1906	}
NYX	0:85b3fd62ea1a	1907
NYX	0:85b3fd62ea1a	1908	/@} end of CMSIS_core_DebugFunctions /
NYX	0:85b3fd62ea1a	1909
NYX	0:85b3fd62ea1a	1910
NYX	0:85b3fd62ea1a	1911
NYX	0:85b3fd62ea1a	1912
NYX	0:85b3fd62ea1a	1913	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	1914	}
NYX	0:85b3fd62ea1a	1915	#endif
NYX	0:85b3fd62ea1a	1916
NYX	0:85b3fd62ea1a	1917	#endif /* __CORE_CM3_H_DEPENDANT */
NYX	0:85b3fd62ea1a	1918
NYX	0:85b3fd62ea1a	1919	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

cmsis/core_cm3.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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