inport from local

Dependents:   Hobbyking_Cheetah_0511

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

Who changed what in which revision?

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NYX 0:85b3fd62ea1a 1 /**************************************************************************//**
NYX 0:85b3fd62ea1a 2 * @file core_cm23.h
NYX 0:85b3fd62ea1a 3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
NYX 0:85b3fd62ea1a 4 * @version V5.0.2
NYX 0:85b3fd62ea1a 5 * @date 13. February 2017
NYX 0:85b3fd62ea1a 6 ******************************************************************************/
NYX 0:85b3fd62ea1a 7 /*
NYX 0:85b3fd62ea1a 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
NYX 0:85b3fd62ea1a 9 *
NYX 0:85b3fd62ea1a 10 * SPDX-License-Identifier: Apache-2.0
NYX 0:85b3fd62ea1a 11 *
NYX 0:85b3fd62ea1a 12 * Licensed under the Apache License, Version 2.0 (the License); you may
NYX 0:85b3fd62ea1a 13 * not use this file except in compliance with the License.
NYX 0:85b3fd62ea1a 14 * You may obtain a copy of the License at
NYX 0:85b3fd62ea1a 15 *
NYX 0:85b3fd62ea1a 16 * www.apache.org/licenses/LICENSE-2.0
NYX 0:85b3fd62ea1a 17 *
NYX 0:85b3fd62ea1a 18 * Unless required by applicable law or agreed to in writing, software
NYX 0:85b3fd62ea1a 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
NYX 0:85b3fd62ea1a 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX 0:85b3fd62ea1a 21 * See the License for the specific language governing permissions and
NYX 0:85b3fd62ea1a 22 * limitations under the License.
NYX 0:85b3fd62ea1a 23 */
NYX 0:85b3fd62ea1a 24
NYX 0:85b3fd62ea1a 25 #if defined ( __ICCARM__ )
NYX 0:85b3fd62ea1a 26 #pragma system_include /* treat file as system include file for MISRA check */
NYX 0:85b3fd62ea1a 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX 0:85b3fd62ea1a 28 #pragma clang system_header /* treat file as system include file */
NYX 0:85b3fd62ea1a 29 #endif
NYX 0:85b3fd62ea1a 30
NYX 0:85b3fd62ea1a 31 #ifndef __CORE_CM23_H_GENERIC
NYX 0:85b3fd62ea1a 32 #define __CORE_CM23_H_GENERIC
NYX 0:85b3fd62ea1a 33
NYX 0:85b3fd62ea1a 34 #include <stdint.h>
NYX 0:85b3fd62ea1a 35
NYX 0:85b3fd62ea1a 36 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 37 extern "C" {
NYX 0:85b3fd62ea1a 38 #endif
NYX 0:85b3fd62ea1a 39
NYX 0:85b3fd62ea1a 40 /**
NYX 0:85b3fd62ea1a 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
NYX 0:85b3fd62ea1a 42 CMSIS violates the following MISRA-C:2004 rules:
NYX 0:85b3fd62ea1a 43
NYX 0:85b3fd62ea1a 44 \li Required Rule 8.5, object/function definition in header file.<br>
NYX 0:85b3fd62ea1a 45 Function definitions in header files are used to allow 'inlining'.
NYX 0:85b3fd62ea1a 46
NYX 0:85b3fd62ea1a 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
NYX 0:85b3fd62ea1a 48 Unions are used for effective representation of core registers.
NYX 0:85b3fd62ea1a 49
NYX 0:85b3fd62ea1a 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
NYX 0:85b3fd62ea1a 51 Function-like macros are used to allow more efficient code.
NYX 0:85b3fd62ea1a 52 */
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 /*******************************************************************************
NYX 0:85b3fd62ea1a 56 * CMSIS definitions
NYX 0:85b3fd62ea1a 57 ******************************************************************************/
NYX 0:85b3fd62ea1a 58 /**
NYX 0:85b3fd62ea1a 59 \ingroup Cortex_M23
NYX 0:85b3fd62ea1a 60 @{
NYX 0:85b3fd62ea1a 61 */
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63 /* CMSIS cmGrebe definitions */
NYX 0:85b3fd62ea1a 64 #define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
NYX 0:85b3fd62ea1a 65 #define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
NYX 0:85b3fd62ea1a 66 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
NYX 0:85b3fd62ea1a 67 __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 #define __CORTEX_M (23U) /*!< Cortex-M Core */
NYX 0:85b3fd62ea1a 70
NYX 0:85b3fd62ea1a 71 /** __FPU_USED indicates whether an FPU is used or not.
NYX 0:85b3fd62ea1a 72 This core does not support an FPU at all
NYX 0:85b3fd62ea1a 73 */
NYX 0:85b3fd62ea1a 74 #define __FPU_USED 0U
NYX 0:85b3fd62ea1a 75
NYX 0:85b3fd62ea1a 76 #if defined ( __CC_ARM )
NYX 0:85b3fd62ea1a 77 #if defined __TARGET_FPU_VFP
NYX 0:85b3fd62ea1a 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 79 #endif
NYX 0:85b3fd62ea1a 80
NYX 0:85b3fd62ea1a 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX 0:85b3fd62ea1a 82 #if defined __ARM_PCS_VFP
NYX 0:85b3fd62ea1a 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 84 #endif
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 #elif defined ( __GNUC__ )
NYX 0:85b3fd62ea1a 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
NYX 0:85b3fd62ea1a 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 89 #endif
NYX 0:85b3fd62ea1a 90
NYX 0:85b3fd62ea1a 91 #elif defined ( __ICCARM__ )
NYX 0:85b3fd62ea1a 92 #if defined __ARMVFP__
NYX 0:85b3fd62ea1a 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 94 #endif
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 #elif defined ( __TI_ARM__ )
NYX 0:85b3fd62ea1a 97 #if defined __TI_VFP_SUPPORT__
NYX 0:85b3fd62ea1a 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 99 #endif
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 #elif defined ( __TASKING__ )
NYX 0:85b3fd62ea1a 102 #if defined __FPU_VFP__
NYX 0:85b3fd62ea1a 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 104 #endif
NYX 0:85b3fd62ea1a 105
NYX 0:85b3fd62ea1a 106 #elif defined ( __CSMC__ )
NYX 0:85b3fd62ea1a 107 #if ( __CSMC__ & 0x400U)
NYX 0:85b3fd62ea1a 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 109 #endif
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 #endif
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115
NYX 0:85b3fd62ea1a 116 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 117 }
NYX 0:85b3fd62ea1a 118 #endif
NYX 0:85b3fd62ea1a 119
NYX 0:85b3fd62ea1a 120 #endif /* __CORE_CM23_H_GENERIC */
NYX 0:85b3fd62ea1a 121
NYX 0:85b3fd62ea1a 122 #ifndef __CMSIS_GENERIC
NYX 0:85b3fd62ea1a 123
NYX 0:85b3fd62ea1a 124 #ifndef __CORE_CM23_H_DEPENDANT
NYX 0:85b3fd62ea1a 125 #define __CORE_CM23_H_DEPENDANT
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 128 extern "C" {
NYX 0:85b3fd62ea1a 129 #endif
NYX 0:85b3fd62ea1a 130
NYX 0:85b3fd62ea1a 131 /* check device defines and use defaults */
NYX 0:85b3fd62ea1a 132 #if defined __CHECK_DEVICE_DEFINES
NYX 0:85b3fd62ea1a 133 #ifndef __CM23_REV
NYX 0:85b3fd62ea1a 134 #define __CM23_REV 0x0000U
NYX 0:85b3fd62ea1a 135 #warning "__CM23_REV not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 136 #endif
NYX 0:85b3fd62ea1a 137
NYX 0:85b3fd62ea1a 138 #ifndef __FPU_PRESENT
NYX 0:85b3fd62ea1a 139 #define __FPU_PRESENT 0U
NYX 0:85b3fd62ea1a 140 #warning "__FPU_PRESENT not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 141 #endif
NYX 0:85b3fd62ea1a 142
NYX 0:85b3fd62ea1a 143 #ifndef __MPU_PRESENT
NYX 0:85b3fd62ea1a 144 #define __MPU_PRESENT 0U
NYX 0:85b3fd62ea1a 145 #warning "__MPU_PRESENT not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 146 #endif
NYX 0:85b3fd62ea1a 147
NYX 0:85b3fd62ea1a 148 #ifndef __SAUREGION_PRESENT
NYX 0:85b3fd62ea1a 149 #define __SAUREGION_PRESENT 0U
NYX 0:85b3fd62ea1a 150 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 151 #endif
NYX 0:85b3fd62ea1a 152
NYX 0:85b3fd62ea1a 153 #ifndef __VTOR_PRESENT
NYX 0:85b3fd62ea1a 154 #define __VTOR_PRESENT 0U
NYX 0:85b3fd62ea1a 155 #warning "__VTOR_PRESENT not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 156 #endif
NYX 0:85b3fd62ea1a 157
NYX 0:85b3fd62ea1a 158 #ifndef __NVIC_PRIO_BITS
NYX 0:85b3fd62ea1a 159 #define __NVIC_PRIO_BITS 2U
NYX 0:85b3fd62ea1a 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 161 #endif
NYX 0:85b3fd62ea1a 162
NYX 0:85b3fd62ea1a 163 #ifndef __Vendor_SysTickConfig
NYX 0:85b3fd62ea1a 164 #define __Vendor_SysTickConfig 0U
NYX 0:85b3fd62ea1a 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 166 #endif
NYX 0:85b3fd62ea1a 167
NYX 0:85b3fd62ea1a 168 #ifndef __ETM_PRESENT
NYX 0:85b3fd62ea1a 169 #define __ETM_PRESENT 0U
NYX 0:85b3fd62ea1a 170 #warning "__ETM_PRESENT not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 171 #endif
NYX 0:85b3fd62ea1a 172
NYX 0:85b3fd62ea1a 173 #ifndef __MTB_PRESENT
NYX 0:85b3fd62ea1a 174 #define __MTB_PRESENT 0U
NYX 0:85b3fd62ea1a 175 #warning "__MTB_PRESENT not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 176 #endif
NYX 0:85b3fd62ea1a 177
NYX 0:85b3fd62ea1a 178 #endif
NYX 0:85b3fd62ea1a 179
NYX 0:85b3fd62ea1a 180 /* IO definitions (access restrictions to peripheral registers) */
NYX 0:85b3fd62ea1a 181 /**
NYX 0:85b3fd62ea1a 182 \defgroup CMSIS_glob_defs CMSIS Global Defines
NYX 0:85b3fd62ea1a 183
NYX 0:85b3fd62ea1a 184 <strong>IO Type Qualifiers</strong> are used
NYX 0:85b3fd62ea1a 185 \li to specify the access to peripheral variables.
NYX 0:85b3fd62ea1a 186 \li for automatic generation of peripheral register debug information.
NYX 0:85b3fd62ea1a 187 */
NYX 0:85b3fd62ea1a 188 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 189 #define __I volatile /*!< Defines 'read only' permissions */
NYX 0:85b3fd62ea1a 190 #else
NYX 0:85b3fd62ea1a 191 #define __I volatile const /*!< Defines 'read only' permissions */
NYX 0:85b3fd62ea1a 192 #endif
NYX 0:85b3fd62ea1a 193 #define __O volatile /*!< Defines 'write only' permissions */
NYX 0:85b3fd62ea1a 194 #define __IO volatile /*!< Defines 'read / write' permissions */
NYX 0:85b3fd62ea1a 195
NYX 0:85b3fd62ea1a 196 /* following defines should be used for structure members */
NYX 0:85b3fd62ea1a 197 #define __IM volatile const /*! Defines 'read only' structure member permissions */
NYX 0:85b3fd62ea1a 198 #define __OM volatile /*! Defines 'write only' structure member permissions */
NYX 0:85b3fd62ea1a 199 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
NYX 0:85b3fd62ea1a 200
NYX 0:85b3fd62ea1a 201 /*@} end of group Cortex_M23 */
NYX 0:85b3fd62ea1a 202
NYX 0:85b3fd62ea1a 203
NYX 0:85b3fd62ea1a 204
NYX 0:85b3fd62ea1a 205 /*******************************************************************************
NYX 0:85b3fd62ea1a 206 * Register Abstraction
NYX 0:85b3fd62ea1a 207 Core Register contain:
NYX 0:85b3fd62ea1a 208 - Core Register
NYX 0:85b3fd62ea1a 209 - Core NVIC Register
NYX 0:85b3fd62ea1a 210 - Core SCB Register
NYX 0:85b3fd62ea1a 211 - Core SysTick Register
NYX 0:85b3fd62ea1a 212 - Core Debug Register
NYX 0:85b3fd62ea1a 213 - Core MPU Register
NYX 0:85b3fd62ea1a 214 - Core SAU Register
NYX 0:85b3fd62ea1a 215 ******************************************************************************/
NYX 0:85b3fd62ea1a 216 /**
NYX 0:85b3fd62ea1a 217 \defgroup CMSIS_core_register Defines and Type Definitions
NYX 0:85b3fd62ea1a 218 \brief Type definitions and defines for Cortex-M processor based devices.
NYX 0:85b3fd62ea1a 219 */
NYX 0:85b3fd62ea1a 220
NYX 0:85b3fd62ea1a 221 /**
NYX 0:85b3fd62ea1a 222 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 223 \defgroup CMSIS_CORE Status and Control Registers
NYX 0:85b3fd62ea1a 224 \brief Core Register type definitions.
NYX 0:85b3fd62ea1a 225 @{
NYX 0:85b3fd62ea1a 226 */
NYX 0:85b3fd62ea1a 227
NYX 0:85b3fd62ea1a 228 /**
NYX 0:85b3fd62ea1a 229 \brief Union type to access the Application Program Status Register (APSR).
NYX 0:85b3fd62ea1a 230 */
NYX 0:85b3fd62ea1a 231 typedef union
NYX 0:85b3fd62ea1a 232 {
NYX 0:85b3fd62ea1a 233 struct
NYX 0:85b3fd62ea1a 234 {
NYX 0:85b3fd62ea1a 235 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
NYX 0:85b3fd62ea1a 236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
NYX 0:85b3fd62ea1a 237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
NYX 0:85b3fd62ea1a 238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
NYX 0:85b3fd62ea1a 239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
NYX 0:85b3fd62ea1a 240 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 241 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 242 } APSR_Type;
NYX 0:85b3fd62ea1a 243
NYX 0:85b3fd62ea1a 244 /* APSR Register Definitions */
NYX 0:85b3fd62ea1a 245 #define APSR_N_Pos 31U /*!< APSR: N Position */
NYX 0:85b3fd62ea1a 246 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
NYX 0:85b3fd62ea1a 247
NYX 0:85b3fd62ea1a 248 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
NYX 0:85b3fd62ea1a 249 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
NYX 0:85b3fd62ea1a 250
NYX 0:85b3fd62ea1a 251 #define APSR_C_Pos 29U /*!< APSR: C Position */
NYX 0:85b3fd62ea1a 252 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
NYX 0:85b3fd62ea1a 253
NYX 0:85b3fd62ea1a 254 #define APSR_V_Pos 28U /*!< APSR: V Position */
NYX 0:85b3fd62ea1a 255 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
NYX 0:85b3fd62ea1a 256
NYX 0:85b3fd62ea1a 257
NYX 0:85b3fd62ea1a 258 /**
NYX 0:85b3fd62ea1a 259 \brief Union type to access the Interrupt Program Status Register (IPSR).
NYX 0:85b3fd62ea1a 260 */
NYX 0:85b3fd62ea1a 261 typedef union
NYX 0:85b3fd62ea1a 262 {
NYX 0:85b3fd62ea1a 263 struct
NYX 0:85b3fd62ea1a 264 {
NYX 0:85b3fd62ea1a 265 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
NYX 0:85b3fd62ea1a 266 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
NYX 0:85b3fd62ea1a 267 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 268 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 269 } IPSR_Type;
NYX 0:85b3fd62ea1a 270
NYX 0:85b3fd62ea1a 271 /* IPSR Register Definitions */
NYX 0:85b3fd62ea1a 272 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
NYX 0:85b3fd62ea1a 273 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
NYX 0:85b3fd62ea1a 274
NYX 0:85b3fd62ea1a 275
NYX 0:85b3fd62ea1a 276 /**
NYX 0:85b3fd62ea1a 277 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
NYX 0:85b3fd62ea1a 278 */
NYX 0:85b3fd62ea1a 279 typedef union
NYX 0:85b3fd62ea1a 280 {
NYX 0:85b3fd62ea1a 281 struct
NYX 0:85b3fd62ea1a 282 {
NYX 0:85b3fd62ea1a 283 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
NYX 0:85b3fd62ea1a 284 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
NYX 0:85b3fd62ea1a 285 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
NYX 0:85b3fd62ea1a 286 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
NYX 0:85b3fd62ea1a 287 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
NYX 0:85b3fd62ea1a 288 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
NYX 0:85b3fd62ea1a 289 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
NYX 0:85b3fd62ea1a 290 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
NYX 0:85b3fd62ea1a 291 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 292 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 293 } xPSR_Type;
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /* xPSR Register Definitions */
NYX 0:85b3fd62ea1a 296 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
NYX 0:85b3fd62ea1a 297 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
NYX 0:85b3fd62ea1a 298
NYX 0:85b3fd62ea1a 299 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
NYX 0:85b3fd62ea1a 300 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
NYX 0:85b3fd62ea1a 301
NYX 0:85b3fd62ea1a 302 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
NYX 0:85b3fd62ea1a 303 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
NYX 0:85b3fd62ea1a 304
NYX 0:85b3fd62ea1a 305 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
NYX 0:85b3fd62ea1a 306 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
NYX 0:85b3fd62ea1a 307
NYX 0:85b3fd62ea1a 308 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
NYX 0:85b3fd62ea1a 309 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
NYX 0:85b3fd62ea1a 310
NYX 0:85b3fd62ea1a 311 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
NYX 0:85b3fd62ea1a 312 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
NYX 0:85b3fd62ea1a 313
NYX 0:85b3fd62ea1a 314
NYX 0:85b3fd62ea1a 315 /**
NYX 0:85b3fd62ea1a 316 \brief Union type to access the Control Registers (CONTROL).
NYX 0:85b3fd62ea1a 317 */
NYX 0:85b3fd62ea1a 318 typedef union
NYX 0:85b3fd62ea1a 319 {
NYX 0:85b3fd62ea1a 320 struct
NYX 0:85b3fd62ea1a 321 {
NYX 0:85b3fd62ea1a 322 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
NYX 0:85b3fd62ea1a 323 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
NYX 0:85b3fd62ea1a 324 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
NYX 0:85b3fd62ea1a 325 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 326 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 327 } CONTROL_Type;
NYX 0:85b3fd62ea1a 328
NYX 0:85b3fd62ea1a 329 /* CONTROL Register Definitions */
NYX 0:85b3fd62ea1a 330 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
NYX 0:85b3fd62ea1a 331 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
NYX 0:85b3fd62ea1a 332
NYX 0:85b3fd62ea1a 333 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
NYX 0:85b3fd62ea1a 334 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
NYX 0:85b3fd62ea1a 335
NYX 0:85b3fd62ea1a 336 /*@} end of group CMSIS_CORE */
NYX 0:85b3fd62ea1a 337
NYX 0:85b3fd62ea1a 338
NYX 0:85b3fd62ea1a 339 /**
NYX 0:85b3fd62ea1a 340 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 341 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
NYX 0:85b3fd62ea1a 342 \brief Type definitions for the NVIC Registers
NYX 0:85b3fd62ea1a 343 @{
NYX 0:85b3fd62ea1a 344 */
NYX 0:85b3fd62ea1a 345
NYX 0:85b3fd62ea1a 346 /**
NYX 0:85b3fd62ea1a 347 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
NYX 0:85b3fd62ea1a 348 */
NYX 0:85b3fd62ea1a 349 typedef struct
NYX 0:85b3fd62ea1a 350 {
NYX 0:85b3fd62ea1a 351 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
NYX 0:85b3fd62ea1a 352 uint32_t RESERVED0[16U];
NYX 0:85b3fd62ea1a 353 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
NYX 0:85b3fd62ea1a 354 uint32_t RSERVED1[16U];
NYX 0:85b3fd62ea1a 355 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
NYX 0:85b3fd62ea1a 356 uint32_t RESERVED2[16U];
NYX 0:85b3fd62ea1a 357 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
NYX 0:85b3fd62ea1a 358 uint32_t RESERVED3[16U];
NYX 0:85b3fd62ea1a 359 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
NYX 0:85b3fd62ea1a 360 uint32_t RESERVED4[16U];
NYX 0:85b3fd62ea1a 361 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
NYX 0:85b3fd62ea1a 362 uint32_t RESERVED5[16U];
NYX 0:85b3fd62ea1a 363 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
NYX 0:85b3fd62ea1a 364 } NVIC_Type;
NYX 0:85b3fd62ea1a 365
NYX 0:85b3fd62ea1a 366 /*@} end of group CMSIS_NVIC */
NYX 0:85b3fd62ea1a 367
NYX 0:85b3fd62ea1a 368
NYX 0:85b3fd62ea1a 369 /**
NYX 0:85b3fd62ea1a 370 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 371 \defgroup CMSIS_SCB System Control Block (SCB)
NYX 0:85b3fd62ea1a 372 \brief Type definitions for the System Control Block Registers
NYX 0:85b3fd62ea1a 373 @{
NYX 0:85b3fd62ea1a 374 */
NYX 0:85b3fd62ea1a 375
NYX 0:85b3fd62ea1a 376 /**
NYX 0:85b3fd62ea1a 377 \brief Structure type to access the System Control Block (SCB).
NYX 0:85b3fd62ea1a 378 */
NYX 0:85b3fd62ea1a 379 typedef struct
NYX 0:85b3fd62ea1a 380 {
NYX 0:85b3fd62ea1a 381 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
NYX 0:85b3fd62ea1a 382 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
NYX 0:85b3fd62ea1a 383 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
NYX 0:85b3fd62ea1a 384 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
NYX 0:85b3fd62ea1a 385 #else
NYX 0:85b3fd62ea1a 386 uint32_t RESERVED0;
NYX 0:85b3fd62ea1a 387 #endif
NYX 0:85b3fd62ea1a 388 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
NYX 0:85b3fd62ea1a 389 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
NYX 0:85b3fd62ea1a 390 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
NYX 0:85b3fd62ea1a 391 uint32_t RESERVED1;
NYX 0:85b3fd62ea1a 392 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
NYX 0:85b3fd62ea1a 393 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
NYX 0:85b3fd62ea1a 394 } SCB_Type;
NYX 0:85b3fd62ea1a 395
NYX 0:85b3fd62ea1a 396 /* SCB CPUID Register Definitions */
NYX 0:85b3fd62ea1a 397 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
NYX 0:85b3fd62ea1a 398 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
NYX 0:85b3fd62ea1a 399
NYX 0:85b3fd62ea1a 400 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
NYX 0:85b3fd62ea1a 401 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
NYX 0:85b3fd62ea1a 402
NYX 0:85b3fd62ea1a 403 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
NYX 0:85b3fd62ea1a 404 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
NYX 0:85b3fd62ea1a 405
NYX 0:85b3fd62ea1a 406 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
NYX 0:85b3fd62ea1a 407 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
NYX 0:85b3fd62ea1a 408
NYX 0:85b3fd62ea1a 409 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
NYX 0:85b3fd62ea1a 410 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
NYX 0:85b3fd62ea1a 411
NYX 0:85b3fd62ea1a 412 /* SCB Interrupt Control State Register Definitions */
NYX 0:85b3fd62ea1a 413 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
NYX 0:85b3fd62ea1a 414 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
NYX 0:85b3fd62ea1a 415
NYX 0:85b3fd62ea1a 416 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
NYX 0:85b3fd62ea1a 417 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
NYX 0:85b3fd62ea1a 418
NYX 0:85b3fd62ea1a 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
NYX 0:85b3fd62ea1a 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
NYX 0:85b3fd62ea1a 421
NYX 0:85b3fd62ea1a 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
NYX 0:85b3fd62ea1a 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
NYX 0:85b3fd62ea1a 424
NYX 0:85b3fd62ea1a 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
NYX 0:85b3fd62ea1a 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
NYX 0:85b3fd62ea1a 427
NYX 0:85b3fd62ea1a 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
NYX 0:85b3fd62ea1a 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
NYX 0:85b3fd62ea1a 430
NYX 0:85b3fd62ea1a 431 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
NYX 0:85b3fd62ea1a 432 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
NYX 0:85b3fd62ea1a 433
NYX 0:85b3fd62ea1a 434 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
NYX 0:85b3fd62ea1a 435 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
NYX 0:85b3fd62ea1a 436
NYX 0:85b3fd62ea1a 437 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
NYX 0:85b3fd62ea1a 438 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
NYX 0:85b3fd62ea1a 439
NYX 0:85b3fd62ea1a 440 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
NYX 0:85b3fd62ea1a 441 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
NYX 0:85b3fd62ea1a 442
NYX 0:85b3fd62ea1a 443 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
NYX 0:85b3fd62ea1a 444 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
NYX 0:85b3fd62ea1a 445
NYX 0:85b3fd62ea1a 446 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
NYX 0:85b3fd62ea1a 447 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
NYX 0:85b3fd62ea1a 448
NYX 0:85b3fd62ea1a 449 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
NYX 0:85b3fd62ea1a 450 /* SCB Vector Table Offset Register Definitions */
NYX 0:85b3fd62ea1a 451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
NYX 0:85b3fd62ea1a 452 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
NYX 0:85b3fd62ea1a 453 #endif
NYX 0:85b3fd62ea1a 454
NYX 0:85b3fd62ea1a 455 /* SCB Application Interrupt and Reset Control Register Definitions */
NYX 0:85b3fd62ea1a 456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
NYX 0:85b3fd62ea1a 457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
NYX 0:85b3fd62ea1a 458
NYX 0:85b3fd62ea1a 459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
NYX 0:85b3fd62ea1a 460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
NYX 0:85b3fd62ea1a 461
NYX 0:85b3fd62ea1a 462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
NYX 0:85b3fd62ea1a 463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
NYX 0:85b3fd62ea1a 464
NYX 0:85b3fd62ea1a 465 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
NYX 0:85b3fd62ea1a 466 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
NYX 0:85b3fd62ea1a 467
NYX 0:85b3fd62ea1a 468 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
NYX 0:85b3fd62ea1a 469 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
NYX 0:85b3fd62ea1a 470
NYX 0:85b3fd62ea1a 471 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
NYX 0:85b3fd62ea1a 472 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
NYX 0:85b3fd62ea1a 473
NYX 0:85b3fd62ea1a 474 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
NYX 0:85b3fd62ea1a 475 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
NYX 0:85b3fd62ea1a 476
NYX 0:85b3fd62ea1a 477 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
NYX 0:85b3fd62ea1a 478 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
NYX 0:85b3fd62ea1a 479
NYX 0:85b3fd62ea1a 480 /* SCB System Control Register Definitions */
NYX 0:85b3fd62ea1a 481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
NYX 0:85b3fd62ea1a 482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
NYX 0:85b3fd62ea1a 483
NYX 0:85b3fd62ea1a 484 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
NYX 0:85b3fd62ea1a 485 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
NYX 0:85b3fd62ea1a 486
NYX 0:85b3fd62ea1a 487 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
NYX 0:85b3fd62ea1a 488 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
NYX 0:85b3fd62ea1a 489
NYX 0:85b3fd62ea1a 490 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
NYX 0:85b3fd62ea1a 491 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
NYX 0:85b3fd62ea1a 492
NYX 0:85b3fd62ea1a 493 /* SCB Configuration Control Register Definitions */
NYX 0:85b3fd62ea1a 494 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
NYX 0:85b3fd62ea1a 495 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
NYX 0:85b3fd62ea1a 496
NYX 0:85b3fd62ea1a 497 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
NYX 0:85b3fd62ea1a 498 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
NYX 0:85b3fd62ea1a 499
NYX 0:85b3fd62ea1a 500 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
NYX 0:85b3fd62ea1a 501 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
NYX 0:85b3fd62ea1a 502
NYX 0:85b3fd62ea1a 503 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
NYX 0:85b3fd62ea1a 504 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
NYX 0:85b3fd62ea1a 505
NYX 0:85b3fd62ea1a 506 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
NYX 0:85b3fd62ea1a 507 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
NYX 0:85b3fd62ea1a 508
NYX 0:85b3fd62ea1a 509 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
NYX 0:85b3fd62ea1a 510 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
NYX 0:85b3fd62ea1a 511
NYX 0:85b3fd62ea1a 512 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
NYX 0:85b3fd62ea1a 513 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
NYX 0:85b3fd62ea1a 514
NYX 0:85b3fd62ea1a 515 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
NYX 0:85b3fd62ea1a 516 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
NYX 0:85b3fd62ea1a 517
NYX 0:85b3fd62ea1a 518 /* SCB System Handler Control and State Register Definitions */
NYX 0:85b3fd62ea1a 519 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
NYX 0:85b3fd62ea1a 520 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
NYX 0:85b3fd62ea1a 521
NYX 0:85b3fd62ea1a 522 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
NYX 0:85b3fd62ea1a 523 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
NYX 0:85b3fd62ea1a 524
NYX 0:85b3fd62ea1a 525 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
NYX 0:85b3fd62ea1a 526 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
NYX 0:85b3fd62ea1a 527
NYX 0:85b3fd62ea1a 528 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
NYX 0:85b3fd62ea1a 529 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
NYX 0:85b3fd62ea1a 530
NYX 0:85b3fd62ea1a 531 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
NYX 0:85b3fd62ea1a 532 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
NYX 0:85b3fd62ea1a 533
NYX 0:85b3fd62ea1a 534 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
NYX 0:85b3fd62ea1a 535 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
NYX 0:85b3fd62ea1a 536
NYX 0:85b3fd62ea1a 537 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
NYX 0:85b3fd62ea1a 538 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
NYX 0:85b3fd62ea1a 539
NYX 0:85b3fd62ea1a 540 /*@} end of group CMSIS_SCB */
NYX 0:85b3fd62ea1a 541
NYX 0:85b3fd62ea1a 542
NYX 0:85b3fd62ea1a 543 /**
NYX 0:85b3fd62ea1a 544 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 545 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
NYX 0:85b3fd62ea1a 546 \brief Type definitions for the System Timer Registers.
NYX 0:85b3fd62ea1a 547 @{
NYX 0:85b3fd62ea1a 548 */
NYX 0:85b3fd62ea1a 549
NYX 0:85b3fd62ea1a 550 /**
NYX 0:85b3fd62ea1a 551 \brief Structure type to access the System Timer (SysTick).
NYX 0:85b3fd62ea1a 552 */
NYX 0:85b3fd62ea1a 553 typedef struct
NYX 0:85b3fd62ea1a 554 {
NYX 0:85b3fd62ea1a 555 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
NYX 0:85b3fd62ea1a 556 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
NYX 0:85b3fd62ea1a 557 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
NYX 0:85b3fd62ea1a 558 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
NYX 0:85b3fd62ea1a 559 } SysTick_Type;
NYX 0:85b3fd62ea1a 560
NYX 0:85b3fd62ea1a 561 /* SysTick Control / Status Register Definitions */
NYX 0:85b3fd62ea1a 562 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
NYX 0:85b3fd62ea1a 563 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
NYX 0:85b3fd62ea1a 564
NYX 0:85b3fd62ea1a 565 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
NYX 0:85b3fd62ea1a 566 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
NYX 0:85b3fd62ea1a 567
NYX 0:85b3fd62ea1a 568 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
NYX 0:85b3fd62ea1a 569 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
NYX 0:85b3fd62ea1a 570
NYX 0:85b3fd62ea1a 571 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
NYX 0:85b3fd62ea1a 572 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
NYX 0:85b3fd62ea1a 573
NYX 0:85b3fd62ea1a 574 /* SysTick Reload Register Definitions */
NYX 0:85b3fd62ea1a 575 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
NYX 0:85b3fd62ea1a 576 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
NYX 0:85b3fd62ea1a 577
NYX 0:85b3fd62ea1a 578 /* SysTick Current Register Definitions */
NYX 0:85b3fd62ea1a 579 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
NYX 0:85b3fd62ea1a 580 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
NYX 0:85b3fd62ea1a 581
NYX 0:85b3fd62ea1a 582 /* SysTick Calibration Register Definitions */
NYX 0:85b3fd62ea1a 583 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
NYX 0:85b3fd62ea1a 584 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
NYX 0:85b3fd62ea1a 585
NYX 0:85b3fd62ea1a 586 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
NYX 0:85b3fd62ea1a 587 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
NYX 0:85b3fd62ea1a 588
NYX 0:85b3fd62ea1a 589 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
NYX 0:85b3fd62ea1a 590 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
NYX 0:85b3fd62ea1a 591
NYX 0:85b3fd62ea1a 592 /*@} end of group CMSIS_SysTick */
NYX 0:85b3fd62ea1a 593
NYX 0:85b3fd62ea1a 594
NYX 0:85b3fd62ea1a 595 /**
NYX 0:85b3fd62ea1a 596 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 597 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
NYX 0:85b3fd62ea1a 598 \brief Type definitions for the Data Watchpoint and Trace (DWT)
NYX 0:85b3fd62ea1a 599 @{
NYX 0:85b3fd62ea1a 600 */
NYX 0:85b3fd62ea1a 601
NYX 0:85b3fd62ea1a 602 /**
NYX 0:85b3fd62ea1a 603 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
NYX 0:85b3fd62ea1a 604 */
NYX 0:85b3fd62ea1a 605 typedef struct
NYX 0:85b3fd62ea1a 606 {
NYX 0:85b3fd62ea1a 607 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
NYX 0:85b3fd62ea1a 608 uint32_t RESERVED0[6U];
NYX 0:85b3fd62ea1a 609 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
NYX 0:85b3fd62ea1a 610 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
NYX 0:85b3fd62ea1a 611 uint32_t RESERVED1[1U];
NYX 0:85b3fd62ea1a 612 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
NYX 0:85b3fd62ea1a 613 uint32_t RESERVED2[1U];
NYX 0:85b3fd62ea1a 614 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
NYX 0:85b3fd62ea1a 615 uint32_t RESERVED3[1U];
NYX 0:85b3fd62ea1a 616 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
NYX 0:85b3fd62ea1a 617 uint32_t RESERVED4[1U];
NYX 0:85b3fd62ea1a 618 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
NYX 0:85b3fd62ea1a 619 uint32_t RESERVED5[1U];
NYX 0:85b3fd62ea1a 620 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
NYX 0:85b3fd62ea1a 621 uint32_t RESERVED6[1U];
NYX 0:85b3fd62ea1a 622 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
NYX 0:85b3fd62ea1a 623 uint32_t RESERVED7[1U];
NYX 0:85b3fd62ea1a 624 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
NYX 0:85b3fd62ea1a 625 uint32_t RESERVED8[1U];
NYX 0:85b3fd62ea1a 626 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
NYX 0:85b3fd62ea1a 627 uint32_t RESERVED9[1U];
NYX 0:85b3fd62ea1a 628 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
NYX 0:85b3fd62ea1a 629 uint32_t RESERVED10[1U];
NYX 0:85b3fd62ea1a 630 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
NYX 0:85b3fd62ea1a 631 uint32_t RESERVED11[1U];
NYX 0:85b3fd62ea1a 632 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
NYX 0:85b3fd62ea1a 633 uint32_t RESERVED12[1U];
NYX 0:85b3fd62ea1a 634 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
NYX 0:85b3fd62ea1a 635 uint32_t RESERVED13[1U];
NYX 0:85b3fd62ea1a 636 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
NYX 0:85b3fd62ea1a 637 uint32_t RESERVED14[1U];
NYX 0:85b3fd62ea1a 638 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
NYX 0:85b3fd62ea1a 639 uint32_t RESERVED15[1U];
NYX 0:85b3fd62ea1a 640 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
NYX 0:85b3fd62ea1a 641 uint32_t RESERVED16[1U];
NYX 0:85b3fd62ea1a 642 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
NYX 0:85b3fd62ea1a 643 uint32_t RESERVED17[1U];
NYX 0:85b3fd62ea1a 644 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
NYX 0:85b3fd62ea1a 645 uint32_t RESERVED18[1U];
NYX 0:85b3fd62ea1a 646 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
NYX 0:85b3fd62ea1a 647 uint32_t RESERVED19[1U];
NYX 0:85b3fd62ea1a 648 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
NYX 0:85b3fd62ea1a 649 uint32_t RESERVED20[1U];
NYX 0:85b3fd62ea1a 650 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
NYX 0:85b3fd62ea1a 651 uint32_t RESERVED21[1U];
NYX 0:85b3fd62ea1a 652 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
NYX 0:85b3fd62ea1a 653 uint32_t RESERVED22[1U];
NYX 0:85b3fd62ea1a 654 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
NYX 0:85b3fd62ea1a 655 uint32_t RESERVED23[1U];
NYX 0:85b3fd62ea1a 656 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
NYX 0:85b3fd62ea1a 657 uint32_t RESERVED24[1U];
NYX 0:85b3fd62ea1a 658 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
NYX 0:85b3fd62ea1a 659 uint32_t RESERVED25[1U];
NYX 0:85b3fd62ea1a 660 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
NYX 0:85b3fd62ea1a 661 uint32_t RESERVED26[1U];
NYX 0:85b3fd62ea1a 662 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
NYX 0:85b3fd62ea1a 663 uint32_t RESERVED27[1U];
NYX 0:85b3fd62ea1a 664 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
NYX 0:85b3fd62ea1a 665 uint32_t RESERVED28[1U];
NYX 0:85b3fd62ea1a 666 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
NYX 0:85b3fd62ea1a 667 uint32_t RESERVED29[1U];
NYX 0:85b3fd62ea1a 668 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
NYX 0:85b3fd62ea1a 669 uint32_t RESERVED30[1U];
NYX 0:85b3fd62ea1a 670 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
NYX 0:85b3fd62ea1a 671 uint32_t RESERVED31[1U];
NYX 0:85b3fd62ea1a 672 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
NYX 0:85b3fd62ea1a 673 } DWT_Type;
NYX 0:85b3fd62ea1a 674
NYX 0:85b3fd62ea1a 675 /* DWT Control Register Definitions */
NYX 0:85b3fd62ea1a 676 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
NYX 0:85b3fd62ea1a 677 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
NYX 0:85b3fd62ea1a 678
NYX 0:85b3fd62ea1a 679 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
NYX 0:85b3fd62ea1a 680 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
NYX 0:85b3fd62ea1a 681
NYX 0:85b3fd62ea1a 682 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
NYX 0:85b3fd62ea1a 683 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
NYX 0:85b3fd62ea1a 684
NYX 0:85b3fd62ea1a 685 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
NYX 0:85b3fd62ea1a 686 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
NYX 0:85b3fd62ea1a 687
NYX 0:85b3fd62ea1a 688 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
NYX 0:85b3fd62ea1a 689 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
NYX 0:85b3fd62ea1a 690
NYX 0:85b3fd62ea1a 691 /* DWT Comparator Function Register Definitions */
NYX 0:85b3fd62ea1a 692 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
NYX 0:85b3fd62ea1a 693 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
NYX 0:85b3fd62ea1a 694
NYX 0:85b3fd62ea1a 695 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
NYX 0:85b3fd62ea1a 696 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
NYX 0:85b3fd62ea1a 697
NYX 0:85b3fd62ea1a 698 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
NYX 0:85b3fd62ea1a 699 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
NYX 0:85b3fd62ea1a 700
NYX 0:85b3fd62ea1a 701 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
NYX 0:85b3fd62ea1a 702 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
NYX 0:85b3fd62ea1a 703
NYX 0:85b3fd62ea1a 704 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
NYX 0:85b3fd62ea1a 705 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
NYX 0:85b3fd62ea1a 706
NYX 0:85b3fd62ea1a 707 /*@}*/ /* end of group CMSIS_DWT */
NYX 0:85b3fd62ea1a 708
NYX 0:85b3fd62ea1a 709
NYX 0:85b3fd62ea1a 710 /**
NYX 0:85b3fd62ea1a 711 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 712 \defgroup CMSIS_TPI Trace Port Interface (TPI)
NYX 0:85b3fd62ea1a 713 \brief Type definitions for the Trace Port Interface (TPI)
NYX 0:85b3fd62ea1a 714 @{
NYX 0:85b3fd62ea1a 715 */
NYX 0:85b3fd62ea1a 716
NYX 0:85b3fd62ea1a 717 /**
NYX 0:85b3fd62ea1a 718 \brief Structure type to access the Trace Port Interface Register (TPI).
NYX 0:85b3fd62ea1a 719 */
NYX 0:85b3fd62ea1a 720 typedef struct
NYX 0:85b3fd62ea1a 721 {
NYX 0:85b3fd62ea1a 722 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
NYX 0:85b3fd62ea1a 723 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
NYX 0:85b3fd62ea1a 724 uint32_t RESERVED0[2U];
NYX 0:85b3fd62ea1a 725 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
NYX 0:85b3fd62ea1a 726 uint32_t RESERVED1[55U];
NYX 0:85b3fd62ea1a 727 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
NYX 0:85b3fd62ea1a 728 uint32_t RESERVED2[131U];
NYX 0:85b3fd62ea1a 729 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
NYX 0:85b3fd62ea1a 730 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
NYX 0:85b3fd62ea1a 731 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
NYX 0:85b3fd62ea1a 732 uint32_t RESERVED3[759U];
NYX 0:85b3fd62ea1a 733 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
NYX 0:85b3fd62ea1a 734 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
NYX 0:85b3fd62ea1a 735 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
NYX 0:85b3fd62ea1a 736 uint32_t RESERVED4[1U];
NYX 0:85b3fd62ea1a 737 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
NYX 0:85b3fd62ea1a 738 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
NYX 0:85b3fd62ea1a 739 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
NYX 0:85b3fd62ea1a 740 uint32_t RESERVED5[39U];
NYX 0:85b3fd62ea1a 741 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
NYX 0:85b3fd62ea1a 742 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
NYX 0:85b3fd62ea1a 743 uint32_t RESERVED7[8U];
NYX 0:85b3fd62ea1a 744 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
NYX 0:85b3fd62ea1a 745 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
NYX 0:85b3fd62ea1a 746 } TPI_Type;
NYX 0:85b3fd62ea1a 747
NYX 0:85b3fd62ea1a 748 /* TPI Asynchronous Clock Prescaler Register Definitions */
NYX 0:85b3fd62ea1a 749 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
NYX 0:85b3fd62ea1a 750 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
NYX 0:85b3fd62ea1a 751
NYX 0:85b3fd62ea1a 752 /* TPI Selected Pin Protocol Register Definitions */
NYX 0:85b3fd62ea1a 753 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
NYX 0:85b3fd62ea1a 754 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
NYX 0:85b3fd62ea1a 755
NYX 0:85b3fd62ea1a 756 /* TPI Formatter and Flush Status Register Definitions */
NYX 0:85b3fd62ea1a 757 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
NYX 0:85b3fd62ea1a 758 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
NYX 0:85b3fd62ea1a 759
NYX 0:85b3fd62ea1a 760 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
NYX 0:85b3fd62ea1a 761 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
NYX 0:85b3fd62ea1a 762
NYX 0:85b3fd62ea1a 763 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
NYX 0:85b3fd62ea1a 764 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
NYX 0:85b3fd62ea1a 765
NYX 0:85b3fd62ea1a 766 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
NYX 0:85b3fd62ea1a 767 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
NYX 0:85b3fd62ea1a 768
NYX 0:85b3fd62ea1a 769 /* TPI Formatter and Flush Control Register Definitions */
NYX 0:85b3fd62ea1a 770 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
NYX 0:85b3fd62ea1a 771 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
NYX 0:85b3fd62ea1a 772
NYX 0:85b3fd62ea1a 773 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
NYX 0:85b3fd62ea1a 774 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
NYX 0:85b3fd62ea1a 775
NYX 0:85b3fd62ea1a 776 /* TPI TRIGGER Register Definitions */
NYX 0:85b3fd62ea1a 777 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
NYX 0:85b3fd62ea1a 778 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
NYX 0:85b3fd62ea1a 779
NYX 0:85b3fd62ea1a 780 /* TPI Integration ETM Data Register Definitions (FIFO0) */
NYX 0:85b3fd62ea1a 781 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
NYX 0:85b3fd62ea1a 782 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
NYX 0:85b3fd62ea1a 783
NYX 0:85b3fd62ea1a 784 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
NYX 0:85b3fd62ea1a 785 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
NYX 0:85b3fd62ea1a 786
NYX 0:85b3fd62ea1a 787 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
NYX 0:85b3fd62ea1a 788 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
NYX 0:85b3fd62ea1a 789
NYX 0:85b3fd62ea1a 790 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
NYX 0:85b3fd62ea1a 791 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
NYX 0:85b3fd62ea1a 792
NYX 0:85b3fd62ea1a 793 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
NYX 0:85b3fd62ea1a 794 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
NYX 0:85b3fd62ea1a 795
NYX 0:85b3fd62ea1a 796 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
NYX 0:85b3fd62ea1a 797 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
NYX 0:85b3fd62ea1a 798
NYX 0:85b3fd62ea1a 799 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
NYX 0:85b3fd62ea1a 800 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
NYX 0:85b3fd62ea1a 801
NYX 0:85b3fd62ea1a 802 /* TPI ITATBCTR2 Register Definitions */
NYX 0:85b3fd62ea1a 803 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
NYX 0:85b3fd62ea1a 804 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
NYX 0:85b3fd62ea1a 805
NYX 0:85b3fd62ea1a 806 /* TPI Integration ITM Data Register Definitions (FIFO1) */
NYX 0:85b3fd62ea1a 807 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
NYX 0:85b3fd62ea1a 808 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
NYX 0:85b3fd62ea1a 809
NYX 0:85b3fd62ea1a 810 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
NYX 0:85b3fd62ea1a 811 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
NYX 0:85b3fd62ea1a 812
NYX 0:85b3fd62ea1a 813 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
NYX 0:85b3fd62ea1a 814 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
NYX 0:85b3fd62ea1a 815
NYX 0:85b3fd62ea1a 816 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
NYX 0:85b3fd62ea1a 817 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
NYX 0:85b3fd62ea1a 818
NYX 0:85b3fd62ea1a 819 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
NYX 0:85b3fd62ea1a 820 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
NYX 0:85b3fd62ea1a 821
NYX 0:85b3fd62ea1a 822 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
NYX 0:85b3fd62ea1a 823 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
NYX 0:85b3fd62ea1a 824
NYX 0:85b3fd62ea1a 825 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
NYX 0:85b3fd62ea1a 826 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
NYX 0:85b3fd62ea1a 827
NYX 0:85b3fd62ea1a 828 /* TPI ITATBCTR0 Register Definitions */
NYX 0:85b3fd62ea1a 829 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
NYX 0:85b3fd62ea1a 830 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
NYX 0:85b3fd62ea1a 831
NYX 0:85b3fd62ea1a 832 /* TPI Integration Mode Control Register Definitions */
NYX 0:85b3fd62ea1a 833 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
NYX 0:85b3fd62ea1a 834 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
NYX 0:85b3fd62ea1a 835
NYX 0:85b3fd62ea1a 836 /* TPI DEVID Register Definitions */
NYX 0:85b3fd62ea1a 837 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
NYX 0:85b3fd62ea1a 838 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
NYX 0:85b3fd62ea1a 839
NYX 0:85b3fd62ea1a 840 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
NYX 0:85b3fd62ea1a 841 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
NYX 0:85b3fd62ea1a 842
NYX 0:85b3fd62ea1a 843 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
NYX 0:85b3fd62ea1a 844 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
NYX 0:85b3fd62ea1a 845
NYX 0:85b3fd62ea1a 846 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
NYX 0:85b3fd62ea1a 847 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
NYX 0:85b3fd62ea1a 848
NYX 0:85b3fd62ea1a 849 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
NYX 0:85b3fd62ea1a 850 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
NYX 0:85b3fd62ea1a 851
NYX 0:85b3fd62ea1a 852 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
NYX 0:85b3fd62ea1a 853 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
NYX 0:85b3fd62ea1a 854
NYX 0:85b3fd62ea1a 855 /* TPI DEVTYPE Register Definitions */
NYX 0:85b3fd62ea1a 856 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
NYX 0:85b3fd62ea1a 857 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
NYX 0:85b3fd62ea1a 858
NYX 0:85b3fd62ea1a 859 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
NYX 0:85b3fd62ea1a 860 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
NYX 0:85b3fd62ea1a 861
NYX 0:85b3fd62ea1a 862 /*@}*/ /* end of group CMSIS_TPI */
NYX 0:85b3fd62ea1a 863
NYX 0:85b3fd62ea1a 864
NYX 0:85b3fd62ea1a 865 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 866 /**
NYX 0:85b3fd62ea1a 867 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 868 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
NYX 0:85b3fd62ea1a 869 \brief Type definitions for the Memory Protection Unit (MPU)
NYX 0:85b3fd62ea1a 870 @{
NYX 0:85b3fd62ea1a 871 */
NYX 0:85b3fd62ea1a 872
NYX 0:85b3fd62ea1a 873 /**
NYX 0:85b3fd62ea1a 874 \brief Structure type to access the Memory Protection Unit (MPU).
NYX 0:85b3fd62ea1a 875 */
NYX 0:85b3fd62ea1a 876 typedef struct
NYX 0:85b3fd62ea1a 877 {
NYX 0:85b3fd62ea1a 878 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
NYX 0:85b3fd62ea1a 879 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
NYX 0:85b3fd62ea1a 880 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
NYX 0:85b3fd62ea1a 881 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
NYX 0:85b3fd62ea1a 882 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
NYX 0:85b3fd62ea1a 883 uint32_t RESERVED0[7U];
NYX 0:85b3fd62ea1a 884 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
NYX 0:85b3fd62ea1a 885 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
NYX 0:85b3fd62ea1a 886 } MPU_Type;
NYX 0:85b3fd62ea1a 887
NYX 0:85b3fd62ea1a 888 /* MPU Type Register Definitions */
NYX 0:85b3fd62ea1a 889 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
NYX 0:85b3fd62ea1a 890 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
NYX 0:85b3fd62ea1a 891
NYX 0:85b3fd62ea1a 892 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
NYX 0:85b3fd62ea1a 893 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
NYX 0:85b3fd62ea1a 894
NYX 0:85b3fd62ea1a 895 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
NYX 0:85b3fd62ea1a 896 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
NYX 0:85b3fd62ea1a 897
NYX 0:85b3fd62ea1a 898 /* MPU Control Register Definitions */
NYX 0:85b3fd62ea1a 899 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
NYX 0:85b3fd62ea1a 900 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
NYX 0:85b3fd62ea1a 901
NYX 0:85b3fd62ea1a 902 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
NYX 0:85b3fd62ea1a 903 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
NYX 0:85b3fd62ea1a 904
NYX 0:85b3fd62ea1a 905 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
NYX 0:85b3fd62ea1a 906 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
NYX 0:85b3fd62ea1a 907
NYX 0:85b3fd62ea1a 908 /* MPU Region Number Register Definitions */
NYX 0:85b3fd62ea1a 909 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
NYX 0:85b3fd62ea1a 910 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
NYX 0:85b3fd62ea1a 911
NYX 0:85b3fd62ea1a 912 /* MPU Region Base Address Register Definitions */
NYX 0:85b3fd62ea1a 913 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
NYX 0:85b3fd62ea1a 914 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
NYX 0:85b3fd62ea1a 915
NYX 0:85b3fd62ea1a 916 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
NYX 0:85b3fd62ea1a 917 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
NYX 0:85b3fd62ea1a 918
NYX 0:85b3fd62ea1a 919 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
NYX 0:85b3fd62ea1a 920 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
NYX 0:85b3fd62ea1a 921
NYX 0:85b3fd62ea1a 922 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
NYX 0:85b3fd62ea1a 923 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
NYX 0:85b3fd62ea1a 924
NYX 0:85b3fd62ea1a 925 /* MPU Region Limit Address Register Definitions */
NYX 0:85b3fd62ea1a 926 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
NYX 0:85b3fd62ea1a 927 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
NYX 0:85b3fd62ea1a 928
NYX 0:85b3fd62ea1a 929 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
NYX 0:85b3fd62ea1a 930 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
NYX 0:85b3fd62ea1a 931
NYX 0:85b3fd62ea1a 932 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
NYX 0:85b3fd62ea1a 933 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
NYX 0:85b3fd62ea1a 934
NYX 0:85b3fd62ea1a 935 /* MPU Memory Attribute Indirection Register 0 Definitions */
NYX 0:85b3fd62ea1a 936 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
NYX 0:85b3fd62ea1a 937 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
NYX 0:85b3fd62ea1a 938
NYX 0:85b3fd62ea1a 939 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
NYX 0:85b3fd62ea1a 940 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
NYX 0:85b3fd62ea1a 941
NYX 0:85b3fd62ea1a 942 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
NYX 0:85b3fd62ea1a 943 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
NYX 0:85b3fd62ea1a 944
NYX 0:85b3fd62ea1a 945 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
NYX 0:85b3fd62ea1a 946 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
NYX 0:85b3fd62ea1a 947
NYX 0:85b3fd62ea1a 948 /* MPU Memory Attribute Indirection Register 1 Definitions */
NYX 0:85b3fd62ea1a 949 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
NYX 0:85b3fd62ea1a 950 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
NYX 0:85b3fd62ea1a 951
NYX 0:85b3fd62ea1a 952 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
NYX 0:85b3fd62ea1a 953 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
NYX 0:85b3fd62ea1a 954
NYX 0:85b3fd62ea1a 955 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
NYX 0:85b3fd62ea1a 956 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
NYX 0:85b3fd62ea1a 957
NYX 0:85b3fd62ea1a 958 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
NYX 0:85b3fd62ea1a 959 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
NYX 0:85b3fd62ea1a 960
NYX 0:85b3fd62ea1a 961 /*@} end of group CMSIS_MPU */
NYX 0:85b3fd62ea1a 962 #endif
NYX 0:85b3fd62ea1a 963
NYX 0:85b3fd62ea1a 964
NYX 0:85b3fd62ea1a 965 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX 0:85b3fd62ea1a 966 /**
NYX 0:85b3fd62ea1a 967 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 968 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
NYX 0:85b3fd62ea1a 969 \brief Type definitions for the Security Attribution Unit (SAU)
NYX 0:85b3fd62ea1a 970 @{
NYX 0:85b3fd62ea1a 971 */
NYX 0:85b3fd62ea1a 972
NYX 0:85b3fd62ea1a 973 /**
NYX 0:85b3fd62ea1a 974 \brief Structure type to access the Security Attribution Unit (SAU).
NYX 0:85b3fd62ea1a 975 */
NYX 0:85b3fd62ea1a 976 typedef struct
NYX 0:85b3fd62ea1a 977 {
NYX 0:85b3fd62ea1a 978 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
NYX 0:85b3fd62ea1a 979 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
NYX 0:85b3fd62ea1a 980 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
NYX 0:85b3fd62ea1a 981 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
NYX 0:85b3fd62ea1a 982 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
NYX 0:85b3fd62ea1a 983 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
NYX 0:85b3fd62ea1a 984 #endif
NYX 0:85b3fd62ea1a 985 } SAU_Type;
NYX 0:85b3fd62ea1a 986
NYX 0:85b3fd62ea1a 987 /* SAU Control Register Definitions */
NYX 0:85b3fd62ea1a 988 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
NYX 0:85b3fd62ea1a 989 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
NYX 0:85b3fd62ea1a 990
NYX 0:85b3fd62ea1a 991 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
NYX 0:85b3fd62ea1a 992 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
NYX 0:85b3fd62ea1a 993
NYX 0:85b3fd62ea1a 994 /* SAU Type Register Definitions */
NYX 0:85b3fd62ea1a 995 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
NYX 0:85b3fd62ea1a 996 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
NYX 0:85b3fd62ea1a 997
NYX 0:85b3fd62ea1a 998 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
NYX 0:85b3fd62ea1a 999 /* SAU Region Number Register Definitions */
NYX 0:85b3fd62ea1a 1000 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
NYX 0:85b3fd62ea1a 1001 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
NYX 0:85b3fd62ea1a 1002
NYX 0:85b3fd62ea1a 1003 /* SAU Region Base Address Register Definitions */
NYX 0:85b3fd62ea1a 1004 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
NYX 0:85b3fd62ea1a 1005 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
NYX 0:85b3fd62ea1a 1006
NYX 0:85b3fd62ea1a 1007 /* SAU Region Limit Address Register Definitions */
NYX 0:85b3fd62ea1a 1008 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
NYX 0:85b3fd62ea1a 1009 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
NYX 0:85b3fd62ea1a 1010
NYX 0:85b3fd62ea1a 1011 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
NYX 0:85b3fd62ea1a 1012 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
NYX 0:85b3fd62ea1a 1013
NYX 0:85b3fd62ea1a 1014 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
NYX 0:85b3fd62ea1a 1015 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
NYX 0:85b3fd62ea1a 1016
NYX 0:85b3fd62ea1a 1017 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
NYX 0:85b3fd62ea1a 1018
NYX 0:85b3fd62ea1a 1019 /*@} end of group CMSIS_SAU */
NYX 0:85b3fd62ea1a 1020 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX 0:85b3fd62ea1a 1021
NYX 0:85b3fd62ea1a 1022
NYX 0:85b3fd62ea1a 1023 /**
NYX 0:85b3fd62ea1a 1024 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 1025 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
NYX 0:85b3fd62ea1a 1026 \brief Type definitions for the Core Debug Registers
NYX 0:85b3fd62ea1a 1027 @{
NYX 0:85b3fd62ea1a 1028 */
NYX 0:85b3fd62ea1a 1029
NYX 0:85b3fd62ea1a 1030 /**
NYX 0:85b3fd62ea1a 1031 \brief Structure type to access the Core Debug Register (CoreDebug).
NYX 0:85b3fd62ea1a 1032 */
NYX 0:85b3fd62ea1a 1033 typedef struct
NYX 0:85b3fd62ea1a 1034 {
NYX 0:85b3fd62ea1a 1035 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
NYX 0:85b3fd62ea1a 1036 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
NYX 0:85b3fd62ea1a 1037 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
NYX 0:85b3fd62ea1a 1038 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
NYX 0:85b3fd62ea1a 1039 uint32_t RESERVED4[1U];
NYX 0:85b3fd62ea1a 1040 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
NYX 0:85b3fd62ea1a 1041 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
NYX 0:85b3fd62ea1a 1042 } CoreDebug_Type;
NYX 0:85b3fd62ea1a 1043
NYX 0:85b3fd62ea1a 1044 /* Debug Halting Control and Status Register Definitions */
NYX 0:85b3fd62ea1a 1045 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
NYX 0:85b3fd62ea1a 1046 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
NYX 0:85b3fd62ea1a 1047
NYX 0:85b3fd62ea1a 1048 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
NYX 0:85b3fd62ea1a 1049 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
NYX 0:85b3fd62ea1a 1050
NYX 0:85b3fd62ea1a 1051 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
NYX 0:85b3fd62ea1a 1052 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
NYX 0:85b3fd62ea1a 1053
NYX 0:85b3fd62ea1a 1054 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
NYX 0:85b3fd62ea1a 1055 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
NYX 0:85b3fd62ea1a 1056
NYX 0:85b3fd62ea1a 1057 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
NYX 0:85b3fd62ea1a 1058 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
NYX 0:85b3fd62ea1a 1059
NYX 0:85b3fd62ea1a 1060 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
NYX 0:85b3fd62ea1a 1061 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
NYX 0:85b3fd62ea1a 1062
NYX 0:85b3fd62ea1a 1063 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
NYX 0:85b3fd62ea1a 1064 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
NYX 0:85b3fd62ea1a 1065
NYX 0:85b3fd62ea1a 1066 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
NYX 0:85b3fd62ea1a 1067 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
NYX 0:85b3fd62ea1a 1068
NYX 0:85b3fd62ea1a 1069 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
NYX 0:85b3fd62ea1a 1070 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
NYX 0:85b3fd62ea1a 1071
NYX 0:85b3fd62ea1a 1072 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
NYX 0:85b3fd62ea1a 1073 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
NYX 0:85b3fd62ea1a 1074
NYX 0:85b3fd62ea1a 1075 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
NYX 0:85b3fd62ea1a 1076 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
NYX 0:85b3fd62ea1a 1077
NYX 0:85b3fd62ea1a 1078 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
NYX 0:85b3fd62ea1a 1079 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
NYX 0:85b3fd62ea1a 1080
NYX 0:85b3fd62ea1a 1081 /* Debug Core Register Selector Register Definitions */
NYX 0:85b3fd62ea1a 1082 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
NYX 0:85b3fd62ea1a 1083 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
NYX 0:85b3fd62ea1a 1084
NYX 0:85b3fd62ea1a 1085 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
NYX 0:85b3fd62ea1a 1086 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
NYX 0:85b3fd62ea1a 1087
NYX 0:85b3fd62ea1a 1088 /* Debug Exception and Monitor Control Register */
NYX 0:85b3fd62ea1a 1089 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
NYX 0:85b3fd62ea1a 1090 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
NYX 0:85b3fd62ea1a 1091
NYX 0:85b3fd62ea1a 1092 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
NYX 0:85b3fd62ea1a 1093 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
NYX 0:85b3fd62ea1a 1094
NYX 0:85b3fd62ea1a 1095 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
NYX 0:85b3fd62ea1a 1096 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
NYX 0:85b3fd62ea1a 1097
NYX 0:85b3fd62ea1a 1098 /* Debug Authentication Control Register Definitions */
NYX 0:85b3fd62ea1a 1099 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
NYX 0:85b3fd62ea1a 1100 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
NYX 0:85b3fd62ea1a 1101
NYX 0:85b3fd62ea1a 1102 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
NYX 0:85b3fd62ea1a 1103 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
NYX 0:85b3fd62ea1a 1104
NYX 0:85b3fd62ea1a 1105 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
NYX 0:85b3fd62ea1a 1106 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
NYX 0:85b3fd62ea1a 1107
NYX 0:85b3fd62ea1a 1108 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
NYX 0:85b3fd62ea1a 1109 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
NYX 0:85b3fd62ea1a 1110
NYX 0:85b3fd62ea1a 1111 /* Debug Security Control and Status Register Definitions */
NYX 0:85b3fd62ea1a 1112 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
NYX 0:85b3fd62ea1a 1113 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
NYX 0:85b3fd62ea1a 1114
NYX 0:85b3fd62ea1a 1115 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
NYX 0:85b3fd62ea1a 1116 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
NYX 0:85b3fd62ea1a 1117
NYX 0:85b3fd62ea1a 1118 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
NYX 0:85b3fd62ea1a 1119 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
NYX 0:85b3fd62ea1a 1120
NYX 0:85b3fd62ea1a 1121 /*@} end of group CMSIS_CoreDebug */
NYX 0:85b3fd62ea1a 1122
NYX 0:85b3fd62ea1a 1123
NYX 0:85b3fd62ea1a 1124 /**
NYX 0:85b3fd62ea1a 1125 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 1126 \defgroup CMSIS_core_bitfield Core register bit field macros
NYX 0:85b3fd62ea1a 1127 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
NYX 0:85b3fd62ea1a 1128 @{
NYX 0:85b3fd62ea1a 1129 */
NYX 0:85b3fd62ea1a 1130
NYX 0:85b3fd62ea1a 1131 /**
NYX 0:85b3fd62ea1a 1132 \brief Mask and shift a bit field value for use in a register bit range.
NYX 0:85b3fd62ea1a 1133 \param[in] field Name of the register bit field.
NYX 0:85b3fd62ea1a 1134 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
NYX 0:85b3fd62ea1a 1135 \return Masked and shifted value.
NYX 0:85b3fd62ea1a 1136 */
NYX 0:85b3fd62ea1a 1137 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
NYX 0:85b3fd62ea1a 1138
NYX 0:85b3fd62ea1a 1139 /**
NYX 0:85b3fd62ea1a 1140 \brief Mask and shift a register value to extract a bit filed value.
NYX 0:85b3fd62ea1a 1141 \param[in] field Name of the register bit field.
NYX 0:85b3fd62ea1a 1142 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
NYX 0:85b3fd62ea1a 1143 \return Masked and shifted bit field value.
NYX 0:85b3fd62ea1a 1144 */
NYX 0:85b3fd62ea1a 1145 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
NYX 0:85b3fd62ea1a 1146
NYX 0:85b3fd62ea1a 1147 /*@} end of group CMSIS_core_bitfield */
NYX 0:85b3fd62ea1a 1148
NYX 0:85b3fd62ea1a 1149
NYX 0:85b3fd62ea1a 1150 /**
NYX 0:85b3fd62ea1a 1151 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 1152 \defgroup CMSIS_core_base Core Definitions
NYX 0:85b3fd62ea1a 1153 \brief Definitions for base addresses, unions, and structures.
NYX 0:85b3fd62ea1a 1154 @{
NYX 0:85b3fd62ea1a 1155 */
NYX 0:85b3fd62ea1a 1156
NYX 0:85b3fd62ea1a 1157 /* Memory mapping of Core Hardware */
NYX 0:85b3fd62ea1a 1158 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
NYX 0:85b3fd62ea1a 1159 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
NYX 0:85b3fd62ea1a 1160 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
NYX 0:85b3fd62ea1a 1161 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
NYX 0:85b3fd62ea1a 1162 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
NYX 0:85b3fd62ea1a 1163 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
NYX 0:85b3fd62ea1a 1164 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
NYX 0:85b3fd62ea1a 1165
NYX 0:85b3fd62ea1a 1166
NYX 0:85b3fd62ea1a 1167 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
NYX 0:85b3fd62ea1a 1168 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
NYX 0:85b3fd62ea1a 1169 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
NYX 0:85b3fd62ea1a 1170 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
NYX 0:85b3fd62ea1a 1171 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
NYX 0:85b3fd62ea1a 1172 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
NYX 0:85b3fd62ea1a 1173
NYX 0:85b3fd62ea1a 1174 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 1175 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
NYX 0:85b3fd62ea1a 1176 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
NYX 0:85b3fd62ea1a 1177 #endif
NYX 0:85b3fd62ea1a 1178
NYX 0:85b3fd62ea1a 1179 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX 0:85b3fd62ea1a 1180 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
NYX 0:85b3fd62ea1a 1181 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
NYX 0:85b3fd62ea1a 1182 #endif
NYX 0:85b3fd62ea1a 1183
NYX 0:85b3fd62ea1a 1184 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX 0:85b3fd62ea1a 1185 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
NYX 0:85b3fd62ea1a 1186 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
NYX 0:85b3fd62ea1a 1187 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
NYX 0:85b3fd62ea1a 1188 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
NYX 0:85b3fd62ea1a 1189 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
NYX 0:85b3fd62ea1a 1190
NYX 0:85b3fd62ea1a 1191 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
NYX 0:85b3fd62ea1a 1192 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
NYX 0:85b3fd62ea1a 1193 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
NYX 0:85b3fd62ea1a 1194 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
NYX 0:85b3fd62ea1a 1195
NYX 0:85b3fd62ea1a 1196 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 1197 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
NYX 0:85b3fd62ea1a 1198 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
NYX 0:85b3fd62ea1a 1199 #endif
NYX 0:85b3fd62ea1a 1200
NYX 0:85b3fd62ea1a 1201 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX 0:85b3fd62ea1a 1202 /*@} */
NYX 0:85b3fd62ea1a 1203
NYX 0:85b3fd62ea1a 1204
NYX 0:85b3fd62ea1a 1205
NYX 0:85b3fd62ea1a 1206 /*******************************************************************************
NYX 0:85b3fd62ea1a 1207 * Hardware Abstraction Layer
NYX 0:85b3fd62ea1a 1208 Core Function Interface contains:
NYX 0:85b3fd62ea1a 1209 - Core NVIC Functions
NYX 0:85b3fd62ea1a 1210 - Core SysTick Functions
NYX 0:85b3fd62ea1a 1211 - Core Register Access Functions
NYX 0:85b3fd62ea1a 1212 ******************************************************************************/
NYX 0:85b3fd62ea1a 1213 /**
NYX 0:85b3fd62ea1a 1214 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
NYX 0:85b3fd62ea1a 1215 */
NYX 0:85b3fd62ea1a 1216
NYX 0:85b3fd62ea1a 1217
NYX 0:85b3fd62ea1a 1218
NYX 0:85b3fd62ea1a 1219 /* ########################## NVIC functions #################################### */
NYX 0:85b3fd62ea1a 1220 /**
NYX 0:85b3fd62ea1a 1221 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 1222 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
NYX 0:85b3fd62ea1a 1223 \brief Functions that manage interrupts and exceptions via the NVIC.
NYX 0:85b3fd62ea1a 1224 @{
NYX 0:85b3fd62ea1a 1225 */
NYX 0:85b3fd62ea1a 1226
NYX 0:85b3fd62ea1a 1227 #ifdef CMSIS_NVIC_VIRTUAL
NYX 0:85b3fd62ea1a 1228 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 1229 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
NYX 0:85b3fd62ea1a 1230 #endif
NYX 0:85b3fd62ea1a 1231 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 1232 #else
NYX 0:85b3fd62ea1a 1233 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
NYX 0:85b3fd62ea1a 1234 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
NYX 0:85b3fd62ea1a 1235 #define NVIC_EnableIRQ __NVIC_EnableIRQ
NYX 0:85b3fd62ea1a 1236 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
NYX 0:85b3fd62ea1a 1237 #define NVIC_DisableIRQ __NVIC_DisableIRQ
NYX 0:85b3fd62ea1a 1238 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
NYX 0:85b3fd62ea1a 1239 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
NYX 0:85b3fd62ea1a 1240 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
NYX 0:85b3fd62ea1a 1241 #define NVIC_GetActive __NVIC_GetActive
NYX 0:85b3fd62ea1a 1242 #define NVIC_SetPriority __NVIC_SetPriority
NYX 0:85b3fd62ea1a 1243 #define NVIC_GetPriority __NVIC_GetPriority
NYX 0:85b3fd62ea1a 1244 #define NVIC_SystemReset __NVIC_SystemReset
NYX 0:85b3fd62ea1a 1245 #endif /* CMSIS_NVIC_VIRTUAL */
NYX 0:85b3fd62ea1a 1246
NYX 0:85b3fd62ea1a 1247 #ifdef CMSIS_VECTAB_VIRTUAL
NYX 0:85b3fd62ea1a 1248 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 1249 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
NYX 0:85b3fd62ea1a 1250 #endif
NYX 0:85b3fd62ea1a 1251 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 1252 #else
NYX 0:85b3fd62ea1a 1253 #define NVIC_SetVector __NVIC_SetVector
NYX 0:85b3fd62ea1a 1254 #define NVIC_GetVector __NVIC_GetVector
NYX 0:85b3fd62ea1a 1255 #endif /* (CMSIS_VECTAB_VIRTUAL) */
NYX 0:85b3fd62ea1a 1256
NYX 0:85b3fd62ea1a 1257 #define NVIC_USER_IRQ_OFFSET 16
NYX 0:85b3fd62ea1a 1258
NYX 0:85b3fd62ea1a 1259
NYX 0:85b3fd62ea1a 1260 /* Interrupt Priorities are WORD accessible only under ARMv6M */
NYX 0:85b3fd62ea1a 1261 /* The following MACROS handle generation of the register offset and byte masks */
NYX 0:85b3fd62ea1a 1262 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
NYX 0:85b3fd62ea1a 1263 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
NYX 0:85b3fd62ea1a 1264 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
NYX 0:85b3fd62ea1a 1265
NYX 0:85b3fd62ea1a 1266
NYX 0:85b3fd62ea1a 1267 /**
NYX 0:85b3fd62ea1a 1268 \brief Enable Interrupt
NYX 0:85b3fd62ea1a 1269 \details Enables a device specific interrupt in the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 1270 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1271 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1272 */
NYX 0:85b3fd62ea1a 1273 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1274 {
NYX 0:85b3fd62ea1a 1275 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1276 {
NYX 0:85b3fd62ea1a 1277 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 1278 }
NYX 0:85b3fd62ea1a 1279 }
NYX 0:85b3fd62ea1a 1280
NYX 0:85b3fd62ea1a 1281
NYX 0:85b3fd62ea1a 1282 /**
NYX 0:85b3fd62ea1a 1283 \brief Get Interrupt Enable status
NYX 0:85b3fd62ea1a 1284 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 1285 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1286 \return 0 Interrupt is not enabled.
NYX 0:85b3fd62ea1a 1287 \return 1 Interrupt is enabled.
NYX 0:85b3fd62ea1a 1288 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1289 */
NYX 0:85b3fd62ea1a 1290 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1291 {
NYX 0:85b3fd62ea1a 1292 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1293 {
NYX 0:85b3fd62ea1a 1294 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1295 }
NYX 0:85b3fd62ea1a 1296 else
NYX 0:85b3fd62ea1a 1297 {
NYX 0:85b3fd62ea1a 1298 return(0U);
NYX 0:85b3fd62ea1a 1299 }
NYX 0:85b3fd62ea1a 1300 }
NYX 0:85b3fd62ea1a 1301
NYX 0:85b3fd62ea1a 1302
NYX 0:85b3fd62ea1a 1303 /**
NYX 0:85b3fd62ea1a 1304 \brief Disable Interrupt
NYX 0:85b3fd62ea1a 1305 \details Disables a device specific interrupt in the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 1306 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1307 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1308 */
NYX 0:85b3fd62ea1a 1309 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1310 {
NYX 0:85b3fd62ea1a 1311 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1312 {
NYX 0:85b3fd62ea1a 1313 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 1314 __DSB();
NYX 0:85b3fd62ea1a 1315 __ISB();
NYX 0:85b3fd62ea1a 1316 }
NYX 0:85b3fd62ea1a 1317 }
NYX 0:85b3fd62ea1a 1318
NYX 0:85b3fd62ea1a 1319
NYX 0:85b3fd62ea1a 1320 /**
NYX 0:85b3fd62ea1a 1321 \brief Get Pending Interrupt
NYX 0:85b3fd62ea1a 1322 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
NYX 0:85b3fd62ea1a 1323 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1324 \return 0 Interrupt status is not pending.
NYX 0:85b3fd62ea1a 1325 \return 1 Interrupt status is pending.
NYX 0:85b3fd62ea1a 1326 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1327 */
NYX 0:85b3fd62ea1a 1328 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1329 {
NYX 0:85b3fd62ea1a 1330 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1331 {
NYX 0:85b3fd62ea1a 1332 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1333 }
NYX 0:85b3fd62ea1a 1334 else
NYX 0:85b3fd62ea1a 1335 {
NYX 0:85b3fd62ea1a 1336 return(0U);
NYX 0:85b3fd62ea1a 1337 }
NYX 0:85b3fd62ea1a 1338 }
NYX 0:85b3fd62ea1a 1339
NYX 0:85b3fd62ea1a 1340
NYX 0:85b3fd62ea1a 1341 /**
NYX 0:85b3fd62ea1a 1342 \brief Set Pending Interrupt
NYX 0:85b3fd62ea1a 1343 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
NYX 0:85b3fd62ea1a 1344 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1345 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1346 */
NYX 0:85b3fd62ea1a 1347 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1348 {
NYX 0:85b3fd62ea1a 1349 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1350 {
NYX 0:85b3fd62ea1a 1351 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 1352 }
NYX 0:85b3fd62ea1a 1353 }
NYX 0:85b3fd62ea1a 1354
NYX 0:85b3fd62ea1a 1355
NYX 0:85b3fd62ea1a 1356 /**
NYX 0:85b3fd62ea1a 1357 \brief Clear Pending Interrupt
NYX 0:85b3fd62ea1a 1358 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
NYX 0:85b3fd62ea1a 1359 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1360 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1361 */
NYX 0:85b3fd62ea1a 1362 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1363 {
NYX 0:85b3fd62ea1a 1364 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1365 {
NYX 0:85b3fd62ea1a 1366 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 1367 }
NYX 0:85b3fd62ea1a 1368 }
NYX 0:85b3fd62ea1a 1369
NYX 0:85b3fd62ea1a 1370
NYX 0:85b3fd62ea1a 1371 /**
NYX 0:85b3fd62ea1a 1372 \brief Get Active Interrupt
NYX 0:85b3fd62ea1a 1373 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
NYX 0:85b3fd62ea1a 1374 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1375 \return 0 Interrupt status is not active.
NYX 0:85b3fd62ea1a 1376 \return 1 Interrupt status is active.
NYX 0:85b3fd62ea1a 1377 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1378 */
NYX 0:85b3fd62ea1a 1379 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1380 {
NYX 0:85b3fd62ea1a 1381 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1382 {
NYX 0:85b3fd62ea1a 1383 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1384 }
NYX 0:85b3fd62ea1a 1385 else
NYX 0:85b3fd62ea1a 1386 {
NYX 0:85b3fd62ea1a 1387 return(0U);
NYX 0:85b3fd62ea1a 1388 }
NYX 0:85b3fd62ea1a 1389 }
NYX 0:85b3fd62ea1a 1390
NYX 0:85b3fd62ea1a 1391
NYX 0:85b3fd62ea1a 1392 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX 0:85b3fd62ea1a 1393 /**
NYX 0:85b3fd62ea1a 1394 \brief Get Interrupt Target State
NYX 0:85b3fd62ea1a 1395 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
NYX 0:85b3fd62ea1a 1396 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1397 \return 0 if interrupt is assigned to Secure
NYX 0:85b3fd62ea1a 1398 \return 1 if interrupt is assigned to Non Secure
NYX 0:85b3fd62ea1a 1399 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1400 */
NYX 0:85b3fd62ea1a 1401 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1402 {
NYX 0:85b3fd62ea1a 1403 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1404 {
NYX 0:85b3fd62ea1a 1405 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1406 }
NYX 0:85b3fd62ea1a 1407 else
NYX 0:85b3fd62ea1a 1408 {
NYX 0:85b3fd62ea1a 1409 return(0U);
NYX 0:85b3fd62ea1a 1410 }
NYX 0:85b3fd62ea1a 1411 }
NYX 0:85b3fd62ea1a 1412
NYX 0:85b3fd62ea1a 1413
NYX 0:85b3fd62ea1a 1414 /**
NYX 0:85b3fd62ea1a 1415 \brief Set Interrupt Target State
NYX 0:85b3fd62ea1a 1416 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
NYX 0:85b3fd62ea1a 1417 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1418 \return 0 if interrupt is assigned to Secure
NYX 0:85b3fd62ea1a 1419 1 if interrupt is assigned to Non Secure
NYX 0:85b3fd62ea1a 1420 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1421 */
NYX 0:85b3fd62ea1a 1422 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1423 {
NYX 0:85b3fd62ea1a 1424 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1425 {
NYX 0:85b3fd62ea1a 1426 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
NYX 0:85b3fd62ea1a 1427 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1428 }
NYX 0:85b3fd62ea1a 1429 else
NYX 0:85b3fd62ea1a 1430 {
NYX 0:85b3fd62ea1a 1431 return(0U);
NYX 0:85b3fd62ea1a 1432 }
NYX 0:85b3fd62ea1a 1433 }
NYX 0:85b3fd62ea1a 1434
NYX 0:85b3fd62ea1a 1435
NYX 0:85b3fd62ea1a 1436 /**
NYX 0:85b3fd62ea1a 1437 \brief Clear Interrupt Target State
NYX 0:85b3fd62ea1a 1438 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
NYX 0:85b3fd62ea1a 1439 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1440 \return 0 if interrupt is assigned to Secure
NYX 0:85b3fd62ea1a 1441 1 if interrupt is assigned to Non Secure
NYX 0:85b3fd62ea1a 1442 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1443 */
NYX 0:85b3fd62ea1a 1444 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1445 {
NYX 0:85b3fd62ea1a 1446 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1447 {
NYX 0:85b3fd62ea1a 1448 NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
NYX 0:85b3fd62ea1a 1449 return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1450 }
NYX 0:85b3fd62ea1a 1451 else
NYX 0:85b3fd62ea1a 1452 {
NYX 0:85b3fd62ea1a 1453 return(0U);
NYX 0:85b3fd62ea1a 1454 }
NYX 0:85b3fd62ea1a 1455 }
NYX 0:85b3fd62ea1a 1456 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX 0:85b3fd62ea1a 1457
NYX 0:85b3fd62ea1a 1458
NYX 0:85b3fd62ea1a 1459 /**
NYX 0:85b3fd62ea1a 1460 \brief Set Interrupt Priority
NYX 0:85b3fd62ea1a 1461 \details Sets the priority of a device specific interrupt or a processor exception.
NYX 0:85b3fd62ea1a 1462 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 1463 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 1464 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 1465 \param [in] priority Priority to set.
NYX 0:85b3fd62ea1a 1466 \note The priority cannot be set for every processor exception.
NYX 0:85b3fd62ea1a 1467 */
NYX 0:85b3fd62ea1a 1468 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
NYX 0:85b3fd62ea1a 1469 {
NYX 0:85b3fd62ea1a 1470 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1471 {
NYX 0:85b3fd62ea1a 1472 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
NYX 0:85b3fd62ea1a 1473 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NYX 0:85b3fd62ea1a 1474 }
NYX 0:85b3fd62ea1a 1475 else
NYX 0:85b3fd62ea1a 1476 {
NYX 0:85b3fd62ea1a 1477 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
NYX 0:85b3fd62ea1a 1478 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NYX 0:85b3fd62ea1a 1479 }
NYX 0:85b3fd62ea1a 1480 }
NYX 0:85b3fd62ea1a 1481
NYX 0:85b3fd62ea1a 1482
NYX 0:85b3fd62ea1a 1483 /**
NYX 0:85b3fd62ea1a 1484 \brief Get Interrupt Priority
NYX 0:85b3fd62ea1a 1485 \details Reads the priority of a device specific interrupt or a processor exception.
NYX 0:85b3fd62ea1a 1486 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 1487 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 1488 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 1489 \return Interrupt Priority.
NYX 0:85b3fd62ea1a 1490 Value is aligned automatically to the implemented priority bits of the microcontroller.
NYX 0:85b3fd62ea1a 1491 */
NYX 0:85b3fd62ea1a 1492 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1493 {
NYX 0:85b3fd62ea1a 1494
NYX 0:85b3fd62ea1a 1495 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1496 {
NYX 0:85b3fd62ea1a 1497 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
NYX 0:85b3fd62ea1a 1498 }
NYX 0:85b3fd62ea1a 1499 else
NYX 0:85b3fd62ea1a 1500 {
NYX 0:85b3fd62ea1a 1501 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
NYX 0:85b3fd62ea1a 1502 }
NYX 0:85b3fd62ea1a 1503 }
NYX 0:85b3fd62ea1a 1504
NYX 0:85b3fd62ea1a 1505
NYX 0:85b3fd62ea1a 1506 /**
NYX 0:85b3fd62ea1a 1507 \brief Set Interrupt Vector
NYX 0:85b3fd62ea1a 1508 \details Sets an interrupt vector in SRAM based interrupt vector table.
NYX 0:85b3fd62ea1a 1509 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 1510 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 1511 VTOR must been relocated to SRAM before.
NYX 0:85b3fd62ea1a 1512 If VTOR is not present address 0 must be mapped to SRAM.
NYX 0:85b3fd62ea1a 1513 \param [in] IRQn Interrupt number
NYX 0:85b3fd62ea1a 1514 \param [in] vector Address of interrupt handler function
NYX 0:85b3fd62ea1a 1515 */
NYX 0:85b3fd62ea1a 1516 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
NYX 0:85b3fd62ea1a 1517 {
NYX 0:85b3fd62ea1a 1518 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
NYX 0:85b3fd62ea1a 1519 uint32_t *vectors = (uint32_t *)SCB->VTOR;
NYX 0:85b3fd62ea1a 1520 #else
NYX 0:85b3fd62ea1a 1521 uint32_t *vectors = (uint32_t *)0x0U;
NYX 0:85b3fd62ea1a 1522 #endif
NYX 0:85b3fd62ea1a 1523 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
NYX 0:85b3fd62ea1a 1524 }
NYX 0:85b3fd62ea1a 1525
NYX 0:85b3fd62ea1a 1526
NYX 0:85b3fd62ea1a 1527 /**
NYX 0:85b3fd62ea1a 1528 \brief Get Interrupt Vector
NYX 0:85b3fd62ea1a 1529 \details Reads an interrupt vector from interrupt vector table.
NYX 0:85b3fd62ea1a 1530 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 1531 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 1532 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 1533 \return Address of interrupt handler function
NYX 0:85b3fd62ea1a 1534 */
NYX 0:85b3fd62ea1a 1535 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1536 {
NYX 0:85b3fd62ea1a 1537 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
NYX 0:85b3fd62ea1a 1538 uint32_t *vectors = (uint32_t *)SCB->VTOR;
NYX 0:85b3fd62ea1a 1539 #else
NYX 0:85b3fd62ea1a 1540 uint32_t *vectors = (uint32_t *)0x0U;
NYX 0:85b3fd62ea1a 1541 #endif
NYX 0:85b3fd62ea1a 1542 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
NYX 0:85b3fd62ea1a 1543 }
NYX 0:85b3fd62ea1a 1544
NYX 0:85b3fd62ea1a 1545
NYX 0:85b3fd62ea1a 1546 /**
NYX 0:85b3fd62ea1a 1547 \brief System Reset
NYX 0:85b3fd62ea1a 1548 \details Initiates a system reset request to reset the MCU.
NYX 0:85b3fd62ea1a 1549 */
NYX 0:85b3fd62ea1a 1550 __STATIC_INLINE void __NVIC_SystemReset(void)
NYX 0:85b3fd62ea1a 1551 {
NYX 0:85b3fd62ea1a 1552 __DSB(); /* Ensure all outstanding memory accesses included
NYX 0:85b3fd62ea1a 1553 buffered write are completed before reset */
NYX 0:85b3fd62ea1a 1554 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
NYX 0:85b3fd62ea1a 1555 SCB_AIRCR_SYSRESETREQ_Msk);
NYX 0:85b3fd62ea1a 1556 __DSB(); /* Ensure completion of memory access */
NYX 0:85b3fd62ea1a 1557
NYX 0:85b3fd62ea1a 1558 for(;;) /* wait until reset */
NYX 0:85b3fd62ea1a 1559 {
NYX 0:85b3fd62ea1a 1560 __NOP();
NYX 0:85b3fd62ea1a 1561 }
NYX 0:85b3fd62ea1a 1562 }
NYX 0:85b3fd62ea1a 1563
NYX 0:85b3fd62ea1a 1564 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX 0:85b3fd62ea1a 1565 /**
NYX 0:85b3fd62ea1a 1566 \brief Enable Interrupt (non-secure)
NYX 0:85b3fd62ea1a 1567 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
NYX 0:85b3fd62ea1a 1568 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1569 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1570 */
NYX 0:85b3fd62ea1a 1571 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1572 {
NYX 0:85b3fd62ea1a 1573 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1574 {
NYX 0:85b3fd62ea1a 1575 NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 1576 }
NYX 0:85b3fd62ea1a 1577 }
NYX 0:85b3fd62ea1a 1578
NYX 0:85b3fd62ea1a 1579
NYX 0:85b3fd62ea1a 1580 /**
NYX 0:85b3fd62ea1a 1581 \brief Get Interrupt Enable status (non-secure)
NYX 0:85b3fd62ea1a 1582 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
NYX 0:85b3fd62ea1a 1583 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1584 \return 0 Interrupt is not enabled.
NYX 0:85b3fd62ea1a 1585 \return 1 Interrupt is enabled.
NYX 0:85b3fd62ea1a 1586 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1587 */
NYX 0:85b3fd62ea1a 1588 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1589 {
NYX 0:85b3fd62ea1a 1590 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1591 {
NYX 0:85b3fd62ea1a 1592 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1593 }
NYX 0:85b3fd62ea1a 1594 else
NYX 0:85b3fd62ea1a 1595 {
NYX 0:85b3fd62ea1a 1596 return(0U);
NYX 0:85b3fd62ea1a 1597 }
NYX 0:85b3fd62ea1a 1598 }
NYX 0:85b3fd62ea1a 1599
NYX 0:85b3fd62ea1a 1600
NYX 0:85b3fd62ea1a 1601 /**
NYX 0:85b3fd62ea1a 1602 \brief Disable Interrupt (non-secure)
NYX 0:85b3fd62ea1a 1603 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
NYX 0:85b3fd62ea1a 1604 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1605 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1606 */
NYX 0:85b3fd62ea1a 1607 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1608 {
NYX 0:85b3fd62ea1a 1609 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1610 {
NYX 0:85b3fd62ea1a 1611 NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 1612 }
NYX 0:85b3fd62ea1a 1613 }
NYX 0:85b3fd62ea1a 1614
NYX 0:85b3fd62ea1a 1615
NYX 0:85b3fd62ea1a 1616 /**
NYX 0:85b3fd62ea1a 1617 \brief Get Pending Interrupt (non-secure)
NYX 0:85b3fd62ea1a 1618 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
NYX 0:85b3fd62ea1a 1619 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1620 \return 0 Interrupt status is not pending.
NYX 0:85b3fd62ea1a 1621 \return 1 Interrupt status is pending.
NYX 0:85b3fd62ea1a 1622 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1623 */
NYX 0:85b3fd62ea1a 1624 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1625 {
NYX 0:85b3fd62ea1a 1626 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1627 {
NYX 0:85b3fd62ea1a 1628 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1629 }
NYX 0:85b3fd62ea1a 1630 }
NYX 0:85b3fd62ea1a 1631
NYX 0:85b3fd62ea1a 1632
NYX 0:85b3fd62ea1a 1633 /**
NYX 0:85b3fd62ea1a 1634 \brief Set Pending Interrupt (non-secure)
NYX 0:85b3fd62ea1a 1635 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
NYX 0:85b3fd62ea1a 1636 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1637 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1638 */
NYX 0:85b3fd62ea1a 1639 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1640 {
NYX 0:85b3fd62ea1a 1641 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1642 {
NYX 0:85b3fd62ea1a 1643 NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 1644 }
NYX 0:85b3fd62ea1a 1645 }
NYX 0:85b3fd62ea1a 1646
NYX 0:85b3fd62ea1a 1647
NYX 0:85b3fd62ea1a 1648 /**
NYX 0:85b3fd62ea1a 1649 \brief Clear Pending Interrupt (non-secure)
NYX 0:85b3fd62ea1a 1650 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
NYX 0:85b3fd62ea1a 1651 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1652 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1653 */
NYX 0:85b3fd62ea1a 1654 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1655 {
NYX 0:85b3fd62ea1a 1656 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1657 {
NYX 0:85b3fd62ea1a 1658 NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 1659 }
NYX 0:85b3fd62ea1a 1660 }
NYX 0:85b3fd62ea1a 1661
NYX 0:85b3fd62ea1a 1662
NYX 0:85b3fd62ea1a 1663 /**
NYX 0:85b3fd62ea1a 1664 \brief Get Active Interrupt (non-secure)
NYX 0:85b3fd62ea1a 1665 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
NYX 0:85b3fd62ea1a 1666 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 1667 \return 0 Interrupt status is not active.
NYX 0:85b3fd62ea1a 1668 \return 1 Interrupt status is active.
NYX 0:85b3fd62ea1a 1669 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 1670 */
NYX 0:85b3fd62ea1a 1671 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1672 {
NYX 0:85b3fd62ea1a 1673 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1674 {
NYX 0:85b3fd62ea1a 1675 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 1676 }
NYX 0:85b3fd62ea1a 1677 else
NYX 0:85b3fd62ea1a 1678 {
NYX 0:85b3fd62ea1a 1679 return(0U);
NYX 0:85b3fd62ea1a 1680 }
NYX 0:85b3fd62ea1a 1681 }
NYX 0:85b3fd62ea1a 1682
NYX 0:85b3fd62ea1a 1683
NYX 0:85b3fd62ea1a 1684 /**
NYX 0:85b3fd62ea1a 1685 \brief Set Interrupt Priority (non-secure)
NYX 0:85b3fd62ea1a 1686 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
NYX 0:85b3fd62ea1a 1687 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 1688 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 1689 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 1690 \param [in] priority Priority to set.
NYX 0:85b3fd62ea1a 1691 \note The priority cannot be set for every non-secure processor exception.
NYX 0:85b3fd62ea1a 1692 */
NYX 0:85b3fd62ea1a 1693 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
NYX 0:85b3fd62ea1a 1694 {
NYX 0:85b3fd62ea1a 1695 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1696 {
NYX 0:85b3fd62ea1a 1697 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
NYX 0:85b3fd62ea1a 1698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NYX 0:85b3fd62ea1a 1699 }
NYX 0:85b3fd62ea1a 1700 else
NYX 0:85b3fd62ea1a 1701 {
NYX 0:85b3fd62ea1a 1702 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
NYX 0:85b3fd62ea1a 1703 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NYX 0:85b3fd62ea1a 1704 }
NYX 0:85b3fd62ea1a 1705 }
NYX 0:85b3fd62ea1a 1706
NYX 0:85b3fd62ea1a 1707
NYX 0:85b3fd62ea1a 1708 /**
NYX 0:85b3fd62ea1a 1709 \brief Get Interrupt Priority (non-secure)
NYX 0:85b3fd62ea1a 1710 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
NYX 0:85b3fd62ea1a 1711 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 1712 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 1713 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 1714 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
NYX 0:85b3fd62ea1a 1715 */
NYX 0:85b3fd62ea1a 1716 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 1717 {
NYX 0:85b3fd62ea1a 1718
NYX 0:85b3fd62ea1a 1719 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 1720 {
NYX 0:85b3fd62ea1a 1721 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
NYX 0:85b3fd62ea1a 1722 }
NYX 0:85b3fd62ea1a 1723 else
NYX 0:85b3fd62ea1a 1724 {
NYX 0:85b3fd62ea1a 1725 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
NYX 0:85b3fd62ea1a 1726 }
NYX 0:85b3fd62ea1a 1727 }
NYX 0:85b3fd62ea1a 1728 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
NYX 0:85b3fd62ea1a 1729
NYX 0:85b3fd62ea1a 1730 /*@} end of CMSIS_Core_NVICFunctions */
NYX 0:85b3fd62ea1a 1731
NYX 0:85b3fd62ea1a 1732
NYX 0:85b3fd62ea1a 1733 /* ########################## FPU functions #################################### */
NYX 0:85b3fd62ea1a 1734 /**
NYX 0:85b3fd62ea1a 1735 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 1736 \defgroup CMSIS_Core_FpuFunctions FPU Functions
NYX 0:85b3fd62ea1a 1737 \brief Function that provides FPU type.
NYX 0:85b3fd62ea1a 1738 @{
NYX 0:85b3fd62ea1a 1739 */
NYX 0:85b3fd62ea1a 1740
NYX 0:85b3fd62ea1a 1741 /**
NYX 0:85b3fd62ea1a 1742 \brief get FPU type
NYX 0:85b3fd62ea1a 1743 \details returns the FPU type
NYX 0:85b3fd62ea1a 1744 \returns
NYX 0:85b3fd62ea1a 1745 - \b 0: No FPU
NYX 0:85b3fd62ea1a 1746 - \b 1: Single precision FPU
NYX 0:85b3fd62ea1a 1747 - \b 2: Double + Single precision FPU
NYX 0:85b3fd62ea1a 1748 */
NYX 0:85b3fd62ea1a 1749 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
NYX 0:85b3fd62ea1a 1750 {
NYX 0:85b3fd62ea1a 1751 return 0U; /* No FPU */
NYX 0:85b3fd62ea1a 1752 }
NYX 0:85b3fd62ea1a 1753
NYX 0:85b3fd62ea1a 1754
NYX 0:85b3fd62ea1a 1755 /*@} end of CMSIS_Core_FpuFunctions */
NYX 0:85b3fd62ea1a 1756
NYX 0:85b3fd62ea1a 1757
NYX 0:85b3fd62ea1a 1758
NYX 0:85b3fd62ea1a 1759 /* ########################## SAU functions #################################### */
NYX 0:85b3fd62ea1a 1760 /**
NYX 0:85b3fd62ea1a 1761 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 1762 \defgroup CMSIS_Core_SAUFunctions SAU Functions
NYX 0:85b3fd62ea1a 1763 \brief Functions that configure the SAU.
NYX 0:85b3fd62ea1a 1764 @{
NYX 0:85b3fd62ea1a 1765 */
NYX 0:85b3fd62ea1a 1766
NYX 0:85b3fd62ea1a 1767 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX 0:85b3fd62ea1a 1768
NYX 0:85b3fd62ea1a 1769 /**
NYX 0:85b3fd62ea1a 1770 \brief Enable SAU
NYX 0:85b3fd62ea1a 1771 \details Enables the Security Attribution Unit (SAU).
NYX 0:85b3fd62ea1a 1772 */
NYX 0:85b3fd62ea1a 1773 __STATIC_INLINE void TZ_SAU_Enable(void)
NYX 0:85b3fd62ea1a 1774 {
NYX 0:85b3fd62ea1a 1775 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
NYX 0:85b3fd62ea1a 1776 }
NYX 0:85b3fd62ea1a 1777
NYX 0:85b3fd62ea1a 1778
NYX 0:85b3fd62ea1a 1779
NYX 0:85b3fd62ea1a 1780 /**
NYX 0:85b3fd62ea1a 1781 \brief Disable SAU
NYX 0:85b3fd62ea1a 1782 \details Disables the Security Attribution Unit (SAU).
NYX 0:85b3fd62ea1a 1783 */
NYX 0:85b3fd62ea1a 1784 __STATIC_INLINE void TZ_SAU_Disable(void)
NYX 0:85b3fd62ea1a 1785 {
NYX 0:85b3fd62ea1a 1786 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
NYX 0:85b3fd62ea1a 1787 }
NYX 0:85b3fd62ea1a 1788
NYX 0:85b3fd62ea1a 1789 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX 0:85b3fd62ea1a 1790
NYX 0:85b3fd62ea1a 1791 /*@} end of CMSIS_Core_SAUFunctions */
NYX 0:85b3fd62ea1a 1792
NYX 0:85b3fd62ea1a 1793
NYX 0:85b3fd62ea1a 1794
NYX 0:85b3fd62ea1a 1795
NYX 0:85b3fd62ea1a 1796 /* ################################## SysTick function ############################################ */
NYX 0:85b3fd62ea1a 1797 /**
NYX 0:85b3fd62ea1a 1798 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 1799 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
NYX 0:85b3fd62ea1a 1800 \brief Functions that configure the System.
NYX 0:85b3fd62ea1a 1801 @{
NYX 0:85b3fd62ea1a 1802 */
NYX 0:85b3fd62ea1a 1803
NYX 0:85b3fd62ea1a 1804 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
NYX 0:85b3fd62ea1a 1805
NYX 0:85b3fd62ea1a 1806 /**
NYX 0:85b3fd62ea1a 1807 \brief System Tick Configuration
NYX 0:85b3fd62ea1a 1808 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
NYX 0:85b3fd62ea1a 1809 Counter is in free running mode to generate periodic interrupts.
NYX 0:85b3fd62ea1a 1810 \param [in] ticks Number of ticks between two interrupts.
NYX 0:85b3fd62ea1a 1811 \return 0 Function succeeded.
NYX 0:85b3fd62ea1a 1812 \return 1 Function failed.
NYX 0:85b3fd62ea1a 1813 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
NYX 0:85b3fd62ea1a 1814 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
NYX 0:85b3fd62ea1a 1815 must contain a vendor-specific implementation of this function.
NYX 0:85b3fd62ea1a 1816 */
NYX 0:85b3fd62ea1a 1817 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
NYX 0:85b3fd62ea1a 1818 {
NYX 0:85b3fd62ea1a 1819 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
NYX 0:85b3fd62ea1a 1820 {
NYX 0:85b3fd62ea1a 1821 return (1UL); /* Reload value impossible */
NYX 0:85b3fd62ea1a 1822 }
NYX 0:85b3fd62ea1a 1823
NYX 0:85b3fd62ea1a 1824 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NYX 0:85b3fd62ea1a 1825 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
NYX 0:85b3fd62ea1a 1826 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NYX 0:85b3fd62ea1a 1827 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
NYX 0:85b3fd62ea1a 1828 SysTick_CTRL_TICKINT_Msk |
NYX 0:85b3fd62ea1a 1829 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
NYX 0:85b3fd62ea1a 1830 return (0UL); /* Function successful */
NYX 0:85b3fd62ea1a 1831 }
NYX 0:85b3fd62ea1a 1832
NYX 0:85b3fd62ea1a 1833 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
NYX 0:85b3fd62ea1a 1834 /**
NYX 0:85b3fd62ea1a 1835 \brief System Tick Configuration (non-secure)
NYX 0:85b3fd62ea1a 1836 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
NYX 0:85b3fd62ea1a 1837 Counter is in free running mode to generate periodic interrupts.
NYX 0:85b3fd62ea1a 1838 \param [in] ticks Number of ticks between two interrupts.
NYX 0:85b3fd62ea1a 1839 \return 0 Function succeeded.
NYX 0:85b3fd62ea1a 1840 \return 1 Function failed.
NYX 0:85b3fd62ea1a 1841 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
NYX 0:85b3fd62ea1a 1842 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
NYX 0:85b3fd62ea1a 1843 must contain a vendor-specific implementation of this function.
NYX 0:85b3fd62ea1a 1844
NYX 0:85b3fd62ea1a 1845 */
NYX 0:85b3fd62ea1a 1846 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
NYX 0:85b3fd62ea1a 1847 {
NYX 0:85b3fd62ea1a 1848 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
NYX 0:85b3fd62ea1a 1849 {
NYX 0:85b3fd62ea1a 1850 return (1UL); /* Reload value impossible */
NYX 0:85b3fd62ea1a 1851 }
NYX 0:85b3fd62ea1a 1852
NYX 0:85b3fd62ea1a 1853 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NYX 0:85b3fd62ea1a 1854 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
NYX 0:85b3fd62ea1a 1855 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
NYX 0:85b3fd62ea1a 1856 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
NYX 0:85b3fd62ea1a 1857 SysTick_CTRL_TICKINT_Msk |
NYX 0:85b3fd62ea1a 1858 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
NYX 0:85b3fd62ea1a 1859 return (0UL); /* Function successful */
NYX 0:85b3fd62ea1a 1860 }
NYX 0:85b3fd62ea1a 1861 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
NYX 0:85b3fd62ea1a 1862
NYX 0:85b3fd62ea1a 1863 #endif
NYX 0:85b3fd62ea1a 1864
NYX 0:85b3fd62ea1a 1865 /*@} end of CMSIS_Core_SysTickFunctions */
NYX 0:85b3fd62ea1a 1866
NYX 0:85b3fd62ea1a 1867
NYX 0:85b3fd62ea1a 1868
NYX 0:85b3fd62ea1a 1869
NYX 0:85b3fd62ea1a 1870 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 1871 }
NYX 0:85b3fd62ea1a 1872 #endif
NYX 0:85b3fd62ea1a 1873
NYX 0:85b3fd62ea1a 1874 #endif /* __CORE_CM23_H_DEPENDANT */
NYX 0:85b3fd62ea1a 1875
NYX 0:85b3fd62ea1a 1876 #endif /* __CMSIS_GENERIC */