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cmsis/core_cm0plus.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

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NYX 0:85b3fd62ea1a 1 /**************************************************************************//**
NYX 0:85b3fd62ea1a 2 * @file core_cm0plus.h
NYX 0:85b3fd62ea1a 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
NYX 0:85b3fd62ea1a 4 * @version V5.0.2
NYX 0:85b3fd62ea1a 5 * @date 13. February 2017
NYX 0:85b3fd62ea1a 6 ******************************************************************************/
NYX 0:85b3fd62ea1a 7 /*
NYX 0:85b3fd62ea1a 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
NYX 0:85b3fd62ea1a 9 *
NYX 0:85b3fd62ea1a 10 * SPDX-License-Identifier: Apache-2.0
NYX 0:85b3fd62ea1a 11 *
NYX 0:85b3fd62ea1a 12 * Licensed under the Apache License, Version 2.0 (the License); you may
NYX 0:85b3fd62ea1a 13 * not use this file except in compliance with the License.
NYX 0:85b3fd62ea1a 14 * You may obtain a copy of the License at
NYX 0:85b3fd62ea1a 15 *
NYX 0:85b3fd62ea1a 16 * www.apache.org/licenses/LICENSE-2.0
NYX 0:85b3fd62ea1a 17 *
NYX 0:85b3fd62ea1a 18 * Unless required by applicable law or agreed to in writing, software
NYX 0:85b3fd62ea1a 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
NYX 0:85b3fd62ea1a 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX 0:85b3fd62ea1a 21 * See the License for the specific language governing permissions and
NYX 0:85b3fd62ea1a 22 * limitations under the License.
NYX 0:85b3fd62ea1a 23 */
NYX 0:85b3fd62ea1a 24
NYX 0:85b3fd62ea1a 25 #if defined ( __ICCARM__ )
NYX 0:85b3fd62ea1a 26 #pragma system_include /* treat file as system include file for MISRA check */
NYX 0:85b3fd62ea1a 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX 0:85b3fd62ea1a 28 #pragma clang system_header /* treat file as system include file */
NYX 0:85b3fd62ea1a 29 #endif
NYX 0:85b3fd62ea1a 30
NYX 0:85b3fd62ea1a 31 #ifndef __CORE_CM0PLUS_H_GENERIC
NYX 0:85b3fd62ea1a 32 #define __CORE_CM0PLUS_H_GENERIC
NYX 0:85b3fd62ea1a 33
NYX 0:85b3fd62ea1a 34 #include <stdint.h>
NYX 0:85b3fd62ea1a 35
NYX 0:85b3fd62ea1a 36 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 37 extern "C" {
NYX 0:85b3fd62ea1a 38 #endif
NYX 0:85b3fd62ea1a 39
NYX 0:85b3fd62ea1a 40 /**
NYX 0:85b3fd62ea1a 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
NYX 0:85b3fd62ea1a 42 CMSIS violates the following MISRA-C:2004 rules:
NYX 0:85b3fd62ea1a 43
NYX 0:85b3fd62ea1a 44 \li Required Rule 8.5, object/function definition in header file.<br>
NYX 0:85b3fd62ea1a 45 Function definitions in header files are used to allow 'inlining'.
NYX 0:85b3fd62ea1a 46
NYX 0:85b3fd62ea1a 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
NYX 0:85b3fd62ea1a 48 Unions are used for effective representation of core registers.
NYX 0:85b3fd62ea1a 49
NYX 0:85b3fd62ea1a 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
NYX 0:85b3fd62ea1a 51 Function-like macros are used to allow more efficient code.
NYX 0:85b3fd62ea1a 52 */
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 /*******************************************************************************
NYX 0:85b3fd62ea1a 56 * CMSIS definitions
NYX 0:85b3fd62ea1a 57 ******************************************************************************/
NYX 0:85b3fd62ea1a 58 /**
NYX 0:85b3fd62ea1a 59 \ingroup Cortex-M0+
NYX 0:85b3fd62ea1a 60 @{
NYX 0:85b3fd62ea1a 61 */
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63 /* CMSIS CM0+ definitions */
NYX 0:85b3fd62ea1a 64 #define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
NYX 0:85b3fd62ea1a 65 #define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
NYX 0:85b3fd62ea1a 66 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
NYX 0:85b3fd62ea1a 67 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
NYX 0:85b3fd62ea1a 70
NYX 0:85b3fd62ea1a 71 /** __FPU_USED indicates whether an FPU is used or not.
NYX 0:85b3fd62ea1a 72 This core does not support an FPU at all
NYX 0:85b3fd62ea1a 73 */
NYX 0:85b3fd62ea1a 74 #define __FPU_USED 0U
NYX 0:85b3fd62ea1a 75
NYX 0:85b3fd62ea1a 76 #if defined ( __CC_ARM )
NYX 0:85b3fd62ea1a 77 #if defined __TARGET_FPU_VFP
NYX 0:85b3fd62ea1a 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 79 #endif
NYX 0:85b3fd62ea1a 80
NYX 0:85b3fd62ea1a 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX 0:85b3fd62ea1a 82 #if defined __ARM_PCS_VFP
NYX 0:85b3fd62ea1a 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 84 #endif
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 #elif defined ( __GNUC__ )
NYX 0:85b3fd62ea1a 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
NYX 0:85b3fd62ea1a 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 89 #endif
NYX 0:85b3fd62ea1a 90
NYX 0:85b3fd62ea1a 91 #elif defined ( __ICCARM__ )
NYX 0:85b3fd62ea1a 92 #if defined __ARMVFP__
NYX 0:85b3fd62ea1a 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 94 #endif
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 #elif defined ( __TI_ARM__ )
NYX 0:85b3fd62ea1a 97 #if defined __TI_VFP_SUPPORT__
NYX 0:85b3fd62ea1a 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 99 #endif
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 #elif defined ( __TASKING__ )
NYX 0:85b3fd62ea1a 102 #if defined __FPU_VFP__
NYX 0:85b3fd62ea1a 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 104 #endif
NYX 0:85b3fd62ea1a 105
NYX 0:85b3fd62ea1a 106 #elif defined ( __CSMC__ )
NYX 0:85b3fd62ea1a 107 #if ( __CSMC__ & 0x400U)
NYX 0:85b3fd62ea1a 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 109 #endif
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 #endif
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115
NYX 0:85b3fd62ea1a 116 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 117 }
NYX 0:85b3fd62ea1a 118 #endif
NYX 0:85b3fd62ea1a 119
NYX 0:85b3fd62ea1a 120 #endif /* __CORE_CM0PLUS_H_GENERIC */
NYX 0:85b3fd62ea1a 121
NYX 0:85b3fd62ea1a 122 #ifndef __CMSIS_GENERIC
NYX 0:85b3fd62ea1a 123
NYX 0:85b3fd62ea1a 124 #ifndef __CORE_CM0PLUS_H_DEPENDANT
NYX 0:85b3fd62ea1a 125 #define __CORE_CM0PLUS_H_DEPENDANT
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 128 extern "C" {
NYX 0:85b3fd62ea1a 129 #endif
NYX 0:85b3fd62ea1a 130
NYX 0:85b3fd62ea1a 131 /* check device defines and use defaults */
NYX 0:85b3fd62ea1a 132 #if defined __CHECK_DEVICE_DEFINES
NYX 0:85b3fd62ea1a 133 #ifndef __CM0PLUS_REV
NYX 0:85b3fd62ea1a 134 #define __CM0PLUS_REV 0x0000U
NYX 0:85b3fd62ea1a 135 #warning "__CM0PLUS_REV not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 136 #endif
NYX 0:85b3fd62ea1a 137
NYX 0:85b3fd62ea1a 138 #ifndef __MPU_PRESENT
NYX 0:85b3fd62ea1a 139 #define __MPU_PRESENT 0U
NYX 0:85b3fd62ea1a 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 141 #endif
NYX 0:85b3fd62ea1a 142
NYX 0:85b3fd62ea1a 143 #ifndef __VTOR_PRESENT
NYX 0:85b3fd62ea1a 144 #define __VTOR_PRESENT 0U
NYX 0:85b3fd62ea1a 145 #warning "__VTOR_PRESENT not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 146 #endif
NYX 0:85b3fd62ea1a 147
NYX 0:85b3fd62ea1a 148 #ifndef __NVIC_PRIO_BITS
NYX 0:85b3fd62ea1a 149 #define __NVIC_PRIO_BITS 2U
NYX 0:85b3fd62ea1a 150 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 151 #endif
NYX 0:85b3fd62ea1a 152
NYX 0:85b3fd62ea1a 153 #ifndef __Vendor_SysTickConfig
NYX 0:85b3fd62ea1a 154 #define __Vendor_SysTickConfig 0U
NYX 0:85b3fd62ea1a 155 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 156 #endif
NYX 0:85b3fd62ea1a 157 #endif
NYX 0:85b3fd62ea1a 158
NYX 0:85b3fd62ea1a 159 /* IO definitions (access restrictions to peripheral registers) */
NYX 0:85b3fd62ea1a 160 /**
NYX 0:85b3fd62ea1a 161 \defgroup CMSIS_glob_defs CMSIS Global Defines
NYX 0:85b3fd62ea1a 162
NYX 0:85b3fd62ea1a 163 <strong>IO Type Qualifiers</strong> are used
NYX 0:85b3fd62ea1a 164 \li to specify the access to peripheral variables.
NYX 0:85b3fd62ea1a 165 \li for automatic generation of peripheral register debug information.
NYX 0:85b3fd62ea1a 166 */
NYX 0:85b3fd62ea1a 167 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 168 #define __I volatile /*!< Defines 'read only' permissions */
NYX 0:85b3fd62ea1a 169 #else
NYX 0:85b3fd62ea1a 170 #define __I volatile const /*!< Defines 'read only' permissions */
NYX 0:85b3fd62ea1a 171 #endif
NYX 0:85b3fd62ea1a 172 #define __O volatile /*!< Defines 'write only' permissions */
NYX 0:85b3fd62ea1a 173 #define __IO volatile /*!< Defines 'read / write' permissions */
NYX 0:85b3fd62ea1a 174
NYX 0:85b3fd62ea1a 175 /* following defines should be used for structure members */
NYX 0:85b3fd62ea1a 176 #define __IM volatile const /*! Defines 'read only' structure member permissions */
NYX 0:85b3fd62ea1a 177 #define __OM volatile /*! Defines 'write only' structure member permissions */
NYX 0:85b3fd62ea1a 178 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
NYX 0:85b3fd62ea1a 179
NYX 0:85b3fd62ea1a 180 /*@} end of group Cortex-M0+ */
NYX 0:85b3fd62ea1a 181
NYX 0:85b3fd62ea1a 182
NYX 0:85b3fd62ea1a 183
NYX 0:85b3fd62ea1a 184 /*******************************************************************************
NYX 0:85b3fd62ea1a 185 * Register Abstraction
NYX 0:85b3fd62ea1a 186 Core Register contain:
NYX 0:85b3fd62ea1a 187 - Core Register
NYX 0:85b3fd62ea1a 188 - Core NVIC Register
NYX 0:85b3fd62ea1a 189 - Core SCB Register
NYX 0:85b3fd62ea1a 190 - Core SysTick Register
NYX 0:85b3fd62ea1a 191 - Core MPU Register
NYX 0:85b3fd62ea1a 192 ******************************************************************************/
NYX 0:85b3fd62ea1a 193 /**
NYX 0:85b3fd62ea1a 194 \defgroup CMSIS_core_register Defines and Type Definitions
NYX 0:85b3fd62ea1a 195 \brief Type definitions and defines for Cortex-M processor based devices.
NYX 0:85b3fd62ea1a 196 */
NYX 0:85b3fd62ea1a 197
NYX 0:85b3fd62ea1a 198 /**
NYX 0:85b3fd62ea1a 199 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 200 \defgroup CMSIS_CORE Status and Control Registers
NYX 0:85b3fd62ea1a 201 \brief Core Register type definitions.
NYX 0:85b3fd62ea1a 202 @{
NYX 0:85b3fd62ea1a 203 */
NYX 0:85b3fd62ea1a 204
NYX 0:85b3fd62ea1a 205 /**
NYX 0:85b3fd62ea1a 206 \brief Union type to access the Application Program Status Register (APSR).
NYX 0:85b3fd62ea1a 207 */
NYX 0:85b3fd62ea1a 208 typedef union
NYX 0:85b3fd62ea1a 209 {
NYX 0:85b3fd62ea1a 210 struct
NYX 0:85b3fd62ea1a 211 {
NYX 0:85b3fd62ea1a 212 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
NYX 0:85b3fd62ea1a 213 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
NYX 0:85b3fd62ea1a 214 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
NYX 0:85b3fd62ea1a 215 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
NYX 0:85b3fd62ea1a 216 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
NYX 0:85b3fd62ea1a 217 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 218 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 219 } APSR_Type;
NYX 0:85b3fd62ea1a 220
NYX 0:85b3fd62ea1a 221 /* APSR Register Definitions */
NYX 0:85b3fd62ea1a 222 #define APSR_N_Pos 31U /*!< APSR: N Position */
NYX 0:85b3fd62ea1a 223 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
NYX 0:85b3fd62ea1a 224
NYX 0:85b3fd62ea1a 225 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
NYX 0:85b3fd62ea1a 226 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
NYX 0:85b3fd62ea1a 227
NYX 0:85b3fd62ea1a 228 #define APSR_C_Pos 29U /*!< APSR: C Position */
NYX 0:85b3fd62ea1a 229 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
NYX 0:85b3fd62ea1a 230
NYX 0:85b3fd62ea1a 231 #define APSR_V_Pos 28U /*!< APSR: V Position */
NYX 0:85b3fd62ea1a 232 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
NYX 0:85b3fd62ea1a 233
NYX 0:85b3fd62ea1a 234
NYX 0:85b3fd62ea1a 235 /**
NYX 0:85b3fd62ea1a 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
NYX 0:85b3fd62ea1a 237 */
NYX 0:85b3fd62ea1a 238 typedef union
NYX 0:85b3fd62ea1a 239 {
NYX 0:85b3fd62ea1a 240 struct
NYX 0:85b3fd62ea1a 241 {
NYX 0:85b3fd62ea1a 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
NYX 0:85b3fd62ea1a 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
NYX 0:85b3fd62ea1a 244 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 245 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 246 } IPSR_Type;
NYX 0:85b3fd62ea1a 247
NYX 0:85b3fd62ea1a 248 /* IPSR Register Definitions */
NYX 0:85b3fd62ea1a 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
NYX 0:85b3fd62ea1a 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
NYX 0:85b3fd62ea1a 251
NYX 0:85b3fd62ea1a 252
NYX 0:85b3fd62ea1a 253 /**
NYX 0:85b3fd62ea1a 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
NYX 0:85b3fd62ea1a 255 */
NYX 0:85b3fd62ea1a 256 typedef union
NYX 0:85b3fd62ea1a 257 {
NYX 0:85b3fd62ea1a 258 struct
NYX 0:85b3fd62ea1a 259 {
NYX 0:85b3fd62ea1a 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
NYX 0:85b3fd62ea1a 261 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
NYX 0:85b3fd62ea1a 262 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
NYX 0:85b3fd62ea1a 263 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
NYX 0:85b3fd62ea1a 264 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
NYX 0:85b3fd62ea1a 265 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
NYX 0:85b3fd62ea1a 266 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
NYX 0:85b3fd62ea1a 267 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
NYX 0:85b3fd62ea1a 268 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 269 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 270 } xPSR_Type;
NYX 0:85b3fd62ea1a 271
NYX 0:85b3fd62ea1a 272 /* xPSR Register Definitions */
NYX 0:85b3fd62ea1a 273 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
NYX 0:85b3fd62ea1a 274 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
NYX 0:85b3fd62ea1a 275
NYX 0:85b3fd62ea1a 276 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
NYX 0:85b3fd62ea1a 277 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
NYX 0:85b3fd62ea1a 278
NYX 0:85b3fd62ea1a 279 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
NYX 0:85b3fd62ea1a 280 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
NYX 0:85b3fd62ea1a 281
NYX 0:85b3fd62ea1a 282 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
NYX 0:85b3fd62ea1a 283 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
NYX 0:85b3fd62ea1a 284
NYX 0:85b3fd62ea1a 285 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
NYX 0:85b3fd62ea1a 286 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
NYX 0:85b3fd62ea1a 287
NYX 0:85b3fd62ea1a 288 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
NYX 0:85b3fd62ea1a 289 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
NYX 0:85b3fd62ea1a 290
NYX 0:85b3fd62ea1a 291
NYX 0:85b3fd62ea1a 292 /**
NYX 0:85b3fd62ea1a 293 \brief Union type to access the Control Registers (CONTROL).
NYX 0:85b3fd62ea1a 294 */
NYX 0:85b3fd62ea1a 295 typedef union
NYX 0:85b3fd62ea1a 296 {
NYX 0:85b3fd62ea1a 297 struct
NYX 0:85b3fd62ea1a 298 {
NYX 0:85b3fd62ea1a 299 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
NYX 0:85b3fd62ea1a 300 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
NYX 0:85b3fd62ea1a 301 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
NYX 0:85b3fd62ea1a 302 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 303 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 304 } CONTROL_Type;
NYX 0:85b3fd62ea1a 305
NYX 0:85b3fd62ea1a 306 /* CONTROL Register Definitions */
NYX 0:85b3fd62ea1a 307 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
NYX 0:85b3fd62ea1a 308 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
NYX 0:85b3fd62ea1a 309
NYX 0:85b3fd62ea1a 310 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
NYX 0:85b3fd62ea1a 311 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
NYX 0:85b3fd62ea1a 312
NYX 0:85b3fd62ea1a 313 /*@} end of group CMSIS_CORE */
NYX 0:85b3fd62ea1a 314
NYX 0:85b3fd62ea1a 315
NYX 0:85b3fd62ea1a 316 /**
NYX 0:85b3fd62ea1a 317 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 318 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
NYX 0:85b3fd62ea1a 319 \brief Type definitions for the NVIC Registers
NYX 0:85b3fd62ea1a 320 @{
NYX 0:85b3fd62ea1a 321 */
NYX 0:85b3fd62ea1a 322
NYX 0:85b3fd62ea1a 323 /**
NYX 0:85b3fd62ea1a 324 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
NYX 0:85b3fd62ea1a 325 */
NYX 0:85b3fd62ea1a 326 typedef struct
NYX 0:85b3fd62ea1a 327 {
NYX 0:85b3fd62ea1a 328 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
NYX 0:85b3fd62ea1a 329 uint32_t RESERVED0[31U];
NYX 0:85b3fd62ea1a 330 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
NYX 0:85b3fd62ea1a 331 uint32_t RSERVED1[31U];
NYX 0:85b3fd62ea1a 332 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
NYX 0:85b3fd62ea1a 333 uint32_t RESERVED2[31U];
NYX 0:85b3fd62ea1a 334 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
NYX 0:85b3fd62ea1a 335 uint32_t RESERVED3[31U];
NYX 0:85b3fd62ea1a 336 uint32_t RESERVED4[64U];
NYX 0:85b3fd62ea1a 337 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
NYX 0:85b3fd62ea1a 338 } NVIC_Type;
NYX 0:85b3fd62ea1a 339
NYX 0:85b3fd62ea1a 340 /*@} end of group CMSIS_NVIC */
NYX 0:85b3fd62ea1a 341
NYX 0:85b3fd62ea1a 342
NYX 0:85b3fd62ea1a 343 /**
NYX 0:85b3fd62ea1a 344 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 345 \defgroup CMSIS_SCB System Control Block (SCB)
NYX 0:85b3fd62ea1a 346 \brief Type definitions for the System Control Block Registers
NYX 0:85b3fd62ea1a 347 @{
NYX 0:85b3fd62ea1a 348 */
NYX 0:85b3fd62ea1a 349
NYX 0:85b3fd62ea1a 350 /**
NYX 0:85b3fd62ea1a 351 \brief Structure type to access the System Control Block (SCB).
NYX 0:85b3fd62ea1a 352 */
NYX 0:85b3fd62ea1a 353 typedef struct
NYX 0:85b3fd62ea1a 354 {
NYX 0:85b3fd62ea1a 355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
NYX 0:85b3fd62ea1a 356 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
NYX 0:85b3fd62ea1a 357 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
NYX 0:85b3fd62ea1a 358 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
NYX 0:85b3fd62ea1a 359 #else
NYX 0:85b3fd62ea1a 360 uint32_t RESERVED0;
NYX 0:85b3fd62ea1a 361 #endif
NYX 0:85b3fd62ea1a 362 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
NYX 0:85b3fd62ea1a 363 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
NYX 0:85b3fd62ea1a 364 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
NYX 0:85b3fd62ea1a 365 uint32_t RESERVED1;
NYX 0:85b3fd62ea1a 366 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
NYX 0:85b3fd62ea1a 367 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
NYX 0:85b3fd62ea1a 368 } SCB_Type;
NYX 0:85b3fd62ea1a 369
NYX 0:85b3fd62ea1a 370 /* SCB CPUID Register Definitions */
NYX 0:85b3fd62ea1a 371 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
NYX 0:85b3fd62ea1a 372 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
NYX 0:85b3fd62ea1a 373
NYX 0:85b3fd62ea1a 374 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
NYX 0:85b3fd62ea1a 375 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
NYX 0:85b3fd62ea1a 376
NYX 0:85b3fd62ea1a 377 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
NYX 0:85b3fd62ea1a 378 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
NYX 0:85b3fd62ea1a 379
NYX 0:85b3fd62ea1a 380 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
NYX 0:85b3fd62ea1a 381 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
NYX 0:85b3fd62ea1a 382
NYX 0:85b3fd62ea1a 383 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
NYX 0:85b3fd62ea1a 384 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
NYX 0:85b3fd62ea1a 385
NYX 0:85b3fd62ea1a 386 /* SCB Interrupt Control State Register Definitions */
NYX 0:85b3fd62ea1a 387 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
NYX 0:85b3fd62ea1a 388 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
NYX 0:85b3fd62ea1a 389
NYX 0:85b3fd62ea1a 390 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
NYX 0:85b3fd62ea1a 391 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
NYX 0:85b3fd62ea1a 392
NYX 0:85b3fd62ea1a 393 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
NYX 0:85b3fd62ea1a 394 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
NYX 0:85b3fd62ea1a 395
NYX 0:85b3fd62ea1a 396 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
NYX 0:85b3fd62ea1a 397 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
NYX 0:85b3fd62ea1a 398
NYX 0:85b3fd62ea1a 399 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
NYX 0:85b3fd62ea1a 400 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
NYX 0:85b3fd62ea1a 401
NYX 0:85b3fd62ea1a 402 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
NYX 0:85b3fd62ea1a 403 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
NYX 0:85b3fd62ea1a 404
NYX 0:85b3fd62ea1a 405 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
NYX 0:85b3fd62ea1a 406 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
NYX 0:85b3fd62ea1a 407
NYX 0:85b3fd62ea1a 408 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
NYX 0:85b3fd62ea1a 409 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
NYX 0:85b3fd62ea1a 410
NYX 0:85b3fd62ea1a 411 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
NYX 0:85b3fd62ea1a 412 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
NYX 0:85b3fd62ea1a 413
NYX 0:85b3fd62ea1a 414 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
NYX 0:85b3fd62ea1a 415 /* SCB Interrupt Control State Register Definitions */
NYX 0:85b3fd62ea1a 416 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
NYX 0:85b3fd62ea1a 417 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
NYX 0:85b3fd62ea1a 418 #endif
NYX 0:85b3fd62ea1a 419
NYX 0:85b3fd62ea1a 420 /* SCB Application Interrupt and Reset Control Register Definitions */
NYX 0:85b3fd62ea1a 421 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
NYX 0:85b3fd62ea1a 422 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
NYX 0:85b3fd62ea1a 423
NYX 0:85b3fd62ea1a 424 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
NYX 0:85b3fd62ea1a 425 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
NYX 0:85b3fd62ea1a 426
NYX 0:85b3fd62ea1a 427 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
NYX 0:85b3fd62ea1a 428 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
NYX 0:85b3fd62ea1a 429
NYX 0:85b3fd62ea1a 430 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
NYX 0:85b3fd62ea1a 431 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
NYX 0:85b3fd62ea1a 432
NYX 0:85b3fd62ea1a 433 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
NYX 0:85b3fd62ea1a 434 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
NYX 0:85b3fd62ea1a 435
NYX 0:85b3fd62ea1a 436 /* SCB System Control Register Definitions */
NYX 0:85b3fd62ea1a 437 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
NYX 0:85b3fd62ea1a 438 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
NYX 0:85b3fd62ea1a 439
NYX 0:85b3fd62ea1a 440 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
NYX 0:85b3fd62ea1a 441 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
NYX 0:85b3fd62ea1a 442
NYX 0:85b3fd62ea1a 443 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
NYX 0:85b3fd62ea1a 444 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
NYX 0:85b3fd62ea1a 445
NYX 0:85b3fd62ea1a 446 /* SCB Configuration Control Register Definitions */
NYX 0:85b3fd62ea1a 447 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
NYX 0:85b3fd62ea1a 448 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
NYX 0:85b3fd62ea1a 449
NYX 0:85b3fd62ea1a 450 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
NYX 0:85b3fd62ea1a 451 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
NYX 0:85b3fd62ea1a 452
NYX 0:85b3fd62ea1a 453 /* SCB System Handler Control and State Register Definitions */
NYX 0:85b3fd62ea1a 454 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
NYX 0:85b3fd62ea1a 455 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
NYX 0:85b3fd62ea1a 456
NYX 0:85b3fd62ea1a 457 /*@} end of group CMSIS_SCB */
NYX 0:85b3fd62ea1a 458
NYX 0:85b3fd62ea1a 459
NYX 0:85b3fd62ea1a 460 /**
NYX 0:85b3fd62ea1a 461 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 462 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
NYX 0:85b3fd62ea1a 463 \brief Type definitions for the System Timer Registers.
NYX 0:85b3fd62ea1a 464 @{
NYX 0:85b3fd62ea1a 465 */
NYX 0:85b3fd62ea1a 466
NYX 0:85b3fd62ea1a 467 /**
NYX 0:85b3fd62ea1a 468 \brief Structure type to access the System Timer (SysTick).
NYX 0:85b3fd62ea1a 469 */
NYX 0:85b3fd62ea1a 470 typedef struct
NYX 0:85b3fd62ea1a 471 {
NYX 0:85b3fd62ea1a 472 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
NYX 0:85b3fd62ea1a 473 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
NYX 0:85b3fd62ea1a 474 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
NYX 0:85b3fd62ea1a 475 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
NYX 0:85b3fd62ea1a 476 } SysTick_Type;
NYX 0:85b3fd62ea1a 477
NYX 0:85b3fd62ea1a 478 /* SysTick Control / Status Register Definitions */
NYX 0:85b3fd62ea1a 479 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
NYX 0:85b3fd62ea1a 480 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
NYX 0:85b3fd62ea1a 481
NYX 0:85b3fd62ea1a 482 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
NYX 0:85b3fd62ea1a 483 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
NYX 0:85b3fd62ea1a 484
NYX 0:85b3fd62ea1a 485 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
NYX 0:85b3fd62ea1a 486 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
NYX 0:85b3fd62ea1a 487
NYX 0:85b3fd62ea1a 488 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
NYX 0:85b3fd62ea1a 489 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
NYX 0:85b3fd62ea1a 490
NYX 0:85b3fd62ea1a 491 /* SysTick Reload Register Definitions */
NYX 0:85b3fd62ea1a 492 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
NYX 0:85b3fd62ea1a 493 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
NYX 0:85b3fd62ea1a 494
NYX 0:85b3fd62ea1a 495 /* SysTick Current Register Definitions */
NYX 0:85b3fd62ea1a 496 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
NYX 0:85b3fd62ea1a 497 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
NYX 0:85b3fd62ea1a 498
NYX 0:85b3fd62ea1a 499 /* SysTick Calibration Register Definitions */
NYX 0:85b3fd62ea1a 500 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
NYX 0:85b3fd62ea1a 501 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
NYX 0:85b3fd62ea1a 502
NYX 0:85b3fd62ea1a 503 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
NYX 0:85b3fd62ea1a 504 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
NYX 0:85b3fd62ea1a 505
NYX 0:85b3fd62ea1a 506 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
NYX 0:85b3fd62ea1a 507 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
NYX 0:85b3fd62ea1a 508
NYX 0:85b3fd62ea1a 509 /*@} end of group CMSIS_SysTick */
NYX 0:85b3fd62ea1a 510
NYX 0:85b3fd62ea1a 511 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 512 /**
NYX 0:85b3fd62ea1a 513 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 514 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
NYX 0:85b3fd62ea1a 515 \brief Type definitions for the Memory Protection Unit (MPU)
NYX 0:85b3fd62ea1a 516 @{
NYX 0:85b3fd62ea1a 517 */
NYX 0:85b3fd62ea1a 518
NYX 0:85b3fd62ea1a 519 /**
NYX 0:85b3fd62ea1a 520 \brief Structure type to access the Memory Protection Unit (MPU).
NYX 0:85b3fd62ea1a 521 */
NYX 0:85b3fd62ea1a 522 typedef struct
NYX 0:85b3fd62ea1a 523 {
NYX 0:85b3fd62ea1a 524 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
NYX 0:85b3fd62ea1a 525 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
NYX 0:85b3fd62ea1a 526 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
NYX 0:85b3fd62ea1a 527 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
NYX 0:85b3fd62ea1a 528 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
NYX 0:85b3fd62ea1a 529 } MPU_Type;
NYX 0:85b3fd62ea1a 530
NYX 0:85b3fd62ea1a 531 /* MPU Type Register Definitions */
NYX 0:85b3fd62ea1a 532 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
NYX 0:85b3fd62ea1a 533 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
NYX 0:85b3fd62ea1a 534
NYX 0:85b3fd62ea1a 535 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
NYX 0:85b3fd62ea1a 536 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
NYX 0:85b3fd62ea1a 537
NYX 0:85b3fd62ea1a 538 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
NYX 0:85b3fd62ea1a 539 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
NYX 0:85b3fd62ea1a 540
NYX 0:85b3fd62ea1a 541 /* MPU Control Register Definitions */
NYX 0:85b3fd62ea1a 542 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
NYX 0:85b3fd62ea1a 543 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
NYX 0:85b3fd62ea1a 544
NYX 0:85b3fd62ea1a 545 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
NYX 0:85b3fd62ea1a 546 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
NYX 0:85b3fd62ea1a 547
NYX 0:85b3fd62ea1a 548 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
NYX 0:85b3fd62ea1a 549 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
NYX 0:85b3fd62ea1a 550
NYX 0:85b3fd62ea1a 551 /* MPU Region Number Register Definitions */
NYX 0:85b3fd62ea1a 552 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
NYX 0:85b3fd62ea1a 553 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
NYX 0:85b3fd62ea1a 554
NYX 0:85b3fd62ea1a 555 /* MPU Region Base Address Register Definitions */
NYX 0:85b3fd62ea1a 556 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
NYX 0:85b3fd62ea1a 557 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
NYX 0:85b3fd62ea1a 558
NYX 0:85b3fd62ea1a 559 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
NYX 0:85b3fd62ea1a 560 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
NYX 0:85b3fd62ea1a 561
NYX 0:85b3fd62ea1a 562 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
NYX 0:85b3fd62ea1a 563 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
NYX 0:85b3fd62ea1a 564
NYX 0:85b3fd62ea1a 565 /* MPU Region Attribute and Size Register Definitions */
NYX 0:85b3fd62ea1a 566 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
NYX 0:85b3fd62ea1a 567 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
NYX 0:85b3fd62ea1a 568
NYX 0:85b3fd62ea1a 569 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
NYX 0:85b3fd62ea1a 570 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
NYX 0:85b3fd62ea1a 571
NYX 0:85b3fd62ea1a 572 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
NYX 0:85b3fd62ea1a 573 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
NYX 0:85b3fd62ea1a 574
NYX 0:85b3fd62ea1a 575 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
NYX 0:85b3fd62ea1a 576 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
NYX 0:85b3fd62ea1a 577
NYX 0:85b3fd62ea1a 578 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
NYX 0:85b3fd62ea1a 579 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
NYX 0:85b3fd62ea1a 580
NYX 0:85b3fd62ea1a 581 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
NYX 0:85b3fd62ea1a 582 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
NYX 0:85b3fd62ea1a 583
NYX 0:85b3fd62ea1a 584 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
NYX 0:85b3fd62ea1a 585 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
NYX 0:85b3fd62ea1a 586
NYX 0:85b3fd62ea1a 587 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
NYX 0:85b3fd62ea1a 588 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
NYX 0:85b3fd62ea1a 589
NYX 0:85b3fd62ea1a 590 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
NYX 0:85b3fd62ea1a 591 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
NYX 0:85b3fd62ea1a 592
NYX 0:85b3fd62ea1a 593 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
NYX 0:85b3fd62ea1a 594 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
NYX 0:85b3fd62ea1a 595
NYX 0:85b3fd62ea1a 596 /*@} end of group CMSIS_MPU */
NYX 0:85b3fd62ea1a 597 #endif
NYX 0:85b3fd62ea1a 598
NYX 0:85b3fd62ea1a 599
NYX 0:85b3fd62ea1a 600 /**
NYX 0:85b3fd62ea1a 601 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 602 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
NYX 0:85b3fd62ea1a 603 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
NYX 0:85b3fd62ea1a 604 Therefore they are not covered by the Cortex-M0+ header file.
NYX 0:85b3fd62ea1a 605 @{
NYX 0:85b3fd62ea1a 606 */
NYX 0:85b3fd62ea1a 607 /*@} end of group CMSIS_CoreDebug */
NYX 0:85b3fd62ea1a 608
NYX 0:85b3fd62ea1a 609
NYX 0:85b3fd62ea1a 610 /**
NYX 0:85b3fd62ea1a 611 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 612 \defgroup CMSIS_core_bitfield Core register bit field macros
NYX 0:85b3fd62ea1a 613 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
NYX 0:85b3fd62ea1a 614 @{
NYX 0:85b3fd62ea1a 615 */
NYX 0:85b3fd62ea1a 616
NYX 0:85b3fd62ea1a 617 /**
NYX 0:85b3fd62ea1a 618 \brief Mask and shift a bit field value for use in a register bit range.
NYX 0:85b3fd62ea1a 619 \param[in] field Name of the register bit field.
NYX 0:85b3fd62ea1a 620 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
NYX 0:85b3fd62ea1a 621 \return Masked and shifted value.
NYX 0:85b3fd62ea1a 622 */
NYX 0:85b3fd62ea1a 623 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
NYX 0:85b3fd62ea1a 624
NYX 0:85b3fd62ea1a 625 /**
NYX 0:85b3fd62ea1a 626 \brief Mask and shift a register value to extract a bit filed value.
NYX 0:85b3fd62ea1a 627 \param[in] field Name of the register bit field.
NYX 0:85b3fd62ea1a 628 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
NYX 0:85b3fd62ea1a 629 \return Masked and shifted bit field value.
NYX 0:85b3fd62ea1a 630 */
NYX 0:85b3fd62ea1a 631 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
NYX 0:85b3fd62ea1a 632
NYX 0:85b3fd62ea1a 633 /*@} end of group CMSIS_core_bitfield */
NYX 0:85b3fd62ea1a 634
NYX 0:85b3fd62ea1a 635
NYX 0:85b3fd62ea1a 636 /**
NYX 0:85b3fd62ea1a 637 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 638 \defgroup CMSIS_core_base Core Definitions
NYX 0:85b3fd62ea1a 639 \brief Definitions for base addresses, unions, and structures.
NYX 0:85b3fd62ea1a 640 @{
NYX 0:85b3fd62ea1a 641 */
NYX 0:85b3fd62ea1a 642
NYX 0:85b3fd62ea1a 643 /* Memory mapping of Core Hardware */
NYX 0:85b3fd62ea1a 644 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
NYX 0:85b3fd62ea1a 645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
NYX 0:85b3fd62ea1a 646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
NYX 0:85b3fd62ea1a 647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
NYX 0:85b3fd62ea1a 648
NYX 0:85b3fd62ea1a 649 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
NYX 0:85b3fd62ea1a 650 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
NYX 0:85b3fd62ea1a 651 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
NYX 0:85b3fd62ea1a 652
NYX 0:85b3fd62ea1a 653 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
NYX 0:85b3fd62ea1a 654 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
NYX 0:85b3fd62ea1a 655 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
NYX 0:85b3fd62ea1a 656 #endif
NYX 0:85b3fd62ea1a 657
NYX 0:85b3fd62ea1a 658 /*@} */
NYX 0:85b3fd62ea1a 659
NYX 0:85b3fd62ea1a 660
NYX 0:85b3fd62ea1a 661
NYX 0:85b3fd62ea1a 662 /*******************************************************************************
NYX 0:85b3fd62ea1a 663 * Hardware Abstraction Layer
NYX 0:85b3fd62ea1a 664 Core Function Interface contains:
NYX 0:85b3fd62ea1a 665 - Core NVIC Functions
NYX 0:85b3fd62ea1a 666 - Core SysTick Functions
NYX 0:85b3fd62ea1a 667 - Core Register Access Functions
NYX 0:85b3fd62ea1a 668 ******************************************************************************/
NYX 0:85b3fd62ea1a 669 /**
NYX 0:85b3fd62ea1a 670 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
NYX 0:85b3fd62ea1a 671 */
NYX 0:85b3fd62ea1a 672
NYX 0:85b3fd62ea1a 673
NYX 0:85b3fd62ea1a 674
NYX 0:85b3fd62ea1a 675 /* ########################## NVIC functions #################################### */
NYX 0:85b3fd62ea1a 676 /**
NYX 0:85b3fd62ea1a 677 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 678 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
NYX 0:85b3fd62ea1a 679 \brief Functions that manage interrupts and exceptions via the NVIC.
NYX 0:85b3fd62ea1a 680 @{
NYX 0:85b3fd62ea1a 681 */
NYX 0:85b3fd62ea1a 682
NYX 0:85b3fd62ea1a 683 #ifdef CMSIS_NVIC_VIRTUAL
NYX 0:85b3fd62ea1a 684 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 685 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
NYX 0:85b3fd62ea1a 686 #endif
NYX 0:85b3fd62ea1a 687 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 688 #else
NYX 0:85b3fd62ea1a 689 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
NYX 0:85b3fd62ea1a 690 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
NYX 0:85b3fd62ea1a 691 #define NVIC_EnableIRQ __NVIC_EnableIRQ
NYX 0:85b3fd62ea1a 692 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
NYX 0:85b3fd62ea1a 693 #define NVIC_DisableIRQ __NVIC_DisableIRQ
NYX 0:85b3fd62ea1a 694 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
NYX 0:85b3fd62ea1a 695 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
NYX 0:85b3fd62ea1a 696 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
NYX 0:85b3fd62ea1a 697 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
NYX 0:85b3fd62ea1a 698 #define NVIC_SetPriority __NVIC_SetPriority
NYX 0:85b3fd62ea1a 699 #define NVIC_GetPriority __NVIC_GetPriority
NYX 0:85b3fd62ea1a 700 #define NVIC_SystemReset __NVIC_SystemReset
NYX 0:85b3fd62ea1a 701 #endif /* CMSIS_NVIC_VIRTUAL */
NYX 0:85b3fd62ea1a 702
NYX 0:85b3fd62ea1a 703 #ifdef CMSIS_VECTAB_VIRTUAL
NYX 0:85b3fd62ea1a 704 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 705 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
NYX 0:85b3fd62ea1a 706 #endif
NYX 0:85b3fd62ea1a 707 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 708 #else
NYX 0:85b3fd62ea1a 709 #define NVIC_SetVector __NVIC_SetVector
NYX 0:85b3fd62ea1a 710 #define NVIC_GetVector __NVIC_GetVector
NYX 0:85b3fd62ea1a 711 #endif /* (CMSIS_VECTAB_VIRTUAL) */
NYX 0:85b3fd62ea1a 712
NYX 0:85b3fd62ea1a 713 #define NVIC_USER_IRQ_OFFSET 16
NYX 0:85b3fd62ea1a 714
NYX 0:85b3fd62ea1a 715
NYX 0:85b3fd62ea1a 716 /* Interrupt Priorities are WORD accessible only under ARMv6M */
NYX 0:85b3fd62ea1a 717 /* The following MACROS handle generation of the register offset and byte masks */
NYX 0:85b3fd62ea1a 718 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
NYX 0:85b3fd62ea1a 719 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
NYX 0:85b3fd62ea1a 720 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
NYX 0:85b3fd62ea1a 721
NYX 0:85b3fd62ea1a 722
NYX 0:85b3fd62ea1a 723 /**
NYX 0:85b3fd62ea1a 724 \brief Enable Interrupt
NYX 0:85b3fd62ea1a 725 \details Enables a device specific interrupt in the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 726 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 727 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 728 */
NYX 0:85b3fd62ea1a 729 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 730 {
NYX 0:85b3fd62ea1a 731 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 732 {
NYX 0:85b3fd62ea1a 733 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 734 }
NYX 0:85b3fd62ea1a 735 }
NYX 0:85b3fd62ea1a 736
NYX 0:85b3fd62ea1a 737
NYX 0:85b3fd62ea1a 738 /**
NYX 0:85b3fd62ea1a 739 \brief Get Interrupt Enable status
NYX 0:85b3fd62ea1a 740 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 741 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 742 \return 0 Interrupt is not enabled.
NYX 0:85b3fd62ea1a 743 \return 1 Interrupt is enabled.
NYX 0:85b3fd62ea1a 744 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 745 */
NYX 0:85b3fd62ea1a 746 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 747 {
NYX 0:85b3fd62ea1a 748 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 749 {
NYX 0:85b3fd62ea1a 750 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 751 }
NYX 0:85b3fd62ea1a 752 else
NYX 0:85b3fd62ea1a 753 {
NYX 0:85b3fd62ea1a 754 return(0U);
NYX 0:85b3fd62ea1a 755 }
NYX 0:85b3fd62ea1a 756 }
NYX 0:85b3fd62ea1a 757
NYX 0:85b3fd62ea1a 758
NYX 0:85b3fd62ea1a 759 /**
NYX 0:85b3fd62ea1a 760 \brief Disable Interrupt
NYX 0:85b3fd62ea1a 761 \details Disables a device specific interrupt in the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 762 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 763 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 764 */
NYX 0:85b3fd62ea1a 765 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 766 {
NYX 0:85b3fd62ea1a 767 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 768 {
NYX 0:85b3fd62ea1a 769 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 770 __DSB();
NYX 0:85b3fd62ea1a 771 __ISB();
NYX 0:85b3fd62ea1a 772 }
NYX 0:85b3fd62ea1a 773 }
NYX 0:85b3fd62ea1a 774
NYX 0:85b3fd62ea1a 775
NYX 0:85b3fd62ea1a 776 /**
NYX 0:85b3fd62ea1a 777 \brief Get Pending Interrupt
NYX 0:85b3fd62ea1a 778 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
NYX 0:85b3fd62ea1a 779 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 780 \return 0 Interrupt status is not pending.
NYX 0:85b3fd62ea1a 781 \return 1 Interrupt status is pending.
NYX 0:85b3fd62ea1a 782 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 783 */
NYX 0:85b3fd62ea1a 784 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 785 {
NYX 0:85b3fd62ea1a 786 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 787 {
NYX 0:85b3fd62ea1a 788 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 789 }
NYX 0:85b3fd62ea1a 790 else
NYX 0:85b3fd62ea1a 791 {
NYX 0:85b3fd62ea1a 792 return(0U);
NYX 0:85b3fd62ea1a 793 }
NYX 0:85b3fd62ea1a 794 }
NYX 0:85b3fd62ea1a 795
NYX 0:85b3fd62ea1a 796
NYX 0:85b3fd62ea1a 797 /**
NYX 0:85b3fd62ea1a 798 \brief Set Pending Interrupt
NYX 0:85b3fd62ea1a 799 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
NYX 0:85b3fd62ea1a 800 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 801 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 802 */
NYX 0:85b3fd62ea1a 803 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 804 {
NYX 0:85b3fd62ea1a 805 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 806 {
NYX 0:85b3fd62ea1a 807 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 808 }
NYX 0:85b3fd62ea1a 809 }
NYX 0:85b3fd62ea1a 810
NYX 0:85b3fd62ea1a 811
NYX 0:85b3fd62ea1a 812 /**
NYX 0:85b3fd62ea1a 813 \brief Clear Pending Interrupt
NYX 0:85b3fd62ea1a 814 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
NYX 0:85b3fd62ea1a 815 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 816 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 817 */
NYX 0:85b3fd62ea1a 818 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 819 {
NYX 0:85b3fd62ea1a 820 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 821 {
NYX 0:85b3fd62ea1a 822 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 823 }
NYX 0:85b3fd62ea1a 824 }
NYX 0:85b3fd62ea1a 825
NYX 0:85b3fd62ea1a 826
NYX 0:85b3fd62ea1a 827 /**
NYX 0:85b3fd62ea1a 828 \brief Set Interrupt Priority
NYX 0:85b3fd62ea1a 829 \details Sets the priority of a device specific interrupt or a processor exception.
NYX 0:85b3fd62ea1a 830 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 831 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 832 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 833 \param [in] priority Priority to set.
NYX 0:85b3fd62ea1a 834 \note The priority cannot be set for every processor exception.
NYX 0:85b3fd62ea1a 835 */
NYX 0:85b3fd62ea1a 836 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
NYX 0:85b3fd62ea1a 837 {
NYX 0:85b3fd62ea1a 838 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 839 {
NYX 0:85b3fd62ea1a 840 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
NYX 0:85b3fd62ea1a 841 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NYX 0:85b3fd62ea1a 842 }
NYX 0:85b3fd62ea1a 843 else
NYX 0:85b3fd62ea1a 844 {
NYX 0:85b3fd62ea1a 845 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
NYX 0:85b3fd62ea1a 846 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NYX 0:85b3fd62ea1a 847 }
NYX 0:85b3fd62ea1a 848 }
NYX 0:85b3fd62ea1a 849
NYX 0:85b3fd62ea1a 850
NYX 0:85b3fd62ea1a 851 /**
NYX 0:85b3fd62ea1a 852 \brief Get Interrupt Priority
NYX 0:85b3fd62ea1a 853 \details Reads the priority of a device specific interrupt or a processor exception.
NYX 0:85b3fd62ea1a 854 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 855 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 856 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 857 \return Interrupt Priority.
NYX 0:85b3fd62ea1a 858 Value is aligned automatically to the implemented priority bits of the microcontroller.
NYX 0:85b3fd62ea1a 859 */
NYX 0:85b3fd62ea1a 860 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 861 {
NYX 0:85b3fd62ea1a 862
NYX 0:85b3fd62ea1a 863 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 864 {
NYX 0:85b3fd62ea1a 865 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
NYX 0:85b3fd62ea1a 866 }
NYX 0:85b3fd62ea1a 867 else
NYX 0:85b3fd62ea1a 868 {
NYX 0:85b3fd62ea1a 869 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
NYX 0:85b3fd62ea1a 870 }
NYX 0:85b3fd62ea1a 871 }
NYX 0:85b3fd62ea1a 872
NYX 0:85b3fd62ea1a 873
NYX 0:85b3fd62ea1a 874 /**
NYX 0:85b3fd62ea1a 875 \brief Set Interrupt Vector
NYX 0:85b3fd62ea1a 876 \details Sets an interrupt vector in SRAM based interrupt vector table.
NYX 0:85b3fd62ea1a 877 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 878 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 879 VTOR must been relocated to SRAM before.
NYX 0:85b3fd62ea1a 880 If VTOR is not present address 0 must be mapped to SRAM.
NYX 0:85b3fd62ea1a 881 \param [in] IRQn Interrupt number
NYX 0:85b3fd62ea1a 882 \param [in] vector Address of interrupt handler function
NYX 0:85b3fd62ea1a 883 */
NYX 0:85b3fd62ea1a 884 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
NYX 0:85b3fd62ea1a 885 {
NYX 0:85b3fd62ea1a 886 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
NYX 0:85b3fd62ea1a 887 uint32_t *vectors = (uint32_t *)SCB->VTOR;
NYX 0:85b3fd62ea1a 888 #else
NYX 0:85b3fd62ea1a 889 uint32_t *vectors = (uint32_t *)0x0U;
NYX 0:85b3fd62ea1a 890 #endif
NYX 0:85b3fd62ea1a 891 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
NYX 0:85b3fd62ea1a 892 }
NYX 0:85b3fd62ea1a 893
NYX 0:85b3fd62ea1a 894
NYX 0:85b3fd62ea1a 895 /**
NYX 0:85b3fd62ea1a 896 \brief Get Interrupt Vector
NYX 0:85b3fd62ea1a 897 \details Reads an interrupt vector from interrupt vector table.
NYX 0:85b3fd62ea1a 898 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 899 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 900 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 901 \return Address of interrupt handler function
NYX 0:85b3fd62ea1a 902 */
NYX 0:85b3fd62ea1a 903 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 904 {
NYX 0:85b3fd62ea1a 905 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
NYX 0:85b3fd62ea1a 906 uint32_t *vectors = (uint32_t *)SCB->VTOR;
NYX 0:85b3fd62ea1a 907 #else
NYX 0:85b3fd62ea1a 908 uint32_t *vectors = (uint32_t *)0x0U;
NYX 0:85b3fd62ea1a 909 #endif
NYX 0:85b3fd62ea1a 910 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
NYX 0:85b3fd62ea1a 911
NYX 0:85b3fd62ea1a 912 }
NYX 0:85b3fd62ea1a 913
NYX 0:85b3fd62ea1a 914
NYX 0:85b3fd62ea1a 915 /**
NYX 0:85b3fd62ea1a 916 \brief System Reset
NYX 0:85b3fd62ea1a 917 \details Initiates a system reset request to reset the MCU.
NYX 0:85b3fd62ea1a 918 */
NYX 0:85b3fd62ea1a 919 __STATIC_INLINE void __NVIC_SystemReset(void)
NYX 0:85b3fd62ea1a 920 {
NYX 0:85b3fd62ea1a 921 __DSB(); /* Ensure all outstanding memory accesses included
NYX 0:85b3fd62ea1a 922 buffered write are completed before reset */
NYX 0:85b3fd62ea1a 923 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
NYX 0:85b3fd62ea1a 924 SCB_AIRCR_SYSRESETREQ_Msk);
NYX 0:85b3fd62ea1a 925 __DSB(); /* Ensure completion of memory access */
NYX 0:85b3fd62ea1a 926
NYX 0:85b3fd62ea1a 927 for(;;) /* wait until reset */
NYX 0:85b3fd62ea1a 928 {
NYX 0:85b3fd62ea1a 929 __NOP();
NYX 0:85b3fd62ea1a 930 }
NYX 0:85b3fd62ea1a 931 }
NYX 0:85b3fd62ea1a 932
NYX 0:85b3fd62ea1a 933 /*@} end of CMSIS_Core_NVICFunctions */
NYX 0:85b3fd62ea1a 934
NYX 0:85b3fd62ea1a 935
NYX 0:85b3fd62ea1a 936 /* ########################## FPU functions #################################### */
NYX 0:85b3fd62ea1a 937 /**
NYX 0:85b3fd62ea1a 938 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 939 \defgroup CMSIS_Core_FpuFunctions FPU Functions
NYX 0:85b3fd62ea1a 940 \brief Function that provides FPU type.
NYX 0:85b3fd62ea1a 941 @{
NYX 0:85b3fd62ea1a 942 */
NYX 0:85b3fd62ea1a 943
NYX 0:85b3fd62ea1a 944 /**
NYX 0:85b3fd62ea1a 945 \brief get FPU type
NYX 0:85b3fd62ea1a 946 \details returns the FPU type
NYX 0:85b3fd62ea1a 947 \returns
NYX 0:85b3fd62ea1a 948 - \b 0: No FPU
NYX 0:85b3fd62ea1a 949 - \b 1: Single precision FPU
NYX 0:85b3fd62ea1a 950 - \b 2: Double + Single precision FPU
NYX 0:85b3fd62ea1a 951 */
NYX 0:85b3fd62ea1a 952 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
NYX 0:85b3fd62ea1a 953 {
NYX 0:85b3fd62ea1a 954 return 0U; /* No FPU */
NYX 0:85b3fd62ea1a 955 }
NYX 0:85b3fd62ea1a 956
NYX 0:85b3fd62ea1a 957
NYX 0:85b3fd62ea1a 958 /*@} end of CMSIS_Core_FpuFunctions */
NYX 0:85b3fd62ea1a 959
NYX 0:85b3fd62ea1a 960
NYX 0:85b3fd62ea1a 961
NYX 0:85b3fd62ea1a 962 /* ################################## SysTick function ############################################ */
NYX 0:85b3fd62ea1a 963 /**
NYX 0:85b3fd62ea1a 964 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 965 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
NYX 0:85b3fd62ea1a 966 \brief Functions that configure the System.
NYX 0:85b3fd62ea1a 967 @{
NYX 0:85b3fd62ea1a 968 */
NYX 0:85b3fd62ea1a 969
NYX 0:85b3fd62ea1a 970 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
NYX 0:85b3fd62ea1a 971
NYX 0:85b3fd62ea1a 972 /**
NYX 0:85b3fd62ea1a 973 \brief System Tick Configuration
NYX 0:85b3fd62ea1a 974 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
NYX 0:85b3fd62ea1a 975 Counter is in free running mode to generate periodic interrupts.
NYX 0:85b3fd62ea1a 976 \param [in] ticks Number of ticks between two interrupts.
NYX 0:85b3fd62ea1a 977 \return 0 Function succeeded.
NYX 0:85b3fd62ea1a 978 \return 1 Function failed.
NYX 0:85b3fd62ea1a 979 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
NYX 0:85b3fd62ea1a 980 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
NYX 0:85b3fd62ea1a 981 must contain a vendor-specific implementation of this function.
NYX 0:85b3fd62ea1a 982 */
NYX 0:85b3fd62ea1a 983 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
NYX 0:85b3fd62ea1a 984 {
NYX 0:85b3fd62ea1a 985 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
NYX 0:85b3fd62ea1a 986 {
NYX 0:85b3fd62ea1a 987 return (1UL); /* Reload value impossible */
NYX 0:85b3fd62ea1a 988 }
NYX 0:85b3fd62ea1a 989
NYX 0:85b3fd62ea1a 990 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NYX 0:85b3fd62ea1a 991 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
NYX 0:85b3fd62ea1a 992 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NYX 0:85b3fd62ea1a 993 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
NYX 0:85b3fd62ea1a 994 SysTick_CTRL_TICKINT_Msk |
NYX 0:85b3fd62ea1a 995 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
NYX 0:85b3fd62ea1a 996 return (0UL); /* Function successful */
NYX 0:85b3fd62ea1a 997 }
NYX 0:85b3fd62ea1a 998
NYX 0:85b3fd62ea1a 999 #endif
NYX 0:85b3fd62ea1a 1000
NYX 0:85b3fd62ea1a 1001 /*@} end of CMSIS_Core_SysTickFunctions */
NYX 0:85b3fd62ea1a 1002
NYX 0:85b3fd62ea1a 1003
NYX 0:85b3fd62ea1a 1004
NYX 0:85b3fd62ea1a 1005
NYX 0:85b3fd62ea1a 1006 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 1007 }
NYX 0:85b3fd62ea1a 1008 #endif
NYX 0:85b3fd62ea1a 1009
NYX 0:85b3fd62ea1a 1010 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
NYX 0:85b3fd62ea1a 1011
NYX 0:85b3fd62ea1a 1012 #endif /* __CMSIS_GENERIC */