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cmsis/core_cm0.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:
NYX
Date:
Mon Mar 16 06:35:48 2020 +0000
Revision:
0:85b3fd62ea1a
reinport to mbed;

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NYX 0:85b3fd62ea1a 1 /**************************************************************************//**
NYX 0:85b3fd62ea1a 2 * @file core_cm0.h
NYX 0:85b3fd62ea1a 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
NYX 0:85b3fd62ea1a 4 * @version V5.0.2
NYX 0:85b3fd62ea1a 5 * @date 13. February 2017
NYX 0:85b3fd62ea1a 6 ******************************************************************************/
NYX 0:85b3fd62ea1a 7 /*
NYX 0:85b3fd62ea1a 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
NYX 0:85b3fd62ea1a 9 *
NYX 0:85b3fd62ea1a 10 * SPDX-License-Identifier: Apache-2.0
NYX 0:85b3fd62ea1a 11 *
NYX 0:85b3fd62ea1a 12 * Licensed under the Apache License, Version 2.0 (the License); you may
NYX 0:85b3fd62ea1a 13 * not use this file except in compliance with the License.
NYX 0:85b3fd62ea1a 14 * You may obtain a copy of the License at
NYX 0:85b3fd62ea1a 15 *
NYX 0:85b3fd62ea1a 16 * www.apache.org/licenses/LICENSE-2.0
NYX 0:85b3fd62ea1a 17 *
NYX 0:85b3fd62ea1a 18 * Unless required by applicable law or agreed to in writing, software
NYX 0:85b3fd62ea1a 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
NYX 0:85b3fd62ea1a 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX 0:85b3fd62ea1a 21 * See the License for the specific language governing permissions and
NYX 0:85b3fd62ea1a 22 * limitations under the License.
NYX 0:85b3fd62ea1a 23 */
NYX 0:85b3fd62ea1a 24
NYX 0:85b3fd62ea1a 25 #if defined ( __ICCARM__ )
NYX 0:85b3fd62ea1a 26 #pragma system_include /* treat file as system include file for MISRA check */
NYX 0:85b3fd62ea1a 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX 0:85b3fd62ea1a 28 #pragma clang system_header /* treat file as system include file */
NYX 0:85b3fd62ea1a 29 #endif
NYX 0:85b3fd62ea1a 30
NYX 0:85b3fd62ea1a 31 #ifndef __CORE_CM0_H_GENERIC
NYX 0:85b3fd62ea1a 32 #define __CORE_CM0_H_GENERIC
NYX 0:85b3fd62ea1a 33
NYX 0:85b3fd62ea1a 34 #include <stdint.h>
NYX 0:85b3fd62ea1a 35
NYX 0:85b3fd62ea1a 36 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 37 extern "C" {
NYX 0:85b3fd62ea1a 38 #endif
NYX 0:85b3fd62ea1a 39
NYX 0:85b3fd62ea1a 40 /**
NYX 0:85b3fd62ea1a 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
NYX 0:85b3fd62ea1a 42 CMSIS violates the following MISRA-C:2004 rules:
NYX 0:85b3fd62ea1a 43
NYX 0:85b3fd62ea1a 44 \li Required Rule 8.5, object/function definition in header file.<br>
NYX 0:85b3fd62ea1a 45 Function definitions in header files are used to allow 'inlining'.
NYX 0:85b3fd62ea1a 46
NYX 0:85b3fd62ea1a 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
NYX 0:85b3fd62ea1a 48 Unions are used for effective representation of core registers.
NYX 0:85b3fd62ea1a 49
NYX 0:85b3fd62ea1a 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
NYX 0:85b3fd62ea1a 51 Function-like macros are used to allow more efficient code.
NYX 0:85b3fd62ea1a 52 */
NYX 0:85b3fd62ea1a 53
NYX 0:85b3fd62ea1a 54
NYX 0:85b3fd62ea1a 55 /*******************************************************************************
NYX 0:85b3fd62ea1a 56 * CMSIS definitions
NYX 0:85b3fd62ea1a 57 ******************************************************************************/
NYX 0:85b3fd62ea1a 58 /**
NYX 0:85b3fd62ea1a 59 \ingroup Cortex_M0
NYX 0:85b3fd62ea1a 60 @{
NYX 0:85b3fd62ea1a 61 */
NYX 0:85b3fd62ea1a 62
NYX 0:85b3fd62ea1a 63 /* CMSIS CM0 definitions */
NYX 0:85b3fd62ea1a 64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
NYX 0:85b3fd62ea1a 65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
NYX 0:85b3fd62ea1a 66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
NYX 0:85b3fd62ea1a 67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
NYX 0:85b3fd62ea1a 68
NYX 0:85b3fd62ea1a 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
NYX 0:85b3fd62ea1a 70
NYX 0:85b3fd62ea1a 71 /** __FPU_USED indicates whether an FPU is used or not.
NYX 0:85b3fd62ea1a 72 This core does not support an FPU at all
NYX 0:85b3fd62ea1a 73 */
NYX 0:85b3fd62ea1a 74 #define __FPU_USED 0U
NYX 0:85b3fd62ea1a 75
NYX 0:85b3fd62ea1a 76 #if defined ( __CC_ARM )
NYX 0:85b3fd62ea1a 77 #if defined __TARGET_FPU_VFP
NYX 0:85b3fd62ea1a 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 79 #endif
NYX 0:85b3fd62ea1a 80
NYX 0:85b3fd62ea1a 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
NYX 0:85b3fd62ea1a 82 #if defined __ARM_PCS_VFP
NYX 0:85b3fd62ea1a 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 84 #endif
NYX 0:85b3fd62ea1a 85
NYX 0:85b3fd62ea1a 86 #elif defined ( __GNUC__ )
NYX 0:85b3fd62ea1a 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
NYX 0:85b3fd62ea1a 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 89 #endif
NYX 0:85b3fd62ea1a 90
NYX 0:85b3fd62ea1a 91 #elif defined ( __ICCARM__ )
NYX 0:85b3fd62ea1a 92 #if defined __ARMVFP__
NYX 0:85b3fd62ea1a 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 94 #endif
NYX 0:85b3fd62ea1a 95
NYX 0:85b3fd62ea1a 96 #elif defined ( __TI_ARM__ )
NYX 0:85b3fd62ea1a 97 #if defined __TI_VFP_SUPPORT__
NYX 0:85b3fd62ea1a 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 99 #endif
NYX 0:85b3fd62ea1a 100
NYX 0:85b3fd62ea1a 101 #elif defined ( __TASKING__ )
NYX 0:85b3fd62ea1a 102 #if defined __FPU_VFP__
NYX 0:85b3fd62ea1a 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 104 #endif
NYX 0:85b3fd62ea1a 105
NYX 0:85b3fd62ea1a 106 #elif defined ( __CSMC__ )
NYX 0:85b3fd62ea1a 107 #if ( __CSMC__ & 0x400U)
NYX 0:85b3fd62ea1a 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX 0:85b3fd62ea1a 109 #endif
NYX 0:85b3fd62ea1a 110
NYX 0:85b3fd62ea1a 111 #endif
NYX 0:85b3fd62ea1a 112
NYX 0:85b3fd62ea1a 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
NYX 0:85b3fd62ea1a 114
NYX 0:85b3fd62ea1a 115
NYX 0:85b3fd62ea1a 116 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 117 }
NYX 0:85b3fd62ea1a 118 #endif
NYX 0:85b3fd62ea1a 119
NYX 0:85b3fd62ea1a 120 #endif /* __CORE_CM0_H_GENERIC */
NYX 0:85b3fd62ea1a 121
NYX 0:85b3fd62ea1a 122 #ifndef __CMSIS_GENERIC
NYX 0:85b3fd62ea1a 123
NYX 0:85b3fd62ea1a 124 #ifndef __CORE_CM0_H_DEPENDANT
NYX 0:85b3fd62ea1a 125 #define __CORE_CM0_H_DEPENDANT
NYX 0:85b3fd62ea1a 126
NYX 0:85b3fd62ea1a 127 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 128 extern "C" {
NYX 0:85b3fd62ea1a 129 #endif
NYX 0:85b3fd62ea1a 130
NYX 0:85b3fd62ea1a 131 /* check device defines and use defaults */
NYX 0:85b3fd62ea1a 132 #if defined __CHECK_DEVICE_DEFINES
NYX 0:85b3fd62ea1a 133 #ifndef __CM0_REV
NYX 0:85b3fd62ea1a 134 #define __CM0_REV 0x0000U
NYX 0:85b3fd62ea1a 135 #warning "__CM0_REV not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 136 #endif
NYX 0:85b3fd62ea1a 137
NYX 0:85b3fd62ea1a 138 #ifndef __NVIC_PRIO_BITS
NYX 0:85b3fd62ea1a 139 #define __NVIC_PRIO_BITS 2U
NYX 0:85b3fd62ea1a 140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 141 #endif
NYX 0:85b3fd62ea1a 142
NYX 0:85b3fd62ea1a 143 #ifndef __Vendor_SysTickConfig
NYX 0:85b3fd62ea1a 144 #define __Vendor_SysTickConfig 0U
NYX 0:85b3fd62ea1a 145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
NYX 0:85b3fd62ea1a 146 #endif
NYX 0:85b3fd62ea1a 147 #endif
NYX 0:85b3fd62ea1a 148
NYX 0:85b3fd62ea1a 149 /* IO definitions (access restrictions to peripheral registers) */
NYX 0:85b3fd62ea1a 150 /**
NYX 0:85b3fd62ea1a 151 \defgroup CMSIS_glob_defs CMSIS Global Defines
NYX 0:85b3fd62ea1a 152
NYX 0:85b3fd62ea1a 153 <strong>IO Type Qualifiers</strong> are used
NYX 0:85b3fd62ea1a 154 \li to specify the access to peripheral variables.
NYX 0:85b3fd62ea1a 155 \li for automatic generation of peripheral register debug information.
NYX 0:85b3fd62ea1a 156 */
NYX 0:85b3fd62ea1a 157 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 158 #define __I volatile /*!< Defines 'read only' permissions */
NYX 0:85b3fd62ea1a 159 #else
NYX 0:85b3fd62ea1a 160 #define __I volatile const /*!< Defines 'read only' permissions */
NYX 0:85b3fd62ea1a 161 #endif
NYX 0:85b3fd62ea1a 162 #define __O volatile /*!< Defines 'write only' permissions */
NYX 0:85b3fd62ea1a 163 #define __IO volatile /*!< Defines 'read / write' permissions */
NYX 0:85b3fd62ea1a 164
NYX 0:85b3fd62ea1a 165 /* following defines should be used for structure members */
NYX 0:85b3fd62ea1a 166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
NYX 0:85b3fd62ea1a 167 #define __OM volatile /*! Defines 'write only' structure member permissions */
NYX 0:85b3fd62ea1a 168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
NYX 0:85b3fd62ea1a 169
NYX 0:85b3fd62ea1a 170 /*@} end of group Cortex_M0 */
NYX 0:85b3fd62ea1a 171
NYX 0:85b3fd62ea1a 172
NYX 0:85b3fd62ea1a 173
NYX 0:85b3fd62ea1a 174 /*******************************************************************************
NYX 0:85b3fd62ea1a 175 * Register Abstraction
NYX 0:85b3fd62ea1a 176 Core Register contain:
NYX 0:85b3fd62ea1a 177 - Core Register
NYX 0:85b3fd62ea1a 178 - Core NVIC Register
NYX 0:85b3fd62ea1a 179 - Core SCB Register
NYX 0:85b3fd62ea1a 180 - Core SysTick Register
NYX 0:85b3fd62ea1a 181 ******************************************************************************/
NYX 0:85b3fd62ea1a 182 /**
NYX 0:85b3fd62ea1a 183 \defgroup CMSIS_core_register Defines and Type Definitions
NYX 0:85b3fd62ea1a 184 \brief Type definitions and defines for Cortex-M processor based devices.
NYX 0:85b3fd62ea1a 185 */
NYX 0:85b3fd62ea1a 186
NYX 0:85b3fd62ea1a 187 /**
NYX 0:85b3fd62ea1a 188 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 189 \defgroup CMSIS_CORE Status and Control Registers
NYX 0:85b3fd62ea1a 190 \brief Core Register type definitions.
NYX 0:85b3fd62ea1a 191 @{
NYX 0:85b3fd62ea1a 192 */
NYX 0:85b3fd62ea1a 193
NYX 0:85b3fd62ea1a 194 /**
NYX 0:85b3fd62ea1a 195 \brief Union type to access the Application Program Status Register (APSR).
NYX 0:85b3fd62ea1a 196 */
NYX 0:85b3fd62ea1a 197 typedef union
NYX 0:85b3fd62ea1a 198 {
NYX 0:85b3fd62ea1a 199 struct
NYX 0:85b3fd62ea1a 200 {
NYX 0:85b3fd62ea1a 201 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
NYX 0:85b3fd62ea1a 202 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
NYX 0:85b3fd62ea1a 203 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
NYX 0:85b3fd62ea1a 204 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
NYX 0:85b3fd62ea1a 205 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
NYX 0:85b3fd62ea1a 206 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 207 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 208 } APSR_Type;
NYX 0:85b3fd62ea1a 209
NYX 0:85b3fd62ea1a 210 /* APSR Register Definitions */
NYX 0:85b3fd62ea1a 211 #define APSR_N_Pos 31U /*!< APSR: N Position */
NYX 0:85b3fd62ea1a 212 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
NYX 0:85b3fd62ea1a 213
NYX 0:85b3fd62ea1a 214 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
NYX 0:85b3fd62ea1a 215 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
NYX 0:85b3fd62ea1a 216
NYX 0:85b3fd62ea1a 217 #define APSR_C_Pos 29U /*!< APSR: C Position */
NYX 0:85b3fd62ea1a 218 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
NYX 0:85b3fd62ea1a 219
NYX 0:85b3fd62ea1a 220 #define APSR_V_Pos 28U /*!< APSR: V Position */
NYX 0:85b3fd62ea1a 221 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
NYX 0:85b3fd62ea1a 222
NYX 0:85b3fd62ea1a 223
NYX 0:85b3fd62ea1a 224 /**
NYX 0:85b3fd62ea1a 225 \brief Union type to access the Interrupt Program Status Register (IPSR).
NYX 0:85b3fd62ea1a 226 */
NYX 0:85b3fd62ea1a 227 typedef union
NYX 0:85b3fd62ea1a 228 {
NYX 0:85b3fd62ea1a 229 struct
NYX 0:85b3fd62ea1a 230 {
NYX 0:85b3fd62ea1a 231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
NYX 0:85b3fd62ea1a 232 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
NYX 0:85b3fd62ea1a 233 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 234 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 235 } IPSR_Type;
NYX 0:85b3fd62ea1a 236
NYX 0:85b3fd62ea1a 237 /* IPSR Register Definitions */
NYX 0:85b3fd62ea1a 238 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
NYX 0:85b3fd62ea1a 239 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
NYX 0:85b3fd62ea1a 240
NYX 0:85b3fd62ea1a 241
NYX 0:85b3fd62ea1a 242 /**
NYX 0:85b3fd62ea1a 243 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
NYX 0:85b3fd62ea1a 244 */
NYX 0:85b3fd62ea1a 245 typedef union
NYX 0:85b3fd62ea1a 246 {
NYX 0:85b3fd62ea1a 247 struct
NYX 0:85b3fd62ea1a 248 {
NYX 0:85b3fd62ea1a 249 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
NYX 0:85b3fd62ea1a 250 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
NYX 0:85b3fd62ea1a 251 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
NYX 0:85b3fd62ea1a 252 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
NYX 0:85b3fd62ea1a 253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
NYX 0:85b3fd62ea1a 254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
NYX 0:85b3fd62ea1a 255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
NYX 0:85b3fd62ea1a 256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
NYX 0:85b3fd62ea1a 257 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 258 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 259 } xPSR_Type;
NYX 0:85b3fd62ea1a 260
NYX 0:85b3fd62ea1a 261 /* xPSR Register Definitions */
NYX 0:85b3fd62ea1a 262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
NYX 0:85b3fd62ea1a 263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
NYX 0:85b3fd62ea1a 264
NYX 0:85b3fd62ea1a 265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
NYX 0:85b3fd62ea1a 266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
NYX 0:85b3fd62ea1a 267
NYX 0:85b3fd62ea1a 268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
NYX 0:85b3fd62ea1a 269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
NYX 0:85b3fd62ea1a 270
NYX 0:85b3fd62ea1a 271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
NYX 0:85b3fd62ea1a 272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
NYX 0:85b3fd62ea1a 273
NYX 0:85b3fd62ea1a 274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
NYX 0:85b3fd62ea1a 275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
NYX 0:85b3fd62ea1a 276
NYX 0:85b3fd62ea1a 277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
NYX 0:85b3fd62ea1a 278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
NYX 0:85b3fd62ea1a 279
NYX 0:85b3fd62ea1a 280
NYX 0:85b3fd62ea1a 281 /**
NYX 0:85b3fd62ea1a 282 \brief Union type to access the Control Registers (CONTROL).
NYX 0:85b3fd62ea1a 283 */
NYX 0:85b3fd62ea1a 284 typedef union
NYX 0:85b3fd62ea1a 285 {
NYX 0:85b3fd62ea1a 286 struct
NYX 0:85b3fd62ea1a 287 {
NYX 0:85b3fd62ea1a 288 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
NYX 0:85b3fd62ea1a 289 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
NYX 0:85b3fd62ea1a 290 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
NYX 0:85b3fd62ea1a 291 } b; /*!< Structure used for bit access */
NYX 0:85b3fd62ea1a 292 uint32_t w; /*!< Type used for word access */
NYX 0:85b3fd62ea1a 293 } CONTROL_Type;
NYX 0:85b3fd62ea1a 294
NYX 0:85b3fd62ea1a 295 /* CONTROL Register Definitions */
NYX 0:85b3fd62ea1a 296 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
NYX 0:85b3fd62ea1a 297 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
NYX 0:85b3fd62ea1a 298
NYX 0:85b3fd62ea1a 299 /*@} end of group CMSIS_CORE */
NYX 0:85b3fd62ea1a 300
NYX 0:85b3fd62ea1a 301
NYX 0:85b3fd62ea1a 302 /**
NYX 0:85b3fd62ea1a 303 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 304 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
NYX 0:85b3fd62ea1a 305 \brief Type definitions for the NVIC Registers
NYX 0:85b3fd62ea1a 306 @{
NYX 0:85b3fd62ea1a 307 */
NYX 0:85b3fd62ea1a 308
NYX 0:85b3fd62ea1a 309 /**
NYX 0:85b3fd62ea1a 310 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
NYX 0:85b3fd62ea1a 311 */
NYX 0:85b3fd62ea1a 312 typedef struct
NYX 0:85b3fd62ea1a 313 {
NYX 0:85b3fd62ea1a 314 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
NYX 0:85b3fd62ea1a 315 uint32_t RESERVED0[31U];
NYX 0:85b3fd62ea1a 316 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
NYX 0:85b3fd62ea1a 317 uint32_t RSERVED1[31U];
NYX 0:85b3fd62ea1a 318 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
NYX 0:85b3fd62ea1a 319 uint32_t RESERVED2[31U];
NYX 0:85b3fd62ea1a 320 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
NYX 0:85b3fd62ea1a 321 uint32_t RESERVED3[31U];
NYX 0:85b3fd62ea1a 322 uint32_t RESERVED4[64U];
NYX 0:85b3fd62ea1a 323 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
NYX 0:85b3fd62ea1a 324 } NVIC_Type;
NYX 0:85b3fd62ea1a 325
NYX 0:85b3fd62ea1a 326 /*@} end of group CMSIS_NVIC */
NYX 0:85b3fd62ea1a 327
NYX 0:85b3fd62ea1a 328
NYX 0:85b3fd62ea1a 329 /**
NYX 0:85b3fd62ea1a 330 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 331 \defgroup CMSIS_SCB System Control Block (SCB)
NYX 0:85b3fd62ea1a 332 \brief Type definitions for the System Control Block Registers
NYX 0:85b3fd62ea1a 333 @{
NYX 0:85b3fd62ea1a 334 */
NYX 0:85b3fd62ea1a 335
NYX 0:85b3fd62ea1a 336 /**
NYX 0:85b3fd62ea1a 337 \brief Structure type to access the System Control Block (SCB).
NYX 0:85b3fd62ea1a 338 */
NYX 0:85b3fd62ea1a 339 typedef struct
NYX 0:85b3fd62ea1a 340 {
NYX 0:85b3fd62ea1a 341 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
NYX 0:85b3fd62ea1a 342 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
NYX 0:85b3fd62ea1a 343 uint32_t RESERVED0;
NYX 0:85b3fd62ea1a 344 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
NYX 0:85b3fd62ea1a 345 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
NYX 0:85b3fd62ea1a 346 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
NYX 0:85b3fd62ea1a 347 uint32_t RESERVED1;
NYX 0:85b3fd62ea1a 348 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
NYX 0:85b3fd62ea1a 349 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
NYX 0:85b3fd62ea1a 350 } SCB_Type;
NYX 0:85b3fd62ea1a 351
NYX 0:85b3fd62ea1a 352 /* SCB CPUID Register Definitions */
NYX 0:85b3fd62ea1a 353 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
NYX 0:85b3fd62ea1a 354 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
NYX 0:85b3fd62ea1a 355
NYX 0:85b3fd62ea1a 356 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
NYX 0:85b3fd62ea1a 357 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
NYX 0:85b3fd62ea1a 358
NYX 0:85b3fd62ea1a 359 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
NYX 0:85b3fd62ea1a 360 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
NYX 0:85b3fd62ea1a 361
NYX 0:85b3fd62ea1a 362 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
NYX 0:85b3fd62ea1a 363 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
NYX 0:85b3fd62ea1a 364
NYX 0:85b3fd62ea1a 365 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
NYX 0:85b3fd62ea1a 366 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
NYX 0:85b3fd62ea1a 367
NYX 0:85b3fd62ea1a 368 /* SCB Interrupt Control State Register Definitions */
NYX 0:85b3fd62ea1a 369 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
NYX 0:85b3fd62ea1a 370 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
NYX 0:85b3fd62ea1a 371
NYX 0:85b3fd62ea1a 372 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
NYX 0:85b3fd62ea1a 373 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
NYX 0:85b3fd62ea1a 374
NYX 0:85b3fd62ea1a 375 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
NYX 0:85b3fd62ea1a 376 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
NYX 0:85b3fd62ea1a 377
NYX 0:85b3fd62ea1a 378 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
NYX 0:85b3fd62ea1a 379 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
NYX 0:85b3fd62ea1a 380
NYX 0:85b3fd62ea1a 381 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
NYX 0:85b3fd62ea1a 382 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
NYX 0:85b3fd62ea1a 383
NYX 0:85b3fd62ea1a 384 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
NYX 0:85b3fd62ea1a 385 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
NYX 0:85b3fd62ea1a 386
NYX 0:85b3fd62ea1a 387 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
NYX 0:85b3fd62ea1a 388 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
NYX 0:85b3fd62ea1a 389
NYX 0:85b3fd62ea1a 390 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
NYX 0:85b3fd62ea1a 391 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
NYX 0:85b3fd62ea1a 392
NYX 0:85b3fd62ea1a 393 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
NYX 0:85b3fd62ea1a 394 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
NYX 0:85b3fd62ea1a 395
NYX 0:85b3fd62ea1a 396 /* SCB Application Interrupt and Reset Control Register Definitions */
NYX 0:85b3fd62ea1a 397 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
NYX 0:85b3fd62ea1a 398 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
NYX 0:85b3fd62ea1a 399
NYX 0:85b3fd62ea1a 400 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
NYX 0:85b3fd62ea1a 401 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
NYX 0:85b3fd62ea1a 402
NYX 0:85b3fd62ea1a 403 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
NYX 0:85b3fd62ea1a 404 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
NYX 0:85b3fd62ea1a 405
NYX 0:85b3fd62ea1a 406 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
NYX 0:85b3fd62ea1a 407 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
NYX 0:85b3fd62ea1a 408
NYX 0:85b3fd62ea1a 409 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
NYX 0:85b3fd62ea1a 410 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
NYX 0:85b3fd62ea1a 411
NYX 0:85b3fd62ea1a 412 /* SCB System Control Register Definitions */
NYX 0:85b3fd62ea1a 413 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
NYX 0:85b3fd62ea1a 414 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
NYX 0:85b3fd62ea1a 415
NYX 0:85b3fd62ea1a 416 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
NYX 0:85b3fd62ea1a 417 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
NYX 0:85b3fd62ea1a 418
NYX 0:85b3fd62ea1a 419 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
NYX 0:85b3fd62ea1a 420 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
NYX 0:85b3fd62ea1a 421
NYX 0:85b3fd62ea1a 422 /* SCB Configuration Control Register Definitions */
NYX 0:85b3fd62ea1a 423 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
NYX 0:85b3fd62ea1a 424 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
NYX 0:85b3fd62ea1a 425
NYX 0:85b3fd62ea1a 426 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
NYX 0:85b3fd62ea1a 427 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
NYX 0:85b3fd62ea1a 428
NYX 0:85b3fd62ea1a 429 /* SCB System Handler Control and State Register Definitions */
NYX 0:85b3fd62ea1a 430 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
NYX 0:85b3fd62ea1a 431 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
NYX 0:85b3fd62ea1a 432
NYX 0:85b3fd62ea1a 433 /*@} end of group CMSIS_SCB */
NYX 0:85b3fd62ea1a 434
NYX 0:85b3fd62ea1a 435
NYX 0:85b3fd62ea1a 436 /**
NYX 0:85b3fd62ea1a 437 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 438 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
NYX 0:85b3fd62ea1a 439 \brief Type definitions for the System Timer Registers.
NYX 0:85b3fd62ea1a 440 @{
NYX 0:85b3fd62ea1a 441 */
NYX 0:85b3fd62ea1a 442
NYX 0:85b3fd62ea1a 443 /**
NYX 0:85b3fd62ea1a 444 \brief Structure type to access the System Timer (SysTick).
NYX 0:85b3fd62ea1a 445 */
NYX 0:85b3fd62ea1a 446 typedef struct
NYX 0:85b3fd62ea1a 447 {
NYX 0:85b3fd62ea1a 448 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
NYX 0:85b3fd62ea1a 449 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
NYX 0:85b3fd62ea1a 450 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
NYX 0:85b3fd62ea1a 451 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
NYX 0:85b3fd62ea1a 452 } SysTick_Type;
NYX 0:85b3fd62ea1a 453
NYX 0:85b3fd62ea1a 454 /* SysTick Control / Status Register Definitions */
NYX 0:85b3fd62ea1a 455 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
NYX 0:85b3fd62ea1a 456 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
NYX 0:85b3fd62ea1a 457
NYX 0:85b3fd62ea1a 458 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
NYX 0:85b3fd62ea1a 459 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
NYX 0:85b3fd62ea1a 460
NYX 0:85b3fd62ea1a 461 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
NYX 0:85b3fd62ea1a 462 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
NYX 0:85b3fd62ea1a 463
NYX 0:85b3fd62ea1a 464 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
NYX 0:85b3fd62ea1a 465 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
NYX 0:85b3fd62ea1a 466
NYX 0:85b3fd62ea1a 467 /* SysTick Reload Register Definitions */
NYX 0:85b3fd62ea1a 468 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
NYX 0:85b3fd62ea1a 469 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
NYX 0:85b3fd62ea1a 470
NYX 0:85b3fd62ea1a 471 /* SysTick Current Register Definitions */
NYX 0:85b3fd62ea1a 472 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
NYX 0:85b3fd62ea1a 473 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
NYX 0:85b3fd62ea1a 474
NYX 0:85b3fd62ea1a 475 /* SysTick Calibration Register Definitions */
NYX 0:85b3fd62ea1a 476 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
NYX 0:85b3fd62ea1a 477 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
NYX 0:85b3fd62ea1a 478
NYX 0:85b3fd62ea1a 479 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
NYX 0:85b3fd62ea1a 480 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
NYX 0:85b3fd62ea1a 481
NYX 0:85b3fd62ea1a 482 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
NYX 0:85b3fd62ea1a 483 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
NYX 0:85b3fd62ea1a 484
NYX 0:85b3fd62ea1a 485 /*@} end of group CMSIS_SysTick */
NYX 0:85b3fd62ea1a 486
NYX 0:85b3fd62ea1a 487
NYX 0:85b3fd62ea1a 488 /**
NYX 0:85b3fd62ea1a 489 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 490 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
NYX 0:85b3fd62ea1a 491 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
NYX 0:85b3fd62ea1a 492 Therefore they are not covered by the Cortex-M0 header file.
NYX 0:85b3fd62ea1a 493 @{
NYX 0:85b3fd62ea1a 494 */
NYX 0:85b3fd62ea1a 495 /*@} end of group CMSIS_CoreDebug */
NYX 0:85b3fd62ea1a 496
NYX 0:85b3fd62ea1a 497
NYX 0:85b3fd62ea1a 498 /**
NYX 0:85b3fd62ea1a 499 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 500 \defgroup CMSIS_core_bitfield Core register bit field macros
NYX 0:85b3fd62ea1a 501 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
NYX 0:85b3fd62ea1a 502 @{
NYX 0:85b3fd62ea1a 503 */
NYX 0:85b3fd62ea1a 504
NYX 0:85b3fd62ea1a 505 /**
NYX 0:85b3fd62ea1a 506 \brief Mask and shift a bit field value for use in a register bit range.
NYX 0:85b3fd62ea1a 507 \param[in] field Name of the register bit field.
NYX 0:85b3fd62ea1a 508 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
NYX 0:85b3fd62ea1a 509 \return Masked and shifted value.
NYX 0:85b3fd62ea1a 510 */
NYX 0:85b3fd62ea1a 511 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
NYX 0:85b3fd62ea1a 512
NYX 0:85b3fd62ea1a 513 /**
NYX 0:85b3fd62ea1a 514 \brief Mask and shift a register value to extract a bit filed value.
NYX 0:85b3fd62ea1a 515 \param[in] field Name of the register bit field.
NYX 0:85b3fd62ea1a 516 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
NYX 0:85b3fd62ea1a 517 \return Masked and shifted bit field value.
NYX 0:85b3fd62ea1a 518 */
NYX 0:85b3fd62ea1a 519 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
NYX 0:85b3fd62ea1a 520
NYX 0:85b3fd62ea1a 521 /*@} end of group CMSIS_core_bitfield */
NYX 0:85b3fd62ea1a 522
NYX 0:85b3fd62ea1a 523
NYX 0:85b3fd62ea1a 524 /**
NYX 0:85b3fd62ea1a 525 \ingroup CMSIS_core_register
NYX 0:85b3fd62ea1a 526 \defgroup CMSIS_core_base Core Definitions
NYX 0:85b3fd62ea1a 527 \brief Definitions for base addresses, unions, and structures.
NYX 0:85b3fd62ea1a 528 @{
NYX 0:85b3fd62ea1a 529 */
NYX 0:85b3fd62ea1a 530
NYX 0:85b3fd62ea1a 531 /* Memory mapping of Core Hardware */
NYX 0:85b3fd62ea1a 532 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
NYX 0:85b3fd62ea1a 533 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
NYX 0:85b3fd62ea1a 534 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
NYX 0:85b3fd62ea1a 535 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
NYX 0:85b3fd62ea1a 536
NYX 0:85b3fd62ea1a 537 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
NYX 0:85b3fd62ea1a 538 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
NYX 0:85b3fd62ea1a 539 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
NYX 0:85b3fd62ea1a 540
NYX 0:85b3fd62ea1a 541
NYX 0:85b3fd62ea1a 542 /*@} */
NYX 0:85b3fd62ea1a 543
NYX 0:85b3fd62ea1a 544
NYX 0:85b3fd62ea1a 545
NYX 0:85b3fd62ea1a 546 /*******************************************************************************
NYX 0:85b3fd62ea1a 547 * Hardware Abstraction Layer
NYX 0:85b3fd62ea1a 548 Core Function Interface contains:
NYX 0:85b3fd62ea1a 549 - Core NVIC Functions
NYX 0:85b3fd62ea1a 550 - Core SysTick Functions
NYX 0:85b3fd62ea1a 551 - Core Register Access Functions
NYX 0:85b3fd62ea1a 552 ******************************************************************************/
NYX 0:85b3fd62ea1a 553 /**
NYX 0:85b3fd62ea1a 554 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
NYX 0:85b3fd62ea1a 555 */
NYX 0:85b3fd62ea1a 556
NYX 0:85b3fd62ea1a 557
NYX 0:85b3fd62ea1a 558
NYX 0:85b3fd62ea1a 559 /* ########################## NVIC functions #################################### */
NYX 0:85b3fd62ea1a 560 /**
NYX 0:85b3fd62ea1a 561 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 562 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
NYX 0:85b3fd62ea1a 563 \brief Functions that manage interrupts and exceptions via the NVIC.
NYX 0:85b3fd62ea1a 564 @{
NYX 0:85b3fd62ea1a 565 */
NYX 0:85b3fd62ea1a 566
NYX 0:85b3fd62ea1a 567 #ifdef CMSIS_NVIC_VIRTUAL
NYX 0:85b3fd62ea1a 568 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 569 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
NYX 0:85b3fd62ea1a 570 #endif
NYX 0:85b3fd62ea1a 571 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 572 #else
NYX 0:85b3fd62ea1a 573 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
NYX 0:85b3fd62ea1a 574 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
NYX 0:85b3fd62ea1a 575 #define NVIC_EnableIRQ __NVIC_EnableIRQ
NYX 0:85b3fd62ea1a 576 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
NYX 0:85b3fd62ea1a 577 #define NVIC_DisableIRQ __NVIC_DisableIRQ
NYX 0:85b3fd62ea1a 578 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
NYX 0:85b3fd62ea1a 579 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
NYX 0:85b3fd62ea1a 580 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
NYX 0:85b3fd62ea1a 581 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
NYX 0:85b3fd62ea1a 582 #define NVIC_SetPriority __NVIC_SetPriority
NYX 0:85b3fd62ea1a 583 #define NVIC_GetPriority __NVIC_GetPriority
NYX 0:85b3fd62ea1a 584 #define NVIC_SystemReset __NVIC_SystemReset
NYX 0:85b3fd62ea1a 585 #endif /* CMSIS_NVIC_VIRTUAL */
NYX 0:85b3fd62ea1a 586
NYX 0:85b3fd62ea1a 587 #ifdef CMSIS_VECTAB_VIRTUAL
NYX 0:85b3fd62ea1a 588 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 589 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
NYX 0:85b3fd62ea1a 590 #endif
NYX 0:85b3fd62ea1a 591 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
NYX 0:85b3fd62ea1a 592 #else
NYX 0:85b3fd62ea1a 593 #define NVIC_SetVector __NVIC_SetVector
NYX 0:85b3fd62ea1a 594 #define NVIC_GetVector __NVIC_GetVector
NYX 0:85b3fd62ea1a 595 #endif /* (CMSIS_VECTAB_VIRTUAL) */
NYX 0:85b3fd62ea1a 596
NYX 0:85b3fd62ea1a 597 #define NVIC_USER_IRQ_OFFSET 16
NYX 0:85b3fd62ea1a 598
NYX 0:85b3fd62ea1a 599
NYX 0:85b3fd62ea1a 600 /* Interrupt Priorities are WORD accessible only under ARMv6M */
NYX 0:85b3fd62ea1a 601 /* The following MACROS handle generation of the register offset and byte masks */
NYX 0:85b3fd62ea1a 602 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
NYX 0:85b3fd62ea1a 603 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
NYX 0:85b3fd62ea1a 604 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
NYX 0:85b3fd62ea1a 605
NYX 0:85b3fd62ea1a 606
NYX 0:85b3fd62ea1a 607 /**
NYX 0:85b3fd62ea1a 608 \brief Enable Interrupt
NYX 0:85b3fd62ea1a 609 \details Enables a device specific interrupt in the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 610 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 611 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 612 */
NYX 0:85b3fd62ea1a 613 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 614 {
NYX 0:85b3fd62ea1a 615 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 616 {
NYX 0:85b3fd62ea1a 617 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 618 }
NYX 0:85b3fd62ea1a 619 }
NYX 0:85b3fd62ea1a 620
NYX 0:85b3fd62ea1a 621
NYX 0:85b3fd62ea1a 622 /**
NYX 0:85b3fd62ea1a 623 \brief Get Interrupt Enable status
NYX 0:85b3fd62ea1a 624 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 625 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 626 \return 0 Interrupt is not enabled.
NYX 0:85b3fd62ea1a 627 \return 1 Interrupt is enabled.
NYX 0:85b3fd62ea1a 628 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 629 */
NYX 0:85b3fd62ea1a 630 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 631 {
NYX 0:85b3fd62ea1a 632 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 633 {
NYX 0:85b3fd62ea1a 634 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 635 }
NYX 0:85b3fd62ea1a 636 else
NYX 0:85b3fd62ea1a 637 {
NYX 0:85b3fd62ea1a 638 return(0U);
NYX 0:85b3fd62ea1a 639 }
NYX 0:85b3fd62ea1a 640 }
NYX 0:85b3fd62ea1a 641
NYX 0:85b3fd62ea1a 642
NYX 0:85b3fd62ea1a 643 /**
NYX 0:85b3fd62ea1a 644 \brief Disable Interrupt
NYX 0:85b3fd62ea1a 645 \details Disables a device specific interrupt in the NVIC interrupt controller.
NYX 0:85b3fd62ea1a 646 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 647 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 648 */
NYX 0:85b3fd62ea1a 649 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 650 {
NYX 0:85b3fd62ea1a 651 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 652 {
NYX 0:85b3fd62ea1a 653 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 654 __DSB();
NYX 0:85b3fd62ea1a 655 __ISB();
NYX 0:85b3fd62ea1a 656 }
NYX 0:85b3fd62ea1a 657 }
NYX 0:85b3fd62ea1a 658
NYX 0:85b3fd62ea1a 659
NYX 0:85b3fd62ea1a 660 /**
NYX 0:85b3fd62ea1a 661 \brief Get Pending Interrupt
NYX 0:85b3fd62ea1a 662 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
NYX 0:85b3fd62ea1a 663 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 664 \return 0 Interrupt status is not pending.
NYX 0:85b3fd62ea1a 665 \return 1 Interrupt status is pending.
NYX 0:85b3fd62ea1a 666 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 667 */
NYX 0:85b3fd62ea1a 668 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 669 {
NYX 0:85b3fd62ea1a 670 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 671 {
NYX 0:85b3fd62ea1a 672 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
NYX 0:85b3fd62ea1a 673 }
NYX 0:85b3fd62ea1a 674 else
NYX 0:85b3fd62ea1a 675 {
NYX 0:85b3fd62ea1a 676 return(0U);
NYX 0:85b3fd62ea1a 677 }
NYX 0:85b3fd62ea1a 678 }
NYX 0:85b3fd62ea1a 679
NYX 0:85b3fd62ea1a 680
NYX 0:85b3fd62ea1a 681 /**
NYX 0:85b3fd62ea1a 682 \brief Set Pending Interrupt
NYX 0:85b3fd62ea1a 683 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
NYX 0:85b3fd62ea1a 684 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 685 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 686 */
NYX 0:85b3fd62ea1a 687 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 688 {
NYX 0:85b3fd62ea1a 689 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 690 {
NYX 0:85b3fd62ea1a 691 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 692 }
NYX 0:85b3fd62ea1a 693 }
NYX 0:85b3fd62ea1a 694
NYX 0:85b3fd62ea1a 695
NYX 0:85b3fd62ea1a 696 /**
NYX 0:85b3fd62ea1a 697 \brief Clear Pending Interrupt
NYX 0:85b3fd62ea1a 698 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
NYX 0:85b3fd62ea1a 699 \param [in] IRQn Device specific interrupt number.
NYX 0:85b3fd62ea1a 700 \note IRQn must not be negative.
NYX 0:85b3fd62ea1a 701 */
NYX 0:85b3fd62ea1a 702 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 703 {
NYX 0:85b3fd62ea1a 704 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 705 {
NYX 0:85b3fd62ea1a 706 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
NYX 0:85b3fd62ea1a 707 }
NYX 0:85b3fd62ea1a 708 }
NYX 0:85b3fd62ea1a 709
NYX 0:85b3fd62ea1a 710
NYX 0:85b3fd62ea1a 711 /**
NYX 0:85b3fd62ea1a 712 \brief Set Interrupt Priority
NYX 0:85b3fd62ea1a 713 \details Sets the priority of a device specific interrupt or a processor exception.
NYX 0:85b3fd62ea1a 714 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 715 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 716 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 717 \param [in] priority Priority to set.
NYX 0:85b3fd62ea1a 718 \note The priority cannot be set for every processor exception.
NYX 0:85b3fd62ea1a 719 */
NYX 0:85b3fd62ea1a 720 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
NYX 0:85b3fd62ea1a 721 {
NYX 0:85b3fd62ea1a 722 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 723 {
NYX 0:85b3fd62ea1a 724 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
NYX 0:85b3fd62ea1a 725 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NYX 0:85b3fd62ea1a 726 }
NYX 0:85b3fd62ea1a 727 else
NYX 0:85b3fd62ea1a 728 {
NYX 0:85b3fd62ea1a 729 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
NYX 0:85b3fd62ea1a 730 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
NYX 0:85b3fd62ea1a 731 }
NYX 0:85b3fd62ea1a 732 }
NYX 0:85b3fd62ea1a 733
NYX 0:85b3fd62ea1a 734
NYX 0:85b3fd62ea1a 735 /**
NYX 0:85b3fd62ea1a 736 \brief Get Interrupt Priority
NYX 0:85b3fd62ea1a 737 \details Reads the priority of a device specific interrupt or a processor exception.
NYX 0:85b3fd62ea1a 738 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 739 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 740 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 741 \return Interrupt Priority.
NYX 0:85b3fd62ea1a 742 Value is aligned automatically to the implemented priority bits of the microcontroller.
NYX 0:85b3fd62ea1a 743 */
NYX 0:85b3fd62ea1a 744 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 745 {
NYX 0:85b3fd62ea1a 746
NYX 0:85b3fd62ea1a 747 if ((int32_t)(IRQn) >= 0)
NYX 0:85b3fd62ea1a 748 {
NYX 0:85b3fd62ea1a 749 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
NYX 0:85b3fd62ea1a 750 }
NYX 0:85b3fd62ea1a 751 else
NYX 0:85b3fd62ea1a 752 {
NYX 0:85b3fd62ea1a 753 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
NYX 0:85b3fd62ea1a 754 }
NYX 0:85b3fd62ea1a 755 }
NYX 0:85b3fd62ea1a 756
NYX 0:85b3fd62ea1a 757
NYX 0:85b3fd62ea1a 758 /**
NYX 0:85b3fd62ea1a 759 \brief Set Interrupt Vector
NYX 0:85b3fd62ea1a 760 \details Sets an interrupt vector in SRAM based interrupt vector table.
NYX 0:85b3fd62ea1a 761 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 762 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 763 Address 0 must be mapped to SRAM.
NYX 0:85b3fd62ea1a 764 \param [in] IRQn Interrupt number
NYX 0:85b3fd62ea1a 765 \param [in] vector Address of interrupt handler function
NYX 0:85b3fd62ea1a 766 */
NYX 0:85b3fd62ea1a 767 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
NYX 0:85b3fd62ea1a 768 {
NYX 0:85b3fd62ea1a 769 uint32_t *vectors = (uint32_t *)0x0U;
NYX 0:85b3fd62ea1a 770 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
NYX 0:85b3fd62ea1a 771 }
NYX 0:85b3fd62ea1a 772
NYX 0:85b3fd62ea1a 773
NYX 0:85b3fd62ea1a 774 /**
NYX 0:85b3fd62ea1a 775 \brief Get Interrupt Vector
NYX 0:85b3fd62ea1a 776 \details Reads an interrupt vector from interrupt vector table.
NYX 0:85b3fd62ea1a 777 The interrupt number can be positive to specify a device specific interrupt,
NYX 0:85b3fd62ea1a 778 or negative to specify a processor exception.
NYX 0:85b3fd62ea1a 779 \param [in] IRQn Interrupt number.
NYX 0:85b3fd62ea1a 780 \return Address of interrupt handler function
NYX 0:85b3fd62ea1a 781 */
NYX 0:85b3fd62ea1a 782 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
NYX 0:85b3fd62ea1a 783 {
NYX 0:85b3fd62ea1a 784 uint32_t *vectors = (uint32_t *)0x0U;
NYX 0:85b3fd62ea1a 785 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
NYX 0:85b3fd62ea1a 786 }
NYX 0:85b3fd62ea1a 787
NYX 0:85b3fd62ea1a 788
NYX 0:85b3fd62ea1a 789 /**
NYX 0:85b3fd62ea1a 790 \brief System Reset
NYX 0:85b3fd62ea1a 791 \details Initiates a system reset request to reset the MCU.
NYX 0:85b3fd62ea1a 792 */
NYX 0:85b3fd62ea1a 793 __STATIC_INLINE void __NVIC_SystemReset(void)
NYX 0:85b3fd62ea1a 794 {
NYX 0:85b3fd62ea1a 795 __DSB(); /* Ensure all outstanding memory accesses included
NYX 0:85b3fd62ea1a 796 buffered write are completed before reset */
NYX 0:85b3fd62ea1a 797 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
NYX 0:85b3fd62ea1a 798 SCB_AIRCR_SYSRESETREQ_Msk);
NYX 0:85b3fd62ea1a 799 __DSB(); /* Ensure completion of memory access */
NYX 0:85b3fd62ea1a 800
NYX 0:85b3fd62ea1a 801 for(;;) /* wait until reset */
NYX 0:85b3fd62ea1a 802 {
NYX 0:85b3fd62ea1a 803 __NOP();
NYX 0:85b3fd62ea1a 804 }
NYX 0:85b3fd62ea1a 805 }
NYX 0:85b3fd62ea1a 806
NYX 0:85b3fd62ea1a 807 /*@} end of CMSIS_Core_NVICFunctions */
NYX 0:85b3fd62ea1a 808
NYX 0:85b3fd62ea1a 809
NYX 0:85b3fd62ea1a 810 /* ########################## FPU functions #################################### */
NYX 0:85b3fd62ea1a 811 /**
NYX 0:85b3fd62ea1a 812 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 813 \defgroup CMSIS_Core_FpuFunctions FPU Functions
NYX 0:85b3fd62ea1a 814 \brief Function that provides FPU type.
NYX 0:85b3fd62ea1a 815 @{
NYX 0:85b3fd62ea1a 816 */
NYX 0:85b3fd62ea1a 817
NYX 0:85b3fd62ea1a 818 /**
NYX 0:85b3fd62ea1a 819 \brief get FPU type
NYX 0:85b3fd62ea1a 820 \details returns the FPU type
NYX 0:85b3fd62ea1a 821 \returns
NYX 0:85b3fd62ea1a 822 - \b 0: No FPU
NYX 0:85b3fd62ea1a 823 - \b 1: Single precision FPU
NYX 0:85b3fd62ea1a 824 - \b 2: Double + Single precision FPU
NYX 0:85b3fd62ea1a 825 */
NYX 0:85b3fd62ea1a 826 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
NYX 0:85b3fd62ea1a 827 {
NYX 0:85b3fd62ea1a 828 return 0U; /* No FPU */
NYX 0:85b3fd62ea1a 829 }
NYX 0:85b3fd62ea1a 830
NYX 0:85b3fd62ea1a 831
NYX 0:85b3fd62ea1a 832 /*@} end of CMSIS_Core_FpuFunctions */
NYX 0:85b3fd62ea1a 833
NYX 0:85b3fd62ea1a 834
NYX 0:85b3fd62ea1a 835
NYX 0:85b3fd62ea1a 836 /* ################################## SysTick function ############################################ */
NYX 0:85b3fd62ea1a 837 /**
NYX 0:85b3fd62ea1a 838 \ingroup CMSIS_Core_FunctionInterface
NYX 0:85b3fd62ea1a 839 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
NYX 0:85b3fd62ea1a 840 \brief Functions that configure the System.
NYX 0:85b3fd62ea1a 841 @{
NYX 0:85b3fd62ea1a 842 */
NYX 0:85b3fd62ea1a 843
NYX 0:85b3fd62ea1a 844 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
NYX 0:85b3fd62ea1a 845
NYX 0:85b3fd62ea1a 846 /**
NYX 0:85b3fd62ea1a 847 \brief System Tick Configuration
NYX 0:85b3fd62ea1a 848 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
NYX 0:85b3fd62ea1a 849 Counter is in free running mode to generate periodic interrupts.
NYX 0:85b3fd62ea1a 850 \param [in] ticks Number of ticks between two interrupts.
NYX 0:85b3fd62ea1a 851 \return 0 Function succeeded.
NYX 0:85b3fd62ea1a 852 \return 1 Function failed.
NYX 0:85b3fd62ea1a 853 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
NYX 0:85b3fd62ea1a 854 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
NYX 0:85b3fd62ea1a 855 must contain a vendor-specific implementation of this function.
NYX 0:85b3fd62ea1a 856 */
NYX 0:85b3fd62ea1a 857 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
NYX 0:85b3fd62ea1a 858 {
NYX 0:85b3fd62ea1a 859 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
NYX 0:85b3fd62ea1a 860 {
NYX 0:85b3fd62ea1a 861 return (1UL); /* Reload value impossible */
NYX 0:85b3fd62ea1a 862 }
NYX 0:85b3fd62ea1a 863
NYX 0:85b3fd62ea1a 864 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NYX 0:85b3fd62ea1a 865 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
NYX 0:85b3fd62ea1a 866 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NYX 0:85b3fd62ea1a 867 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
NYX 0:85b3fd62ea1a 868 SysTick_CTRL_TICKINT_Msk |
NYX 0:85b3fd62ea1a 869 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
NYX 0:85b3fd62ea1a 870 return (0UL); /* Function successful */
NYX 0:85b3fd62ea1a 871 }
NYX 0:85b3fd62ea1a 872
NYX 0:85b3fd62ea1a 873 #endif
NYX 0:85b3fd62ea1a 874
NYX 0:85b3fd62ea1a 875 /*@} end of CMSIS_Core_SysTickFunctions */
NYX 0:85b3fd62ea1a 876
NYX 0:85b3fd62ea1a 877
NYX 0:85b3fd62ea1a 878
NYX 0:85b3fd62ea1a 879
NYX 0:85b3fd62ea1a 880 #ifdef __cplusplus
NYX 0:85b3fd62ea1a 881 }
NYX 0:85b3fd62ea1a 882 #endif
NYX 0:85b3fd62ea1a 883
NYX 0:85b3fd62ea1a 884 #endif /* __CORE_CM0_H_DEPENDANT */
NYX 0:85b3fd62ea1a 885
NYX 0:85b3fd62ea1a 886 #endif /* __CMSIS_GENERIC */