mbed-dev - inport from local

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inport from local

cmsis/core_ca.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

Committer:: NYX
Date:: Mon Mar 16 06:35:48 2020 +0000
Revision:: 0:85b3fd62ea1a

reinport to mbed;

Who changed what in which revision?

User	Revision	Line number	New contents of line
NYX	0:85b3fd62ea1a	1	/************************************************************************//
NYX	0:85b3fd62ea1a	2	* @file core_ca.h
NYX	0:85b3fd62ea1a	3	* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
NYX	0:85b3fd62ea1a	4	* @version V1.00
NYX	0:85b3fd62ea1a	5	* @date 22. Feb 2017
NYX	0:85b3fd62ea1a	6	******************************************************************************/
NYX	0:85b3fd62ea1a	7	/*
NYX	0:85b3fd62ea1a	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
NYX	0:85b3fd62ea1a	9	*
NYX	0:85b3fd62ea1a	10	* SPDX-License-Identifier: Apache-2.0
NYX	0:85b3fd62ea1a	11	*
NYX	0:85b3fd62ea1a	12	* Licensed under the Apache License, Version 2.0 (the License); you may
NYX	0:85b3fd62ea1a	13	* not use this file except in compliance with the License.
NYX	0:85b3fd62ea1a	14	* You may obtain a copy of the License at
NYX	0:85b3fd62ea1a	15	*
NYX	0:85b3fd62ea1a	16	* www.apache.org/licenses/LICENSE-2.0
NYX	0:85b3fd62ea1a	17	*
NYX	0:85b3fd62ea1a	18	* Unless required by applicable law or agreed to in writing, software
NYX	0:85b3fd62ea1a	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
NYX	0:85b3fd62ea1a	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
NYX	0:85b3fd62ea1a	21	* See the License for the specific language governing permissions and
NYX	0:85b3fd62ea1a	22	* limitations under the License.
NYX	0:85b3fd62ea1a	23	*/
NYX	0:85b3fd62ea1a	24
NYX	0:85b3fd62ea1a	25	#if defined ( __ICCARM__ )
NYX	0:85b3fd62ea1a	26	#pragma system_include /* treat file as system include file for MISRA check */
NYX	0:85b3fd62ea1a	27	#endif
NYX	0:85b3fd62ea1a	28
NYX	0:85b3fd62ea1a	29	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	30	extern "C" {
NYX	0:85b3fd62ea1a	31	#endif
NYX	0:85b3fd62ea1a	32
NYX	0:85b3fd62ea1a	33	#ifndef __CORE_CA_H_GENERIC
NYX	0:85b3fd62ea1a	34	#define __CORE_CA_H_GENERIC
NYX	0:85b3fd62ea1a	35
NYX	0:85b3fd62ea1a	36
NYX	0:85b3fd62ea1a	37	/*******************************************************************************
NYX	0:85b3fd62ea1a	38	* CMSIS definitions
NYX	0:85b3fd62ea1a	39	******************************************************************************/
NYX	0:85b3fd62ea1a	40
NYX	0:85b3fd62ea1a	41	/* CMSIS CA definitions */
NYX	0:85b3fd62ea1a	42	#define __CA_CMSIS_VERSION_MAIN (1U) /!< \brief [31:16] CMSIS HAL main version /
NYX	0:85b3fd62ea1a	43	#define __CA_CMSIS_VERSION_SUB (0U) /!< \brief [15:0] CMSIS HAL sub version /
NYX	0:85b3fd62ea1a	44	#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) \| \
NYX	0:85b3fd62ea1a	45	__CA_CMSIS_VERSION_SUB ) /!< \brief CMSIS HAL version number /
NYX	0:85b3fd62ea1a	46
NYX	0:85b3fd62ea1a	47	#if defined ( __CC_ARM )
NYX	0:85b3fd62ea1a	48	#if defined __TARGET_FPU_VFP
NYX	0:85b3fd62ea1a	49	#if (__FPU_PRESENT == 1)
NYX	0:85b3fd62ea1a	50	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	51	#else
NYX	0:85b3fd62ea1a	52	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	53	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	54	#endif
NYX	0:85b3fd62ea1a	55	#else
NYX	0:85b3fd62ea1a	56	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	57	#endif
NYX	0:85b3fd62ea1a	58
NYX	0:85b3fd62ea1a	59	#elif defined ( __ICCARM__ )
NYX	0:85b3fd62ea1a	60	#if defined __ARMVFP__
NYX	0:85b3fd62ea1a	61	#if (__FPU_PRESENT == 1)
NYX	0:85b3fd62ea1a	62	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	63	#else
NYX	0:85b3fd62ea1a	64	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	65	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	66	#endif
NYX	0:85b3fd62ea1a	67	#else
NYX	0:85b3fd62ea1a	68	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	69	#endif
NYX	0:85b3fd62ea1a	70
NYX	0:85b3fd62ea1a	71	#elif defined ( __TMS470__ )
NYX	0:85b3fd62ea1a	72	#if defined __TI_VFP_SUPPORT__
NYX	0:85b3fd62ea1a	73	#if (__FPU_PRESENT == 1)
NYX	0:85b3fd62ea1a	74	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	75	#else
NYX	0:85b3fd62ea1a	76	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	77	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	78	#endif
NYX	0:85b3fd62ea1a	79	#else
NYX	0:85b3fd62ea1a	80	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	81	#endif
NYX	0:85b3fd62ea1a	82
NYX	0:85b3fd62ea1a	83	#elif defined ( __GNUC__ )
NYX	0:85b3fd62ea1a	84	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
NYX	0:85b3fd62ea1a	85	#if (__FPU_PRESENT == 1)
NYX	0:85b3fd62ea1a	86	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	87	#else
NYX	0:85b3fd62ea1a	88	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	89	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	90	#endif
NYX	0:85b3fd62ea1a	91	#else
NYX	0:85b3fd62ea1a	92	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	93	#endif
NYX	0:85b3fd62ea1a	94
NYX	0:85b3fd62ea1a	95	#elif defined ( __TASKING__ )
NYX	0:85b3fd62ea1a	96	#if defined __FPU_VFP__
NYX	0:85b3fd62ea1a	97	#if (__FPU_PRESENT == 1)
NYX	0:85b3fd62ea1a	98	#define __FPU_USED 1U
NYX	0:85b3fd62ea1a	99	#else
NYX	0:85b3fd62ea1a	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
NYX	0:85b3fd62ea1a	101	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	102	#endif
NYX	0:85b3fd62ea1a	103	#else
NYX	0:85b3fd62ea1a	104	#define __FPU_USED 0U
NYX	0:85b3fd62ea1a	105	#endif
NYX	0:85b3fd62ea1a	106	#endif
NYX	0:85b3fd62ea1a	107
NYX	0:85b3fd62ea1a	108	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
NYX	0:85b3fd62ea1a	109
NYX	0:85b3fd62ea1a	110	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	111	}
NYX	0:85b3fd62ea1a	112	#endif
NYX	0:85b3fd62ea1a	113
NYX	0:85b3fd62ea1a	114	#endif /* __CORE_CA_H_GENERIC */
NYX	0:85b3fd62ea1a	115
NYX	0:85b3fd62ea1a	116	#ifndef __CMSIS_GENERIC
NYX	0:85b3fd62ea1a	117
NYX	0:85b3fd62ea1a	118	#ifndef __CORE_CA_H_DEPENDANT
NYX	0:85b3fd62ea1a	119	#define __CORE_CA_H_DEPENDANT
NYX	0:85b3fd62ea1a	120
NYX	0:85b3fd62ea1a	121	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	122	extern "C" {
NYX	0:85b3fd62ea1a	123	#endif
NYX	0:85b3fd62ea1a	124
NYX	0:85b3fd62ea1a	125	/* check device defines and use defaults */
NYX	0:85b3fd62ea1a	126	#if defined __CHECK_DEVICE_DEFINES
NYX	0:85b3fd62ea1a	127	#ifndef __CA_REV
NYX	0:85b3fd62ea1a	128	#define __CA_REV 0x0000U
NYX	0:85b3fd62ea1a	129	#warning "__CA_REV not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	130	#endif
NYX	0:85b3fd62ea1a	131
NYX	0:85b3fd62ea1a	132	#ifndef __FPU_PRESENT
NYX	0:85b3fd62ea1a	133	#define __FPU_PRESENT 0U
NYX	0:85b3fd62ea1a	134	#warning "__FPU_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	135	#endif
NYX	0:85b3fd62ea1a	136
NYX	0:85b3fd62ea1a	137	#ifndef __MPU_PRESENT
NYX	0:85b3fd62ea1a	138	#define __MPU_PRESENT 0U
NYX	0:85b3fd62ea1a	139	#warning "__MPU_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	140	#endif
NYX	0:85b3fd62ea1a	141
NYX	0:85b3fd62ea1a	142	#ifndef __GIC_PRESENT
NYX	0:85b3fd62ea1a	143	#define __GIC_PRESENT 1U
NYX	0:85b3fd62ea1a	144	#warning "__GIC_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	145	#endif
NYX	0:85b3fd62ea1a	146
NYX	0:85b3fd62ea1a	147	#ifndef __TIM_PRESENT
NYX	0:85b3fd62ea1a	148	#define __TIM_PRESENT 1U
NYX	0:85b3fd62ea1a	149	#warning "__TIM_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	150	#endif
NYX	0:85b3fd62ea1a	151
NYX	0:85b3fd62ea1a	152	#ifndef __L2C_PRESENT
NYX	0:85b3fd62ea1a	153	#define __L2C_PRESENT 0U
NYX	0:85b3fd62ea1a	154	#warning "__L2C_PRESENT not defined in device header file; using default!"
NYX	0:85b3fd62ea1a	155	#endif
NYX	0:85b3fd62ea1a	156	#endif
NYX	0:85b3fd62ea1a	157
NYX	0:85b3fd62ea1a	158	/* IO definitions (access restrictions to peripheral registers) */
NYX	0:85b3fd62ea1a	159	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	160	#define __I volatile /!< \brief Defines 'read only' permissions /
NYX	0:85b3fd62ea1a	161	#else
NYX	0:85b3fd62ea1a	162	#define __I volatile const /!< \brief Defines 'read only' permissions /
NYX	0:85b3fd62ea1a	163	#endif
NYX	0:85b3fd62ea1a	164	#define __O volatile /!< \brief Defines 'write only' permissions /
NYX	0:85b3fd62ea1a	165	#define __IO volatile /!< \brief Defines 'read / write' permissions /
NYX	0:85b3fd62ea1a	166
NYX	0:85b3fd62ea1a	167	/* following defines should be used for structure members */
NYX	0:85b3fd62ea1a	168	#define __IM volatile const /!< \brief Defines 'read only' structure member permissions /
NYX	0:85b3fd62ea1a	169	#define __OM volatile /!< \brief Defines 'write only' structure member permissions /
NYX	0:85b3fd62ea1a	170	#define __IOM volatile /!< \brief Defines 'read / write' structure member permissions /
NYX	0:85b3fd62ea1a	171
NYX	0:85b3fd62ea1a	172
NYX	0:85b3fd62ea1a	173	/*******************************************************************************
NYX	0:85b3fd62ea1a	174	* Register Abstraction
NYX	0:85b3fd62ea1a	175	Core Register contain:
NYX	0:85b3fd62ea1a	176	- CPSR
NYX	0:85b3fd62ea1a	177	- CP15 Registers
NYX	0:85b3fd62ea1a	178	- L2C-310 Cache Controller
NYX	0:85b3fd62ea1a	179	- Generic Interrupt Controller Distributor
NYX	0:85b3fd62ea1a	180	- Generic Interrupt Controller Interface
NYX	0:85b3fd62ea1a	181	******************************************************************************/
NYX	0:85b3fd62ea1a	182
NYX	0:85b3fd62ea1a	183	/* Core Register CPSR */
NYX	0:85b3fd62ea1a	184	typedef union
NYX	0:85b3fd62ea1a	185	{
NYX	0:85b3fd62ea1a	186	struct
NYX	0:85b3fd62ea1a	187	{
NYX	0:85b3fd62ea1a	188	uint32_t M:5; /!< \brief bit: 0.. 4 Mode field /
NYX	0:85b3fd62ea1a	189	uint32_t T:1; /!< \brief bit: 5 Thumb execution state bit /
NYX	0:85b3fd62ea1a	190	uint32_t F:1; /!< \brief bit: 6 FIQ mask bit /
NYX	0:85b3fd62ea1a	191	uint32_t I:1; /!< \brief bit: 7 IRQ mask bit /
NYX	0:85b3fd62ea1a	192	uint32_t A:1; /!< \brief bit: 8 Asynchronous abort mask bit /
NYX	0:85b3fd62ea1a	193	uint32_t E:1; /!< \brief bit: 9 Endianness execution state bit /
NYX	0:85b3fd62ea1a	194	uint32_t IT1:6; /!< \brief bit: 10..15 If-Then execution state bits 2-7 /
NYX	0:85b3fd62ea1a	195	uint32_t GE:4; /!< \brief bit: 16..19 Greater than or Equal flags /
NYX	0:85b3fd62ea1a	196	uint32_t _reserved0:4; /!< \brief bit: 20..23 Reserved /
NYX	0:85b3fd62ea1a	197	uint32_t J:1; /!< \brief bit: 24 Jazelle bit /
NYX	0:85b3fd62ea1a	198	uint32_t IT0:2; /!< \brief bit: 25..26 If-Then execution state bits 0-1 /
NYX	0:85b3fd62ea1a	199	uint32_t Q:1; /!< \brief bit: 27 Saturation condition flag /
NYX	0:85b3fd62ea1a	200	uint32_t V:1; /!< \brief bit: 28 Overflow condition code flag /
NYX	0:85b3fd62ea1a	201	uint32_t C:1; /!< \brief bit: 29 Carry condition code flag /
NYX	0:85b3fd62ea1a	202	uint32_t Z:1; /!< \brief bit: 30 Zero condition code flag /
NYX	0:85b3fd62ea1a	203	uint32_t N:1; /!< \brief bit: 31 Negative condition code flag /
NYX	0:85b3fd62ea1a	204	} b; /!< \brief Structure used for bit access /
NYX	0:85b3fd62ea1a	205	uint32_t w; /!< \brief Type used for word access /
NYX	0:85b3fd62ea1a	206	} CPSR_Type;
NYX	0:85b3fd62ea1a	207
NYX	0:85b3fd62ea1a	208	/* CPSR Register Definitions */
NYX	0:85b3fd62ea1a	209	#define CPSR_N_Pos 31U /!< \brief CPSR: N Position /
NYX	0:85b3fd62ea1a	210	#define CPSR_N_Msk (1UL << CPSR_N_Pos) /!< \brief CPSR: N Mask /
NYX	0:85b3fd62ea1a	211
NYX	0:85b3fd62ea1a	212	#define CPSR_Z_Pos 30U /!< \brief CPSR: Z Position /
NYX	0:85b3fd62ea1a	213	#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /!< \brief CPSR: Z Mask /
NYX	0:85b3fd62ea1a	214
NYX	0:85b3fd62ea1a	215	#define CPSR_C_Pos 29U /!< \brief CPSR: C Position /
NYX	0:85b3fd62ea1a	216	#define CPSR_C_Msk (1UL << CPSR_C_Pos) /!< \brief CPSR: C Mask /
NYX	0:85b3fd62ea1a	217
NYX	0:85b3fd62ea1a	218	#define CPSR_V_Pos 28U /!< \brief CPSR: V Position /
NYX	0:85b3fd62ea1a	219	#define CPSR_V_Msk (1UL << CPSR_V_Pos) /!< \brief CPSR: V Mask /
NYX	0:85b3fd62ea1a	220
NYX	0:85b3fd62ea1a	221	#define CPSR_Q_Pos 27U /!< \brief CPSR: Q Position /
NYX	0:85b3fd62ea1a	222	#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /!< \brief CPSR: Q Mask /
NYX	0:85b3fd62ea1a	223
NYX	0:85b3fd62ea1a	224	#define CPSR_IT0_Pos 25U /!< \brief CPSR: IT0 Position /
NYX	0:85b3fd62ea1a	225	#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /!< \brief CPSR: IT0 Mask /
NYX	0:85b3fd62ea1a	226
NYX	0:85b3fd62ea1a	227	#define CPSR_J_Pos 24U /!< \brief CPSR: J Position /
NYX	0:85b3fd62ea1a	228	#define CPSR_J_Msk (1UL << CPSR_J_Pos) /!< \brief CPSR: J Mask /
NYX	0:85b3fd62ea1a	229
NYX	0:85b3fd62ea1a	230	#define CPSR_GE_Pos 16U /!< \brief CPSR: GE Position /
NYX	0:85b3fd62ea1a	231	#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /!< \brief CPSR: GE Mask /
NYX	0:85b3fd62ea1a	232
NYX	0:85b3fd62ea1a	233	#define CPSR_IT1_Pos 10U /!< \brief CPSR: IT1 Position /
NYX	0:85b3fd62ea1a	234	#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /!< \brief CPSR: IT1 Mask /
NYX	0:85b3fd62ea1a	235
NYX	0:85b3fd62ea1a	236	#define CPSR_E_Pos 9U /!< \brief CPSR: E Position /
NYX	0:85b3fd62ea1a	237	#define CPSR_E_Msk (1UL << CPSR_E_Pos) /!< \brief CPSR: E Mask /
NYX	0:85b3fd62ea1a	238
NYX	0:85b3fd62ea1a	239	#define CPSR_A_Pos 8U /!< \brief CPSR: A Position /
NYX	0:85b3fd62ea1a	240	#define CPSR_A_Msk (1UL << CPSR_A_Pos) /!< \brief CPSR: A Mask /
NYX	0:85b3fd62ea1a	241
NYX	0:85b3fd62ea1a	242	#define CPSR_I_Pos 7U /!< \brief CPSR: I Position /
NYX	0:85b3fd62ea1a	243	#define CPSR_I_Msk (1UL << CPSR_I_Pos) /!< \brief CPSR: I Mask /
NYX	0:85b3fd62ea1a	244
NYX	0:85b3fd62ea1a	245	#define CPSR_F_Pos 6U /!< \brief CPSR: F Position /
NYX	0:85b3fd62ea1a	246	#define CPSR_F_Msk (1UL << CPSR_F_Pos) /!< \brief CPSR: F Mask /
NYX	0:85b3fd62ea1a	247
NYX	0:85b3fd62ea1a	248	#define CPSR_T_Pos 5U /!< \brief CPSR: T Position /
NYX	0:85b3fd62ea1a	249	#define CPSR_T_Msk (1UL << CPSR_T_Pos) /!< \brief CPSR: T Mask /
NYX	0:85b3fd62ea1a	250
NYX	0:85b3fd62ea1a	251	#define CPSR_M_Pos 0U /!< \brief CPSR: M Position /
NYX	0:85b3fd62ea1a	252	#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /!< \brief CPSR: M Mask /
NYX	0:85b3fd62ea1a	253
NYX	0:85b3fd62ea1a	254	/* CP15 Register SCTLR */
NYX	0:85b3fd62ea1a	255	typedef union
NYX	0:85b3fd62ea1a	256	{
NYX	0:85b3fd62ea1a	257	struct
NYX	0:85b3fd62ea1a	258	{
NYX	0:85b3fd62ea1a	259	uint32_t M:1; /!< \brief bit: 0 MMU enable /
NYX	0:85b3fd62ea1a	260	uint32_t A:1; /!< \brief bit: 1 Alignment check enable /
NYX	0:85b3fd62ea1a	261	uint32_t C:1; /!< \brief bit: 2 Cache enable /
NYX	0:85b3fd62ea1a	262	uint32_t _reserved0:2; /!< \brief bit: 3.. 4 Reserved /
NYX	0:85b3fd62ea1a	263	uint32_t CP15BEN:1; /!< \brief bit: 5 CP15 barrier enable /
NYX	0:85b3fd62ea1a	264	uint32_t _reserved1:1; /!< \brief bit: 6 Reserved /
NYX	0:85b3fd62ea1a	265	uint32_t B:1; /!< \brief bit: 7 Endianness model /
NYX	0:85b3fd62ea1a	266	uint32_t _reserved2:2; /!< \brief bit: 8.. 9 Reserved /
NYX	0:85b3fd62ea1a	267	uint32_t SW:1; /!< \brief bit: 10 SWP and SWPB enable /
NYX	0:85b3fd62ea1a	268	uint32_t Z:1; /!< \brief bit: 11 Branch prediction enable /
NYX	0:85b3fd62ea1a	269	uint32_t I:1; /!< \brief bit: 12 Instruction cache enable /
NYX	0:85b3fd62ea1a	270	uint32_t V:1; /!< \brief bit: 13 Vectors bit /
NYX	0:85b3fd62ea1a	271	uint32_t RR:1; /!< \brief bit: 14 Round Robin select /
NYX	0:85b3fd62ea1a	272	uint32_t _reserved3:2; /!< \brief bit:15..16 Reserved /
NYX	0:85b3fd62ea1a	273	uint32_t HA:1; /!< \brief bit: 17 Hardware Access flag enable /
NYX	0:85b3fd62ea1a	274	uint32_t _reserved4:1; /!< \brief bit: 18 Reserved /
NYX	0:85b3fd62ea1a	275	uint32_t WXN:1; /!< \brief bit: 19 Write permission implies XN /
NYX	0:85b3fd62ea1a	276	uint32_t UWXN:1; /!< \brief bit: 20 Unprivileged write permission implies PL1 XN /
NYX	0:85b3fd62ea1a	277	uint32_t FI:1; /!< \brief bit: 21 Fast interrupts configuration enable /
NYX	0:85b3fd62ea1a	278	uint32_t U:1; /!< \brief bit: 22 Alignment model /
NYX	0:85b3fd62ea1a	279	uint32_t _reserved5:1; /!< \brief bit: 23 Reserved /
NYX	0:85b3fd62ea1a	280	uint32_t VE:1; /!< \brief bit: 24 Interrupt Vectors Enable /
NYX	0:85b3fd62ea1a	281	uint32_t EE:1; /!< \brief bit: 25 Exception Endianness /
NYX	0:85b3fd62ea1a	282	uint32_t _reserved6:1; /!< \brief bit: 26 Reserved /
NYX	0:85b3fd62ea1a	283	uint32_t NMFI:1; /!< \brief bit: 27 Non-maskable FIQ (NMFI) support /
NYX	0:85b3fd62ea1a	284	uint32_t TRE:1; /!< \brief bit: 28 TEX remap enable. /
NYX	0:85b3fd62ea1a	285	uint32_t AFE:1; /!< \brief bit: 29 Access flag enable /
NYX	0:85b3fd62ea1a	286	uint32_t TE:1; /!< \brief bit: 30 Thumb Exception enable /
NYX	0:85b3fd62ea1a	287	uint32_t _reserved7:1; /!< \brief bit: 31 Reserved /
NYX	0:85b3fd62ea1a	288	} b; /!< \brief Structure used for bit access /
NYX	0:85b3fd62ea1a	289	uint32_t w; /!< \brief Type used for word access /
NYX	0:85b3fd62ea1a	290	} SCTLR_Type;
NYX	0:85b3fd62ea1a	291
NYX	0:85b3fd62ea1a	292	#define SCTLR_TE_Pos 30U /!< \brief SCTLR: TE Position /
NYX	0:85b3fd62ea1a	293	#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /!< \brief SCTLR: TE Mask /
NYX	0:85b3fd62ea1a	294
NYX	0:85b3fd62ea1a	295	#define SCTLR_AFE_Pos 29U /!< \brief SCTLR: AFE Position /
NYX	0:85b3fd62ea1a	296	#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /!< \brief SCTLR: AFE Mask /
NYX	0:85b3fd62ea1a	297
NYX	0:85b3fd62ea1a	298	#define SCTLR_TRE_Pos 28U /!< \brief SCTLR: TRE Position /
NYX	0:85b3fd62ea1a	299	#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /!< \brief SCTLR: TRE Mask /
NYX	0:85b3fd62ea1a	300
NYX	0:85b3fd62ea1a	301	#define SCTLR_NMFI_Pos 27U /!< \brief SCTLR: NMFI Position /
NYX	0:85b3fd62ea1a	302	#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /!< \brief SCTLR: NMFI Mask /
NYX	0:85b3fd62ea1a	303
NYX	0:85b3fd62ea1a	304	#define SCTLR_EE_Pos 25U /!< \brief SCTLR: EE Position /
NYX	0:85b3fd62ea1a	305	#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /!< \brief SCTLR: EE Mask /
NYX	0:85b3fd62ea1a	306
NYX	0:85b3fd62ea1a	307	#define SCTLR_VE_Pos 24U /!< \brief SCTLR: VE Position /
NYX	0:85b3fd62ea1a	308	#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /!< \brief SCTLR: VE Mask /
NYX	0:85b3fd62ea1a	309
NYX	0:85b3fd62ea1a	310	#define SCTLR_U_Pos 22U /!< \brief SCTLR: U Position /
NYX	0:85b3fd62ea1a	311	#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /!< \brief SCTLR: U Mask /
NYX	0:85b3fd62ea1a	312
NYX	0:85b3fd62ea1a	313	#define SCTLR_FI_Pos 21U /!< \brief SCTLR: FI Position /
NYX	0:85b3fd62ea1a	314	#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /!< \brief SCTLR: FI Mask /
NYX	0:85b3fd62ea1a	315
NYX	0:85b3fd62ea1a	316	#define SCTLR_UWXN_Pos 20U /!< \brief SCTLR: UWXN Position /
NYX	0:85b3fd62ea1a	317	#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /!< \brief SCTLR: UWXN Mask /
NYX	0:85b3fd62ea1a	318
NYX	0:85b3fd62ea1a	319	#define SCTLR_WXN_Pos 19U /!< \brief SCTLR: WXN Position /
NYX	0:85b3fd62ea1a	320	#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /!< \brief SCTLR: WXN Mask /
NYX	0:85b3fd62ea1a	321
NYX	0:85b3fd62ea1a	322	#define SCTLR_HA_Pos 17U /!< \brief SCTLR: HA Position /
NYX	0:85b3fd62ea1a	323	#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /!< \brief SCTLR: HA Mask /
NYX	0:85b3fd62ea1a	324
NYX	0:85b3fd62ea1a	325	#define SCTLR_RR_Pos 14U /!< \brief SCTLR: RR Position /
NYX	0:85b3fd62ea1a	326	#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /!< \brief SCTLR: RR Mask /
NYX	0:85b3fd62ea1a	327
NYX	0:85b3fd62ea1a	328	#define SCTLR_V_Pos 13U /!< \brief SCTLR: V Position /
NYX	0:85b3fd62ea1a	329	#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /!< \brief SCTLR: V Mask /
NYX	0:85b3fd62ea1a	330
NYX	0:85b3fd62ea1a	331	#define SCTLR_I_Pos 12U /!< \brief SCTLR: I Position /
NYX	0:85b3fd62ea1a	332	#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /!< \brief SCTLR: I Mask /
NYX	0:85b3fd62ea1a	333
NYX	0:85b3fd62ea1a	334	#define SCTLR_Z_Pos 11U /!< \brief SCTLR: Z Position /
NYX	0:85b3fd62ea1a	335	#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /!< \brief SCTLR: Z Mask /
NYX	0:85b3fd62ea1a	336
NYX	0:85b3fd62ea1a	337	#define SCTLR_SW_Pos 10U /!< \brief SCTLR: SW Position /
NYX	0:85b3fd62ea1a	338	#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /!< \brief SCTLR: SW Mask /
NYX	0:85b3fd62ea1a	339
NYX	0:85b3fd62ea1a	340	#define SCTLR_B_Pos 7U /!< \brief SCTLR: B Position /
NYX	0:85b3fd62ea1a	341	#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /!< \brief SCTLR: B Mask /
NYX	0:85b3fd62ea1a	342
NYX	0:85b3fd62ea1a	343	#define SCTLR_CP15BEN_Pos 5U /!< \brief SCTLR: CP15BEN Position /
NYX	0:85b3fd62ea1a	344	#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /!< \brief SCTLR: CP15BEN Mask /
NYX	0:85b3fd62ea1a	345
NYX	0:85b3fd62ea1a	346	#define SCTLR_C_Pos 2U /!< \brief SCTLR: C Position /
NYX	0:85b3fd62ea1a	347	#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /!< \brief SCTLR: C Mask /
NYX	0:85b3fd62ea1a	348
NYX	0:85b3fd62ea1a	349	#define SCTLR_A_Pos 1U /!< \brief SCTLR: A Position /
NYX	0:85b3fd62ea1a	350	#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /!< \brief SCTLR: A Mask /
NYX	0:85b3fd62ea1a	351
NYX	0:85b3fd62ea1a	352	#define SCTLR_M_Pos 0U /!< \brief SCTLR: M Position /
NYX	0:85b3fd62ea1a	353	#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /!< \brief SCTLR: M Mask /
NYX	0:85b3fd62ea1a	354
NYX	0:85b3fd62ea1a	355	/* CP15 Register CPACR */
NYX	0:85b3fd62ea1a	356	typedef union
NYX	0:85b3fd62ea1a	357	{
NYX	0:85b3fd62ea1a	358	struct
NYX	0:85b3fd62ea1a	359	{
NYX	0:85b3fd62ea1a	360	uint32_t _reserved0:20; /!< \brief bit: 0..19 Reserved /
NYX	0:85b3fd62ea1a	361	uint32_t cp10:2; /!< \brief bit:20..21 Access rights for coprocessor 10 /
NYX	0:85b3fd62ea1a	362	uint32_t cp11:2; /!< \brief bit:22..23 Access rights for coprocessor 11 /
NYX	0:85b3fd62ea1a	363	uint32_t _reserved1:6; /!< \brief bit:24..29 Reserved /
NYX	0:85b3fd62ea1a	364	uint32_t D32DIS:1; /!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file /
NYX	0:85b3fd62ea1a	365	uint32_t ASEDIS:1; /!< \brief bit: 31 Disable Advanced SIMD Functionality /
NYX	0:85b3fd62ea1a	366	} b; /!< \brief Structure used for bit access /
NYX	0:85b3fd62ea1a	367	uint32_t w; /!< \brief Type used for word access /
NYX	0:85b3fd62ea1a	368	} CPACR_Type;
NYX	0:85b3fd62ea1a	369
NYX	0:85b3fd62ea1a	370	#define CPACR_ASEDIS_Pos 31U /!< \brief CPACR: ASEDIS Position /
NYX	0:85b3fd62ea1a	371	#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /!< \brief CPACR: ASEDIS Mask /
NYX	0:85b3fd62ea1a	372
NYX	0:85b3fd62ea1a	373	#define CPACR_D32DIS_Pos 30U /!< \brief CPACR: D32DIS Position /
NYX	0:85b3fd62ea1a	374	#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /!< \brief CPACR: D32DIS Mask /
NYX	0:85b3fd62ea1a	375
NYX	0:85b3fd62ea1a	376	#define CPACR_cp11_Pos 22U /!< \brief CPACR: cp11 Position /
NYX	0:85b3fd62ea1a	377	#define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /!< \brief CPACR: cp11 Mask /
NYX	0:85b3fd62ea1a	378
NYX	0:85b3fd62ea1a	379	#define CPACR_cp10_Pos 20U /!< \brief CPACR: cp10 Position /
NYX	0:85b3fd62ea1a	380	#define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /!< \brief CPACR: cp10 Mask /
NYX	0:85b3fd62ea1a	381
NYX	0:85b3fd62ea1a	382	/* CP15 Register DFSR */
NYX	0:85b3fd62ea1a	383	typedef union
NYX	0:85b3fd62ea1a	384	{
NYX	0:85b3fd62ea1a	385	struct
NYX	0:85b3fd62ea1a	386	{
NYX	0:85b3fd62ea1a	387	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
NYX	0:85b3fd62ea1a	388	uint32_t Domain:4; /!< \brief bit: 4.. 7 Fault on which domain /
NYX	0:85b3fd62ea1a	389	uint32_t _reserved0:2; /!< \brief bit: 8.. 9 Reserved /
NYX	0:85b3fd62ea1a	390	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
NYX	0:85b3fd62ea1a	391	uint32_t WnR:1; /!< \brief bit: 11 Write not Read bit /
NYX	0:85b3fd62ea1a	392	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
NYX	0:85b3fd62ea1a	393	uint32_t CM:1; /!< \brief bit: 13 Cache maintenance fault /
NYX	0:85b3fd62ea1a	394	uint32_t _reserved1:18; /!< \brief bit:14..31 Reserved /
NYX	0:85b3fd62ea1a	395	} b; /!< \brief Structure used for bit access /
NYX	0:85b3fd62ea1a	396	uint32_t w; /!< \brief Type used for word access /
NYX	0:85b3fd62ea1a	397	} DFSR_Type;
NYX	0:85b3fd62ea1a	398
NYX	0:85b3fd62ea1a	399	#define DFSR_CM_Pos 13U /!< \brief DFSR: CM Position /
NYX	0:85b3fd62ea1a	400	#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /!< \brief DFSR: CM Mask /
NYX	0:85b3fd62ea1a	401
NYX	0:85b3fd62ea1a	402	#define DFSR_Ext_Pos 12U /!< \brief DFSR: Ext Position /
NYX	0:85b3fd62ea1a	403	#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /!< \brief DFSR: Ext Mask /
NYX	0:85b3fd62ea1a	404
NYX	0:85b3fd62ea1a	405	#define DFSR_WnR_Pos 11U /!< \brief DFSR: WnR Position /
NYX	0:85b3fd62ea1a	406	#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /!< \brief DFSR: WnR Mask /
NYX	0:85b3fd62ea1a	407
NYX	0:85b3fd62ea1a	408	#define DFSR_FS1_Pos 10U /!< \brief DFSR: FS1 Position /
NYX	0:85b3fd62ea1a	409	#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /!< \brief DFSR: FS1 Mask /
NYX	0:85b3fd62ea1a	410
NYX	0:85b3fd62ea1a	411	#define DFSR_Domain_Pos 4U /!< \brief DFSR: Domain Position /
NYX	0:85b3fd62ea1a	412	#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /!< \brief DFSR: Domain Mask /
NYX	0:85b3fd62ea1a	413
NYX	0:85b3fd62ea1a	414	#define DFSR_FS0_Pos 0U /!< \brief DFSR: FS0 Position /
NYX	0:85b3fd62ea1a	415	#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /!< \brief DFSR: FS0 Mask /
NYX	0:85b3fd62ea1a	416
NYX	0:85b3fd62ea1a	417	/* CP15 Register IFSR */
NYX	0:85b3fd62ea1a	418	typedef union
NYX	0:85b3fd62ea1a	419	{
NYX	0:85b3fd62ea1a	420	struct
NYX	0:85b3fd62ea1a	421	{
NYX	0:85b3fd62ea1a	422	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
NYX	0:85b3fd62ea1a	423	uint32_t _reserved0:6; /!< \brief bit: 4.. 9 Reserved /
NYX	0:85b3fd62ea1a	424	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
NYX	0:85b3fd62ea1a	425	uint32_t _reserved1:1; /!< \brief bit: 11 Reserved /
NYX	0:85b3fd62ea1a	426	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
NYX	0:85b3fd62ea1a	427	uint32_t _reserved2:19; /!< \brief bit:13..31 Reserved /
NYX	0:85b3fd62ea1a	428	} b; /!< \brief Structure used for bit access /
NYX	0:85b3fd62ea1a	429	uint32_t w; /!< \brief Type used for word access /
NYX	0:85b3fd62ea1a	430	} IFSR_Type;
NYX	0:85b3fd62ea1a	431
NYX	0:85b3fd62ea1a	432	#define IFSR_ExT_Pos 12U /!< \brief IFSR: ExT Position /
NYX	0:85b3fd62ea1a	433	#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /!< \brief IFSR: ExT Mask /
NYX	0:85b3fd62ea1a	434
NYX	0:85b3fd62ea1a	435	#define IFSR_FS1_Pos 10U /!< \brief IFSR: FS1 Position /
NYX	0:85b3fd62ea1a	436	#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /!< \brief IFSR: FS1 Mask /
NYX	0:85b3fd62ea1a	437
NYX	0:85b3fd62ea1a	438	#define IFSR_FS0_Pos 0U /!< \brief IFSR: FS0 Position /
NYX	0:85b3fd62ea1a	439	#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /!< \brief IFSR: FS0 Mask /
NYX	0:85b3fd62ea1a	440
NYX	0:85b3fd62ea1a	441	/* CP15 Register ISR */
NYX	0:85b3fd62ea1a	442	typedef union
NYX	0:85b3fd62ea1a	443	{
NYX	0:85b3fd62ea1a	444	struct
NYX	0:85b3fd62ea1a	445	{
NYX	0:85b3fd62ea1a	446	uint32_t _reserved0:6; /!< \brief bit: 0.. 5 Reserved /
NYX	0:85b3fd62ea1a	447	uint32_t F:1; /!< \brief bit: 6 FIQ pending bit /
NYX	0:85b3fd62ea1a	448	uint32_t I:1; /!< \brief bit: 7 IRQ pending bit /
NYX	0:85b3fd62ea1a	449	uint32_t A:1; /!< \brief bit: 8 External abort pending bit /
NYX	0:85b3fd62ea1a	450	uint32_t _reserved1:23; /!< \brief bit:14..31 Reserved /
NYX	0:85b3fd62ea1a	451	} b; /!< \brief Structure used for bit access /
NYX	0:85b3fd62ea1a	452	uint32_t w; /!< \brief Type used for word access /
NYX	0:85b3fd62ea1a	453	} ISR_Type;
NYX	0:85b3fd62ea1a	454
NYX	0:85b3fd62ea1a	455	#define ISR_A_Pos 13U /!< \brief ISR: A Position /
NYX	0:85b3fd62ea1a	456	#define ISR_A_Msk (1UL << ISR_A_Pos) /!< \brief ISR: A Mask /
NYX	0:85b3fd62ea1a	457
NYX	0:85b3fd62ea1a	458	#define ISR_I_Pos 12U /!< \brief ISR: I Position /
NYX	0:85b3fd62ea1a	459	#define ISR_I_Msk (1UL << ISR_I_Pos) /!< \brief ISR: I Mask /
NYX	0:85b3fd62ea1a	460
NYX	0:85b3fd62ea1a	461	#define ISR_F_Pos 11U /!< \brief ISR: F Position /
NYX	0:85b3fd62ea1a	462	#define ISR_F_Msk (1UL << ISR_F_Pos) /!< \brief ISR: F Mask /
NYX	0:85b3fd62ea1a	463
NYX	0:85b3fd62ea1a	464
NYX	0:85b3fd62ea1a	465	/**
NYX	0:85b3fd62ea1a	466	\brief Union type to access the L2C_310 Cache Controller.
NYX	0:85b3fd62ea1a	467	*/
NYX	0:85b3fd62ea1a	468	#if (__L2C_PRESENT == 1U)
NYX	0:85b3fd62ea1a	469	typedef struct
NYX	0:85b3fd62ea1a	470	{
NYX	0:85b3fd62ea1a	471	__I uint32_t CACHE_ID; /!< \brief Offset: 0x0000 Cache ID Register /
NYX	0:85b3fd62ea1a	472	__I uint32_t CACHE_TYPE; /!< \brief Offset: 0x0004 Cache Type Register /
NYX	0:85b3fd62ea1a	473	uint32_t RESERVED0[0x3e];
NYX	0:85b3fd62ea1a	474	__IO uint32_t CONTROL; /!< \brief Offset: 0x0100 Control Register /
NYX	0:85b3fd62ea1a	475	__IO uint32_t AUX_CNT; /!< \brief Offset: 0x0104 Auxiliary Control /
NYX	0:85b3fd62ea1a	476	uint32_t RESERVED1[0x3e];
NYX	0:85b3fd62ea1a	477	__IO uint32_t EVENT_CONTROL; /!< \brief Offset: 0x0200 Event Counter Control /
NYX	0:85b3fd62ea1a	478	__IO uint32_t EVENT_COUNTER1_CONF; /!< \brief Offset: 0x0204 Event Counter 1 Configuration /
NYX	0:85b3fd62ea1a	479	__IO uint32_t EVENT_COUNTER0_CONF; /!< \brief Offset: 0x0208 Event Counter 1 Configuration /
NYX	0:85b3fd62ea1a	480	uint32_t RESERVED2[0x2];
NYX	0:85b3fd62ea1a	481	__IO uint32_t INTERRUPT_MASK; /!< \brief Offset: 0x0214 Interrupt Mask /
NYX	0:85b3fd62ea1a	482	__I uint32_t MASKED_INT_STATUS; /!< \brief Offset: 0x0218 Masked Interrupt Status /
NYX	0:85b3fd62ea1a	483	__I uint32_t RAW_INT_STATUS; /!< \brief Offset: 0x021c Raw Interrupt Status /
NYX	0:85b3fd62ea1a	484	__O uint32_t INTERRUPT_CLEAR; /!< \brief Offset: 0x0220 Interrupt Clear /
NYX	0:85b3fd62ea1a	485	uint32_t RESERVED3[0x143];
NYX	0:85b3fd62ea1a	486	__IO uint32_t CACHE_SYNC; /!< \brief Offset: 0x0730 Cache Sync /
NYX	0:85b3fd62ea1a	487	uint32_t RESERVED4[0xf];
NYX	0:85b3fd62ea1a	488	__IO uint32_t INV_LINE_PA; /!< \brief Offset: 0x0770 Invalidate Line By PA /
NYX	0:85b3fd62ea1a	489	uint32_t RESERVED6[2];
NYX	0:85b3fd62ea1a	490	__IO uint32_t INV_WAY; /!< \brief Offset: 0x077c Invalidate by Way /
NYX	0:85b3fd62ea1a	491	uint32_t RESERVED5[0xc];
NYX	0:85b3fd62ea1a	492	__IO uint32_t CLEAN_LINE_PA; /!< \brief Offset: 0x07b0 Clean Line by PA /
NYX	0:85b3fd62ea1a	493	uint32_t RESERVED7[1];
NYX	0:85b3fd62ea1a	494	__IO uint32_t CLEAN_LINE_INDEX_WAY; /!< \brief Offset: 0x07b8 Clean Line by Index/Way /
NYX	0:85b3fd62ea1a	495	__IO uint32_t CLEAN_WAY; /!< \brief Offset: 0x07bc Clean by Way /
NYX	0:85b3fd62ea1a	496	uint32_t RESERVED8[0xc];
NYX	0:85b3fd62ea1a	497	__IO uint32_t CLEAN_INV_LINE_PA; /!< \brief Offset: 0x07f0 Clean and Invalidate Line by PA /
NYX	0:85b3fd62ea1a	498	uint32_t RESERVED9[1];
NYX	0:85b3fd62ea1a	499	__IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /!< \brief Offset: 0x07f8 Clean and Invalidate Line by Index/Way /
NYX	0:85b3fd62ea1a	500	__IO uint32_t CLEAN_INV_WAY; /!< \brief Offset: 0x07fc Clean and Invalidate by Way /
NYX	0:85b3fd62ea1a	501	uint32_t RESERVED10[0x40];
NYX	0:85b3fd62ea1a	502	__IO uint32_t DATA_LOCK_0_WAY; /!< \brief Offset: 0x0900 Data Lockdown 0 by Way /
NYX	0:85b3fd62ea1a	503	__IO uint32_t INST_LOCK_0_WAY; /!< \brief Offset: 0x0904 Instruction Lockdown 0 by Way /
NYX	0:85b3fd62ea1a	504	__IO uint32_t DATA_LOCK_1_WAY; /!< \brief Offset: 0x0908 Data Lockdown 1 by Way /
NYX	0:85b3fd62ea1a	505	__IO uint32_t INST_LOCK_1_WAY; /!< \brief Offset: 0x090c Instruction Lockdown 1 by Way /
NYX	0:85b3fd62ea1a	506	__IO uint32_t DATA_LOCK_2_WAY; /!< \brief Offset: 0x0910 Data Lockdown 2 by Way /
NYX	0:85b3fd62ea1a	507	__IO uint32_t INST_LOCK_2_WAY; /!< \brief Offset: 0x0914 Instruction Lockdown 2 by Way /
NYX	0:85b3fd62ea1a	508	__IO uint32_t DATA_LOCK_3_WAY; /!< \brief Offset: 0x0918 Data Lockdown 3 by Way /
NYX	0:85b3fd62ea1a	509	__IO uint32_t INST_LOCK_3_WAY; /!< \brief Offset: 0x091c Instruction Lockdown 3 by Way /
NYX	0:85b3fd62ea1a	510	__IO uint32_t DATA_LOCK_4_WAY; /!< \brief Offset: 0x0920 Data Lockdown 4 by Way /
NYX	0:85b3fd62ea1a	511	__IO uint32_t INST_LOCK_4_WAY; /!< \brief Offset: 0x0924 Instruction Lockdown 4 by Way /
NYX	0:85b3fd62ea1a	512	__IO uint32_t DATA_LOCK_5_WAY; /!< \brief Offset: 0x0928 Data Lockdown 5 by Way /
NYX	0:85b3fd62ea1a	513	__IO uint32_t INST_LOCK_5_WAY; /!< \brief Offset: 0x092c Instruction Lockdown 5 by Way /
NYX	0:85b3fd62ea1a	514	__IO uint32_t DATA_LOCK_6_WAY; /!< \brief Offset: 0x0930 Data Lockdown 5 by Way /
NYX	0:85b3fd62ea1a	515	__IO uint32_t INST_LOCK_6_WAY; /!< \brief Offset: 0x0934 Instruction Lockdown 5 by Way /
NYX	0:85b3fd62ea1a	516	__IO uint32_t DATA_LOCK_7_WAY; /!< \brief Offset: 0x0938 Data Lockdown 6 by Way /
NYX	0:85b3fd62ea1a	517	__IO uint32_t INST_LOCK_7_WAY; /!< \brief Offset: 0x093c Instruction Lockdown 6 by Way /
NYX	0:85b3fd62ea1a	518	uint32_t RESERVED11[0x4];
NYX	0:85b3fd62ea1a	519	__IO uint32_t LOCK_LINE_EN; /!< \brief Offset: 0x0950 Lockdown by Line Enable /
NYX	0:85b3fd62ea1a	520	__IO uint32_t UNLOCK_ALL_BY_WAY; /!< \brief Offset: 0x0954 Unlock All Lines by Way /
NYX	0:85b3fd62ea1a	521	uint32_t RESERVED12[0xaa];
NYX	0:85b3fd62ea1a	522	__IO uint32_t ADDRESS_FILTER_START; /!< \brief Offset: 0x0c00 Address Filtering Start /
NYX	0:85b3fd62ea1a	523	__IO uint32_t ADDRESS_FILTER_END; /!< \brief Offset: 0x0c04 Address Filtering End /
NYX	0:85b3fd62ea1a	524	uint32_t RESERVED13[0xce];
NYX	0:85b3fd62ea1a	525	__IO uint32_t DEBUG_CONTROL; /!< \brief Offset: 0x0f40 Debug Control Register /
NYX	0:85b3fd62ea1a	526	} L2C_310_TypeDef;
NYX	0:85b3fd62ea1a	527
NYX	0:85b3fd62ea1a	528	#define L2C_310 ((L2C_310_TypeDef )L2C_310_BASE) /!< \brief L2C_310 Declaration */
NYX	0:85b3fd62ea1a	529	#endif
NYX	0:85b3fd62ea1a	530
NYX	0:85b3fd62ea1a	531	#if (__GIC_PRESENT == 1U)
NYX	0:85b3fd62ea1a	532	/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
NYX	0:85b3fd62ea1a	533	*/
NYX	0:85b3fd62ea1a	534	typedef struct
NYX	0:85b3fd62ea1a	535	{
NYX	0:85b3fd62ea1a	536	__IO uint32_t ICDDCR;
NYX	0:85b3fd62ea1a	537	__I uint32_t ICDICTR;
NYX	0:85b3fd62ea1a	538	__I uint32_t ICDIIDR;
NYX	0:85b3fd62ea1a	539	uint32_t RESERVED0[29];
NYX	0:85b3fd62ea1a	540	__IO uint32_t ICDISR[32];
NYX	0:85b3fd62ea1a	541	__IO uint32_t ICDISER[32];
NYX	0:85b3fd62ea1a	542	__IO uint32_t ICDICER[32];
NYX	0:85b3fd62ea1a	543	__IO uint32_t ICDISPR[32];
NYX	0:85b3fd62ea1a	544	__IO uint32_t ICDICPR[32];
NYX	0:85b3fd62ea1a	545	__I uint32_t ICDABR[32];
NYX	0:85b3fd62ea1a	546	uint32_t RESERVED1[32];
NYX	0:85b3fd62ea1a	547	__IO uint32_t ICDIPR[256];
NYX	0:85b3fd62ea1a	548	__IO uint32_t ICDIPTR[256];
NYX	0:85b3fd62ea1a	549	__IO uint32_t ICDICFR[64];
NYX	0:85b3fd62ea1a	550	uint32_t RESERVED2[128];
NYX	0:85b3fd62ea1a	551	__IO uint32_t ICDSGIR;
NYX	0:85b3fd62ea1a	552	} GICDistributor_Type;
NYX	0:85b3fd62ea1a	553
NYX	0:85b3fd62ea1a	554	#define GICDistributor ((GICDistributor_Type ) GIC_DISTRIBUTOR_BASE ) /!< GIC Distributor configuration struct */
NYX	0:85b3fd62ea1a	555
NYX	0:85b3fd62ea1a	556	/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
NYX	0:85b3fd62ea1a	557	*/
NYX	0:85b3fd62ea1a	558	typedef struct
NYX	0:85b3fd62ea1a	559	{
NYX	0:85b3fd62ea1a	560	__IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register
NYX	0:85b3fd62ea1a	561	__IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register
NYX	0:85b3fd62ea1a	562	__IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register
NYX	0:85b3fd62ea1a	563	__I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register
NYX	0:85b3fd62ea1a	564	__IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register
NYX	0:85b3fd62ea1a	565	__I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register
NYX	0:85b3fd62ea1a	566	__I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register
NYX	0:85b3fd62ea1a	567	__IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register
NYX	0:85b3fd62ea1a	568	uint32_t RESERVED[55];
NYX	0:85b3fd62ea1a	569	__I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register
NYX	0:85b3fd62ea1a	570	} GICInterface_Type;
NYX	0:85b3fd62ea1a	571
NYX	0:85b3fd62ea1a	572	#define GICInterface ((GICInterface_Type ) GIC_INTERFACE_BASE ) /!< GIC Interface configuration struct */
NYX	0:85b3fd62ea1a	573	#endif
NYX	0:85b3fd62ea1a	574
NYX	0:85b3fd62ea1a	575	#if (__TIM_PRESENT == 1U)
NYX	0:85b3fd62ea1a	576	#if ((__CORTEX_A == 5U)\|\|(__CORTEX_A == 9U))
NYX	0:85b3fd62ea1a	577	/** \brief Structure type to access the Private Timer
NYX	0:85b3fd62ea1a	578	*/
NYX	0:85b3fd62ea1a	579	typedef struct
NYX	0:85b3fd62ea1a	580	{
NYX	0:85b3fd62ea1a	581	__IO uint32_t LOAD; //!< \brief +0x000 - RW - Private Timer Load Register
NYX	0:85b3fd62ea1a	582	__IO uint32_t COUNTER; //!< \brief +0x004 - RW - Private Timer Counter Register
NYX	0:85b3fd62ea1a	583	__IO uint32_t CONTROL; //!< \brief +0x008 - RW - Private Timer Control Register
NYX	0:85b3fd62ea1a	584	__IO uint32_t ISR; //!< \brief +0x00C - RO - Private Timer Interrupt Status Register
NYX	0:85b3fd62ea1a	585	uint32_t RESERVED[8];
NYX	0:85b3fd62ea1a	586	__IO uint32_t WLOAD; //!< \brief +0x020 - RW - Watchdog Load Register
NYX	0:85b3fd62ea1a	587	__IO uint32_t WCOUNTER; //!< \brief +0x024 - RW - Watchdog Counter Register
NYX	0:85b3fd62ea1a	588	__IO uint32_t WCONTROL; //!< \brief +0x028 - RW - Watchdog Control Register
NYX	0:85b3fd62ea1a	589	__IO uint32_t WISR; //!< \brief +0x02C - RW - Watchdog Interrupt Status Register
NYX	0:85b3fd62ea1a	590	__IO uint32_t WRESET; //!< \brief +0x030 - RW - Watchdog Reset Status Register
NYX	0:85b3fd62ea1a	591	__I uint32_t WDISABLE; //!< \brief +0x0FC - RO - Watchdog Disable Register
NYX	0:85b3fd62ea1a	592	} Timer_Type;
NYX	0:85b3fd62ea1a	593	#define PTIM ((Timer_Type ) TIMER_BASE ) /!< \brief Timer configuration struct */
NYX	0:85b3fd62ea1a	594	#endif
NYX	0:85b3fd62ea1a	595	#endif
NYX	0:85b3fd62ea1a	596
NYX	0:85b3fd62ea1a	597	/*******************************************************************************
NYX	0:85b3fd62ea1a	598	* Hardware Abstraction Layer
NYX	0:85b3fd62ea1a	599	Core Function Interface contains:
NYX	0:85b3fd62ea1a	600	- L1 Cache Functions
NYX	0:85b3fd62ea1a	601	- L2C-310 Cache Controller Functions
NYX	0:85b3fd62ea1a	602	- PL1 Timer Functions
NYX	0:85b3fd62ea1a	603	- GIC Functions
NYX	0:85b3fd62ea1a	604	- MMU Functions
NYX	0:85b3fd62ea1a	605	******************************************************************************/
NYX	0:85b3fd62ea1a	606
NYX	0:85b3fd62ea1a	607	/* ########################## L1 Cache functions ################################# */
NYX	0:85b3fd62ea1a	608
NYX	0:85b3fd62ea1a	609	/** \brief Enable Caches
NYX	0:85b3fd62ea1a	610
NYX	0:85b3fd62ea1a	611	Enable Caches
NYX	0:85b3fd62ea1a	612	*/
NYX	0:85b3fd62ea1a	613	__STATIC_INLINE void L1C_EnableCaches(void) {
NYX	0:85b3fd62ea1a	614	// Set I bit 12 to enable I Cache
NYX	0:85b3fd62ea1a	615	// Set C bit 2 to enable D Cache
NYX	0:85b3fd62ea1a	616	__set_SCTLR( __get_SCTLR() \| (1 << 12) \| (1 << 2));
NYX	0:85b3fd62ea1a	617	}
NYX	0:85b3fd62ea1a	618
NYX	0:85b3fd62ea1a	619	/** \brief Disable Caches
NYX	0:85b3fd62ea1a	620
NYX	0:85b3fd62ea1a	621	Disable Caches
NYX	0:85b3fd62ea1a	622	*/
NYX	0:85b3fd62ea1a	623	__STATIC_INLINE void L1C_DisableCaches(void) {
NYX	0:85b3fd62ea1a	624	// Clear I bit 12 to disable I Cache
NYX	0:85b3fd62ea1a	625	// Clear C bit 2 to disable D Cache
NYX	0:85b3fd62ea1a	626	__set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
NYX	0:85b3fd62ea1a	627	__ISB();
NYX	0:85b3fd62ea1a	628	}
NYX	0:85b3fd62ea1a	629
NYX	0:85b3fd62ea1a	630	/** \brief Enable BTAC
NYX	0:85b3fd62ea1a	631
NYX	0:85b3fd62ea1a	632	Enable BTAC
NYX	0:85b3fd62ea1a	633	*/
NYX	0:85b3fd62ea1a	634	__STATIC_INLINE void L1C_EnableBTAC(void) {
NYX	0:85b3fd62ea1a	635	// Set Z bit 11 to enable branch prediction
NYX	0:85b3fd62ea1a	636	__set_SCTLR( __get_SCTLR() \| (1 << 11));
NYX	0:85b3fd62ea1a	637	__ISB();
NYX	0:85b3fd62ea1a	638	}
NYX	0:85b3fd62ea1a	639
NYX	0:85b3fd62ea1a	640	/** \brief Disable BTAC
NYX	0:85b3fd62ea1a	641
NYX	0:85b3fd62ea1a	642	Disable BTAC
NYX	0:85b3fd62ea1a	643	*/
NYX	0:85b3fd62ea1a	644	__STATIC_INLINE void L1C_DisableBTAC(void) {
NYX	0:85b3fd62ea1a	645	// Clear Z bit 11 to disable branch prediction
NYX	0:85b3fd62ea1a	646	__set_SCTLR( __get_SCTLR() & ~(1 << 11));
NYX	0:85b3fd62ea1a	647	}
NYX	0:85b3fd62ea1a	648
NYX	0:85b3fd62ea1a	649	/** \brief Invalidate entire branch predictor array
NYX	0:85b3fd62ea1a	650
NYX	0:85b3fd62ea1a	651	BPIALL. Branch Predictor Invalidate All.
NYX	0:85b3fd62ea1a	652	*/
NYX	0:85b3fd62ea1a	653
NYX	0:85b3fd62ea1a	654	__STATIC_INLINE void L1C_InvalidateBTAC(void) {
NYX	0:85b3fd62ea1a	655	__set_BPIALL(0);
NYX	0:85b3fd62ea1a	656	__DSB(); //ensure completion of the invalidation
NYX	0:85b3fd62ea1a	657	__ISB(); //ensure instruction fetch path sees new state
NYX	0:85b3fd62ea1a	658	}
NYX	0:85b3fd62ea1a	659
NYX	0:85b3fd62ea1a	660	/** \brief Invalidate the whole I$
NYX	0:85b3fd62ea1a	661
NYX	0:85b3fd62ea1a	662	ICIALLU. Instruction Cache Invalidate All to PoU
NYX	0:85b3fd62ea1a	663	*/
NYX	0:85b3fd62ea1a	664	__STATIC_INLINE void L1C_InvalidateICacheAll(void) {
NYX	0:85b3fd62ea1a	665	__set_ICIALLU(0);
NYX	0:85b3fd62ea1a	666	__DSB(); //ensure completion of the invalidation
NYX	0:85b3fd62ea1a	667	__ISB(); //ensure instruction fetch path sees new I cache state
NYX	0:85b3fd62ea1a	668	}
NYX	0:85b3fd62ea1a	669
NYX	0:85b3fd62ea1a	670	/** \brief Clean D$ by MVA
NYX	0:85b3fd62ea1a	671
NYX	0:85b3fd62ea1a	672	DCCMVAC. Data cache clean by MVA to PoC
NYX	0:85b3fd62ea1a	673	*/
NYX	0:85b3fd62ea1a	674	__STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
NYX	0:85b3fd62ea1a	675	__set_DCCMVAC((uint32_t)va);
NYX	0:85b3fd62ea1a	676	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
NYX	0:85b3fd62ea1a	677	}
NYX	0:85b3fd62ea1a	678
NYX	0:85b3fd62ea1a	679	/** \brief Invalidate D$ by MVA
NYX	0:85b3fd62ea1a	680
NYX	0:85b3fd62ea1a	681	DCIMVAC. Data cache invalidate by MVA to PoC
NYX	0:85b3fd62ea1a	682	*/
NYX	0:85b3fd62ea1a	683	__STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
NYX	0:85b3fd62ea1a	684	__set_DCIMVAC((uint32_t)va);
NYX	0:85b3fd62ea1a	685	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
NYX	0:85b3fd62ea1a	686	}
NYX	0:85b3fd62ea1a	687
NYX	0:85b3fd62ea1a	688	/** \brief Clean and Invalidate D$ by MVA
NYX	0:85b3fd62ea1a	689
NYX	0:85b3fd62ea1a	690	DCCIMVAC. Data cache clean and invalidate by MVA to PoC
NYX	0:85b3fd62ea1a	691	*/
NYX	0:85b3fd62ea1a	692	__STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
NYX	0:85b3fd62ea1a	693	__set_DCCIMVAC((uint32_t)va);
NYX	0:85b3fd62ea1a	694	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
NYX	0:85b3fd62ea1a	695	}
NYX	0:85b3fd62ea1a	696
NYX	0:85b3fd62ea1a	697	/** \brief Clean and Invalidate the entire data or unified cache
NYX	0:85b3fd62ea1a	698
NYX	0:85b3fd62ea1a	699	Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
NYX	0:85b3fd62ea1a	700	*/
NYX	0:85b3fd62ea1a	701	__STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
NYX	0:85b3fd62ea1a	702	__L1C_CleanInvalidateCache(op); // compiler specific call
NYX	0:85b3fd62ea1a	703	}
NYX	0:85b3fd62ea1a	704
NYX	0:85b3fd62ea1a	705
NYX	0:85b3fd62ea1a	706	/** \brief Invalidate the whole D$
NYX	0:85b3fd62ea1a	707
NYX	0:85b3fd62ea1a	708	DCISW. Invalidate by Set/Way
NYX	0:85b3fd62ea1a	709	*/
NYX	0:85b3fd62ea1a	710
NYX	0:85b3fd62ea1a	711	__STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
NYX	0:85b3fd62ea1a	712	L1C_CleanInvalidateCache(0);
NYX	0:85b3fd62ea1a	713	}
NYX	0:85b3fd62ea1a	714
NYX	0:85b3fd62ea1a	715	/** \brief Clean the whole D$
NYX	0:85b3fd62ea1a	716
NYX	0:85b3fd62ea1a	717	DCCSW. Clean by Set/Way
NYX	0:85b3fd62ea1a	718	*/
NYX	0:85b3fd62ea1a	719
NYX	0:85b3fd62ea1a	720	__STATIC_INLINE void L1C_CleanDCacheAll(void) {
NYX	0:85b3fd62ea1a	721	L1C_CleanInvalidateCache(1);
NYX	0:85b3fd62ea1a	722	}
NYX	0:85b3fd62ea1a	723
NYX	0:85b3fd62ea1a	724	/** \brief Clean and invalidate the whole D$
NYX	0:85b3fd62ea1a	725
NYX	0:85b3fd62ea1a	726	DCCISW. Clean and Invalidate by Set/Way
NYX	0:85b3fd62ea1a	727	*/
NYX	0:85b3fd62ea1a	728
NYX	0:85b3fd62ea1a	729	__STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
NYX	0:85b3fd62ea1a	730	L1C_CleanInvalidateCache(2);
NYX	0:85b3fd62ea1a	731	}
NYX	0:85b3fd62ea1a	732
NYX	0:85b3fd62ea1a	733
NYX	0:85b3fd62ea1a	734	/* ########################## L2 Cache functions ################################# */
NYX	0:85b3fd62ea1a	735	#if (__L2C_PRESENT == 1U)
NYX	0:85b3fd62ea1a	736	//Cache Sync operation
NYX	0:85b3fd62ea1a	737	__STATIC_INLINE void L2C_Sync(void)
NYX	0:85b3fd62ea1a	738	{
NYX	0:85b3fd62ea1a	739	L2C_310->CACHE_SYNC = 0x0;
NYX	0:85b3fd62ea1a	740	}
NYX	0:85b3fd62ea1a	741
NYX	0:85b3fd62ea1a	742	//return Cache controller cache ID
NYX	0:85b3fd62ea1a	743	__STATIC_INLINE int L2C_GetID (void)
NYX	0:85b3fd62ea1a	744	{
NYX	0:85b3fd62ea1a	745	return L2C_310->CACHE_ID;
NYX	0:85b3fd62ea1a	746	}
NYX	0:85b3fd62ea1a	747
NYX	0:85b3fd62ea1a	748	//return Cache controller cache Type
NYX	0:85b3fd62ea1a	749	__STATIC_INLINE int L2C_GetType (void)
NYX	0:85b3fd62ea1a	750	{
NYX	0:85b3fd62ea1a	751	return L2C_310->CACHE_TYPE;
NYX	0:85b3fd62ea1a	752	}
NYX	0:85b3fd62ea1a	753
NYX	0:85b3fd62ea1a	754	//Invalidate all cache by way
NYX	0:85b3fd62ea1a	755	__STATIC_INLINE void L2C_InvAllByWay (void)
NYX	0:85b3fd62ea1a	756	{
NYX	0:85b3fd62ea1a	757	unsigned int assoc;
NYX	0:85b3fd62ea1a	758
NYX	0:85b3fd62ea1a	759	if (L2C_310->AUX_CNT & (1<<16))
NYX	0:85b3fd62ea1a	760	assoc = 16;
NYX	0:85b3fd62ea1a	761	else
NYX	0:85b3fd62ea1a	762	assoc = 8;
NYX	0:85b3fd62ea1a	763
NYX	0:85b3fd62ea1a	764	L2C_310->INV_WAY = (1 << assoc) - 1;
NYX	0:85b3fd62ea1a	765	while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
NYX	0:85b3fd62ea1a	766
NYX	0:85b3fd62ea1a	767	L2C_Sync();
NYX	0:85b3fd62ea1a	768	}
NYX	0:85b3fd62ea1a	769
NYX	0:85b3fd62ea1a	770	//Clean and Invalidate all cache by way
NYX	0:85b3fd62ea1a	771	__STATIC_INLINE void L2C_CleanInvAllByWay (void)
NYX	0:85b3fd62ea1a	772	{
NYX	0:85b3fd62ea1a	773	unsigned int assoc;
NYX	0:85b3fd62ea1a	774
NYX	0:85b3fd62ea1a	775	if (L2C_310->AUX_CNT & (1<<16))
NYX	0:85b3fd62ea1a	776	assoc = 16;
NYX	0:85b3fd62ea1a	777	else
NYX	0:85b3fd62ea1a	778	assoc = 8;
NYX	0:85b3fd62ea1a	779
NYX	0:85b3fd62ea1a	780	L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
NYX	0:85b3fd62ea1a	781	while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
NYX	0:85b3fd62ea1a	782
NYX	0:85b3fd62ea1a	783	L2C_Sync();
NYX	0:85b3fd62ea1a	784	}
NYX	0:85b3fd62ea1a	785
NYX	0:85b3fd62ea1a	786	//Enable Cache
NYX	0:85b3fd62ea1a	787	__STATIC_INLINE void L2C_Enable(void)
NYX	0:85b3fd62ea1a	788	{
NYX	0:85b3fd62ea1a	789	L2C_310->CONTROL = 0;
NYX	0:85b3fd62ea1a	790	L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
NYX	0:85b3fd62ea1a	791	L2C_310->DEBUG_CONTROL = 0;
NYX	0:85b3fd62ea1a	792	L2C_310->DATA_LOCK_0_WAY = 0;
NYX	0:85b3fd62ea1a	793	L2C_310->CACHE_SYNC = 0;
NYX	0:85b3fd62ea1a	794	L2C_310->CONTROL = 0x01;
NYX	0:85b3fd62ea1a	795	L2C_Sync();
NYX	0:85b3fd62ea1a	796	}
NYX	0:85b3fd62ea1a	797	//Disable Cache
NYX	0:85b3fd62ea1a	798	__STATIC_INLINE void L2C_Disable(void)
NYX	0:85b3fd62ea1a	799	{
NYX	0:85b3fd62ea1a	800	L2C_310->CONTROL = 0x00;
NYX	0:85b3fd62ea1a	801	L2C_Sync();
NYX	0:85b3fd62ea1a	802	}
NYX	0:85b3fd62ea1a	803
NYX	0:85b3fd62ea1a	804	//Invalidate cache by physical address
NYX	0:85b3fd62ea1a	805	__STATIC_INLINE void L2C_InvPa (void *pa)
NYX	0:85b3fd62ea1a	806	{
NYX	0:85b3fd62ea1a	807	L2C_310->INV_LINE_PA = (unsigned int)pa;
NYX	0:85b3fd62ea1a	808	L2C_Sync();
NYX	0:85b3fd62ea1a	809	}
NYX	0:85b3fd62ea1a	810
NYX	0:85b3fd62ea1a	811	//Clean cache by physical address
NYX	0:85b3fd62ea1a	812	__STATIC_INLINE void L2C_CleanPa (void *pa)
NYX	0:85b3fd62ea1a	813	{
NYX	0:85b3fd62ea1a	814	L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
NYX	0:85b3fd62ea1a	815	L2C_Sync();
NYX	0:85b3fd62ea1a	816	}
NYX	0:85b3fd62ea1a	817
NYX	0:85b3fd62ea1a	818	//Clean and invalidate cache by physical address
NYX	0:85b3fd62ea1a	819	__STATIC_INLINE void L2C_CleanInvPa (void *pa)
NYX	0:85b3fd62ea1a	820	{
NYX	0:85b3fd62ea1a	821	L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
NYX	0:85b3fd62ea1a	822	L2C_Sync();
NYX	0:85b3fd62ea1a	823	}
NYX	0:85b3fd62ea1a	824	#endif
NYX	0:85b3fd62ea1a	825
NYX	0:85b3fd62ea1a	826	/* ########################## GIC functions ###################################### */
NYX	0:85b3fd62ea1a	827	#if (__GIC_PRESENT == 1U)
NYX	0:85b3fd62ea1a	828
NYX	0:85b3fd62ea1a	829	__STATIC_INLINE void GIC_EnableDistributor(void)
NYX	0:85b3fd62ea1a	830	{
NYX	0:85b3fd62ea1a	831	GICDistributor->ICDDCR \|= 1; //enable distributor
NYX	0:85b3fd62ea1a	832	}
NYX	0:85b3fd62ea1a	833
NYX	0:85b3fd62ea1a	834	__STATIC_INLINE void GIC_DisableDistributor(void)
NYX	0:85b3fd62ea1a	835	{
NYX	0:85b3fd62ea1a	836	GICDistributor->ICDDCR &=~1; //disable distributor
NYX	0:85b3fd62ea1a	837	}
NYX	0:85b3fd62ea1a	838
NYX	0:85b3fd62ea1a	839	__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
NYX	0:85b3fd62ea1a	840	{
NYX	0:85b3fd62ea1a	841	return (uint32_t)(GICDistributor->ICDICTR);
NYX	0:85b3fd62ea1a	842	}
NYX	0:85b3fd62ea1a	843
NYX	0:85b3fd62ea1a	844	__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
NYX	0:85b3fd62ea1a	845	{
NYX	0:85b3fd62ea1a	846	return (uint32_t)(GICDistributor->ICDIIDR);
NYX	0:85b3fd62ea1a	847	}
NYX	0:85b3fd62ea1a	848
NYX	0:85b3fd62ea1a	849	__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
NYX	0:85b3fd62ea1a	850	{
NYX	0:85b3fd62ea1a	851	char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
NYX	0:85b3fd62ea1a	852	field += IRQn % 4;
NYX	0:85b3fd62ea1a	853	*field = (char)cpu_target & 0xf;
NYX	0:85b3fd62ea1a	854	}
NYX	0:85b3fd62ea1a	855
NYX	0:85b3fd62ea1a	856	__STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
NYX	0:85b3fd62ea1a	857	{
NYX	0:85b3fd62ea1a	858	uint32_t i, num_irq;
NYX	0:85b3fd62ea1a	859
NYX	0:85b3fd62ea1a	860	//Get the maximum number of interrupts that the GIC supports
NYX	0:85b3fd62ea1a	861	num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
NYX	0:85b3fd62ea1a	862
NYX	0:85b3fd62ea1a	863	for (i = 0; i < (num_irq/16); i++)
NYX	0:85b3fd62ea1a	864	{
NYX	0:85b3fd62ea1a	865	GICDistributor->ICDISPR[i] = *ICDICFRn++;
NYX	0:85b3fd62ea1a	866	}
NYX	0:85b3fd62ea1a	867	}
NYX	0:85b3fd62ea1a	868
NYX	0:85b3fd62ea1a	869	__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	870	{
NYX	0:85b3fd62ea1a	871	char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
NYX	0:85b3fd62ea1a	872	field += IRQn % 4;
NYX	0:85b3fd62ea1a	873	return ((uint32_t)*field & 0xf);
NYX	0:85b3fd62ea1a	874	}
NYX	0:85b3fd62ea1a	875
NYX	0:85b3fd62ea1a	876	__STATIC_INLINE void GIC_EnableInterface(void)
NYX	0:85b3fd62ea1a	877	{
NYX	0:85b3fd62ea1a	878	GICInterface->ICCICR \|= 1; //enable interface
NYX	0:85b3fd62ea1a	879	}
NYX	0:85b3fd62ea1a	880
NYX	0:85b3fd62ea1a	881	__STATIC_INLINE void GIC_DisableInterface(void)
NYX	0:85b3fd62ea1a	882	{
NYX	0:85b3fd62ea1a	883	GICInterface->ICCICR &=~1; //disable distributor
NYX	0:85b3fd62ea1a	884	}
NYX	0:85b3fd62ea1a	885
NYX	0:85b3fd62ea1a	886	__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
NYX	0:85b3fd62ea1a	887	{
NYX	0:85b3fd62ea1a	888	return (IRQn_Type)(GICInterface->ICCIAR);
NYX	0:85b3fd62ea1a	889	}
NYX	0:85b3fd62ea1a	890
NYX	0:85b3fd62ea1a	891	__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	892	{
NYX	0:85b3fd62ea1a	893	GICInterface->ICCEOIR = IRQn;
NYX	0:85b3fd62ea1a	894	}
NYX	0:85b3fd62ea1a	895
NYX	0:85b3fd62ea1a	896	__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	897	{
NYX	0:85b3fd62ea1a	898	GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
NYX	0:85b3fd62ea1a	899	}
NYX	0:85b3fd62ea1a	900
NYX	0:85b3fd62ea1a	901	__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	902	{
NYX	0:85b3fd62ea1a	903	GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
NYX	0:85b3fd62ea1a	904	}
NYX	0:85b3fd62ea1a	905
NYX	0:85b3fd62ea1a	906	__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	907	{
NYX	0:85b3fd62ea1a	908	GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
NYX	0:85b3fd62ea1a	909	}
NYX	0:85b3fd62ea1a	910
NYX	0:85b3fd62ea1a	911	__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	912	{
NYX	0:85b3fd62ea1a	913	GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
NYX	0:85b3fd62ea1a	914	}
NYX	0:85b3fd62ea1a	915
NYX	0:85b3fd62ea1a	916	__STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
NYX	0:85b3fd62ea1a	917	{
NYX	0:85b3fd62ea1a	918	// Word-size read/writes must be used to access this register
NYX	0:85b3fd62ea1a	919	volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
NYX	0:85b3fd62ea1a	920	unsigned bit_shift = (IRQn % 16)<<1;
NYX	0:85b3fd62ea1a	921	unsigned int save_word;
NYX	0:85b3fd62ea1a	922
NYX	0:85b3fd62ea1a	923	save_word = *field;
NYX	0:85b3fd62ea1a	924	save_word &= (~(3 << bit_shift));
NYX	0:85b3fd62ea1a	925
NYX	0:85b3fd62ea1a	926	*field = (save_word \| (((edge_level<<1) \| model) << bit_shift));
NYX	0:85b3fd62ea1a	927	}
NYX	0:85b3fd62ea1a	928
NYX	0:85b3fd62ea1a	929	__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
NYX	0:85b3fd62ea1a	930	{
NYX	0:85b3fd62ea1a	931	char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
NYX	0:85b3fd62ea1a	932	field += IRQn % 4;
NYX	0:85b3fd62ea1a	933	*field = (char)priority;
NYX	0:85b3fd62ea1a	934	}
NYX	0:85b3fd62ea1a	935
NYX	0:85b3fd62ea1a	936	__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	937	{
NYX	0:85b3fd62ea1a	938	char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
NYX	0:85b3fd62ea1a	939	field += IRQn % 4;
NYX	0:85b3fd62ea1a	940	return (uint32_t)*field;
NYX	0:85b3fd62ea1a	941	}
NYX	0:85b3fd62ea1a	942
NYX	0:85b3fd62ea1a	943	__STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
NYX	0:85b3fd62ea1a	944	{
NYX	0:85b3fd62ea1a	945	GICInterface->ICCPMR = priority & 0xff; //set priority mask
NYX	0:85b3fd62ea1a	946	}
NYX	0:85b3fd62ea1a	947
NYX	0:85b3fd62ea1a	948	__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
NYX	0:85b3fd62ea1a	949	{
NYX	0:85b3fd62ea1a	950	GICInterface->ICCBPR = binary_point & 0x07; //set binary point
NYX	0:85b3fd62ea1a	951	}
NYX	0:85b3fd62ea1a	952
NYX	0:85b3fd62ea1a	953	__STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
NYX	0:85b3fd62ea1a	954	{
NYX	0:85b3fd62ea1a	955	return (uint32_t)GICInterface->ICCBPR;
NYX	0:85b3fd62ea1a	956	}
NYX	0:85b3fd62ea1a	957
NYX	0:85b3fd62ea1a	958	__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
NYX	0:85b3fd62ea1a	959	{
NYX	0:85b3fd62ea1a	960	uint32_t pending, active;
NYX	0:85b3fd62ea1a	961
NYX	0:85b3fd62ea1a	962	active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
NYX	0:85b3fd62ea1a	963	pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
NYX	0:85b3fd62ea1a	964
NYX	0:85b3fd62ea1a	965	return ((active<<1) \| pending);
NYX	0:85b3fd62ea1a	966	}
NYX	0:85b3fd62ea1a	967
NYX	0:85b3fd62ea1a	968	__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
NYX	0:85b3fd62ea1a	969	{
NYX	0:85b3fd62ea1a	970	GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) \| ((target_list & 0xff) << 16) \| (IRQn & 0xf);
NYX	0:85b3fd62ea1a	971	}
NYX	0:85b3fd62ea1a	972
NYX	0:85b3fd62ea1a	973	__STATIC_INLINE void GIC_DistInit(void)
NYX	0:85b3fd62ea1a	974	{
NYX	0:85b3fd62ea1a	975	IRQn_Type i;
NYX	0:85b3fd62ea1a	976	uint32_t num_irq = 0;
NYX	0:85b3fd62ea1a	977	uint32_t priority_field;
NYX	0:85b3fd62ea1a	978
NYX	0:85b3fd62ea1a	979	//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
NYX	0:85b3fd62ea1a	980	//configuring all of the interrupts as Secure.
NYX	0:85b3fd62ea1a	981
NYX	0:85b3fd62ea1a	982	//Disable interrupt forwarding
NYX	0:85b3fd62ea1a	983	GIC_DisableDistributor();
NYX	0:85b3fd62ea1a	984	//Get the maximum number of interrupts that the GIC supports
NYX	0:85b3fd62ea1a	985	num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
NYX	0:85b3fd62ea1a	986
NYX	0:85b3fd62ea1a	987	/* Priority level is implementation defined.
NYX	0:85b3fd62ea1a	988	To determine the number of priority bits implemented write 0xFF to an ICDIPR
NYX	0:85b3fd62ea1a	989	priority field and read back the value stored.*/
NYX	0:85b3fd62ea1a	990	GIC_SetPriority((IRQn_Type)0, 0xff);
NYX	0:85b3fd62ea1a	991	priority_field = GIC_GetPriority((IRQn_Type)0);
NYX	0:85b3fd62ea1a	992
NYX	0:85b3fd62ea1a	993	for (i = (IRQn_Type)32; i < num_irq; i++)
NYX	0:85b3fd62ea1a	994	{
NYX	0:85b3fd62ea1a	995	//Disable the SPI interrupt
NYX	0:85b3fd62ea1a	996	GIC_DisableIRQ(i);
NYX	0:85b3fd62ea1a	997	//Set level-sensitive and 1-N model
NYX	0:85b3fd62ea1a	998	GIC_SetLevelModel(i, 0, 1);
NYX	0:85b3fd62ea1a	999	//Set priority
NYX	0:85b3fd62ea1a	1000	GIC_SetPriority(i, priority_field/2);
NYX	0:85b3fd62ea1a	1001	//Set target list to CPU0
NYX	0:85b3fd62ea1a	1002	GIC_SetTarget(i, 1);
NYX	0:85b3fd62ea1a	1003	}
NYX	0:85b3fd62ea1a	1004	//Enable distributor
NYX	0:85b3fd62ea1a	1005	GIC_EnableDistributor();
NYX	0:85b3fd62ea1a	1006	}
NYX	0:85b3fd62ea1a	1007
NYX	0:85b3fd62ea1a	1008	__STATIC_INLINE void GIC_CPUInterfaceInit(void)
NYX	0:85b3fd62ea1a	1009	{
NYX	0:85b3fd62ea1a	1010	IRQn_Type i;
NYX	0:85b3fd62ea1a	1011	uint32_t priority_field;
NYX	0:85b3fd62ea1a	1012
NYX	0:85b3fd62ea1a	1013	//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
NYX	0:85b3fd62ea1a	1014	//configuring all of the interrupts as Secure.
NYX	0:85b3fd62ea1a	1015
NYX	0:85b3fd62ea1a	1016	//Disable interrupt forwarding
NYX	0:85b3fd62ea1a	1017	GIC_DisableInterface();
NYX	0:85b3fd62ea1a	1018
NYX	0:85b3fd62ea1a	1019	/* Priority level is implementation defined.
NYX	0:85b3fd62ea1a	1020	To determine the number of priority bits implemented write 0xFF to an ICDIPR
NYX	0:85b3fd62ea1a	1021	priority field and read back the value stored.*/
NYX	0:85b3fd62ea1a	1022	GIC_SetPriority((IRQn_Type)0, 0xff);
NYX	0:85b3fd62ea1a	1023	priority_field = GIC_GetPriority((IRQn_Type)0);
NYX	0:85b3fd62ea1a	1024
NYX	0:85b3fd62ea1a	1025	//SGI and PPI
NYX	0:85b3fd62ea1a	1026	for (i = (IRQn_Type)0; i < 32; i++)
NYX	0:85b3fd62ea1a	1027	{
NYX	0:85b3fd62ea1a	1028	//Set level-sensitive and 1-N model for PPI
NYX	0:85b3fd62ea1a	1029	if(i > 15)
NYX	0:85b3fd62ea1a	1030	GIC_SetLevelModel(i, 0, 1);
NYX	0:85b3fd62ea1a	1031	//Disable SGI and PPI interrupts
NYX	0:85b3fd62ea1a	1032	GIC_DisableIRQ(i);
NYX	0:85b3fd62ea1a	1033	//Set priority
NYX	0:85b3fd62ea1a	1034	GIC_SetPriority(i, priority_field/2);
NYX	0:85b3fd62ea1a	1035	}
NYX	0:85b3fd62ea1a	1036	//Enable interface
NYX	0:85b3fd62ea1a	1037	GIC_EnableInterface();
NYX	0:85b3fd62ea1a	1038	//Set binary point to 0
NYX	0:85b3fd62ea1a	1039	GIC_SetBinaryPoint(0);
NYX	0:85b3fd62ea1a	1040	//Set priority mask
NYX	0:85b3fd62ea1a	1041	GIC_InterfacePriorityMask(0xff);
NYX	0:85b3fd62ea1a	1042	}
NYX	0:85b3fd62ea1a	1043
NYX	0:85b3fd62ea1a	1044	__STATIC_INLINE void GIC_Enable(void)
NYX	0:85b3fd62ea1a	1045	{
NYX	0:85b3fd62ea1a	1046	GIC_DistInit();
NYX	0:85b3fd62ea1a	1047	GIC_CPUInterfaceInit(); //per CPU
NYX	0:85b3fd62ea1a	1048	}
NYX	0:85b3fd62ea1a	1049	#endif
NYX	0:85b3fd62ea1a	1050
NYX	0:85b3fd62ea1a	1051	/* ########################## Generic Timer functions ############################ */
NYX	0:85b3fd62ea1a	1052	#if (__TIM_PRESENT == 1U)
NYX	0:85b3fd62ea1a	1053
NYX	0:85b3fd62ea1a	1054	/* PL1 Physical Timer */
NYX	0:85b3fd62ea1a	1055	#if (__CORTEX_A == 7U)
NYX	0:85b3fd62ea1a	1056	__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
NYX	0:85b3fd62ea1a	1057	__set_CNTP_TVAL(value);
NYX	0:85b3fd62ea1a	1058	__ISB();
NYX	0:85b3fd62ea1a	1059	}
NYX	0:85b3fd62ea1a	1060
NYX	0:85b3fd62ea1a	1061	__STATIC_INLINE uint32_t PL1_GetCurrentValue() {
NYX	0:85b3fd62ea1a	1062	return(__get_CNTP_TVAL());
NYX	0:85b3fd62ea1a	1063	}
NYX	0:85b3fd62ea1a	1064
NYX	0:85b3fd62ea1a	1065	__STATIC_INLINE void PL1_SetControl(uint32_t value) {
NYX	0:85b3fd62ea1a	1066	__set_CNTP_CTL(value);
NYX	0:85b3fd62ea1a	1067	__ISB();
NYX	0:85b3fd62ea1a	1068	}
NYX	0:85b3fd62ea1a	1069
NYX	0:85b3fd62ea1a	1070	/* Private Timer */
NYX	0:85b3fd62ea1a	1071	#elif ((__CORTEX_A == 5U)\|\|(__CORTEX_A == 9U))
NYX	0:85b3fd62ea1a	1072	__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
NYX	0:85b3fd62ea1a	1073	PTIM->LOAD = value;
NYX	0:85b3fd62ea1a	1074	}
NYX	0:85b3fd62ea1a	1075
NYX	0:85b3fd62ea1a	1076	__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
NYX	0:85b3fd62ea1a	1077	return(PTIM->LOAD);
NYX	0:85b3fd62ea1a	1078	}
NYX	0:85b3fd62ea1a	1079
NYX	0:85b3fd62ea1a	1080	__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
NYX	0:85b3fd62ea1a	1081	return(PTIM->COUNTER);
NYX	0:85b3fd62ea1a	1082	}
NYX	0:85b3fd62ea1a	1083
NYX	0:85b3fd62ea1a	1084	__STATIC_INLINE void PTIM_SetControl(uint32_t value) {
NYX	0:85b3fd62ea1a	1085	PTIM->CONTROL = value;
NYX	0:85b3fd62ea1a	1086	}
NYX	0:85b3fd62ea1a	1087
NYX	0:85b3fd62ea1a	1088	__STATIC_INLINE uint32_t PTIM_GetControl(void) {
NYX	0:85b3fd62ea1a	1089	return(PTIM->CONTROL);
NYX	0:85b3fd62ea1a	1090	}
NYX	0:85b3fd62ea1a	1091
NYX	0:85b3fd62ea1a	1092	__STATIC_INLINE void PTIM_ClearEventFlag(void) {
NYX	0:85b3fd62ea1a	1093	PTIM->ISR = 1;
NYX	0:85b3fd62ea1a	1094	}
NYX	0:85b3fd62ea1a	1095	#endif
NYX	0:85b3fd62ea1a	1096	#endif
NYX	0:85b3fd62ea1a	1097
NYX	0:85b3fd62ea1a	1098	/* ########################## MMU functions ###################################### */
NYX	0:85b3fd62ea1a	1099
NYX	0:85b3fd62ea1a	1100	#define SECTION_DESCRIPTOR (0x2)
NYX	0:85b3fd62ea1a	1101	#define SECTION_MASK (0xFFFFFFFC)
NYX	0:85b3fd62ea1a	1102
NYX	0:85b3fd62ea1a	1103	#define SECTION_TEXCB_MASK (0xFFFF8FF3)
NYX	0:85b3fd62ea1a	1104	#define SECTION_B_SHIFT (2)
NYX	0:85b3fd62ea1a	1105	#define SECTION_C_SHIFT (3)
NYX	0:85b3fd62ea1a	1106	#define SECTION_TEX0_SHIFT (12)
NYX	0:85b3fd62ea1a	1107	#define SECTION_TEX1_SHIFT (13)
NYX	0:85b3fd62ea1a	1108	#define SECTION_TEX2_SHIFT (14)
NYX	0:85b3fd62ea1a	1109
NYX	0:85b3fd62ea1a	1110	#define SECTION_XN_MASK (0xFFFFFFEF)
NYX	0:85b3fd62ea1a	1111	#define SECTION_XN_SHIFT (4)
NYX	0:85b3fd62ea1a	1112
NYX	0:85b3fd62ea1a	1113	#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
NYX	0:85b3fd62ea1a	1114	#define SECTION_DOMAIN_SHIFT (5)
NYX	0:85b3fd62ea1a	1115
NYX	0:85b3fd62ea1a	1116	#define SECTION_P_MASK (0xFFFFFDFF)
NYX	0:85b3fd62ea1a	1117	#define SECTION_P_SHIFT (9)
NYX	0:85b3fd62ea1a	1118
NYX	0:85b3fd62ea1a	1119	#define SECTION_AP_MASK (0xFFFF73FF)
NYX	0:85b3fd62ea1a	1120	#define SECTION_AP_SHIFT (10)
NYX	0:85b3fd62ea1a	1121	#define SECTION_AP2_SHIFT (15)
NYX	0:85b3fd62ea1a	1122
NYX	0:85b3fd62ea1a	1123	#define SECTION_S_MASK (0xFFFEFFFF)
NYX	0:85b3fd62ea1a	1124	#define SECTION_S_SHIFT (16)
NYX	0:85b3fd62ea1a	1125
NYX	0:85b3fd62ea1a	1126	#define SECTION_NG_MASK (0xFFFDFFFF)
NYX	0:85b3fd62ea1a	1127	#define SECTION_NG_SHIFT (17)
NYX	0:85b3fd62ea1a	1128
NYX	0:85b3fd62ea1a	1129	#define SECTION_NS_MASK (0xFFF7FFFF)
NYX	0:85b3fd62ea1a	1130	#define SECTION_NS_SHIFT (19)
NYX	0:85b3fd62ea1a	1131
NYX	0:85b3fd62ea1a	1132	#define PAGE_L1_DESCRIPTOR (0x1)
NYX	0:85b3fd62ea1a	1133	#define PAGE_L1_MASK (0xFFFFFFFC)
NYX	0:85b3fd62ea1a	1134
NYX	0:85b3fd62ea1a	1135	#define PAGE_L2_4K_DESC (0x2)
NYX	0:85b3fd62ea1a	1136	#define PAGE_L2_4K_MASK (0xFFFFFFFD)
NYX	0:85b3fd62ea1a	1137
NYX	0:85b3fd62ea1a	1138	#define PAGE_L2_64K_DESC (0x1)
NYX	0:85b3fd62ea1a	1139	#define PAGE_L2_64K_MASK (0xFFFFFFFC)
NYX	0:85b3fd62ea1a	1140
NYX	0:85b3fd62ea1a	1141	#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
NYX	0:85b3fd62ea1a	1142	#define PAGE_4K_B_SHIFT (2)
NYX	0:85b3fd62ea1a	1143	#define PAGE_4K_C_SHIFT (3)
NYX	0:85b3fd62ea1a	1144	#define PAGE_4K_TEX0_SHIFT (6)
NYX	0:85b3fd62ea1a	1145	#define PAGE_4K_TEX1_SHIFT (7)
NYX	0:85b3fd62ea1a	1146	#define PAGE_4K_TEX2_SHIFT (8)
NYX	0:85b3fd62ea1a	1147
NYX	0:85b3fd62ea1a	1148	#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
NYX	0:85b3fd62ea1a	1149	#define PAGE_64K_B_SHIFT (2)
NYX	0:85b3fd62ea1a	1150	#define PAGE_64K_C_SHIFT (3)
NYX	0:85b3fd62ea1a	1151	#define PAGE_64K_TEX0_SHIFT (12)
NYX	0:85b3fd62ea1a	1152	#define PAGE_64K_TEX1_SHIFT (13)
NYX	0:85b3fd62ea1a	1153	#define PAGE_64K_TEX2_SHIFT (14)
NYX	0:85b3fd62ea1a	1154
NYX	0:85b3fd62ea1a	1155	#define PAGE_TEXCB_MASK (0xFFFF8FF3)
NYX	0:85b3fd62ea1a	1156	#define PAGE_B_SHIFT (2)
NYX	0:85b3fd62ea1a	1157	#define PAGE_C_SHIFT (3)
NYX	0:85b3fd62ea1a	1158	#define PAGE_TEX_SHIFT (12)
NYX	0:85b3fd62ea1a	1159
NYX	0:85b3fd62ea1a	1160	#define PAGE_XN_4K_MASK (0xFFFFFFFE)
NYX	0:85b3fd62ea1a	1161	#define PAGE_XN_4K_SHIFT (0)
NYX	0:85b3fd62ea1a	1162	#define PAGE_XN_64K_MASK (0xFFFF7FFF)
NYX	0:85b3fd62ea1a	1163	#define PAGE_XN_64K_SHIFT (15)
NYX	0:85b3fd62ea1a	1164
NYX	0:85b3fd62ea1a	1165	#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
NYX	0:85b3fd62ea1a	1166	#define PAGE_DOMAIN_SHIFT (5)
NYX	0:85b3fd62ea1a	1167
NYX	0:85b3fd62ea1a	1168	#define PAGE_P_MASK (0xFFFFFDFF)
NYX	0:85b3fd62ea1a	1169	#define PAGE_P_SHIFT (9)
NYX	0:85b3fd62ea1a	1170
NYX	0:85b3fd62ea1a	1171	#define PAGE_AP_MASK (0xFFFFFDCF)
NYX	0:85b3fd62ea1a	1172	#define PAGE_AP_SHIFT (4)
NYX	0:85b3fd62ea1a	1173	#define PAGE_AP2_SHIFT (9)
NYX	0:85b3fd62ea1a	1174
NYX	0:85b3fd62ea1a	1175	#define PAGE_S_MASK (0xFFFFFBFF)
NYX	0:85b3fd62ea1a	1176	#define PAGE_S_SHIFT (10)
NYX	0:85b3fd62ea1a	1177
NYX	0:85b3fd62ea1a	1178	#define PAGE_NG_MASK (0xFFFFF7FF)
NYX	0:85b3fd62ea1a	1179	#define PAGE_NG_SHIFT (11)
NYX	0:85b3fd62ea1a	1180
NYX	0:85b3fd62ea1a	1181	#define PAGE_NS_MASK (0xFFFFFFF7)
NYX	0:85b3fd62ea1a	1182	#define PAGE_NS_SHIFT (3)
NYX	0:85b3fd62ea1a	1183
NYX	0:85b3fd62ea1a	1184	#define OFFSET_1M (0x00100000)
NYX	0:85b3fd62ea1a	1185	#define OFFSET_64K (0x00010000)
NYX	0:85b3fd62ea1a	1186	#define OFFSET_4K (0x00001000)
NYX	0:85b3fd62ea1a	1187
NYX	0:85b3fd62ea1a	1188	#define DESCRIPTOR_FAULT (0x00000000)
NYX	0:85b3fd62ea1a	1189
NYX	0:85b3fd62ea1a	1190	/* Attributes enumerations */
NYX	0:85b3fd62ea1a	1191
NYX	0:85b3fd62ea1a	1192	/* Region size attributes */
NYX	0:85b3fd62ea1a	1193	typedef enum
NYX	0:85b3fd62ea1a	1194	{
NYX	0:85b3fd62ea1a	1195	SECTION,
NYX	0:85b3fd62ea1a	1196	PAGE_4k,
NYX	0:85b3fd62ea1a	1197	PAGE_64k,
NYX	0:85b3fd62ea1a	1198	} mmu_region_size_Type;
NYX	0:85b3fd62ea1a	1199
NYX	0:85b3fd62ea1a	1200	/* Region type attributes */
NYX	0:85b3fd62ea1a	1201	typedef enum
NYX	0:85b3fd62ea1a	1202	{
NYX	0:85b3fd62ea1a	1203	NORMAL,
NYX	0:85b3fd62ea1a	1204	DEVICE,
NYX	0:85b3fd62ea1a	1205	SHARED_DEVICE,
NYX	0:85b3fd62ea1a	1206	NON_SHARED_DEVICE,
NYX	0:85b3fd62ea1a	1207	STRONGLY_ORDERED
NYX	0:85b3fd62ea1a	1208	} mmu_memory_Type;
NYX	0:85b3fd62ea1a	1209
NYX	0:85b3fd62ea1a	1210	/* Region cacheability attributes */
NYX	0:85b3fd62ea1a	1211	typedef enum
NYX	0:85b3fd62ea1a	1212	{
NYX	0:85b3fd62ea1a	1213	NON_CACHEABLE,
NYX	0:85b3fd62ea1a	1214	WB_WA,
NYX	0:85b3fd62ea1a	1215	WT,
NYX	0:85b3fd62ea1a	1216	WB_NO_WA,
NYX	0:85b3fd62ea1a	1217	} mmu_cacheability_Type;
NYX	0:85b3fd62ea1a	1218
NYX	0:85b3fd62ea1a	1219	/* Region parity check attributes */
NYX	0:85b3fd62ea1a	1220	typedef enum
NYX	0:85b3fd62ea1a	1221	{
NYX	0:85b3fd62ea1a	1222	ECC_DISABLED,
NYX	0:85b3fd62ea1a	1223	ECC_ENABLED,
NYX	0:85b3fd62ea1a	1224	} mmu_ecc_check_Type;
NYX	0:85b3fd62ea1a	1225
NYX	0:85b3fd62ea1a	1226	/* Region execution attributes */
NYX	0:85b3fd62ea1a	1227	typedef enum
NYX	0:85b3fd62ea1a	1228	{
NYX	0:85b3fd62ea1a	1229	EXECUTE,
NYX	0:85b3fd62ea1a	1230	NON_EXECUTE,
NYX	0:85b3fd62ea1a	1231	} mmu_execute_Type;
NYX	0:85b3fd62ea1a	1232
NYX	0:85b3fd62ea1a	1233	/* Region global attributes */
NYX	0:85b3fd62ea1a	1234	typedef enum
NYX	0:85b3fd62ea1a	1235	{
NYX	0:85b3fd62ea1a	1236	GLOBAL,
NYX	0:85b3fd62ea1a	1237	NON_GLOBAL,
NYX	0:85b3fd62ea1a	1238	} mmu_global_Type;
NYX	0:85b3fd62ea1a	1239
NYX	0:85b3fd62ea1a	1240	/* Region shareability attributes */
NYX	0:85b3fd62ea1a	1241	typedef enum
NYX	0:85b3fd62ea1a	1242	{
NYX	0:85b3fd62ea1a	1243	NON_SHARED,
NYX	0:85b3fd62ea1a	1244	SHARED,
NYX	0:85b3fd62ea1a	1245	} mmu_shared_Type;
NYX	0:85b3fd62ea1a	1246
NYX	0:85b3fd62ea1a	1247	/* Region security attributes */
NYX	0:85b3fd62ea1a	1248	typedef enum
NYX	0:85b3fd62ea1a	1249	{
NYX	0:85b3fd62ea1a	1250	SECURE,
NYX	0:85b3fd62ea1a	1251	NON_SECURE,
NYX	0:85b3fd62ea1a	1252	} mmu_secure_Type;
NYX	0:85b3fd62ea1a	1253
NYX	0:85b3fd62ea1a	1254	/* Region access attributes */
NYX	0:85b3fd62ea1a	1255	typedef enum
NYX	0:85b3fd62ea1a	1256	{
NYX	0:85b3fd62ea1a	1257	NO_ACCESS,
NYX	0:85b3fd62ea1a	1258	RW,
NYX	0:85b3fd62ea1a	1259	READ,
NYX	0:85b3fd62ea1a	1260	} mmu_access_Type;
NYX	0:85b3fd62ea1a	1261
NYX	0:85b3fd62ea1a	1262	/* Memory Region definition */
NYX	0:85b3fd62ea1a	1263	typedef struct RegionStruct {
NYX	0:85b3fd62ea1a	1264	mmu_region_size_Type rg_t;
NYX	0:85b3fd62ea1a	1265	mmu_memory_Type mem_t;
NYX	0:85b3fd62ea1a	1266	uint8_t domain;
NYX	0:85b3fd62ea1a	1267	mmu_cacheability_Type inner_norm_t;
NYX	0:85b3fd62ea1a	1268	mmu_cacheability_Type outer_norm_t;
NYX	0:85b3fd62ea1a	1269	mmu_ecc_check_Type e_t;
NYX	0:85b3fd62ea1a	1270	mmu_execute_Type xn_t;
NYX	0:85b3fd62ea1a	1271	mmu_global_Type g_t;
NYX	0:85b3fd62ea1a	1272	mmu_secure_Type sec_t;
NYX	0:85b3fd62ea1a	1273	mmu_access_Type priv_t;
NYX	0:85b3fd62ea1a	1274	mmu_access_Type user_t;
NYX	0:85b3fd62ea1a	1275	mmu_shared_Type sh_t;
NYX	0:85b3fd62ea1a	1276
NYX	0:85b3fd62ea1a	1277	} mmu_region_attributes_Type;
NYX	0:85b3fd62ea1a	1278
NYX	0:85b3fd62ea1a	1279	//Following macros define the descriptors and attributes
NYX	0:85b3fd62ea1a	1280	//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
NYX	0:85b3fd62ea1a	1281	#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
NYX	0:85b3fd62ea1a	1282	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1283	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1284	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1285	region.inner_norm_t = WB_WA; \
NYX	0:85b3fd62ea1a	1286	region.outer_norm_t = WB_WA; \
NYX	0:85b3fd62ea1a	1287	region.mem_t = NORMAL; \
NYX	0:85b3fd62ea1a	1288	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1289	region.xn_t = EXECUTE; \
NYX	0:85b3fd62ea1a	1290	region.priv_t = RW; \
NYX	0:85b3fd62ea1a	1291	region.user_t = RW; \
NYX	0:85b3fd62ea1a	1292	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1293	MMU_GetSectionDescriptor(&descriptor_l1, region);
NYX	0:85b3fd62ea1a	1294
NYX	0:85b3fd62ea1a	1295	//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
NYX	0:85b3fd62ea1a	1296	#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
NYX	0:85b3fd62ea1a	1297	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1298	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1299	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1300	region.inner_norm_t = WB_WA; \
NYX	0:85b3fd62ea1a	1301	region.outer_norm_t = WB_WA; \
NYX	0:85b3fd62ea1a	1302	region.mem_t = NORMAL; \
NYX	0:85b3fd62ea1a	1303	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1304	region.xn_t = EXECUTE; \
NYX	0:85b3fd62ea1a	1305	region.priv_t = READ; \
NYX	0:85b3fd62ea1a	1306	region.user_t = READ; \
NYX	0:85b3fd62ea1a	1307	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1308	MMU_GetSectionDescriptor(&descriptor_l1, region);
NYX	0:85b3fd62ea1a	1309
NYX	0:85b3fd62ea1a	1310	//Sect_Normal_RO. Sect_Normal_Cod, but not executable
NYX	0:85b3fd62ea1a	1311	#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
NYX	0:85b3fd62ea1a	1312	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1313	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1314	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1315	region.inner_norm_t = WB_WA; \
NYX	0:85b3fd62ea1a	1316	region.outer_norm_t = WB_WA; \
NYX	0:85b3fd62ea1a	1317	region.mem_t = NORMAL; \
NYX	0:85b3fd62ea1a	1318	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1319	region.xn_t = NON_EXECUTE; \
NYX	0:85b3fd62ea1a	1320	region.priv_t = READ; \
NYX	0:85b3fd62ea1a	1321	region.user_t = READ; \
NYX	0:85b3fd62ea1a	1322	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1323	MMU_GetSectionDescriptor(&descriptor_l1, region);
NYX	0:85b3fd62ea1a	1324
NYX	0:85b3fd62ea1a	1325	//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
NYX	0:85b3fd62ea1a	1326	#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
NYX	0:85b3fd62ea1a	1327	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1328	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1329	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1330	region.inner_norm_t = WB_WA; \
NYX	0:85b3fd62ea1a	1331	region.outer_norm_t = WB_WA; \
NYX	0:85b3fd62ea1a	1332	region.mem_t = NORMAL; \
NYX	0:85b3fd62ea1a	1333	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1334	region.xn_t = NON_EXECUTE; \
NYX	0:85b3fd62ea1a	1335	region.priv_t = RW; \
NYX	0:85b3fd62ea1a	1336	region.user_t = RW; \
NYX	0:85b3fd62ea1a	1337	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1338	MMU_GetSectionDescriptor(&descriptor_l1, region);
NYX	0:85b3fd62ea1a	1339	//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
NYX	0:85b3fd62ea1a	1340	#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
NYX	0:85b3fd62ea1a	1341	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1342	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1343	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1344	region.inner_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1345	region.outer_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1346	region.mem_t = STRONGLY_ORDERED; \
NYX	0:85b3fd62ea1a	1347	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1348	region.xn_t = NON_EXECUTE; \
NYX	0:85b3fd62ea1a	1349	region.priv_t = RW; \
NYX	0:85b3fd62ea1a	1350	region.user_t = RW; \
NYX	0:85b3fd62ea1a	1351	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1352	MMU_GetSectionDescriptor(&descriptor_l1, region);
NYX	0:85b3fd62ea1a	1353
NYX	0:85b3fd62ea1a	1354	//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
NYX	0:85b3fd62ea1a	1355	#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
NYX	0:85b3fd62ea1a	1356	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1357	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1358	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1359	region.inner_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1360	region.outer_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1361	region.mem_t = STRONGLY_ORDERED; \
NYX	0:85b3fd62ea1a	1362	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1363	region.xn_t = NON_EXECUTE; \
NYX	0:85b3fd62ea1a	1364	region.priv_t = READ; \
NYX	0:85b3fd62ea1a	1365	region.user_t = READ; \
NYX	0:85b3fd62ea1a	1366	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1367	MMU_GetSectionDescriptor(&descriptor_l1, region);
NYX	0:85b3fd62ea1a	1368
NYX	0:85b3fd62ea1a	1369	//Sect_Device_RW. Sect_Device_RO, but writeable
NYX	0:85b3fd62ea1a	1370	#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
NYX	0:85b3fd62ea1a	1371	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1372	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1373	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1374	region.inner_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1375	region.outer_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1376	region.mem_t = STRONGLY_ORDERED; \
NYX	0:85b3fd62ea1a	1377	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1378	region.xn_t = NON_EXECUTE; \
NYX	0:85b3fd62ea1a	1379	region.priv_t = RW; \
NYX	0:85b3fd62ea1a	1380	region.user_t = RW; \
NYX	0:85b3fd62ea1a	1381	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1382	MMU_GetSectionDescriptor(&descriptor_l1, region);
NYX	0:85b3fd62ea1a	1383	//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
NYX	0:85b3fd62ea1a	1384	#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
NYX	0:85b3fd62ea1a	1385	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1386	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1387	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1388	region.inner_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1389	region.outer_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1390	region.mem_t = SHARED_DEVICE; \
NYX	0:85b3fd62ea1a	1391	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1392	region.xn_t = NON_EXECUTE; \
NYX	0:85b3fd62ea1a	1393	region.priv_t = RW; \
NYX	0:85b3fd62ea1a	1394	region.user_t = RW; \
NYX	0:85b3fd62ea1a	1395	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1396	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
NYX	0:85b3fd62ea1a	1397
NYX	0:85b3fd62ea1a	1398	//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
NYX	0:85b3fd62ea1a	1399	#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
NYX	0:85b3fd62ea1a	1400	region.domain = 0x0; \
NYX	0:85b3fd62ea1a	1401	region.e_t = ECC_DISABLED; \
NYX	0:85b3fd62ea1a	1402	region.g_t = GLOBAL; \
NYX	0:85b3fd62ea1a	1403	region.inner_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1404	region.outer_norm_t = NON_CACHEABLE; \
NYX	0:85b3fd62ea1a	1405	region.mem_t = SHARED_DEVICE; \
NYX	0:85b3fd62ea1a	1406	region.sec_t = SECURE; \
NYX	0:85b3fd62ea1a	1407	region.xn_t = NON_EXECUTE; \
NYX	0:85b3fd62ea1a	1408	region.priv_t = RW; \
NYX	0:85b3fd62ea1a	1409	region.user_t = RW; \
NYX	0:85b3fd62ea1a	1410	region.sh_t = NON_SHARED; \
NYX	0:85b3fd62ea1a	1411	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
NYX	0:85b3fd62ea1a	1412
NYX	0:85b3fd62ea1a	1413	/** \brief Set section execution-never attribute
NYX	0:85b3fd62ea1a	1414
NYX	0:85b3fd62ea1a	1415	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1416	\param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
NYX	0:85b3fd62ea1a	1417
NYX	0:85b3fd62ea1a	1418	\return 0
NYX	0:85b3fd62ea1a	1419	*/
NYX	0:85b3fd62ea1a	1420	__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
NYX	0:85b3fd62ea1a	1421	{
NYX	0:85b3fd62ea1a	1422	*descriptor_l1 &= SECTION_XN_MASK;
NYX	0:85b3fd62ea1a	1423	*descriptor_l1 \|= ((xn & 0x1) << SECTION_XN_SHIFT);
NYX	0:85b3fd62ea1a	1424	return 0;
NYX	0:85b3fd62ea1a	1425	}
NYX	0:85b3fd62ea1a	1426
NYX	0:85b3fd62ea1a	1427	/** \brief Set section domain
NYX	0:85b3fd62ea1a	1428
NYX	0:85b3fd62ea1a	1429	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1430	\param [in] domain Section domain
NYX	0:85b3fd62ea1a	1431
NYX	0:85b3fd62ea1a	1432	\return 0
NYX	0:85b3fd62ea1a	1433	*/
NYX	0:85b3fd62ea1a	1434	__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
NYX	0:85b3fd62ea1a	1435	{
NYX	0:85b3fd62ea1a	1436	*descriptor_l1 &= SECTION_DOMAIN_MASK;
NYX	0:85b3fd62ea1a	1437	*descriptor_l1 \|= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
NYX	0:85b3fd62ea1a	1438	return 0;
NYX	0:85b3fd62ea1a	1439	}
NYX	0:85b3fd62ea1a	1440
NYX	0:85b3fd62ea1a	1441	/** \brief Set section parity check
NYX	0:85b3fd62ea1a	1442
NYX	0:85b3fd62ea1a	1443	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1444	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
NYX	0:85b3fd62ea1a	1445
NYX	0:85b3fd62ea1a	1446	\return 0
NYX	0:85b3fd62ea1a	1447	*/
NYX	0:85b3fd62ea1a	1448	__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
NYX	0:85b3fd62ea1a	1449	{
NYX	0:85b3fd62ea1a	1450	*descriptor_l1 &= SECTION_P_MASK;
NYX	0:85b3fd62ea1a	1451	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
NYX	0:85b3fd62ea1a	1452	return 0;
NYX	0:85b3fd62ea1a	1453	}
NYX	0:85b3fd62ea1a	1454
NYX	0:85b3fd62ea1a	1455	/** \brief Set section access privileges
NYX	0:85b3fd62ea1a	1456
NYX	0:85b3fd62ea1a	1457	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1458	\param [in] user User Level Access: NO_ACCESS, RW, READ
NYX	0:85b3fd62ea1a	1459	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
NYX	0:85b3fd62ea1a	1460	\param [in] afe Access flag enable
NYX	0:85b3fd62ea1a	1461
NYX	0:85b3fd62ea1a	1462	\return 0
NYX	0:85b3fd62ea1a	1463	*/
NYX	0:85b3fd62ea1a	1464	__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
NYX	0:85b3fd62ea1a	1465	{
NYX	0:85b3fd62ea1a	1466	uint32_t ap = 0;
NYX	0:85b3fd62ea1a	1467
NYX	0:85b3fd62ea1a	1468	if (afe == 0) { //full access
NYX	0:85b3fd62ea1a	1469	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
NYX	0:85b3fd62ea1a	1470	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
NYX	0:85b3fd62ea1a	1471	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
NYX	0:85b3fd62ea1a	1472	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
NYX	0:85b3fd62ea1a	1473	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
NYX	0:85b3fd62ea1a	1474	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
NYX	0:85b3fd62ea1a	1475	}
NYX	0:85b3fd62ea1a	1476
NYX	0:85b3fd62ea1a	1477	else { //Simplified access
NYX	0:85b3fd62ea1a	1478	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
NYX	0:85b3fd62ea1a	1479	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
NYX	0:85b3fd62ea1a	1480	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
NYX	0:85b3fd62ea1a	1481	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
NYX	0:85b3fd62ea1a	1482	}
NYX	0:85b3fd62ea1a	1483
NYX	0:85b3fd62ea1a	1484	*descriptor_l1 &= SECTION_AP_MASK;
NYX	0:85b3fd62ea1a	1485	*descriptor_l1 \|= (ap & 0x3) << SECTION_AP_SHIFT;
NYX	0:85b3fd62ea1a	1486	*descriptor_l1 \|= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
NYX	0:85b3fd62ea1a	1487
NYX	0:85b3fd62ea1a	1488	return 0;
NYX	0:85b3fd62ea1a	1489	}
NYX	0:85b3fd62ea1a	1490
NYX	0:85b3fd62ea1a	1491	/** \brief Set section shareability
NYX	0:85b3fd62ea1a	1492
NYX	0:85b3fd62ea1a	1493	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1494	\param [in] s_bit Section shareability: NON_SHARED, SHARED
NYX	0:85b3fd62ea1a	1495
NYX	0:85b3fd62ea1a	1496	\return 0
NYX	0:85b3fd62ea1a	1497	*/
NYX	0:85b3fd62ea1a	1498	__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
NYX	0:85b3fd62ea1a	1499	{
NYX	0:85b3fd62ea1a	1500	*descriptor_l1 &= SECTION_S_MASK;
NYX	0:85b3fd62ea1a	1501	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_S_SHIFT);
NYX	0:85b3fd62ea1a	1502	return 0;
NYX	0:85b3fd62ea1a	1503	}
NYX	0:85b3fd62ea1a	1504
NYX	0:85b3fd62ea1a	1505	/** \brief Set section Global attribute
NYX	0:85b3fd62ea1a	1506
NYX	0:85b3fd62ea1a	1507	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1508	\param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
NYX	0:85b3fd62ea1a	1509
NYX	0:85b3fd62ea1a	1510	\return 0
NYX	0:85b3fd62ea1a	1511	*/
NYX	0:85b3fd62ea1a	1512	__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
NYX	0:85b3fd62ea1a	1513	{
NYX	0:85b3fd62ea1a	1514	*descriptor_l1 &= SECTION_NG_MASK;
NYX	0:85b3fd62ea1a	1515	*descriptor_l1 \|= ((g_bit & 0x1) << SECTION_NG_SHIFT);
NYX	0:85b3fd62ea1a	1516	return 0;
NYX	0:85b3fd62ea1a	1517	}
NYX	0:85b3fd62ea1a	1518
NYX	0:85b3fd62ea1a	1519	/** \brief Set section Security attribute
NYX	0:85b3fd62ea1a	1520
NYX	0:85b3fd62ea1a	1521	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1522	\param [in] s_bit Section Security attribute: SECURE, NON_SECURE
NYX	0:85b3fd62ea1a	1523
NYX	0:85b3fd62ea1a	1524	\return 0
NYX	0:85b3fd62ea1a	1525	*/
NYX	0:85b3fd62ea1a	1526	__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
NYX	0:85b3fd62ea1a	1527	{
NYX	0:85b3fd62ea1a	1528	*descriptor_l1 &= SECTION_NS_MASK;
NYX	0:85b3fd62ea1a	1529	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_NS_SHIFT);
NYX	0:85b3fd62ea1a	1530	return 0;
NYX	0:85b3fd62ea1a	1531	}
NYX	0:85b3fd62ea1a	1532
NYX	0:85b3fd62ea1a	1533	/* Page 4k or 64k */
NYX	0:85b3fd62ea1a	1534	/** \brief Set 4k/64k page execution-never attribute
NYX	0:85b3fd62ea1a	1535
NYX	0:85b3fd62ea1a	1536	\param [out] descriptor_l2 L2 descriptor.
NYX	0:85b3fd62ea1a	1537	\param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
NYX	0:85b3fd62ea1a	1538	\param [in] page Page size: PAGE_4k, PAGE_64k,
NYX	0:85b3fd62ea1a	1539
NYX	0:85b3fd62ea1a	1540	\return 0
NYX	0:85b3fd62ea1a	1541	*/
NYX	0:85b3fd62ea1a	1542	__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
NYX	0:85b3fd62ea1a	1543	{
NYX	0:85b3fd62ea1a	1544	if (page == PAGE_4k)
NYX	0:85b3fd62ea1a	1545	{
NYX	0:85b3fd62ea1a	1546	*descriptor_l2 &= PAGE_XN_4K_MASK;
NYX	0:85b3fd62ea1a	1547	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
NYX	0:85b3fd62ea1a	1548	}
NYX	0:85b3fd62ea1a	1549	else
NYX	0:85b3fd62ea1a	1550	{
NYX	0:85b3fd62ea1a	1551	*descriptor_l2 &= PAGE_XN_64K_MASK;
NYX	0:85b3fd62ea1a	1552	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
NYX	0:85b3fd62ea1a	1553	}
NYX	0:85b3fd62ea1a	1554	return 0;
NYX	0:85b3fd62ea1a	1555	}
NYX	0:85b3fd62ea1a	1556
NYX	0:85b3fd62ea1a	1557	/** \brief Set 4k/64k page domain
NYX	0:85b3fd62ea1a	1558
NYX	0:85b3fd62ea1a	1559	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1560	\param [in] domain Page domain
NYX	0:85b3fd62ea1a	1561
NYX	0:85b3fd62ea1a	1562	\return 0
NYX	0:85b3fd62ea1a	1563	*/
NYX	0:85b3fd62ea1a	1564	__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
NYX	0:85b3fd62ea1a	1565	{
NYX	0:85b3fd62ea1a	1566	*descriptor_l1 &= PAGE_DOMAIN_MASK;
NYX	0:85b3fd62ea1a	1567	*descriptor_l1 \|= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
NYX	0:85b3fd62ea1a	1568	return 0;
NYX	0:85b3fd62ea1a	1569	}
NYX	0:85b3fd62ea1a	1570
NYX	0:85b3fd62ea1a	1571	/** \brief Set 4k/64k page parity check
NYX	0:85b3fd62ea1a	1572
NYX	0:85b3fd62ea1a	1573	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1574	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
NYX	0:85b3fd62ea1a	1575
NYX	0:85b3fd62ea1a	1576	\return 0
NYX	0:85b3fd62ea1a	1577	*/
NYX	0:85b3fd62ea1a	1578	__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
NYX	0:85b3fd62ea1a	1579	{
NYX	0:85b3fd62ea1a	1580	*descriptor_l1 &= SECTION_P_MASK;
NYX	0:85b3fd62ea1a	1581	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
NYX	0:85b3fd62ea1a	1582	return 0;
NYX	0:85b3fd62ea1a	1583	}
NYX	0:85b3fd62ea1a	1584
NYX	0:85b3fd62ea1a	1585	/** \brief Set 4k/64k page access privileges
NYX	0:85b3fd62ea1a	1586
NYX	0:85b3fd62ea1a	1587	\param [out] descriptor_l2 L2 descriptor.
NYX	0:85b3fd62ea1a	1588	\param [in] user User Level Access: NO_ACCESS, RW, READ
NYX	0:85b3fd62ea1a	1589	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
NYX	0:85b3fd62ea1a	1590	\param [in] afe Access flag enable
NYX	0:85b3fd62ea1a	1591
NYX	0:85b3fd62ea1a	1592	\return 0
NYX	0:85b3fd62ea1a	1593	*/
NYX	0:85b3fd62ea1a	1594	__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
NYX	0:85b3fd62ea1a	1595	{
NYX	0:85b3fd62ea1a	1596	uint32_t ap = 0;
NYX	0:85b3fd62ea1a	1597
NYX	0:85b3fd62ea1a	1598	if (afe == 0) { //full access
NYX	0:85b3fd62ea1a	1599	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
NYX	0:85b3fd62ea1a	1600	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
NYX	0:85b3fd62ea1a	1601	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
NYX	0:85b3fd62ea1a	1602	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
NYX	0:85b3fd62ea1a	1603	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
NYX	0:85b3fd62ea1a	1604	else if ((priv == READ) && (user == READ)) { ap = 0x6; }
NYX	0:85b3fd62ea1a	1605	}
NYX	0:85b3fd62ea1a	1606
NYX	0:85b3fd62ea1a	1607	else { //Simplified access
NYX	0:85b3fd62ea1a	1608	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
NYX	0:85b3fd62ea1a	1609	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
NYX	0:85b3fd62ea1a	1610	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
NYX	0:85b3fd62ea1a	1611	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
NYX	0:85b3fd62ea1a	1612	}
NYX	0:85b3fd62ea1a	1613
NYX	0:85b3fd62ea1a	1614	*descriptor_l2 &= PAGE_AP_MASK;
NYX	0:85b3fd62ea1a	1615	*descriptor_l2 \|= (ap & 0x3) << PAGE_AP_SHIFT;
NYX	0:85b3fd62ea1a	1616	*descriptor_l2 \|= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
NYX	0:85b3fd62ea1a	1617
NYX	0:85b3fd62ea1a	1618	return 0;
NYX	0:85b3fd62ea1a	1619	}
NYX	0:85b3fd62ea1a	1620
NYX	0:85b3fd62ea1a	1621	/** \brief Set 4k/64k page shareability
NYX	0:85b3fd62ea1a	1622
NYX	0:85b3fd62ea1a	1623	\param [out] descriptor_l2 L2 descriptor.
NYX	0:85b3fd62ea1a	1624	\param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
NYX	0:85b3fd62ea1a	1625
NYX	0:85b3fd62ea1a	1626	\return 0
NYX	0:85b3fd62ea1a	1627	*/
NYX	0:85b3fd62ea1a	1628	__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
NYX	0:85b3fd62ea1a	1629	{
NYX	0:85b3fd62ea1a	1630	*descriptor_l2 &= PAGE_S_MASK;
NYX	0:85b3fd62ea1a	1631	*descriptor_l2 \|= ((s_bit & 0x1) << PAGE_S_SHIFT);
NYX	0:85b3fd62ea1a	1632	return 0;
NYX	0:85b3fd62ea1a	1633	}
NYX	0:85b3fd62ea1a	1634
NYX	0:85b3fd62ea1a	1635	/** \brief Set 4k/64k page Global attribute
NYX	0:85b3fd62ea1a	1636
NYX	0:85b3fd62ea1a	1637	\param [out] descriptor_l2 L2 descriptor.
NYX	0:85b3fd62ea1a	1638	\param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
NYX	0:85b3fd62ea1a	1639
NYX	0:85b3fd62ea1a	1640	\return 0
NYX	0:85b3fd62ea1a	1641	*/
NYX	0:85b3fd62ea1a	1642	__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
NYX	0:85b3fd62ea1a	1643	{
NYX	0:85b3fd62ea1a	1644	*descriptor_l2 &= PAGE_NG_MASK;
NYX	0:85b3fd62ea1a	1645	*descriptor_l2 \|= ((g_bit & 0x1) << PAGE_NG_SHIFT);
NYX	0:85b3fd62ea1a	1646	return 0;
NYX	0:85b3fd62ea1a	1647	}
NYX	0:85b3fd62ea1a	1648
NYX	0:85b3fd62ea1a	1649	/** \brief Set 4k/64k page Security attribute
NYX	0:85b3fd62ea1a	1650
NYX	0:85b3fd62ea1a	1651	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1652	\param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
NYX	0:85b3fd62ea1a	1653
NYX	0:85b3fd62ea1a	1654	\return 0
NYX	0:85b3fd62ea1a	1655	*/
NYX	0:85b3fd62ea1a	1656	__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
NYX	0:85b3fd62ea1a	1657	{
NYX	0:85b3fd62ea1a	1658	*descriptor_l1 &= PAGE_NS_MASK;
NYX	0:85b3fd62ea1a	1659	*descriptor_l1 \|= ((s_bit & 0x1) << PAGE_NS_SHIFT);
NYX	0:85b3fd62ea1a	1660	return 0;
NYX	0:85b3fd62ea1a	1661	}
NYX	0:85b3fd62ea1a	1662
NYX	0:85b3fd62ea1a	1663	/** \brief Set Section memory attributes
NYX	0:85b3fd62ea1a	1664
NYX	0:85b3fd62ea1a	1665	\param [out] descriptor_l1 L1 descriptor.
NYX	0:85b3fd62ea1a	1666	\param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
NYX	0:85b3fd62ea1a	1667	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
NYX	0:85b3fd62ea1a	1668	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
NYX	0:85b3fd62ea1a	1669
NYX	0:85b3fd62ea1a	1670	\return 0
NYX	0:85b3fd62ea1a	1671	*/
NYX	0:85b3fd62ea1a	1672	__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
NYX	0:85b3fd62ea1a	1673	{
NYX	0:85b3fd62ea1a	1674	*descriptor_l1 &= SECTION_TEXCB_MASK;
NYX	0:85b3fd62ea1a	1675
NYX	0:85b3fd62ea1a	1676	if (STRONGLY_ORDERED == mem)
NYX	0:85b3fd62ea1a	1677	{
NYX	0:85b3fd62ea1a	1678	return 0;
NYX	0:85b3fd62ea1a	1679	}
NYX	0:85b3fd62ea1a	1680	else if (SHARED_DEVICE == mem)
NYX	0:85b3fd62ea1a	1681	{
NYX	0:85b3fd62ea1a	1682	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
NYX	0:85b3fd62ea1a	1683	}
NYX	0:85b3fd62ea1a	1684	else if (NON_SHARED_DEVICE == mem)
NYX	0:85b3fd62ea1a	1685	{
NYX	0:85b3fd62ea1a	1686	*descriptor_l1 \|= (1 << SECTION_TEX1_SHIFT);
NYX	0:85b3fd62ea1a	1687	}
NYX	0:85b3fd62ea1a	1688	else if (NORMAL == mem)
NYX	0:85b3fd62ea1a	1689	{
NYX	0:85b3fd62ea1a	1690	*descriptor_l1 \|= 1 << SECTION_TEX2_SHIFT;
NYX	0:85b3fd62ea1a	1691	switch(inner)
NYX	0:85b3fd62ea1a	1692	{
NYX	0:85b3fd62ea1a	1693	case NON_CACHEABLE:
NYX	0:85b3fd62ea1a	1694	break;
NYX	0:85b3fd62ea1a	1695	case WB_WA:
NYX	0:85b3fd62ea1a	1696	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
NYX	0:85b3fd62ea1a	1697	break;
NYX	0:85b3fd62ea1a	1698	case WT:
NYX	0:85b3fd62ea1a	1699	*descriptor_l1 \|= 1 << SECTION_C_SHIFT;
NYX	0:85b3fd62ea1a	1700	break;
NYX	0:85b3fd62ea1a	1701	case WB_NO_WA:
NYX	0:85b3fd62ea1a	1702	*descriptor_l1 \|= (1 << SECTION_B_SHIFT) \| (1 << SECTION_C_SHIFT);
NYX	0:85b3fd62ea1a	1703	break;
NYX	0:85b3fd62ea1a	1704	}
NYX	0:85b3fd62ea1a	1705	switch(outer)
NYX	0:85b3fd62ea1a	1706	{
NYX	0:85b3fd62ea1a	1707	case NON_CACHEABLE:
NYX	0:85b3fd62ea1a	1708	break;
NYX	0:85b3fd62ea1a	1709	case WB_WA:
NYX	0:85b3fd62ea1a	1710	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT);
NYX	0:85b3fd62ea1a	1711	break;
NYX	0:85b3fd62ea1a	1712	case WT:
NYX	0:85b3fd62ea1a	1713	*descriptor_l1 \|= 1 << SECTION_TEX1_SHIFT;
NYX	0:85b3fd62ea1a	1714	break;
NYX	0:85b3fd62ea1a	1715	case WB_NO_WA:
NYX	0:85b3fd62ea1a	1716	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT) \| (1 << SECTION_TEX0_SHIFT);
NYX	0:85b3fd62ea1a	1717	break;
NYX	0:85b3fd62ea1a	1718	}
NYX	0:85b3fd62ea1a	1719	}
NYX	0:85b3fd62ea1a	1720	return 0;
NYX	0:85b3fd62ea1a	1721	}
NYX	0:85b3fd62ea1a	1722
NYX	0:85b3fd62ea1a	1723	/** \brief Set 4k/64k page memory attributes
NYX	0:85b3fd62ea1a	1724
NYX	0:85b3fd62ea1a	1725	\param [out] descriptor_l2 L2 descriptor.
NYX	0:85b3fd62ea1a	1726	\param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
NYX	0:85b3fd62ea1a	1727	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
NYX	0:85b3fd62ea1a	1728	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
NYX	0:85b3fd62ea1a	1729	\param [in] page Page size
NYX	0:85b3fd62ea1a	1730
NYX	0:85b3fd62ea1a	1731	\return 0
NYX	0:85b3fd62ea1a	1732	*/
NYX	0:85b3fd62ea1a	1733	__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
NYX	0:85b3fd62ea1a	1734	{
NYX	0:85b3fd62ea1a	1735	*descriptor_l2 &= PAGE_4K_TEXCB_MASK;
NYX	0:85b3fd62ea1a	1736
NYX	0:85b3fd62ea1a	1737	if (page == PAGE_64k)
NYX	0:85b3fd62ea1a	1738	{
NYX	0:85b3fd62ea1a	1739	//same as section
NYX	0:85b3fd62ea1a	1740	MMU_MemorySection(descriptor_l2, mem, outer, inner);
NYX	0:85b3fd62ea1a	1741	}
NYX	0:85b3fd62ea1a	1742	else
NYX	0:85b3fd62ea1a	1743	{
NYX	0:85b3fd62ea1a	1744	if (STRONGLY_ORDERED == mem)
NYX	0:85b3fd62ea1a	1745	{
NYX	0:85b3fd62ea1a	1746	return 0;
NYX	0:85b3fd62ea1a	1747	}
NYX	0:85b3fd62ea1a	1748	else if (SHARED_DEVICE == mem)
NYX	0:85b3fd62ea1a	1749	{
NYX	0:85b3fd62ea1a	1750	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
NYX	0:85b3fd62ea1a	1751	}
NYX	0:85b3fd62ea1a	1752	else if (NON_SHARED_DEVICE == mem)
NYX	0:85b3fd62ea1a	1753	{
NYX	0:85b3fd62ea1a	1754	*descriptor_l2 \|= (1 << PAGE_4K_TEX1_SHIFT);
NYX	0:85b3fd62ea1a	1755	}
NYX	0:85b3fd62ea1a	1756	else if (NORMAL == mem)
NYX	0:85b3fd62ea1a	1757	{
NYX	0:85b3fd62ea1a	1758	*descriptor_l2 \|= 1 << PAGE_4K_TEX2_SHIFT;
NYX	0:85b3fd62ea1a	1759	switch(inner)
NYX	0:85b3fd62ea1a	1760	{
NYX	0:85b3fd62ea1a	1761	case NON_CACHEABLE:
NYX	0:85b3fd62ea1a	1762	break;
NYX	0:85b3fd62ea1a	1763	case WB_WA:
NYX	0:85b3fd62ea1a	1764	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
NYX	0:85b3fd62ea1a	1765	break;
NYX	0:85b3fd62ea1a	1766	case WT:
NYX	0:85b3fd62ea1a	1767	*descriptor_l2 \|= 1 << PAGE_4K_C_SHIFT;
NYX	0:85b3fd62ea1a	1768	break;
NYX	0:85b3fd62ea1a	1769	case WB_NO_WA:
NYX	0:85b3fd62ea1a	1770	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT) \| (1 << PAGE_4K_C_SHIFT);
NYX	0:85b3fd62ea1a	1771	break;
NYX	0:85b3fd62ea1a	1772	}
NYX	0:85b3fd62ea1a	1773	switch(outer)
NYX	0:85b3fd62ea1a	1774	{
NYX	0:85b3fd62ea1a	1775	case NON_CACHEABLE:
NYX	0:85b3fd62ea1a	1776	break;
NYX	0:85b3fd62ea1a	1777	case WB_WA:
NYX	0:85b3fd62ea1a	1778	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT);
NYX	0:85b3fd62ea1a	1779	break;
NYX	0:85b3fd62ea1a	1780	case WT:
NYX	0:85b3fd62ea1a	1781	*descriptor_l2 \|= 1 << PAGE_4K_TEX1_SHIFT;
NYX	0:85b3fd62ea1a	1782	break;
NYX	0:85b3fd62ea1a	1783	case WB_NO_WA:
NYX	0:85b3fd62ea1a	1784	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT) \| (1 << PAGE_4K_TEX0_SHIFT);
NYX	0:85b3fd62ea1a	1785	break;
NYX	0:85b3fd62ea1a	1786	}
NYX	0:85b3fd62ea1a	1787	}
NYX	0:85b3fd62ea1a	1788	}
NYX	0:85b3fd62ea1a	1789
NYX	0:85b3fd62ea1a	1790	return 0;
NYX	0:85b3fd62ea1a	1791	}
NYX	0:85b3fd62ea1a	1792
NYX	0:85b3fd62ea1a	1793	/** \brief Create a L1 section descriptor
NYX	0:85b3fd62ea1a	1794
NYX	0:85b3fd62ea1a	1795	\param [out] descriptor L1 descriptor
NYX	0:85b3fd62ea1a	1796	\param [in] reg Section attributes
NYX	0:85b3fd62ea1a	1797
NYX	0:85b3fd62ea1a	1798	\return 0
NYX	0:85b3fd62ea1a	1799	*/
NYX	0:85b3fd62ea1a	1800	__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
NYX	0:85b3fd62ea1a	1801	{
NYX	0:85b3fd62ea1a	1802	*descriptor = 0;
NYX	0:85b3fd62ea1a	1803
NYX	0:85b3fd62ea1a	1804	MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
NYX	0:85b3fd62ea1a	1805	MMU_XNSection(descriptor,reg.xn_t);
NYX	0:85b3fd62ea1a	1806	MMU_DomainSection(descriptor, reg.domain);
NYX	0:85b3fd62ea1a	1807	MMU_PSection(descriptor, reg.e_t);
NYX	0:85b3fd62ea1a	1808	MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
NYX	0:85b3fd62ea1a	1809	MMU_SharedSection(descriptor,reg.sh_t);
NYX	0:85b3fd62ea1a	1810	MMU_GlobalSection(descriptor,reg.g_t);
NYX	0:85b3fd62ea1a	1811	MMU_SecureSection(descriptor,reg.sec_t);
NYX	0:85b3fd62ea1a	1812	*descriptor &= SECTION_MASK;
NYX	0:85b3fd62ea1a	1813	*descriptor \|= SECTION_DESCRIPTOR;
NYX	0:85b3fd62ea1a	1814
NYX	0:85b3fd62ea1a	1815	return 0;
NYX	0:85b3fd62ea1a	1816	}
NYX	0:85b3fd62ea1a	1817
NYX	0:85b3fd62ea1a	1818
NYX	0:85b3fd62ea1a	1819	/** \brief Create a L1 and L2 4k/64k page descriptor
NYX	0:85b3fd62ea1a	1820
NYX	0:85b3fd62ea1a	1821	\param [out] descriptor L1 descriptor
NYX	0:85b3fd62ea1a	1822	\param [out] descriptor2 L2 descriptor
NYX	0:85b3fd62ea1a	1823	\param [in] reg 4k/64k page attributes
NYX	0:85b3fd62ea1a	1824
NYX	0:85b3fd62ea1a	1825	\return 0
NYX	0:85b3fd62ea1a	1826	*/
NYX	0:85b3fd62ea1a	1827	__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t descriptor, uint32_t descriptor2, mmu_region_attributes_Type reg)
NYX	0:85b3fd62ea1a	1828	{
NYX	0:85b3fd62ea1a	1829	*descriptor = 0;
NYX	0:85b3fd62ea1a	1830	*descriptor2 = 0;
NYX	0:85b3fd62ea1a	1831
NYX	0:85b3fd62ea1a	1832	switch (reg.rg_t)
NYX	0:85b3fd62ea1a	1833	{
NYX	0:85b3fd62ea1a	1834	case PAGE_4k:
NYX	0:85b3fd62ea1a	1835	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
NYX	0:85b3fd62ea1a	1836	MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
NYX	0:85b3fd62ea1a	1837	MMU_DomainPage(descriptor, reg.domain);
NYX	0:85b3fd62ea1a	1838	MMU_PPage(descriptor, reg.e_t);
NYX	0:85b3fd62ea1a	1839	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
NYX	0:85b3fd62ea1a	1840	MMU_SharedPage(descriptor2,reg.sh_t);
NYX	0:85b3fd62ea1a	1841	MMU_GlobalPage(descriptor2,reg.g_t);
NYX	0:85b3fd62ea1a	1842	MMU_SecurePage(descriptor,reg.sec_t);
NYX	0:85b3fd62ea1a	1843	*descriptor &= PAGE_L1_MASK;
NYX	0:85b3fd62ea1a	1844	*descriptor \|= PAGE_L1_DESCRIPTOR;
NYX	0:85b3fd62ea1a	1845	*descriptor2 &= PAGE_L2_4K_MASK;
NYX	0:85b3fd62ea1a	1846	*descriptor2 \|= PAGE_L2_4K_DESC;
NYX	0:85b3fd62ea1a	1847	break;
NYX	0:85b3fd62ea1a	1848
NYX	0:85b3fd62ea1a	1849	case PAGE_64k:
NYX	0:85b3fd62ea1a	1850	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
NYX	0:85b3fd62ea1a	1851	MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
NYX	0:85b3fd62ea1a	1852	MMU_DomainPage(descriptor, reg.domain);
NYX	0:85b3fd62ea1a	1853	MMU_PPage(descriptor, reg.e_t);
NYX	0:85b3fd62ea1a	1854	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
NYX	0:85b3fd62ea1a	1855	MMU_SharedPage(descriptor2,reg.sh_t);
NYX	0:85b3fd62ea1a	1856	MMU_GlobalPage(descriptor2,reg.g_t);
NYX	0:85b3fd62ea1a	1857	MMU_SecurePage(descriptor,reg.sec_t);
NYX	0:85b3fd62ea1a	1858	*descriptor &= PAGE_L1_MASK;
NYX	0:85b3fd62ea1a	1859	*descriptor \|= PAGE_L1_DESCRIPTOR;
NYX	0:85b3fd62ea1a	1860	*descriptor2 &= PAGE_L2_64K_MASK;
NYX	0:85b3fd62ea1a	1861	*descriptor2 \|= PAGE_L2_64K_DESC;
NYX	0:85b3fd62ea1a	1862	break;
NYX	0:85b3fd62ea1a	1863
NYX	0:85b3fd62ea1a	1864	case SECTION:
NYX	0:85b3fd62ea1a	1865	//error
NYX	0:85b3fd62ea1a	1866	break;
NYX	0:85b3fd62ea1a	1867	}
NYX	0:85b3fd62ea1a	1868
NYX	0:85b3fd62ea1a	1869	return 0;
NYX	0:85b3fd62ea1a	1870	}
NYX	0:85b3fd62ea1a	1871
NYX	0:85b3fd62ea1a	1872	/** \brief Create a 1MB Section
NYX	0:85b3fd62ea1a	1873
NYX	0:85b3fd62ea1a	1874	\param [in] ttb Translation table base address
NYX	0:85b3fd62ea1a	1875	\param [in] base_address Section base address
NYX	0:85b3fd62ea1a	1876	\param [in] count Number of sections to create
NYX	0:85b3fd62ea1a	1877	\param [in] descriptor_l1 L1 descriptor (region attributes)
NYX	0:85b3fd62ea1a	1878
NYX	0:85b3fd62ea1a	1879	*/
NYX	0:85b3fd62ea1a	1880	__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
NYX	0:85b3fd62ea1a	1881	{
NYX	0:85b3fd62ea1a	1882	uint32_t offset;
NYX	0:85b3fd62ea1a	1883	uint32_t entry;
NYX	0:85b3fd62ea1a	1884	uint32_t i;
NYX	0:85b3fd62ea1a	1885
NYX	0:85b3fd62ea1a	1886	offset = base_address >> 20;
NYX	0:85b3fd62ea1a	1887	entry = (base_address & 0xFFF00000) \| descriptor_l1;
NYX	0:85b3fd62ea1a	1888
NYX	0:85b3fd62ea1a	1889	//4 bytes aligned
NYX	0:85b3fd62ea1a	1890	ttb = ttb + offset;
NYX	0:85b3fd62ea1a	1891
NYX	0:85b3fd62ea1a	1892	for (i = 0; i < count; i++ )
NYX	0:85b3fd62ea1a	1893	{
NYX	0:85b3fd62ea1a	1894	//4 bytes aligned
NYX	0:85b3fd62ea1a	1895	*ttb++ = entry;
NYX	0:85b3fd62ea1a	1896	entry += OFFSET_1M;
NYX	0:85b3fd62ea1a	1897	}
NYX	0:85b3fd62ea1a	1898	}
NYX	0:85b3fd62ea1a	1899
NYX	0:85b3fd62ea1a	1900	/** \brief Create a 4k page entry
NYX	0:85b3fd62ea1a	1901
NYX	0:85b3fd62ea1a	1902	\param [in] ttb L1 table base address
NYX	0:85b3fd62ea1a	1903	\param [in] base_address 4k base address
NYX	0:85b3fd62ea1a	1904	\param [in] count Number of 4k pages to create
NYX	0:85b3fd62ea1a	1905	\param [in] descriptor_l1 L1 descriptor (region attributes)
NYX	0:85b3fd62ea1a	1906	\param [in] ttb_l2 L2 table base address
NYX	0:85b3fd62ea1a	1907	\param [in] descriptor_l2 L2 descriptor (region attributes)
NYX	0:85b3fd62ea1a	1908
NYX	0:85b3fd62ea1a	1909	*/
NYX	0:85b3fd62ea1a	1910	__STATIC_INLINE void MMU_TTPage4k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
NYX	0:85b3fd62ea1a	1911	{
NYX	0:85b3fd62ea1a	1912
NYX	0:85b3fd62ea1a	1913	uint32_t offset, offset2;
NYX	0:85b3fd62ea1a	1914	uint32_t entry, entry2;
NYX	0:85b3fd62ea1a	1915	uint32_t i;
NYX	0:85b3fd62ea1a	1916
NYX	0:85b3fd62ea1a	1917	offset = base_address >> 20;
NYX	0:85b3fd62ea1a	1918	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
NYX	0:85b3fd62ea1a	1919
NYX	0:85b3fd62ea1a	1920	//4 bytes aligned
NYX	0:85b3fd62ea1a	1921	ttb += offset;
NYX	0:85b3fd62ea1a	1922	//create l1_entry
NYX	0:85b3fd62ea1a	1923	*ttb = entry;
NYX	0:85b3fd62ea1a	1924
NYX	0:85b3fd62ea1a	1925	offset2 = (base_address & 0xff000) >> 12;
NYX	0:85b3fd62ea1a	1926	ttb_l2 += offset2;
NYX	0:85b3fd62ea1a	1927	entry2 = (base_address & 0xFFFFF000) \| descriptor_l2;
NYX	0:85b3fd62ea1a	1928	for (i = 0; i < count; i++ )
NYX	0:85b3fd62ea1a	1929	{
NYX	0:85b3fd62ea1a	1930	//4 bytes aligned
NYX	0:85b3fd62ea1a	1931	*ttb_l2++ = entry2;
NYX	0:85b3fd62ea1a	1932	entry2 += OFFSET_4K;
NYX	0:85b3fd62ea1a	1933	}
NYX	0:85b3fd62ea1a	1934	}
NYX	0:85b3fd62ea1a	1935
NYX	0:85b3fd62ea1a	1936	/** \brief Create a 64k page entry
NYX	0:85b3fd62ea1a	1937
NYX	0:85b3fd62ea1a	1938	\param [in] ttb L1 table base address
NYX	0:85b3fd62ea1a	1939	\param [in] base_address 64k base address
NYX	0:85b3fd62ea1a	1940	\param [in] count Number of 64k pages to create
NYX	0:85b3fd62ea1a	1941	\param [in] descriptor_l1 L1 descriptor (region attributes)
NYX	0:85b3fd62ea1a	1942	\param [in] ttb_l2 L2 table base address
NYX	0:85b3fd62ea1a	1943	\param [in] descriptor_l2 L2 descriptor (region attributes)
NYX	0:85b3fd62ea1a	1944
NYX	0:85b3fd62ea1a	1945	*/
NYX	0:85b3fd62ea1a	1946	__STATIC_INLINE void MMU_TTPage64k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
NYX	0:85b3fd62ea1a	1947	{
NYX	0:85b3fd62ea1a	1948	uint32_t offset, offset2;
NYX	0:85b3fd62ea1a	1949	uint32_t entry, entry2;
NYX	0:85b3fd62ea1a	1950	uint32_t i,j;
NYX	0:85b3fd62ea1a	1951
NYX	0:85b3fd62ea1a	1952
NYX	0:85b3fd62ea1a	1953	offset = base_address >> 20;
NYX	0:85b3fd62ea1a	1954	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
NYX	0:85b3fd62ea1a	1955
NYX	0:85b3fd62ea1a	1956	//4 bytes aligned
NYX	0:85b3fd62ea1a	1957	ttb += offset;
NYX	0:85b3fd62ea1a	1958	//create l1_entry
NYX	0:85b3fd62ea1a	1959	*ttb = entry;
NYX	0:85b3fd62ea1a	1960
NYX	0:85b3fd62ea1a	1961	offset2 = (base_address & 0xff000) >> 12;
NYX	0:85b3fd62ea1a	1962	ttb_l2 += offset2;
NYX	0:85b3fd62ea1a	1963	entry2 = (base_address & 0xFFFF0000) \| descriptor_l2;
NYX	0:85b3fd62ea1a	1964	for (i = 0; i < count; i++ )
NYX	0:85b3fd62ea1a	1965	{
NYX	0:85b3fd62ea1a	1966	//create 16 entries
NYX	0:85b3fd62ea1a	1967	for (j = 0; j < 16; j++)
NYX	0:85b3fd62ea1a	1968	{
NYX	0:85b3fd62ea1a	1969	//4 bytes aligned
NYX	0:85b3fd62ea1a	1970	*ttb_l2++ = entry2;
NYX	0:85b3fd62ea1a	1971	}
NYX	0:85b3fd62ea1a	1972	entry2 += OFFSET_64K;
NYX	0:85b3fd62ea1a	1973	}
NYX	0:85b3fd62ea1a	1974	}
NYX	0:85b3fd62ea1a	1975
NYX	0:85b3fd62ea1a	1976	/** \brief Enable MMU
NYX	0:85b3fd62ea1a	1977
NYX	0:85b3fd62ea1a	1978	Enable MMU
NYX	0:85b3fd62ea1a	1979	*/
NYX	0:85b3fd62ea1a	1980	__STATIC_INLINE void MMU_Enable(void) {
NYX	0:85b3fd62ea1a	1981	// Set M bit 0 to enable the MMU
NYX	0:85b3fd62ea1a	1982	// Set AFE bit to enable simplified access permissions model
NYX	0:85b3fd62ea1a	1983	// Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
NYX	0:85b3fd62ea1a	1984	__set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) \| 1 \| (1 << 29));
NYX	0:85b3fd62ea1a	1985	__ISB();
NYX	0:85b3fd62ea1a	1986	}
NYX	0:85b3fd62ea1a	1987
NYX	0:85b3fd62ea1a	1988	/** \brief Disable MMU
NYX	0:85b3fd62ea1a	1989
NYX	0:85b3fd62ea1a	1990	Disable MMU
NYX	0:85b3fd62ea1a	1991	*/
NYX	0:85b3fd62ea1a	1992	__STATIC_INLINE void MMU_Disable(void) {
NYX	0:85b3fd62ea1a	1993	// Clear M bit 0 to disable the MMU
NYX	0:85b3fd62ea1a	1994	__set_SCTLR( __get_SCTLR() & ~1);
NYX	0:85b3fd62ea1a	1995	__ISB();
NYX	0:85b3fd62ea1a	1996	}
NYX	0:85b3fd62ea1a	1997
NYX	0:85b3fd62ea1a	1998	/** \brief Invalidate entire unified TLB
NYX	0:85b3fd62ea1a	1999
NYX	0:85b3fd62ea1a	2000	TLBIALL. Invalidate entire unified TLB
NYX	0:85b3fd62ea1a	2001	*/
NYX	0:85b3fd62ea1a	2002
NYX	0:85b3fd62ea1a	2003	__STATIC_INLINE void MMU_InvalidateTLB(void) {
NYX	0:85b3fd62ea1a	2004	__set_TLBIALL(0);
NYX	0:85b3fd62ea1a	2005	__DSB(); //ensure completion of the invalidation
NYX	0:85b3fd62ea1a	2006	__ISB(); //ensure instruction fetch path sees new state
NYX	0:85b3fd62ea1a	2007	}
NYX	0:85b3fd62ea1a	2008
NYX	0:85b3fd62ea1a	2009
NYX	0:85b3fd62ea1a	2010	#ifdef __cplusplus
NYX	0:85b3fd62ea1a	2011	}
NYX	0:85b3fd62ea1a	2012	#endif
NYX	0:85b3fd62ea1a	2013
NYX	0:85b3fd62ea1a	2014	#endif /* __CORE_CA_H_DEPENDANT */
NYX	0:85b3fd62ea1a	2015
NYX	0:85b3fd62ea1a	2016	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	16 Mar 2020
Imports:	73
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	2

cmsis/core_ca.h@0:85b3fd62ea1a, 2020-03-16 (annotated)

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