Nordic stack and drivers for the mbed BLE API
Fork of nRF51822 by
TARGET_MCU_NRF51822/sdk/source/drivers_nrf/hal/nrf_gpio.h@640:c90ae1400bf2, 2016-09-14 (annotated)
- Committer:
- Vincent Coubard
- Date:
- Wed Sep 14 14:39:43 2016 +0100
- Revision:
- 640:c90ae1400bf2
Sync with bdab10dc0f90748b6989c8b577771bb403ca6bd8 from ARMmbed/mbed-os.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Vincent Coubard |
640:c90ae1400bf2 | 1 | /* |
Vincent Coubard |
640:c90ae1400bf2 | 2 | * Copyright (c) Nordic Semiconductor ASA |
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640:c90ae1400bf2 | 3 | * All rights reserved. |
Vincent Coubard |
640:c90ae1400bf2 | 4 | * |
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640:c90ae1400bf2 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
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640:c90ae1400bf2 | 6 | * are permitted provided that the following conditions are met: |
Vincent Coubard |
640:c90ae1400bf2 | 7 | * |
Vincent Coubard |
640:c90ae1400bf2 | 8 | * 1. Redistributions of source code must retain the above copyright notice, this |
Vincent Coubard |
640:c90ae1400bf2 | 9 | * list of conditions and the following disclaimer. |
Vincent Coubard |
640:c90ae1400bf2 | 10 | * |
Vincent Coubard |
640:c90ae1400bf2 | 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, this |
Vincent Coubard |
640:c90ae1400bf2 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
Vincent Coubard |
640:c90ae1400bf2 | 13 | * other materials provided with the distribution. |
Vincent Coubard |
640:c90ae1400bf2 | 14 | * |
Vincent Coubard |
640:c90ae1400bf2 | 15 | * 3. Neither the name of Nordic Semiconductor ASA nor the names of other |
Vincent Coubard |
640:c90ae1400bf2 | 16 | * contributors to this software may be used to endorse or promote products |
Vincent Coubard |
640:c90ae1400bf2 | 17 | * derived from this software without specific prior written permission. |
Vincent Coubard |
640:c90ae1400bf2 | 18 | * |
Vincent Coubard |
640:c90ae1400bf2 | 19 | * |
Vincent Coubard |
640:c90ae1400bf2 | 20 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
Vincent Coubard |
640:c90ae1400bf2 | 21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
Vincent Coubard |
640:c90ae1400bf2 | 22 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Vincent Coubard |
640:c90ae1400bf2 | 23 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
Vincent Coubard |
640:c90ae1400bf2 | 24 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
Vincent Coubard |
640:c90ae1400bf2 | 25 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
Vincent Coubard |
640:c90ae1400bf2 | 26 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
Vincent Coubard |
640:c90ae1400bf2 | 27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
Vincent Coubard |
640:c90ae1400bf2 | 28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
Vincent Coubard |
640:c90ae1400bf2 | 29 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Vincent Coubard |
640:c90ae1400bf2 | 30 | * |
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640:c90ae1400bf2 | 31 | */ |
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640:c90ae1400bf2 | 32 | #ifndef NRF_GPIO_H__ |
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640:c90ae1400bf2 | 33 | #define NRF_GPIO_H__ |
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640:c90ae1400bf2 | 34 | |
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640:c90ae1400bf2 | 35 | #include "nrf.h" |
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640:c90ae1400bf2 | 36 | #include <stdbool.h> |
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640:c90ae1400bf2 | 37 | |
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640:c90ae1400bf2 | 38 | /** |
Vincent Coubard |
640:c90ae1400bf2 | 39 | * @defgroup nrf_gpio GPIO abstraction |
Vincent Coubard |
640:c90ae1400bf2 | 40 | * @{ |
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640:c90ae1400bf2 | 41 | * @ingroup nrf_drivers |
Vincent Coubard |
640:c90ae1400bf2 | 42 | * @brief GPIO pin abstraction and port abstraction for reading and writing byte-wise to GPIO ports. |
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640:c90ae1400bf2 | 43 | * |
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640:c90ae1400bf2 | 44 | * Here, the GPIO ports are defined as follows: |
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640:c90ae1400bf2 | 45 | * - Port 0 -> pin 0-7 |
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640:c90ae1400bf2 | 46 | * - Port 1 -> pin 8-15 |
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640:c90ae1400bf2 | 47 | * - Port 2 -> pin 16-23 |
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640:c90ae1400bf2 | 48 | * - Port 3 -> pin 24-31 |
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640:c90ae1400bf2 | 49 | */ |
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640:c90ae1400bf2 | 50 | |
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640:c90ae1400bf2 | 51 | #define NUMBER_OF_PINS 32 |
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640:c90ae1400bf2 | 52 | |
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640:c90ae1400bf2 | 53 | /** |
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640:c90ae1400bf2 | 54 | * @brief Enumerator used for selecting between port 0 - 3. |
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640:c90ae1400bf2 | 55 | */ |
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640:c90ae1400bf2 | 56 | typedef enum |
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640:c90ae1400bf2 | 57 | { |
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640:c90ae1400bf2 | 58 | NRF_GPIO_PORT_SELECT_PORT0 = 0, ///< Port 0 (GPIO pin 0-7) |
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640:c90ae1400bf2 | 59 | NRF_GPIO_PORT_SELECT_PORT1, ///< Port 1 (GPIO pin 8-15) |
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640:c90ae1400bf2 | 60 | NRF_GPIO_PORT_SELECT_PORT2, ///< Port 2 (GPIO pin 16-23) |
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640:c90ae1400bf2 | 61 | NRF_GPIO_PORT_SELECT_PORT3, ///< Port 3 (GPIO pin 24-31) |
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640:c90ae1400bf2 | 62 | } nrf_gpio_port_select_t; |
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640:c90ae1400bf2 | 63 | |
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640:c90ae1400bf2 | 64 | /** |
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640:c90ae1400bf2 | 65 | * @brief Enumerator used for setting the direction of a GPIO port. |
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640:c90ae1400bf2 | 66 | */ |
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640:c90ae1400bf2 | 67 | typedef enum |
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640:c90ae1400bf2 | 68 | { |
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640:c90ae1400bf2 | 69 | NRF_GPIO_PORT_DIR_OUTPUT, ///< Output |
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640:c90ae1400bf2 | 70 | NRF_GPIO_PORT_DIR_INPUT ///< Input |
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640:c90ae1400bf2 | 71 | } nrf_gpio_port_dir_t; |
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640:c90ae1400bf2 | 72 | |
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640:c90ae1400bf2 | 73 | /** |
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640:c90ae1400bf2 | 74 | * @brief Pin direction definitions. |
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640:c90ae1400bf2 | 75 | */ |
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640:c90ae1400bf2 | 76 | typedef enum |
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640:c90ae1400bf2 | 77 | { |
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640:c90ae1400bf2 | 78 | NRF_GPIO_PIN_DIR_INPUT = GPIO_PIN_CNF_DIR_Input, ///< Input |
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640:c90ae1400bf2 | 79 | NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output ///< Output |
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640:c90ae1400bf2 | 80 | } nrf_gpio_pin_dir_t; |
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640:c90ae1400bf2 | 81 | |
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640:c90ae1400bf2 | 82 | /** |
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640:c90ae1400bf2 | 83 | * @brief Connection of input buffer |
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640:c90ae1400bf2 | 84 | */ |
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640:c90ae1400bf2 | 85 | typedef enum |
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640:c90ae1400bf2 | 86 | { |
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640:c90ae1400bf2 | 87 | NRF_GPIO_PIN_INPUT_CONNECT = GPIO_PIN_CNF_INPUT_Connect, ///< Connect input buffer |
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640:c90ae1400bf2 | 88 | NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer |
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640:c90ae1400bf2 | 89 | } nrf_gpio_pin_input_t; |
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640:c90ae1400bf2 | 90 | |
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640:c90ae1400bf2 | 91 | /** |
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640:c90ae1400bf2 | 92 | * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration |
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640:c90ae1400bf2 | 93 | */ |
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640:c90ae1400bf2 | 94 | typedef enum |
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640:c90ae1400bf2 | 95 | { |
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640:c90ae1400bf2 | 96 | NRF_GPIO_PIN_NOPULL = GPIO_PIN_CNF_PULL_Disabled, ///< Pin pullup resistor disabled |
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640:c90ae1400bf2 | 97 | NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown, ///< Pin pulldown resistor enabled |
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640:c90ae1400bf2 | 98 | NRF_GPIO_PIN_PULLUP = GPIO_PIN_CNF_PULL_Pullup, ///< Pin pullup resistor enabled |
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640:c90ae1400bf2 | 99 | } nrf_gpio_pin_pull_t; |
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640:c90ae1400bf2 | 100 | |
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640:c90ae1400bf2 | 101 | /** |
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640:c90ae1400bf2 | 102 | * @brief Enumerator used for selecting output drive mode |
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640:c90ae1400bf2 | 103 | */ |
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640:c90ae1400bf2 | 104 | typedef enum |
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640:c90ae1400bf2 | 105 | { |
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640:c90ae1400bf2 | 106 | NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1' |
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640:c90ae1400bf2 | 107 | NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High drive '0', standard '1' |
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640:c90ae1400bf2 | 108 | NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high drive '1' |
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640:c90ae1400bf2 | 109 | NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high 'drive '1'' |
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640:c90ae1400bf2 | 110 | NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1' |
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640:c90ae1400bf2 | 111 | NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high drive '1' |
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640:c90ae1400bf2 | 112 | NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0'. disconnect '1' |
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640:c90ae1400bf2 | 113 | NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High drive '0', disconnect '1' |
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640:c90ae1400bf2 | 114 | } nrf_gpio_pin_drive_t; |
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640:c90ae1400bf2 | 115 | |
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640:c90ae1400bf2 | 116 | /** |
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640:c90ae1400bf2 | 117 | * @brief Enumerator used for selecting the pin to sense high or low level on the pin input. |
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640:c90ae1400bf2 | 118 | */ |
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640:c90ae1400bf2 | 119 | typedef enum |
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640:c90ae1400bf2 | 120 | { |
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640:c90ae1400bf2 | 121 | NRF_GPIO_PIN_NOSENSE = GPIO_PIN_CNF_SENSE_Disabled, ///< Pin sense level disabled. |
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640:c90ae1400bf2 | 122 | NRF_GPIO_PIN_SENSE_LOW = GPIO_PIN_CNF_SENSE_Low, ///< Pin sense low level. |
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640:c90ae1400bf2 | 123 | NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High, ///< Pin sense high level. |
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640:c90ae1400bf2 | 124 | } nrf_gpio_pin_sense_t; |
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640:c90ae1400bf2 | 125 | |
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640:c90ae1400bf2 | 126 | |
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640:c90ae1400bf2 | 127 | /** |
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640:c90ae1400bf2 | 128 | * @brief Function for configuring the GPIO pin range as outputs with normal drive strength. |
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640:c90ae1400bf2 | 129 | * This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). |
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640:c90ae1400bf2 | 130 | * |
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640:c90ae1400bf2 | 131 | * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30) |
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640:c90ae1400bf2 | 132 | * |
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640:c90ae1400bf2 | 133 | * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30) |
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640:c90ae1400bf2 | 134 | * |
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640:c90ae1400bf2 | 135 | * @note For configuring only one pin as output use @ref nrf_gpio_cfg_output |
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640:c90ae1400bf2 | 136 | * Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output. |
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640:c90ae1400bf2 | 137 | */ |
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640:c90ae1400bf2 | 138 | __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end); |
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640:c90ae1400bf2 | 139 | |
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640:c90ae1400bf2 | 140 | /** |
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640:c90ae1400bf2 | 141 | * @brief Function for configuring the GPIO pin range as inputs with given initial value set, hiding inner details. |
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640:c90ae1400bf2 | 142 | * This function can be used to configure pin range as simple input. |
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640:c90ae1400bf2 | 143 | * |
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640:c90ae1400bf2 | 144 | * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30) |
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640:c90ae1400bf2 | 145 | * |
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640:c90ae1400bf2 | 146 | * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30) |
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640:c90ae1400bf2 | 147 | * |
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640:c90ae1400bf2 | 148 | * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high) |
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640:c90ae1400bf2 | 149 | * |
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640:c90ae1400bf2 | 150 | * @note For configuring only one pin as input use @ref nrf_gpio_cfg_input |
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640:c90ae1400bf2 | 151 | * Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable |
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640:c90ae1400bf2 | 152 | */ |
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640:c90ae1400bf2 | 153 | __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config); |
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640:c90ae1400bf2 | 154 | |
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640:c90ae1400bf2 | 155 | /** |
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640:c90ae1400bf2 | 156 | * @brief Pin configuration function |
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640:c90ae1400bf2 | 157 | * |
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640:c90ae1400bf2 | 158 | * The main pin configuration function. |
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640:c90ae1400bf2 | 159 | * This function allows to set any aspect in PIN_CNF register. |
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640:c90ae1400bf2 | 160 | * @param pin_number Specifies the pin number (allowed values 0-31). |
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640:c90ae1400bf2 | 161 | * @param dir Pin direction |
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640:c90ae1400bf2 | 162 | * @param input Connect or disconnect input buffer |
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640:c90ae1400bf2 | 163 | * @param pull Pull configuration |
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640:c90ae1400bf2 | 164 | * @param drive Drive configuration |
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640:c90ae1400bf2 | 165 | * @param sense Pin sensing mechanism |
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640:c90ae1400bf2 | 166 | */ |
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640:c90ae1400bf2 | 167 | __STATIC_INLINE void nrf_gpio_cfg( |
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640:c90ae1400bf2 | 168 | uint32_t pin_number, |
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640:c90ae1400bf2 | 169 | nrf_gpio_pin_dir_t dir, |
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640:c90ae1400bf2 | 170 | nrf_gpio_pin_input_t input, |
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640:c90ae1400bf2 | 171 | nrf_gpio_pin_pull_t pull, |
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640:c90ae1400bf2 | 172 | nrf_gpio_pin_drive_t drive, |
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640:c90ae1400bf2 | 173 | nrf_gpio_pin_sense_t sense); |
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640:c90ae1400bf2 | 174 | |
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640:c90ae1400bf2 | 175 | /** |
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640:c90ae1400bf2 | 176 | * @brief Function for configuring the given GPIO pin number as output with given initial value set, hiding inner details. |
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640:c90ae1400bf2 | 177 | * This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). |
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640:c90ae1400bf2 | 178 | * |
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640:c90ae1400bf2 | 179 | * @param pin_number specifies the pin number (allowed values 0-31) |
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640:c90ae1400bf2 | 180 | * |
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640:c90ae1400bf2 | 181 | * @note Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output. |
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640:c90ae1400bf2 | 182 | */ |
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640:c90ae1400bf2 | 183 | __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number); |
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640:c90ae1400bf2 | 184 | |
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640:c90ae1400bf2 | 185 | /** |
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640:c90ae1400bf2 | 186 | * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details. |
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640:c90ae1400bf2 | 187 | * This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). |
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640:c90ae1400bf2 | 188 | * |
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640:c90ae1400bf2 | 189 | * @param pin_number Specifies the pin number (allowed values 0-30). |
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640:c90ae1400bf2 | 190 | * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high). |
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640:c90ae1400bf2 | 191 | * |
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640:c90ae1400bf2 | 192 | * @note Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable |
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640:c90ae1400bf2 | 193 | */ |
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640:c90ae1400bf2 | 194 | __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config); |
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640:c90ae1400bf2 | 195 | |
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640:c90ae1400bf2 | 196 | /** |
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640:c90ae1400bf2 | 197 | * @brief Function for reseting pin configuration to its default state. |
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640:c90ae1400bf2 | 198 | * |
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640:c90ae1400bf2 | 199 | * @param pin_number Specifies the pin number (allowed values 0-31). |
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640:c90ae1400bf2 | 200 | */ |
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640:c90ae1400bf2 | 201 | __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number); |
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640:c90ae1400bf2 | 202 | |
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640:c90ae1400bf2 | 203 | /** |
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640:c90ae1400bf2 | 204 | * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected. |
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640:c90ae1400bf2 | 205 | * |
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640:c90ae1400bf2 | 206 | * @param pin_number Specifies the pin number (allowed values 0-31). |
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640:c90ae1400bf2 | 207 | * |
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640:c90ae1400bf2 | 208 | */ |
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640:c90ae1400bf2 | 209 | __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number); |
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640:c90ae1400bf2 | 210 | |
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640:c90ae1400bf2 | 211 | /** |
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640:c90ae1400bf2 | 212 | * @brief Function for disconnecting input for the given GPIO. |
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640:c90ae1400bf2 | 213 | * |
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640:c90ae1400bf2 | 214 | * @param pin_number Specifies the pin number (allowed values 0-31). |
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640:c90ae1400bf2 | 215 | * |
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640:c90ae1400bf2 | 216 | */ |
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640:c90ae1400bf2 | 217 | __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number); |
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640:c90ae1400bf2 | 218 | |
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640:c90ae1400bf2 | 219 | /** |
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640:c90ae1400bf2 | 220 | * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details. |
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640:c90ae1400bf2 | 221 | * This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases). |
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640:c90ae1400bf2 | 222 | * Sense capability on the pin is configurable, and input is connected to buffer so that the GPIO->IN register is readable. |
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640:c90ae1400bf2 | 223 | * |
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640:c90ae1400bf2 | 224 | * @param pin_number Specifies the pin number (allowed values 0-30). |
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640:c90ae1400bf2 | 225 | * @param pull_config State of the pin pull resistor (no pull, pulled down or pulled high). |
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640:c90ae1400bf2 | 226 | * @param sense_config Sense level of the pin (no sense, sense low or sense high). |
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640:c90ae1400bf2 | 227 | */ |
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640:c90ae1400bf2 | 228 | __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config); |
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640:c90ae1400bf2 | 229 | |
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640:c90ae1400bf2 | 230 | /** |
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640:c90ae1400bf2 | 231 | * @brief Function for configuring sense level for the given GPIO. |
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640:c90ae1400bf2 | 232 | * |
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640:c90ae1400bf2 | 233 | * @param pin_number Specifies the pin number of gpio pin numbers to be configured (allowed values 0-30). |
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640:c90ae1400bf2 | 234 | * @param sense_config Sense configuration. |
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640:c90ae1400bf2 | 235 | * |
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640:c90ae1400bf2 | 236 | */ |
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640:c90ae1400bf2 | 237 | __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config); |
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640:c90ae1400bf2 | 238 | |
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640:c90ae1400bf2 | 239 | /** |
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640:c90ae1400bf2 | 240 | * @brief Function for setting the direction for a GPIO pin. |
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640:c90ae1400bf2 | 241 | * |
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640:c90ae1400bf2 | 242 | * @param pin_number specifies the pin number [0:31] for which to |
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640:c90ae1400bf2 | 243 | * set the direction. |
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640:c90ae1400bf2 | 244 | * |
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640:c90ae1400bf2 | 245 | * @param direction specifies the direction |
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640:c90ae1400bf2 | 246 | */ |
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640:c90ae1400bf2 | 247 | __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction); |
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640:c90ae1400bf2 | 248 | |
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640:c90ae1400bf2 | 249 | /** |
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640:c90ae1400bf2 | 250 | * @brief Function for setting a GPIO pin. |
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640:c90ae1400bf2 | 251 | * |
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640:c90ae1400bf2 | 252 | * Note that the pin must be configured as an output for this |
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640:c90ae1400bf2 | 253 | * function to have any effect. |
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640:c90ae1400bf2 | 254 | * |
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640:c90ae1400bf2 | 255 | * @param pin_number specifies the pin number [0:31] to |
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640:c90ae1400bf2 | 256 | * set. |
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640:c90ae1400bf2 | 257 | */ |
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640:c90ae1400bf2 | 258 | __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number); |
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640:c90ae1400bf2 | 259 | |
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640:c90ae1400bf2 | 260 | /** |
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640:c90ae1400bf2 | 261 | * @brief Function for setting GPIO pins. |
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640:c90ae1400bf2 | 262 | * |
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640:c90ae1400bf2 | 263 | * Note that pins must be configured as an output for this |
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640:c90ae1400bf2 | 264 | * function to have any effect. |
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640:c90ae1400bf2 | 265 | * |
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640:c90ae1400bf2 | 266 | * @param pin_mask Specifies the pins to set. |
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640:c90ae1400bf2 | 267 | * set. |
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640:c90ae1400bf2 | 268 | */ |
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640:c90ae1400bf2 | 269 | __STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask); |
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640:c90ae1400bf2 | 270 | |
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640:c90ae1400bf2 | 271 | /** |
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640:c90ae1400bf2 | 272 | * @brief Function for clearing a GPIO pin. |
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640:c90ae1400bf2 | 273 | * |
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640:c90ae1400bf2 | 274 | * Note that the pin must be configured as an output for this |
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640:c90ae1400bf2 | 275 | * function to have any effect. |
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640:c90ae1400bf2 | 276 | * |
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640:c90ae1400bf2 | 277 | * @param pin_number specifies the pin number [0:31] to |
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640:c90ae1400bf2 | 278 | * clear. |
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640:c90ae1400bf2 | 279 | */ |
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640:c90ae1400bf2 | 280 | __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number); |
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640:c90ae1400bf2 | 281 | |
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640:c90ae1400bf2 | 282 | /** |
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640:c90ae1400bf2 | 283 | * @brief Function for clearing GPIO pins. |
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640:c90ae1400bf2 | 284 | * |
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640:c90ae1400bf2 | 285 | * Note that pins must be configured as an output for this |
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640:c90ae1400bf2 | 286 | * function to have any effect. |
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640:c90ae1400bf2 | 287 | * |
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640:c90ae1400bf2 | 288 | * @param pin_mask Specifies the pins to clear. |
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640:c90ae1400bf2 | 289 | * set. |
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640:c90ae1400bf2 | 290 | */ |
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640:c90ae1400bf2 | 291 | __STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask); |
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640:c90ae1400bf2 | 292 | |
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640:c90ae1400bf2 | 293 | /** |
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640:c90ae1400bf2 | 294 | * @brief Function for toggling a GPIO pin. |
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640:c90ae1400bf2 | 295 | * |
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640:c90ae1400bf2 | 296 | * Note that the pin must be configured as an output for this |
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640:c90ae1400bf2 | 297 | * function to have any effect. |
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640:c90ae1400bf2 | 298 | * |
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640:c90ae1400bf2 | 299 | * @param pin_number specifies the pin number [0:31] to |
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640:c90ae1400bf2 | 300 | * toggle. |
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640:c90ae1400bf2 | 301 | */ |
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640:c90ae1400bf2 | 302 | __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number); |
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640:c90ae1400bf2 | 303 | |
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640:c90ae1400bf2 | 304 | /** |
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640:c90ae1400bf2 | 305 | * @brief Function for writing a value to a GPIO pin. |
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640:c90ae1400bf2 | 306 | * |
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640:c90ae1400bf2 | 307 | * Note that the pin must be configured as an output for this |
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640:c90ae1400bf2 | 308 | * function to have any effect. |
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640:c90ae1400bf2 | 309 | * |
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640:c90ae1400bf2 | 310 | * @param pin_number specifies the pin number [0:31] to |
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640:c90ae1400bf2 | 311 | * write. |
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640:c90ae1400bf2 | 312 | * |
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640:c90ae1400bf2 | 313 | * @param value specifies the value to be written to the pin. |
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640:c90ae1400bf2 | 314 | * @arg 0 clears the pin |
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640:c90ae1400bf2 | 315 | * @arg >=1 sets the pin. |
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640:c90ae1400bf2 | 316 | */ |
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640:c90ae1400bf2 | 317 | __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value); |
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640:c90ae1400bf2 | 318 | |
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640:c90ae1400bf2 | 319 | /** |
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640:c90ae1400bf2 | 320 | * @brief Function for reading the input level of a GPIO pin. |
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640:c90ae1400bf2 | 321 | * |
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640:c90ae1400bf2 | 322 | * Note that the pin must have input connected for the value |
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640:c90ae1400bf2 | 323 | * returned from this function to be valid. |
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640:c90ae1400bf2 | 324 | * |
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640:c90ae1400bf2 | 325 | * @param pin_number specifies the pin number [0:31] to |
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640:c90ae1400bf2 | 326 | * read. |
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640:c90ae1400bf2 | 327 | * |
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640:c90ae1400bf2 | 328 | * @return |
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640:c90ae1400bf2 | 329 | * @retval 0 if the pin input level is low. |
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640:c90ae1400bf2 | 330 | * @retval 1 if the pin input level is high. |
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640:c90ae1400bf2 | 331 | * @retval > 1 should never occur. |
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640:c90ae1400bf2 | 332 | */ |
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640:c90ae1400bf2 | 333 | __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number); |
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640:c90ae1400bf2 | 334 | |
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640:c90ae1400bf2 | 335 | /** |
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640:c90ae1400bf2 | 336 | * @brief Function for reading the input level of all GPIO pins. |
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640:c90ae1400bf2 | 337 | * |
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640:c90ae1400bf2 | 338 | * Note that the pin must have input connected for the value |
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640:c90ae1400bf2 | 339 | * returned from this function to be valid. |
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640:c90ae1400bf2 | 340 | * |
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640:c90ae1400bf2 | 341 | * @retval Status of input of all pins |
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640:c90ae1400bf2 | 342 | */ |
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640:c90ae1400bf2 | 343 | __STATIC_INLINE uint32_t nrf_gpio_pins_read(void); |
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640:c90ae1400bf2 | 344 | |
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640:c90ae1400bf2 | 345 | /** |
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640:c90ae1400bf2 | 346 | * @brief Function for reading the sense configuration of a GPIO pin. |
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640:c90ae1400bf2 | 347 | * |
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640:c90ae1400bf2 | 348 | * @param pin_number specifies the pin number [0:31] to |
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640:c90ae1400bf2 | 349 | * read. |
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640:c90ae1400bf2 | 350 | * |
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640:c90ae1400bf2 | 351 | * @retval Sense configuration |
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640:c90ae1400bf2 | 352 | */ |
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640:c90ae1400bf2 | 353 | __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number); |
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640:c90ae1400bf2 | 354 | |
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640:c90ae1400bf2 | 355 | /** |
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640:c90ae1400bf2 | 356 | * @brief Generic function for writing a single byte of a 32 bit word at a given |
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640:c90ae1400bf2 | 357 | * address. |
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640:c90ae1400bf2 | 358 | * |
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640:c90ae1400bf2 | 359 | * This function should not be called from outside the nrf_gpio |
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640:c90ae1400bf2 | 360 | * abstraction layer. |
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640:c90ae1400bf2 | 361 | * |
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640:c90ae1400bf2 | 362 | * @param word_address is the address of the word to be written. |
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640:c90ae1400bf2 | 363 | * |
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640:c90ae1400bf2 | 364 | * @param byte_no is the word byte number (0-3) to be written. |
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640:c90ae1400bf2 | 365 | * |
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640:c90ae1400bf2 | 366 | * @param value is the value to be written to byte "byte_no" of word |
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640:c90ae1400bf2 | 367 | * at address "word_address" |
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640:c90ae1400bf2 | 368 | */ |
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640:c90ae1400bf2 | 369 | __STATIC_INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value); |
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640:c90ae1400bf2 | 370 | |
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640:c90ae1400bf2 | 371 | /** |
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640:c90ae1400bf2 | 372 | * @brief Generic function for reading a single byte of a 32 bit word at a given |
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640:c90ae1400bf2 | 373 | * address. |
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640:c90ae1400bf2 | 374 | * |
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640:c90ae1400bf2 | 375 | * This function should not be called from outside the nrf_gpio |
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640:c90ae1400bf2 | 376 | * abstraction layer. |
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640:c90ae1400bf2 | 377 | * |
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640:c90ae1400bf2 | 378 | * @param word_address is the address of the word to be read. |
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640:c90ae1400bf2 | 379 | * |
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640:c90ae1400bf2 | 380 | * @param byte_no is the byte number (0-3) of the word to be read. |
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640:c90ae1400bf2 | 381 | * |
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640:c90ae1400bf2 | 382 | * @return byte "byte_no" of word at address "word_address". |
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640:c90ae1400bf2 | 383 | */ |
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640:c90ae1400bf2 | 384 | __STATIC_INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no); |
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640:c90ae1400bf2 | 385 | |
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640:c90ae1400bf2 | 386 | /** |
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640:c90ae1400bf2 | 387 | * @brief Function for setting the direction of a port. |
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640:c90ae1400bf2 | 388 | * |
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640:c90ae1400bf2 | 389 | * @param port is the port for which to set the direction. |
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640:c90ae1400bf2 | 390 | * |
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640:c90ae1400bf2 | 391 | * @param dir direction to be set for this port. |
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640:c90ae1400bf2 | 392 | */ |
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640:c90ae1400bf2 | 393 | __STATIC_INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir); |
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640:c90ae1400bf2 | 394 | |
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640:c90ae1400bf2 | 395 | /** |
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640:c90ae1400bf2 | 396 | * @brief Function for reading a GPIO port. |
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640:c90ae1400bf2 | 397 | * |
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640:c90ae1400bf2 | 398 | * @param port is the port to read. |
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640:c90ae1400bf2 | 399 | * |
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640:c90ae1400bf2 | 400 | * @return the input value on this port. |
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640:c90ae1400bf2 | 401 | */ |
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640:c90ae1400bf2 | 402 | __STATIC_INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port); |
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640:c90ae1400bf2 | 403 | |
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640:c90ae1400bf2 | 404 | /** |
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640:c90ae1400bf2 | 405 | * @brief Function for writing to a GPIO port. |
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640:c90ae1400bf2 | 406 | * |
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640:c90ae1400bf2 | 407 | * @param port is the port to write. |
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640:c90ae1400bf2 | 408 | * |
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640:c90ae1400bf2 | 409 | * @param value is the value to write to this port. |
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640:c90ae1400bf2 | 410 | * |
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640:c90ae1400bf2 | 411 | * @sa nrf_gpio_port_dir_set() |
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640:c90ae1400bf2 | 412 | */ |
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640:c90ae1400bf2 | 413 | __STATIC_INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value); |
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640:c90ae1400bf2 | 414 | |
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640:c90ae1400bf2 | 415 | /** |
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640:c90ae1400bf2 | 416 | * @brief Function for setting individual pins on GPIO port. |
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640:c90ae1400bf2 | 417 | * |
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640:c90ae1400bf2 | 418 | * @param port is the port for which to set the pins. |
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640:c90ae1400bf2 | 419 | * |
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640:c90ae1400bf2 | 420 | * @param set_mask is a mask specifying which pins to set. A bit |
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640:c90ae1400bf2 | 421 | * set to 1 indicates that the corresponding port pin shall be |
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640:c90ae1400bf2 | 422 | * set. |
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640:c90ae1400bf2 | 423 | * |
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640:c90ae1400bf2 | 424 | * @sa nrf_gpio_port_dir_set() |
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640:c90ae1400bf2 | 425 | */ |
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640:c90ae1400bf2 | 426 | __STATIC_INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask); |
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640:c90ae1400bf2 | 427 | |
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640:c90ae1400bf2 | 428 | /** |
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640:c90ae1400bf2 | 429 | * @brief Function for clearing individual pins on GPIO port. |
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640:c90ae1400bf2 | 430 | * |
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640:c90ae1400bf2 | 431 | * @param port is the port for which to clear the pins. |
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640:c90ae1400bf2 | 432 | * |
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640:c90ae1400bf2 | 433 | * @param clr_mask is a mask specifying which pins to clear. A bit |
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640:c90ae1400bf2 | 434 | * set to 1 indicates that the corresponding port pin shall be |
Vincent Coubard |
640:c90ae1400bf2 | 435 | * cleared. |
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640:c90ae1400bf2 | 436 | * |
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640:c90ae1400bf2 | 437 | * @sa nrf_gpio_port_dir_set() |
Vincent Coubard |
640:c90ae1400bf2 | 438 | */ |
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640:c90ae1400bf2 | 439 | __STATIC_INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask); |
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640:c90ae1400bf2 | 440 | |
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640:c90ae1400bf2 | 441 | #ifndef SUPPRESS_INLINE_IMPLEMENTATION |
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640:c90ae1400bf2 | 442 | __STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end) |
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640:c90ae1400bf2 | 443 | { |
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640:c90ae1400bf2 | 444 | /*lint -e{845} // A zero has been given as right argument to operator '|'" */ |
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640:c90ae1400bf2 | 445 | for (; pin_range_start <= pin_range_end; pin_range_start++) |
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640:c90ae1400bf2 | 446 | { |
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640:c90ae1400bf2 | 447 | nrf_gpio_cfg_output(pin_range_start); |
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640:c90ae1400bf2 | 448 | } |
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640:c90ae1400bf2 | 449 | } |
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640:c90ae1400bf2 | 450 | |
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640:c90ae1400bf2 | 451 | __STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config) |
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640:c90ae1400bf2 | 452 | { |
Vincent Coubard |
640:c90ae1400bf2 | 453 | /*lint -e{845} // A zero has been given as right argument to operator '|'" */ |
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640:c90ae1400bf2 | 454 | for (; pin_range_start <= pin_range_end; pin_range_start++) |
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640:c90ae1400bf2 | 455 | { |
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640:c90ae1400bf2 | 456 | nrf_gpio_cfg_input(pin_range_start, pull_config); |
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640:c90ae1400bf2 | 457 | } |
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640:c90ae1400bf2 | 458 | } |
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640:c90ae1400bf2 | 459 | |
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640:c90ae1400bf2 | 460 | __STATIC_INLINE void nrf_gpio_cfg( |
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640:c90ae1400bf2 | 461 | uint32_t pin_number, |
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640:c90ae1400bf2 | 462 | nrf_gpio_pin_dir_t dir, |
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640:c90ae1400bf2 | 463 | nrf_gpio_pin_input_t input, |
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640:c90ae1400bf2 | 464 | nrf_gpio_pin_pull_t pull, |
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640:c90ae1400bf2 | 465 | nrf_gpio_pin_drive_t drive, |
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640:c90ae1400bf2 | 466 | nrf_gpio_pin_sense_t sense) |
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640:c90ae1400bf2 | 467 | { |
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640:c90ae1400bf2 | 468 | NRF_GPIO->PIN_CNF[pin_number] = ((uint32_t)dir << GPIO_PIN_CNF_DIR_Pos) |
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640:c90ae1400bf2 | 469 | | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos) |
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640:c90ae1400bf2 | 470 | | ((uint32_t)pull << GPIO_PIN_CNF_PULL_Pos) |
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640:c90ae1400bf2 | 471 | | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) |
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640:c90ae1400bf2 | 472 | | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos); |
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640:c90ae1400bf2 | 473 | } |
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640:c90ae1400bf2 | 474 | |
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640:c90ae1400bf2 | 475 | __STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number) |
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640:c90ae1400bf2 | 476 | { |
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640:c90ae1400bf2 | 477 | nrf_gpio_cfg( |
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640:c90ae1400bf2 | 478 | pin_number, |
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640:c90ae1400bf2 | 479 | NRF_GPIO_PIN_DIR_OUTPUT, |
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640:c90ae1400bf2 | 480 | NRF_GPIO_PIN_INPUT_DISCONNECT, |
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640:c90ae1400bf2 | 481 | NRF_GPIO_PIN_NOPULL, |
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640:c90ae1400bf2 | 482 | NRF_GPIO_PIN_S0S1, |
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640:c90ae1400bf2 | 483 | NRF_GPIO_PIN_NOSENSE); |
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640:c90ae1400bf2 | 484 | } |
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640:c90ae1400bf2 | 485 | |
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640:c90ae1400bf2 | 486 | __STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config) |
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640:c90ae1400bf2 | 487 | { |
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640:c90ae1400bf2 | 488 | nrf_gpio_cfg( |
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640:c90ae1400bf2 | 489 | pin_number, |
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640:c90ae1400bf2 | 490 | NRF_GPIO_PIN_DIR_INPUT, |
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640:c90ae1400bf2 | 491 | NRF_GPIO_PIN_INPUT_CONNECT, |
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640:c90ae1400bf2 | 492 | pull_config, |
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640:c90ae1400bf2 | 493 | NRF_GPIO_PIN_S0S1, |
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640:c90ae1400bf2 | 494 | NRF_GPIO_PIN_NOSENSE); |
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640:c90ae1400bf2 | 495 | } |
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640:c90ae1400bf2 | 496 | |
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640:c90ae1400bf2 | 497 | __STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number) |
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640:c90ae1400bf2 | 498 | { |
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640:c90ae1400bf2 | 499 | nrf_gpio_cfg( |
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640:c90ae1400bf2 | 500 | pin_number, |
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640:c90ae1400bf2 | 501 | NRF_GPIO_PIN_DIR_INPUT, |
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640:c90ae1400bf2 | 502 | NRF_GPIO_PIN_INPUT_DISCONNECT, |
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640:c90ae1400bf2 | 503 | NRF_GPIO_PIN_NOPULL, |
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640:c90ae1400bf2 | 504 | NRF_GPIO_PIN_S0S1, |
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640:c90ae1400bf2 | 505 | NRF_GPIO_PIN_NOSENSE); |
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640:c90ae1400bf2 | 506 | } |
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640:c90ae1400bf2 | 507 | |
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640:c90ae1400bf2 | 508 | __STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number) |
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640:c90ae1400bf2 | 509 | { |
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640:c90ae1400bf2 | 510 | /*lint -e{845} // A zero has been given as right argument to operator '|'" */ |
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640:c90ae1400bf2 | 511 | uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; |
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640:c90ae1400bf2 | 512 | NRF_GPIO->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); |
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640:c90ae1400bf2 | 513 | } |
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640:c90ae1400bf2 | 514 | |
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640:c90ae1400bf2 | 515 | __STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number) |
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640:c90ae1400bf2 | 516 | { |
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640:c90ae1400bf2 | 517 | /*lint -e{845} // A zero has been given as right argument to operator '|'" */ |
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640:c90ae1400bf2 | 518 | uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk; |
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640:c90ae1400bf2 | 519 | NRF_GPIO->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos); |
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640:c90ae1400bf2 | 520 | } |
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640:c90ae1400bf2 | 521 | |
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640:c90ae1400bf2 | 522 | __STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config) |
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640:c90ae1400bf2 | 523 | { |
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640:c90ae1400bf2 | 524 | nrf_gpio_cfg( |
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640:c90ae1400bf2 | 525 | pin_number, |
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640:c90ae1400bf2 | 526 | NRF_GPIO_PIN_DIR_INPUT, |
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640:c90ae1400bf2 | 527 | NRF_GPIO_PIN_INPUT_CONNECT, |
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640:c90ae1400bf2 | 528 | pull_config, |
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640:c90ae1400bf2 | 529 | NRF_GPIO_PIN_S0S1, |
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640:c90ae1400bf2 | 530 | sense_config); |
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640:c90ae1400bf2 | 531 | } |
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640:c90ae1400bf2 | 532 | |
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640:c90ae1400bf2 | 533 | __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config) |
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640:c90ae1400bf2 | 534 | { |
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640:c90ae1400bf2 | 535 | /*lint -e{845} // A zero has been given as right argument to operator '|'" */ |
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640:c90ae1400bf2 | 536 | //uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk; |
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640:c90ae1400bf2 | 537 | NRF_GPIO->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk; |
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640:c90ae1400bf2 | 538 | NRF_GPIO->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos); |
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640:c90ae1400bf2 | 539 | } |
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640:c90ae1400bf2 | 540 | |
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640:c90ae1400bf2 | 541 | __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction) |
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640:c90ae1400bf2 | 542 | { |
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640:c90ae1400bf2 | 543 | if(direction == NRF_GPIO_PIN_DIR_INPUT) |
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640:c90ae1400bf2 | 544 | { |
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640:c90ae1400bf2 | 545 | nrf_gpio_cfg( |
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640:c90ae1400bf2 | 546 | pin_number, |
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640:c90ae1400bf2 | 547 | NRF_GPIO_PIN_DIR_INPUT, |
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640:c90ae1400bf2 | 548 | NRF_GPIO_PIN_INPUT_CONNECT, |
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640:c90ae1400bf2 | 549 | NRF_GPIO_PIN_NOPULL, |
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640:c90ae1400bf2 | 550 | NRF_GPIO_PIN_S0S1, |
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640:c90ae1400bf2 | 551 | NRF_GPIO_PIN_NOSENSE); |
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640:c90ae1400bf2 | 552 | } |
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640:c90ae1400bf2 | 553 | else |
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640:c90ae1400bf2 | 554 | { |
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640:c90ae1400bf2 | 555 | NRF_GPIO->DIRSET = (1UL << pin_number); |
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640:c90ae1400bf2 | 556 | } |
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640:c90ae1400bf2 | 557 | } |
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640:c90ae1400bf2 | 558 | |
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640:c90ae1400bf2 | 559 | __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number) |
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640:c90ae1400bf2 | 560 | { |
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640:c90ae1400bf2 | 561 | NRF_GPIO->OUTSET = (1UL << pin_number); |
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640:c90ae1400bf2 | 562 | } |
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640:c90ae1400bf2 | 563 | |
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640:c90ae1400bf2 | 564 | __STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask) |
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640:c90ae1400bf2 | 565 | { |
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640:c90ae1400bf2 | 566 | NRF_GPIO->OUTSET = pin_mask; |
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640:c90ae1400bf2 | 567 | } |
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640:c90ae1400bf2 | 568 | |
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640:c90ae1400bf2 | 569 | __STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number) |
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640:c90ae1400bf2 | 570 | { |
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640:c90ae1400bf2 | 571 | NRF_GPIO->OUTCLR = (1UL << pin_number); |
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640:c90ae1400bf2 | 572 | } |
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640:c90ae1400bf2 | 573 | |
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640:c90ae1400bf2 | 574 | __STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask) |
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640:c90ae1400bf2 | 575 | { |
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640:c90ae1400bf2 | 576 | NRF_GPIO->OUTCLR = pin_mask; |
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640:c90ae1400bf2 | 577 | } |
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640:c90ae1400bf2 | 578 | |
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640:c90ae1400bf2 | 579 | __STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number) |
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640:c90ae1400bf2 | 580 | { |
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640:c90ae1400bf2 | 581 | const uint32_t pin_bit = 1UL << pin_number; |
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640:c90ae1400bf2 | 582 | const uint32_t pin_state = ((NRF_GPIO->OUT >> pin_number) & 1UL); |
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640:c90ae1400bf2 | 583 | |
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640:c90ae1400bf2 | 584 | if (pin_state == 0) |
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640:c90ae1400bf2 | 585 | { |
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640:c90ae1400bf2 | 586 | // Current state low, set high. |
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640:c90ae1400bf2 | 587 | NRF_GPIO->OUTSET = pin_bit; |
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640:c90ae1400bf2 | 588 | } |
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640:c90ae1400bf2 | 589 | else |
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640:c90ae1400bf2 | 590 | { |
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640:c90ae1400bf2 | 591 | // Current state high, set low. |
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640:c90ae1400bf2 | 592 | NRF_GPIO->OUTCLR = pin_bit; |
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640:c90ae1400bf2 | 593 | } |
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640:c90ae1400bf2 | 594 | } |
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640:c90ae1400bf2 | 595 | |
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640:c90ae1400bf2 | 596 | __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value) |
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640:c90ae1400bf2 | 597 | { |
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640:c90ae1400bf2 | 598 | if (value == 0) |
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640:c90ae1400bf2 | 599 | { |
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640:c90ae1400bf2 | 600 | nrf_gpio_pin_clear(pin_number); |
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640:c90ae1400bf2 | 601 | } |
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640:c90ae1400bf2 | 602 | else |
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640:c90ae1400bf2 | 603 | { |
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640:c90ae1400bf2 | 604 | nrf_gpio_pin_set(pin_number); |
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640:c90ae1400bf2 | 605 | } |
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640:c90ae1400bf2 | 606 | } |
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640:c90ae1400bf2 | 607 | |
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640:c90ae1400bf2 | 608 | __STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number) |
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640:c90ae1400bf2 | 609 | { |
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640:c90ae1400bf2 | 610 | return ((NRF_GPIO->IN >> pin_number) & 1UL); |
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640:c90ae1400bf2 | 611 | } |
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640:c90ae1400bf2 | 612 | |
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640:c90ae1400bf2 | 613 | __STATIC_INLINE uint32_t nrf_gpio_pins_read(void) |
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640:c90ae1400bf2 | 614 | { |
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640:c90ae1400bf2 | 615 | return NRF_GPIO->IN; |
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640:c90ae1400bf2 | 616 | } |
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640:c90ae1400bf2 | 617 | |
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640:c90ae1400bf2 | 618 | __STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number) |
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640:c90ae1400bf2 | 619 | { |
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640:c90ae1400bf2 | 620 | return (nrf_gpio_pin_sense_t)((NRF_GPIO->PIN_CNF[pin_number] & GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos); |
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640:c90ae1400bf2 | 621 | } |
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640:c90ae1400bf2 | 622 | |
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640:c90ae1400bf2 | 623 | __STATIC_INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value) |
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640:c90ae1400bf2 | 624 | { |
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640:c90ae1400bf2 | 625 | *((volatile uint8_t*)(word_address) + byte_no) = value; |
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640:c90ae1400bf2 | 626 | } |
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640:c90ae1400bf2 | 627 | |
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640:c90ae1400bf2 | 628 | __STATIC_INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no) |
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640:c90ae1400bf2 | 629 | { |
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640:c90ae1400bf2 | 630 | return (*((const volatile uint8_t*)(word_address) + byte_no)); |
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640:c90ae1400bf2 | 631 | } |
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640:c90ae1400bf2 | 632 | |
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640:c90ae1400bf2 | 633 | __STATIC_INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir) |
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640:c90ae1400bf2 | 634 | { |
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640:c90ae1400bf2 | 635 | if (dir == NRF_GPIO_PORT_DIR_OUTPUT) |
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640:c90ae1400bf2 | 636 | { |
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640:c90ae1400bf2 | 637 | nrf_gpio_word_byte_write(&NRF_GPIO->DIRSET, port, 0xFF); |
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640:c90ae1400bf2 | 638 | } |
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640:c90ae1400bf2 | 639 | else |
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640:c90ae1400bf2 | 640 | { |
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640:c90ae1400bf2 | 641 | nrf_gpio_range_cfg_input(port*8, (port+1)*8-1, NRF_GPIO_PIN_NOPULL); |
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640:c90ae1400bf2 | 642 | } |
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640:c90ae1400bf2 | 643 | } |
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640:c90ae1400bf2 | 644 | |
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640:c90ae1400bf2 | 645 | __STATIC_INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port) |
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640:c90ae1400bf2 | 646 | { |
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640:c90ae1400bf2 | 647 | return nrf_gpio_word_byte_read(&NRF_GPIO->IN, port); |
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640:c90ae1400bf2 | 648 | } |
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640:c90ae1400bf2 | 649 | |
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640:c90ae1400bf2 | 650 | __STATIC_INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value) |
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640:c90ae1400bf2 | 651 | { |
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640:c90ae1400bf2 | 652 | nrf_gpio_word_byte_write(&NRF_GPIO->OUT, port, value); |
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640:c90ae1400bf2 | 653 | } |
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640:c90ae1400bf2 | 654 | |
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640:c90ae1400bf2 | 655 | __STATIC_INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask) |
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640:c90ae1400bf2 | 656 | { |
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640:c90ae1400bf2 | 657 | nrf_gpio_word_byte_write(&NRF_GPIO->OUTSET, port, set_mask); |
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640:c90ae1400bf2 | 658 | } |
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640:c90ae1400bf2 | 659 | |
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640:c90ae1400bf2 | 660 | __STATIC_INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask) |
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640:c90ae1400bf2 | 661 | { |
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640:c90ae1400bf2 | 662 | nrf_gpio_word_byte_write(&NRF_GPIO->OUTCLR, port, clr_mask); |
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640:c90ae1400bf2 | 663 | } |
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640:c90ae1400bf2 | 664 | #endif //SUPPRESS_INLINE_IMPLEMENTATION |
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640:c90ae1400bf2 | 665 | /** @} */ |
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640:c90ae1400bf2 | 666 | |
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640:c90ae1400bf2 | 667 | #endif |