Mustahsin Chowdhury / nRF51822

Nordic stack and drivers for the mbed BLE API

Fork of nRF51822 by Nordic Semiconductor

TARGET_MCU_NRF51822/sdk/source/device/nrf51.h@640:c90ae1400bf2, 2016-09-14 (annotated)

Committer:
Vincent Coubard
Date:
Wed Sep 14 14:39:43 2016 +0100
Revision:
640:c90ae1400bf2
Sync with bdab10dc0f90748b6989c8b577771bb403ca6bd8 from ARMmbed/mbed-os.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Vincent Coubard 640:c90ae1400bf2 1 /*
Vincent Coubard 640:c90ae1400bf2 2 * Copyright (c) Nordic Semiconductor ASA
Vincent Coubard 640:c90ae1400bf2 3 * All rights reserved.
Vincent Coubard 640:c90ae1400bf2 4 *
Vincent Coubard 640:c90ae1400bf2 5 * Redistribution and use in source and binary forms, with or without modification,
Vincent Coubard 640:c90ae1400bf2 6 * are permitted provided that the following conditions are met:
Vincent Coubard 640:c90ae1400bf2 7 *
Vincent Coubard 640:c90ae1400bf2 8 * 1. Redistributions of source code must retain the above copyright notice, this
Vincent Coubard 640:c90ae1400bf2 9 * list of conditions and the following disclaimer.
Vincent Coubard 640:c90ae1400bf2 10 *
Vincent Coubard 640:c90ae1400bf2 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
Vincent Coubard 640:c90ae1400bf2 12 * list of conditions and the following disclaimer in the documentation and/or
Vincent Coubard 640:c90ae1400bf2 13 * other materials provided with the distribution.
Vincent Coubard 640:c90ae1400bf2 14 *
Vincent Coubard 640:c90ae1400bf2 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
Vincent Coubard 640:c90ae1400bf2 16 * contributors to this software may be used to endorse or promote products
Vincent Coubard 640:c90ae1400bf2 17 * derived from this software without specific prior written permission.
Vincent Coubard 640:c90ae1400bf2 18 *
Vincent Coubard 640:c90ae1400bf2 19 *
Vincent Coubard 640:c90ae1400bf2 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Vincent Coubard 640:c90ae1400bf2 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Vincent Coubard 640:c90ae1400bf2 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Vincent Coubard 640:c90ae1400bf2 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Vincent Coubard 640:c90ae1400bf2 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Vincent Coubard 640:c90ae1400bf2 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Vincent Coubard 640:c90ae1400bf2 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Vincent Coubard 640:c90ae1400bf2 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Vincent Coubard 640:c90ae1400bf2 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Vincent Coubard 640:c90ae1400bf2 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Vincent Coubard 640:c90ae1400bf2 30 *
Vincent Coubard 640:c90ae1400bf2 31 */
Vincent Coubard 640:c90ae1400bf2 32
Vincent Coubard 640:c90ae1400bf2 33 #ifndef NRF51_H
Vincent Coubard 640:c90ae1400bf2 34 #define NRF51_H
Vincent Coubard 640:c90ae1400bf2 35
Vincent Coubard 640:c90ae1400bf2 36 #ifdef __cplusplus
Vincent Coubard 640:c90ae1400bf2 37 extern "C" {
Vincent Coubard 640:c90ae1400bf2 38 #endif
Vincent Coubard 640:c90ae1400bf2 39
Vincent Coubard 640:c90ae1400bf2 40
Vincent Coubard 640:c90ae1400bf2 41 /* ------------------------- Interrupt Number Definition ------------------------ */
Vincent Coubard 640:c90ae1400bf2 42
Vincent Coubard 640:c90ae1400bf2 43 typedef enum {
Vincent Coubard 640:c90ae1400bf2 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Vincent Coubard 640:c90ae1400bf2 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
Vincent Coubard 640:c90ae1400bf2 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
Vincent Coubard 640:c90ae1400bf2 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
Vincent Coubard 640:c90ae1400bf2 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
Vincent Coubard 640:c90ae1400bf2 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
Vincent Coubard 640:c90ae1400bf2 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
Vincent Coubard 640:c90ae1400bf2 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
Vincent Coubard 640:c90ae1400bf2 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
Vincent Coubard 640:c90ae1400bf2 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
Vincent Coubard 640:c90ae1400bf2 54 RADIO_IRQn = 1, /*!< 1 RADIO */
Vincent Coubard 640:c90ae1400bf2 55 UART0_IRQn = 2, /*!< 2 UART0 */
Vincent Coubard 640:c90ae1400bf2 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
Vincent Coubard 640:c90ae1400bf2 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
Vincent Coubard 640:c90ae1400bf2 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
Vincent Coubard 640:c90ae1400bf2 59 ADC_IRQn = 7, /*!< 7 ADC */
Vincent Coubard 640:c90ae1400bf2 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
Vincent Coubard 640:c90ae1400bf2 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
Vincent Coubard 640:c90ae1400bf2 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
Vincent Coubard 640:c90ae1400bf2 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
Vincent Coubard 640:c90ae1400bf2 64 TEMP_IRQn = 12, /*!< 12 TEMP */
Vincent Coubard 640:c90ae1400bf2 65 RNG_IRQn = 13, /*!< 13 RNG */
Vincent Coubard 640:c90ae1400bf2 66 ECB_IRQn = 14, /*!< 14 ECB */
Vincent Coubard 640:c90ae1400bf2 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
Vincent Coubard 640:c90ae1400bf2 68 WDT_IRQn = 16, /*!< 16 WDT */
Vincent Coubard 640:c90ae1400bf2 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
Vincent Coubard 640:c90ae1400bf2 70 QDEC_IRQn = 18, /*!< 18 QDEC */
Vincent Coubard 640:c90ae1400bf2 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
Vincent Coubard 640:c90ae1400bf2 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
Vincent Coubard 640:c90ae1400bf2 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
Vincent Coubard 640:c90ae1400bf2 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
Vincent Coubard 640:c90ae1400bf2 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
Vincent Coubard 640:c90ae1400bf2 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
Vincent Coubard 640:c90ae1400bf2 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
Vincent Coubard 640:c90ae1400bf2 78 } IRQn_Type;
Vincent Coubard 640:c90ae1400bf2 79
Vincent Coubard 640:c90ae1400bf2 80
Vincent Coubard 640:c90ae1400bf2 81 /** @addtogroup Configuration_of_CMSIS
Vincent Coubard 640:c90ae1400bf2 82 * @{
Vincent Coubard 640:c90ae1400bf2 83 */
Vincent Coubard 640:c90ae1400bf2 84
Vincent Coubard 640:c90ae1400bf2 85
Vincent Coubard 640:c90ae1400bf2 86 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 87 /* ================ Processor and Core Peripheral Section ================ */
Vincent Coubard 640:c90ae1400bf2 88 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 89
Vincent Coubard 640:c90ae1400bf2 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
Vincent Coubard 640:c90ae1400bf2 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
Vincent Coubard 640:c90ae1400bf2 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
Vincent Coubard 640:c90ae1400bf2 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
Vincent Coubard 640:c90ae1400bf2 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Vincent Coubard 640:c90ae1400bf2 95 /** @} */ /* End of group Configuration_of_CMSIS */
Vincent Coubard 640:c90ae1400bf2 96
Vincent Coubard 640:c90ae1400bf2 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
Vincent Coubard 640:c90ae1400bf2 98 #include "system_nrf51.h" /*!< nrf51 System */
Vincent Coubard 640:c90ae1400bf2 99
Vincent Coubard 640:c90ae1400bf2 100
Vincent Coubard 640:c90ae1400bf2 101 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 102 /* ================ Device Specific Peripheral Section ================ */
Vincent Coubard 640:c90ae1400bf2 103 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 104
Vincent Coubard 640:c90ae1400bf2 105
Vincent Coubard 640:c90ae1400bf2 106 /** @addtogroup Device_Peripheral_Registers
Vincent Coubard 640:c90ae1400bf2 107 * @{
Vincent Coubard 640:c90ae1400bf2 108 */
Vincent Coubard 640:c90ae1400bf2 109
Vincent Coubard 640:c90ae1400bf2 110
Vincent Coubard 640:c90ae1400bf2 111 /* ------------------- Start of section using anonymous unions ------------------ */
Vincent Coubard 640:c90ae1400bf2 112 #if defined(__CC_ARM)
Vincent Coubard 640:c90ae1400bf2 113 #pragma push
Vincent Coubard 640:c90ae1400bf2 114 #pragma anon_unions
Vincent Coubard 640:c90ae1400bf2 115 #elif defined(__ICCARM__)
Vincent Coubard 640:c90ae1400bf2 116 #pragma language=extended
Vincent Coubard 640:c90ae1400bf2 117 #elif defined(__GNUC__)
Vincent Coubard 640:c90ae1400bf2 118 /* anonymous unions are enabled by default */
Vincent Coubard 640:c90ae1400bf2 119 #elif defined(__TMS470__)
Vincent Coubard 640:c90ae1400bf2 120 /* anonymous unions are enabled by default */
Vincent Coubard 640:c90ae1400bf2 121 #elif defined(__TASKING__)
Vincent Coubard 640:c90ae1400bf2 122 #pragma warning 586
Vincent Coubard 640:c90ae1400bf2 123 #else
Vincent Coubard 640:c90ae1400bf2 124 #warning Not supported compiler type
Vincent Coubard 640:c90ae1400bf2 125 #endif
Vincent Coubard 640:c90ae1400bf2 126
Vincent Coubard 640:c90ae1400bf2 127
Vincent Coubard 640:c90ae1400bf2 128 typedef struct {
Vincent Coubard 640:c90ae1400bf2 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
Vincent Coubard 640:c90ae1400bf2 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
Vincent Coubard 640:c90ae1400bf2 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
Vincent Coubard 640:c90ae1400bf2 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
Vincent Coubard 640:c90ae1400bf2 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
Vincent Coubard 640:c90ae1400bf2 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
Vincent Coubard 640:c90ae1400bf2 135 } AMLI_RAMPRI_Type;
Vincent Coubard 640:c90ae1400bf2 136
Vincent Coubard 640:c90ae1400bf2 137 typedef struct {
Vincent Coubard 640:c90ae1400bf2 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
Vincent Coubard 640:c90ae1400bf2 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
Vincent Coubard 640:c90ae1400bf2 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
Vincent Coubard 640:c90ae1400bf2 141 } SPIM_PSEL_Type;
Vincent Coubard 640:c90ae1400bf2 142
Vincent Coubard 640:c90ae1400bf2 143 typedef struct {
Vincent Coubard 640:c90ae1400bf2 144 __IO uint32_t PTR; /*!< Data pointer. */
Vincent Coubard 640:c90ae1400bf2 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
Vincent Coubard 640:c90ae1400bf2 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
Vincent Coubard 640:c90ae1400bf2 147 } SPIM_RXD_Type;
Vincent Coubard 640:c90ae1400bf2 148
Vincent Coubard 640:c90ae1400bf2 149 typedef struct {
Vincent Coubard 640:c90ae1400bf2 150 __IO uint32_t PTR; /*!< Data pointer. */
Vincent Coubard 640:c90ae1400bf2 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
Vincent Coubard 640:c90ae1400bf2 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
Vincent Coubard 640:c90ae1400bf2 153 } SPIM_TXD_Type;
Vincent Coubard 640:c90ae1400bf2 154
Vincent Coubard 640:c90ae1400bf2 155 typedef struct {
Vincent Coubard 640:c90ae1400bf2 156 __O uint32_t EN; /*!< Enable channel group. */
Vincent Coubard 640:c90ae1400bf2 157 __O uint32_t DIS; /*!< Disable channel group. */
Vincent Coubard 640:c90ae1400bf2 158 } PPI_TASKS_CHG_Type;
Vincent Coubard 640:c90ae1400bf2 159
Vincent Coubard 640:c90ae1400bf2 160 typedef struct {
Vincent Coubard 640:c90ae1400bf2 161 __IO uint32_t EEP; /*!< Channel event end-point. */
Vincent Coubard 640:c90ae1400bf2 162 __IO uint32_t TEP; /*!< Channel task end-point. */
Vincent Coubard 640:c90ae1400bf2 163 } PPI_CH_Type;
Vincent Coubard 640:c90ae1400bf2 164
Vincent Coubard 640:c90ae1400bf2 165
Vincent Coubard 640:c90ae1400bf2 166 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 167 /* ================ POWER ================ */
Vincent Coubard 640:c90ae1400bf2 168 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 169
Vincent Coubard 640:c90ae1400bf2 170
Vincent Coubard 640:c90ae1400bf2 171 /**
Vincent Coubard 640:c90ae1400bf2 172 * @brief Power Control. (POWER)
Vincent Coubard 640:c90ae1400bf2 173 */
Vincent Coubard 640:c90ae1400bf2 174
Vincent Coubard 640:c90ae1400bf2 175 typedef struct { /*!< POWER Structure */
Vincent Coubard 640:c90ae1400bf2 176 __I uint32_t RESERVED0[30];
Vincent Coubard 640:c90ae1400bf2 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
Vincent Coubard 640:c90ae1400bf2 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
Vincent Coubard 640:c90ae1400bf2 179 __I uint32_t RESERVED1[34];
Vincent Coubard 640:c90ae1400bf2 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
Vincent Coubard 640:c90ae1400bf2 181 __I uint32_t RESERVED2[126];
Vincent Coubard 640:c90ae1400bf2 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 184 __I uint32_t RESERVED3[61];
Vincent Coubard 640:c90ae1400bf2 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
Vincent Coubard 640:c90ae1400bf2 186 __I uint32_t RESERVED4[9];
Vincent Coubard 640:c90ae1400bf2 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
Vincent Coubard 640:c90ae1400bf2 188 __I uint32_t RESERVED5[53];
Vincent Coubard 640:c90ae1400bf2 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
Vincent Coubard 640:c90ae1400bf2 190 __I uint32_t RESERVED6[3];
Vincent Coubard 640:c90ae1400bf2 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
Vincent Coubard 640:c90ae1400bf2 192 __I uint32_t RESERVED7[2];
Vincent Coubard 640:c90ae1400bf2 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
Vincent Coubard 640:c90ae1400bf2 194 register. */
Vincent Coubard 640:c90ae1400bf2 195 __I uint32_t RESERVED8;
Vincent Coubard 640:c90ae1400bf2 196 __IO uint32_t RAMON; /*!< Ram on/off. */
Vincent Coubard 640:c90ae1400bf2 197 __I uint32_t RESERVED9[7];
Vincent Coubard 640:c90ae1400bf2 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
Vincent Coubard 640:c90ae1400bf2 199 is a retained register. */
Vincent Coubard 640:c90ae1400bf2 200 __I uint32_t RESERVED10[3];
Vincent Coubard 640:c90ae1400bf2 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
Vincent Coubard 640:c90ae1400bf2 202 __I uint32_t RESERVED11[8];
Vincent Coubard 640:c90ae1400bf2 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
Vincent Coubard 640:c90ae1400bf2 204 __I uint32_t RESERVED12[291];
Vincent Coubard 640:c90ae1400bf2 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
Vincent Coubard 640:c90ae1400bf2 206 } NRF_POWER_Type;
Vincent Coubard 640:c90ae1400bf2 207
Vincent Coubard 640:c90ae1400bf2 208
Vincent Coubard 640:c90ae1400bf2 209 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 210 /* ================ CLOCK ================ */
Vincent Coubard 640:c90ae1400bf2 211 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 212
Vincent Coubard 640:c90ae1400bf2 213
Vincent Coubard 640:c90ae1400bf2 214 /**
Vincent Coubard 640:c90ae1400bf2 215 * @brief Clock control. (CLOCK)
Vincent Coubard 640:c90ae1400bf2 216 */
Vincent Coubard 640:c90ae1400bf2 217
Vincent Coubard 640:c90ae1400bf2 218 typedef struct { /*!< CLOCK Structure */
Vincent Coubard 640:c90ae1400bf2 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
Vincent Coubard 640:c90ae1400bf2 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
Vincent Coubard 640:c90ae1400bf2 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
Vincent Coubard 640:c90ae1400bf2 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
Vincent Coubard 640:c90ae1400bf2 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
Vincent Coubard 640:c90ae1400bf2 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
Vincent Coubard 640:c90ae1400bf2 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
Vincent Coubard 640:c90ae1400bf2 226 __I uint32_t RESERVED0[57];
Vincent Coubard 640:c90ae1400bf2 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
Vincent Coubard 640:c90ae1400bf2 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
Vincent Coubard 640:c90ae1400bf2 229 __I uint32_t RESERVED1;
Vincent Coubard 640:c90ae1400bf2 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
Vincent Coubard 640:c90ae1400bf2 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
Vincent Coubard 640:c90ae1400bf2 232 __I uint32_t RESERVED2[124];
Vincent Coubard 640:c90ae1400bf2 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 235 __I uint32_t RESERVED3[63];
Vincent Coubard 640:c90ae1400bf2 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
Vincent Coubard 640:c90ae1400bf2 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
Vincent Coubard 640:c90ae1400bf2 238 __I uint32_t RESERVED4;
Vincent Coubard 640:c90ae1400bf2 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
Vincent Coubard 640:c90ae1400bf2 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
Vincent Coubard 640:c90ae1400bf2 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Vincent Coubard 640:c90ae1400bf2 242 triggered. */
Vincent Coubard 640:c90ae1400bf2 243 __I uint32_t RESERVED5[62];
Vincent Coubard 640:c90ae1400bf2 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
Vincent Coubard 640:c90ae1400bf2 245 __I uint32_t RESERVED6[7];
Vincent Coubard 640:c90ae1400bf2 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
Vincent Coubard 640:c90ae1400bf2 247 __I uint32_t RESERVED7[5];
Vincent Coubard 640:c90ae1400bf2 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
Vincent Coubard 640:c90ae1400bf2 249 } NRF_CLOCK_Type;
Vincent Coubard 640:c90ae1400bf2 250
Vincent Coubard 640:c90ae1400bf2 251
Vincent Coubard 640:c90ae1400bf2 252 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 253 /* ================ MPU ================ */
Vincent Coubard 640:c90ae1400bf2 254 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 255
Vincent Coubard 640:c90ae1400bf2 256
Vincent Coubard 640:c90ae1400bf2 257 /**
Vincent Coubard 640:c90ae1400bf2 258 * @brief Memory Protection Unit. (MPU)
Vincent Coubard 640:c90ae1400bf2 259 */
Vincent Coubard 640:c90ae1400bf2 260
Vincent Coubard 640:c90ae1400bf2 261 typedef struct { /*!< MPU Structure */
Vincent Coubard 640:c90ae1400bf2 262 __I uint32_t RESERVED0[330];
Vincent Coubard 640:c90ae1400bf2 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
Vincent Coubard 640:c90ae1400bf2 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
Vincent Coubard 640:c90ae1400bf2 265 __I uint32_t RESERVED1[52];
Vincent Coubard 640:c90ae1400bf2 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
Vincent Coubard 640:c90ae1400bf2 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
Vincent Coubard 640:c90ae1400bf2 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
Vincent Coubard 640:c90ae1400bf2 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
Vincent Coubard 640:c90ae1400bf2 270 } NRF_MPU_Type;
Vincent Coubard 640:c90ae1400bf2 271
Vincent Coubard 640:c90ae1400bf2 272
Vincent Coubard 640:c90ae1400bf2 273 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 274 /* ================ AMLI ================ */
Vincent Coubard 640:c90ae1400bf2 275 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 276
Vincent Coubard 640:c90ae1400bf2 277
Vincent Coubard 640:c90ae1400bf2 278 /**
Vincent Coubard 640:c90ae1400bf2 279 * @brief AHB Multi-Layer Interface. (AMLI)
Vincent Coubard 640:c90ae1400bf2 280 */
Vincent Coubard 640:c90ae1400bf2 281
Vincent Coubard 640:c90ae1400bf2 282 typedef struct { /*!< AMLI Structure */
Vincent Coubard 640:c90ae1400bf2 283 __I uint32_t RESERVED0[896];
Vincent Coubard 640:c90ae1400bf2 284 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
Vincent Coubard 640:c90ae1400bf2 285 } NRF_AMLI_Type;
Vincent Coubard 640:c90ae1400bf2 286
Vincent Coubard 640:c90ae1400bf2 287
Vincent Coubard 640:c90ae1400bf2 288 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 289 /* ================ RADIO ================ */
Vincent Coubard 640:c90ae1400bf2 290 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 291
Vincent Coubard 640:c90ae1400bf2 292
Vincent Coubard 640:c90ae1400bf2 293 /**
Vincent Coubard 640:c90ae1400bf2 294 * @brief The radio. (RADIO)
Vincent Coubard 640:c90ae1400bf2 295 */
Vincent Coubard 640:c90ae1400bf2 296
Vincent Coubard 640:c90ae1400bf2 297 typedef struct { /*!< RADIO Structure */
Vincent Coubard 640:c90ae1400bf2 298 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
Vincent Coubard 640:c90ae1400bf2 299 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
Vincent Coubard 640:c90ae1400bf2 300 __O uint32_t TASKS_START; /*!< Start radio. */
Vincent Coubard 640:c90ae1400bf2 301 __O uint32_t TASKS_STOP; /*!< Stop radio. */
Vincent Coubard 640:c90ae1400bf2 302 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
Vincent Coubard 640:c90ae1400bf2 303 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
Vincent Coubard 640:c90ae1400bf2 304 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
Vincent Coubard 640:c90ae1400bf2 305 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
Vincent Coubard 640:c90ae1400bf2 306 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
Vincent Coubard 640:c90ae1400bf2 307 __I uint32_t RESERVED0[55];
Vincent Coubard 640:c90ae1400bf2 308 __IO uint32_t EVENTS_READY; /*!< Ready event. */
Vincent Coubard 640:c90ae1400bf2 309 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
Vincent Coubard 640:c90ae1400bf2 310 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
Vincent Coubard 640:c90ae1400bf2 311 __IO uint32_t EVENTS_END; /*!< End event. */
Vincent Coubard 640:c90ae1400bf2 312 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
Vincent Coubard 640:c90ae1400bf2 313 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
Vincent Coubard 640:c90ae1400bf2 314 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
Vincent Coubard 640:c90ae1400bf2 315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
Vincent Coubard 640:c90ae1400bf2 316 sample is ready for readout at the RSSISAMPLE register. */
Vincent Coubard 640:c90ae1400bf2 317 __I uint32_t RESERVED1[2];
Vincent Coubard 640:c90ae1400bf2 318 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
Vincent Coubard 640:c90ae1400bf2 319 __I uint32_t RESERVED2[53];
Vincent Coubard 640:c90ae1400bf2 320 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
Vincent Coubard 640:c90ae1400bf2 321 __I uint32_t RESERVED3[64];
Vincent Coubard 640:c90ae1400bf2 322 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 323 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 324 __I uint32_t RESERVED4[61];
Vincent Coubard 640:c90ae1400bf2 325 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
Vincent Coubard 640:c90ae1400bf2 326 __I uint32_t RESERVED5;
Vincent Coubard 640:c90ae1400bf2 327 __I uint32_t RXMATCH; /*!< Received address. */
Vincent Coubard 640:c90ae1400bf2 328 __I uint32_t RXCRC; /*!< Received CRC. */
Vincent Coubard 640:c90ae1400bf2 329 __I uint32_t DAI; /*!< Device address match index. */
Vincent Coubard 640:c90ae1400bf2 330 __I uint32_t RESERVED6[60];
Vincent Coubard 640:c90ae1400bf2 331 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
Vincent Coubard 640:c90ae1400bf2 332 __IO uint32_t FREQUENCY; /*!< Frequency. */
Vincent Coubard 640:c90ae1400bf2 333 __IO uint32_t TXPOWER; /*!< Output power. */
Vincent Coubard 640:c90ae1400bf2 334 __IO uint32_t MODE; /*!< Data rate and modulation. */
Vincent Coubard 640:c90ae1400bf2 335 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
Vincent Coubard 640:c90ae1400bf2 336 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
Vincent Coubard 640:c90ae1400bf2 337 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
Vincent Coubard 640:c90ae1400bf2 338 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
Vincent Coubard 640:c90ae1400bf2 339 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
Vincent Coubard 640:c90ae1400bf2 340 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
Vincent Coubard 640:c90ae1400bf2 341 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
Vincent Coubard 640:c90ae1400bf2 342 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
Vincent Coubard 640:c90ae1400bf2 343 __IO uint32_t CRCCNF; /*!< CRC configuration. */
Vincent Coubard 640:c90ae1400bf2 344 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
Vincent Coubard 640:c90ae1400bf2 345 __IO uint32_t CRCINIT; /*!< CRC initial value. */
Vincent Coubard 640:c90ae1400bf2 346 __IO uint32_t TEST; /*!< Test features enable register. */
Vincent Coubard 640:c90ae1400bf2 347 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
Vincent Coubard 640:c90ae1400bf2 348 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
Vincent Coubard 640:c90ae1400bf2 349 __I uint32_t RESERVED7;
Vincent Coubard 640:c90ae1400bf2 350 __I uint32_t STATE; /*!< Current radio state. */
Vincent Coubard 640:c90ae1400bf2 351 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
Vincent Coubard 640:c90ae1400bf2 352 __I uint32_t RESERVED8[2];
Vincent Coubard 640:c90ae1400bf2 353 __IO uint32_t BCC; /*!< Bit counter compare. */
Vincent Coubard 640:c90ae1400bf2 354 __I uint32_t RESERVED9[39];
Vincent Coubard 640:c90ae1400bf2 355 __IO uint32_t DAB[8]; /*!< Device address base segment. */
Vincent Coubard 640:c90ae1400bf2 356 __IO uint32_t DAP[8]; /*!< Device address prefix. */
Vincent Coubard 640:c90ae1400bf2 357 __IO uint32_t DACNF; /*!< Device address match configuration. */
Vincent Coubard 640:c90ae1400bf2 358 __I uint32_t RESERVED10[56];
Vincent Coubard 640:c90ae1400bf2 359 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
Vincent Coubard 640:c90ae1400bf2 360 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
Vincent Coubard 640:c90ae1400bf2 361 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
Vincent Coubard 640:c90ae1400bf2 362 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
Vincent Coubard 640:c90ae1400bf2 363 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
Vincent Coubard 640:c90ae1400bf2 364 __I uint32_t RESERVED11[561];
Vincent Coubard 640:c90ae1400bf2 365 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 366 } NRF_RADIO_Type;
Vincent Coubard 640:c90ae1400bf2 367
Vincent Coubard 640:c90ae1400bf2 368
Vincent Coubard 640:c90ae1400bf2 369 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 370 /* ================ UART ================ */
Vincent Coubard 640:c90ae1400bf2 371 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 372
Vincent Coubard 640:c90ae1400bf2 373
Vincent Coubard 640:c90ae1400bf2 374 /**
Vincent Coubard 640:c90ae1400bf2 375 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
Vincent Coubard 640:c90ae1400bf2 376 */
Vincent Coubard 640:c90ae1400bf2 377
Vincent Coubard 640:c90ae1400bf2 378 typedef struct { /*!< UART Structure */
Vincent Coubard 640:c90ae1400bf2 379 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
Vincent Coubard 640:c90ae1400bf2 380 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
Vincent Coubard 640:c90ae1400bf2 381 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
Vincent Coubard 640:c90ae1400bf2 382 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
Vincent Coubard 640:c90ae1400bf2 383 __I uint32_t RESERVED0[3];
Vincent Coubard 640:c90ae1400bf2 384 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
Vincent Coubard 640:c90ae1400bf2 385 __I uint32_t RESERVED1[56];
Vincent Coubard 640:c90ae1400bf2 386 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
Vincent Coubard 640:c90ae1400bf2 387 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
Vincent Coubard 640:c90ae1400bf2 388 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
Vincent Coubard 640:c90ae1400bf2 389 __I uint32_t RESERVED2[4];
Vincent Coubard 640:c90ae1400bf2 390 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
Vincent Coubard 640:c90ae1400bf2 391 __I uint32_t RESERVED3;
Vincent Coubard 640:c90ae1400bf2 392 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
Vincent Coubard 640:c90ae1400bf2 393 __I uint32_t RESERVED4[7];
Vincent Coubard 640:c90ae1400bf2 394 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
Vincent Coubard 640:c90ae1400bf2 395 __I uint32_t RESERVED5[46];
Vincent Coubard 640:c90ae1400bf2 396 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
Vincent Coubard 640:c90ae1400bf2 397 __I uint32_t RESERVED6[64];
Vincent Coubard 640:c90ae1400bf2 398 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 399 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 400 __I uint32_t RESERVED7[93];
Vincent Coubard 640:c90ae1400bf2 401 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
Vincent Coubard 640:c90ae1400bf2 402 __I uint32_t RESERVED8[31];
Vincent Coubard 640:c90ae1400bf2 403 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
Vincent Coubard 640:c90ae1400bf2 404 __I uint32_t RESERVED9;
Vincent Coubard 640:c90ae1400bf2 405 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
Vincent Coubard 640:c90ae1400bf2 406 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
Vincent Coubard 640:c90ae1400bf2 407 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
Vincent Coubard 640:c90ae1400bf2 408 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
Vincent Coubard 640:c90ae1400bf2 409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Vincent Coubard 640:c90ae1400bf2 410 Once read the character is consumed. If read when no character
Vincent Coubard 640:c90ae1400bf2 411 available, the UART will stop working. */
Vincent Coubard 640:c90ae1400bf2 412 __O uint32_t TXD; /*!< TXD register. */
Vincent Coubard 640:c90ae1400bf2 413 __I uint32_t RESERVED10;
Vincent Coubard 640:c90ae1400bf2 414 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
Vincent Coubard 640:c90ae1400bf2 415 __I uint32_t RESERVED11[17];
Vincent Coubard 640:c90ae1400bf2 416 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
Vincent Coubard 640:c90ae1400bf2 417 __I uint32_t RESERVED12[675];
Vincent Coubard 640:c90ae1400bf2 418 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 419 } NRF_UART_Type;
Vincent Coubard 640:c90ae1400bf2 420
Vincent Coubard 640:c90ae1400bf2 421
Vincent Coubard 640:c90ae1400bf2 422 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 423 /* ================ SPI ================ */
Vincent Coubard 640:c90ae1400bf2 424 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 425
Vincent Coubard 640:c90ae1400bf2 426
Vincent Coubard 640:c90ae1400bf2 427 /**
Vincent Coubard 640:c90ae1400bf2 428 * @brief SPI master 0. (SPI)
Vincent Coubard 640:c90ae1400bf2 429 */
Vincent Coubard 640:c90ae1400bf2 430
Vincent Coubard 640:c90ae1400bf2 431 typedef struct { /*!< SPI Structure */
Vincent Coubard 640:c90ae1400bf2 432 __I uint32_t RESERVED0[66];
Vincent Coubard 640:c90ae1400bf2 433 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
Vincent Coubard 640:c90ae1400bf2 434 __I uint32_t RESERVED1[126];
Vincent Coubard 640:c90ae1400bf2 435 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 436 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 437 __I uint32_t RESERVED2[125];
Vincent Coubard 640:c90ae1400bf2 438 __IO uint32_t ENABLE; /*!< Enable SPI. */
Vincent Coubard 640:c90ae1400bf2 439 __I uint32_t RESERVED3;
Vincent Coubard 640:c90ae1400bf2 440 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Vincent Coubard 640:c90ae1400bf2 441 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Vincent Coubard 640:c90ae1400bf2 442 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Vincent Coubard 640:c90ae1400bf2 443 __I uint32_t RESERVED4;
Vincent Coubard 640:c90ae1400bf2 444 __I uint32_t RXD; /*!< RX data. */
Vincent Coubard 640:c90ae1400bf2 445 __IO uint32_t TXD; /*!< TX data. */
Vincent Coubard 640:c90ae1400bf2 446 __I uint32_t RESERVED5;
Vincent Coubard 640:c90ae1400bf2 447 __IO uint32_t FREQUENCY; /*!< SPI frequency */
Vincent Coubard 640:c90ae1400bf2 448 __I uint32_t RESERVED6[11];
Vincent Coubard 640:c90ae1400bf2 449 __IO uint32_t CONFIG; /*!< Configuration register. */
Vincent Coubard 640:c90ae1400bf2 450 __I uint32_t RESERVED7[681];
Vincent Coubard 640:c90ae1400bf2 451 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 452 } NRF_SPI_Type;
Vincent Coubard 640:c90ae1400bf2 453
Vincent Coubard 640:c90ae1400bf2 454
Vincent Coubard 640:c90ae1400bf2 455 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 456 /* ================ TWI ================ */
Vincent Coubard 640:c90ae1400bf2 457 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 458
Vincent Coubard 640:c90ae1400bf2 459
Vincent Coubard 640:c90ae1400bf2 460 /**
Vincent Coubard 640:c90ae1400bf2 461 * @brief Two-wire interface master 0. (TWI)
Vincent Coubard 640:c90ae1400bf2 462 */
Vincent Coubard 640:c90ae1400bf2 463
Vincent Coubard 640:c90ae1400bf2 464 typedef struct { /*!< TWI Structure */
Vincent Coubard 640:c90ae1400bf2 465 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
Vincent Coubard 640:c90ae1400bf2 466 __I uint32_t RESERVED0;
Vincent Coubard 640:c90ae1400bf2 467 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
Vincent Coubard 640:c90ae1400bf2 468 __I uint32_t RESERVED1[2];
Vincent Coubard 640:c90ae1400bf2 469 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
Vincent Coubard 640:c90ae1400bf2 470 __I uint32_t RESERVED2;
Vincent Coubard 640:c90ae1400bf2 471 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
Vincent Coubard 640:c90ae1400bf2 472 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
Vincent Coubard 640:c90ae1400bf2 473 __I uint32_t RESERVED3[56];
Vincent Coubard 640:c90ae1400bf2 474 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
Vincent Coubard 640:c90ae1400bf2 475 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
Vincent Coubard 640:c90ae1400bf2 476 __I uint32_t RESERVED4[4];
Vincent Coubard 640:c90ae1400bf2 477 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
Vincent Coubard 640:c90ae1400bf2 478 __I uint32_t RESERVED5;
Vincent Coubard 640:c90ae1400bf2 479 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
Vincent Coubard 640:c90ae1400bf2 480 __I uint32_t RESERVED6[4];
Vincent Coubard 640:c90ae1400bf2 481 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
Vincent Coubard 640:c90ae1400bf2 482 __I uint32_t RESERVED7[3];
Vincent Coubard 640:c90ae1400bf2 483 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
Vincent Coubard 640:c90ae1400bf2 484 __I uint32_t RESERVED8[45];
Vincent Coubard 640:c90ae1400bf2 485 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Vincent Coubard 640:c90ae1400bf2 486 __I uint32_t RESERVED9[64];
Vincent Coubard 640:c90ae1400bf2 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 489 __I uint32_t RESERVED10[110];
Vincent Coubard 640:c90ae1400bf2 490 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
Vincent Coubard 640:c90ae1400bf2 491 __I uint32_t RESERVED11[14];
Vincent Coubard 640:c90ae1400bf2 492 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
Vincent Coubard 640:c90ae1400bf2 493 __I uint32_t RESERVED12;
Vincent Coubard 640:c90ae1400bf2 494 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
Vincent Coubard 640:c90ae1400bf2 495 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
Vincent Coubard 640:c90ae1400bf2 496 __I uint32_t RESERVED13[2];
Vincent Coubard 640:c90ae1400bf2 497 __I uint32_t RXD; /*!< RX data register. */
Vincent Coubard 640:c90ae1400bf2 498 __IO uint32_t TXD; /*!< TX data register. */
Vincent Coubard 640:c90ae1400bf2 499 __I uint32_t RESERVED14;
Vincent Coubard 640:c90ae1400bf2 500 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
Vincent Coubard 640:c90ae1400bf2 501 __I uint32_t RESERVED15[24];
Vincent Coubard 640:c90ae1400bf2 502 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
Vincent Coubard 640:c90ae1400bf2 503 __I uint32_t RESERVED16[668];
Vincent Coubard 640:c90ae1400bf2 504 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 505 } NRF_TWI_Type;
Vincent Coubard 640:c90ae1400bf2 506
Vincent Coubard 640:c90ae1400bf2 507
Vincent Coubard 640:c90ae1400bf2 508 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 509 /* ================ SPIS ================ */
Vincent Coubard 640:c90ae1400bf2 510 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 511
Vincent Coubard 640:c90ae1400bf2 512
Vincent Coubard 640:c90ae1400bf2 513 /**
Vincent Coubard 640:c90ae1400bf2 514 * @brief SPI slave 1. (SPIS)
Vincent Coubard 640:c90ae1400bf2 515 */
Vincent Coubard 640:c90ae1400bf2 516
Vincent Coubard 640:c90ae1400bf2 517 typedef struct { /*!< SPIS Structure */
Vincent Coubard 640:c90ae1400bf2 518 __I uint32_t RESERVED0[9];
Vincent Coubard 640:c90ae1400bf2 519 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
Vincent Coubard 640:c90ae1400bf2 520 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
Vincent Coubard 640:c90ae1400bf2 521 __I uint32_t RESERVED1[54];
Vincent Coubard 640:c90ae1400bf2 522 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
Vincent Coubard 640:c90ae1400bf2 523 __I uint32_t RESERVED2[2];
Vincent Coubard 640:c90ae1400bf2 524 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
Vincent Coubard 640:c90ae1400bf2 525 __I uint32_t RESERVED3[5];
Vincent Coubard 640:c90ae1400bf2 526 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
Vincent Coubard 640:c90ae1400bf2 527 __I uint32_t RESERVED4[53];
Vincent Coubard 640:c90ae1400bf2 528 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
Vincent Coubard 640:c90ae1400bf2 529 __I uint32_t RESERVED5[64];
Vincent Coubard 640:c90ae1400bf2 530 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 531 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 532 __I uint32_t RESERVED6[61];
Vincent Coubard 640:c90ae1400bf2 533 __I uint32_t SEMSTAT; /*!< Semaphore status. */
Vincent Coubard 640:c90ae1400bf2 534 __I uint32_t RESERVED7[15];
Vincent Coubard 640:c90ae1400bf2 535 __IO uint32_t STATUS; /*!< Status from last transaction. */
Vincent Coubard 640:c90ae1400bf2 536 __I uint32_t RESERVED8[47];
Vincent Coubard 640:c90ae1400bf2 537 __IO uint32_t ENABLE; /*!< Enable SPIS. */
Vincent Coubard 640:c90ae1400bf2 538 __I uint32_t RESERVED9;
Vincent Coubard 640:c90ae1400bf2 539 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Vincent Coubard 640:c90ae1400bf2 540 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Vincent Coubard 640:c90ae1400bf2 541 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Vincent Coubard 640:c90ae1400bf2 542 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
Vincent Coubard 640:c90ae1400bf2 543 __I uint32_t RESERVED10[7];
Vincent Coubard 640:c90ae1400bf2 544 __IO uint32_t RXDPTR; /*!< RX data pointer. */
Vincent Coubard 640:c90ae1400bf2 545 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
Vincent Coubard 640:c90ae1400bf2 546 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
Vincent Coubard 640:c90ae1400bf2 547 __I uint32_t RESERVED11;
Vincent Coubard 640:c90ae1400bf2 548 __IO uint32_t TXDPTR; /*!< TX data pointer. */
Vincent Coubard 640:c90ae1400bf2 549 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
Vincent Coubard 640:c90ae1400bf2 550 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
Vincent Coubard 640:c90ae1400bf2 551 __I uint32_t RESERVED12;
Vincent Coubard 640:c90ae1400bf2 552 __IO uint32_t CONFIG; /*!< Configuration register. */
Vincent Coubard 640:c90ae1400bf2 553 __I uint32_t RESERVED13;
Vincent Coubard 640:c90ae1400bf2 554 __IO uint32_t DEF; /*!< Default character. */
Vincent Coubard 640:c90ae1400bf2 555 __I uint32_t RESERVED14[24];
Vincent Coubard 640:c90ae1400bf2 556 __IO uint32_t ORC; /*!< Over-read character. */
Vincent Coubard 640:c90ae1400bf2 557 __I uint32_t RESERVED15[654];
Vincent Coubard 640:c90ae1400bf2 558 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 559 } NRF_SPIS_Type;
Vincent Coubard 640:c90ae1400bf2 560
Vincent Coubard 640:c90ae1400bf2 561
Vincent Coubard 640:c90ae1400bf2 562 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 563 /* ================ SPIM ================ */
Vincent Coubard 640:c90ae1400bf2 564 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 565
Vincent Coubard 640:c90ae1400bf2 566
Vincent Coubard 640:c90ae1400bf2 567 /**
Vincent Coubard 640:c90ae1400bf2 568 * @brief SPI master with easyDMA 1. (SPIM)
Vincent Coubard 640:c90ae1400bf2 569 */
Vincent Coubard 640:c90ae1400bf2 570
Vincent Coubard 640:c90ae1400bf2 571 typedef struct { /*!< SPIM Structure */
Vincent Coubard 640:c90ae1400bf2 572 __I uint32_t RESERVED0[4];
Vincent Coubard 640:c90ae1400bf2 573 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
Vincent Coubard 640:c90ae1400bf2 574 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
Vincent Coubard 640:c90ae1400bf2 575 __I uint32_t RESERVED1;
Vincent Coubard 640:c90ae1400bf2 576 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
Vincent Coubard 640:c90ae1400bf2 577 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
Vincent Coubard 640:c90ae1400bf2 578 __I uint32_t RESERVED2[56];
Vincent Coubard 640:c90ae1400bf2 579 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
Vincent Coubard 640:c90ae1400bf2 580 __I uint32_t RESERVED3[2];
Vincent Coubard 640:c90ae1400bf2 581 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
Vincent Coubard 640:c90ae1400bf2 582 __I uint32_t RESERVED4[3];
Vincent Coubard 640:c90ae1400bf2 583 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
Vincent Coubard 640:c90ae1400bf2 584 __I uint32_t RESERVED5[10];
Vincent Coubard 640:c90ae1400bf2 585 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
Vincent Coubard 640:c90ae1400bf2 586 __I uint32_t RESERVED6[109];
Vincent Coubard 640:c90ae1400bf2 587 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 588 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 589 __I uint32_t RESERVED7[125];
Vincent Coubard 640:c90ae1400bf2 590 __IO uint32_t ENABLE; /*!< Enable SPIM. */
Vincent Coubard 640:c90ae1400bf2 591 __I uint32_t RESERVED8;
Vincent Coubard 640:c90ae1400bf2 592 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
Vincent Coubard 640:c90ae1400bf2 593 __I uint32_t RESERVED9[4];
Vincent Coubard 640:c90ae1400bf2 594 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
Vincent Coubard 640:c90ae1400bf2 595 __I uint32_t RESERVED10[3];
Vincent Coubard 640:c90ae1400bf2 596 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
Vincent Coubard 640:c90ae1400bf2 597 __I uint32_t RESERVED11;
Vincent Coubard 640:c90ae1400bf2 598 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
Vincent Coubard 640:c90ae1400bf2 599 __I uint32_t RESERVED12;
Vincent Coubard 640:c90ae1400bf2 600 __IO uint32_t CONFIG; /*!< Configuration register. */
Vincent Coubard 640:c90ae1400bf2 601 __I uint32_t RESERVED13[26];
Vincent Coubard 640:c90ae1400bf2 602 __IO uint32_t ORC; /*!< Over-read character. */
Vincent Coubard 640:c90ae1400bf2 603 __I uint32_t RESERVED14[654];
Vincent Coubard 640:c90ae1400bf2 604 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 605 } NRF_SPIM_Type;
Vincent Coubard 640:c90ae1400bf2 606
Vincent Coubard 640:c90ae1400bf2 607
Vincent Coubard 640:c90ae1400bf2 608 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 609 /* ================ GPIOTE ================ */
Vincent Coubard 640:c90ae1400bf2 610 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 611
Vincent Coubard 640:c90ae1400bf2 612
Vincent Coubard 640:c90ae1400bf2 613 /**
Vincent Coubard 640:c90ae1400bf2 614 * @brief GPIO tasks and events. (GPIOTE)
Vincent Coubard 640:c90ae1400bf2 615 */
Vincent Coubard 640:c90ae1400bf2 616
Vincent Coubard 640:c90ae1400bf2 617 typedef struct { /*!< GPIOTE Structure */
Vincent Coubard 640:c90ae1400bf2 618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
Vincent Coubard 640:c90ae1400bf2 619 __I uint32_t RESERVED0[60];
Vincent Coubard 640:c90ae1400bf2 620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
Vincent Coubard 640:c90ae1400bf2 621 __I uint32_t RESERVED1[27];
Vincent Coubard 640:c90ae1400bf2 622 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
Vincent Coubard 640:c90ae1400bf2 623 __I uint32_t RESERVED2[97];
Vincent Coubard 640:c90ae1400bf2 624 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 625 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 626 __I uint32_t RESERVED3[129];
Vincent Coubard 640:c90ae1400bf2 627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
Vincent Coubard 640:c90ae1400bf2 628 __I uint32_t RESERVED4[695];
Vincent Coubard 640:c90ae1400bf2 629 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 630 } NRF_GPIOTE_Type;
Vincent Coubard 640:c90ae1400bf2 631
Vincent Coubard 640:c90ae1400bf2 632
Vincent Coubard 640:c90ae1400bf2 633 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 634 /* ================ ADC ================ */
Vincent Coubard 640:c90ae1400bf2 635 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 636
Vincent Coubard 640:c90ae1400bf2 637
Vincent Coubard 640:c90ae1400bf2 638 /**
Vincent Coubard 640:c90ae1400bf2 639 * @brief Analog to digital converter. (ADC)
Vincent Coubard 640:c90ae1400bf2 640 */
Vincent Coubard 640:c90ae1400bf2 641
Vincent Coubard 640:c90ae1400bf2 642 typedef struct { /*!< ADC Structure */
Vincent Coubard 640:c90ae1400bf2 643 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
Vincent Coubard 640:c90ae1400bf2 644 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
Vincent Coubard 640:c90ae1400bf2 645 __I uint32_t RESERVED0[62];
Vincent Coubard 640:c90ae1400bf2 646 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
Vincent Coubard 640:c90ae1400bf2 647 __I uint32_t RESERVED1[128];
Vincent Coubard 640:c90ae1400bf2 648 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 649 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 650 __I uint32_t RESERVED2[61];
Vincent Coubard 640:c90ae1400bf2 651 __I uint32_t BUSY; /*!< ADC busy register. */
Vincent Coubard 640:c90ae1400bf2 652 __I uint32_t RESERVED3[63];
Vincent Coubard 640:c90ae1400bf2 653 __IO uint32_t ENABLE; /*!< ADC enable. */
Vincent Coubard 640:c90ae1400bf2 654 __IO uint32_t CONFIG; /*!< ADC configuration register. */
Vincent Coubard 640:c90ae1400bf2 655 __I uint32_t RESULT; /*!< Result of ADC conversion. */
Vincent Coubard 640:c90ae1400bf2 656 __I uint32_t RESERVED4[700];
Vincent Coubard 640:c90ae1400bf2 657 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 658 } NRF_ADC_Type;
Vincent Coubard 640:c90ae1400bf2 659
Vincent Coubard 640:c90ae1400bf2 660
Vincent Coubard 640:c90ae1400bf2 661 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 662 /* ================ TIMER ================ */
Vincent Coubard 640:c90ae1400bf2 663 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 664
Vincent Coubard 640:c90ae1400bf2 665
Vincent Coubard 640:c90ae1400bf2 666 /**
Vincent Coubard 640:c90ae1400bf2 667 * @brief Timer 0. (TIMER)
Vincent Coubard 640:c90ae1400bf2 668 */
Vincent Coubard 640:c90ae1400bf2 669
Vincent Coubard 640:c90ae1400bf2 670 typedef struct { /*!< TIMER Structure */
Vincent Coubard 640:c90ae1400bf2 671 __O uint32_t TASKS_START; /*!< Start Timer. */
Vincent Coubard 640:c90ae1400bf2 672 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
Vincent Coubard 640:c90ae1400bf2 673 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
Vincent Coubard 640:c90ae1400bf2 674 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
Vincent Coubard 640:c90ae1400bf2 675 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
Vincent Coubard 640:c90ae1400bf2 676 __I uint32_t RESERVED0[11];
Vincent Coubard 640:c90ae1400bf2 677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
Vincent Coubard 640:c90ae1400bf2 678 __I uint32_t RESERVED1[60];
Vincent Coubard 640:c90ae1400bf2 679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Vincent Coubard 640:c90ae1400bf2 680 __I uint32_t RESERVED2[44];
Vincent Coubard 640:c90ae1400bf2 681 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
Vincent Coubard 640:c90ae1400bf2 682 __I uint32_t RESERVED3[64];
Vincent Coubard 640:c90ae1400bf2 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 685 __I uint32_t RESERVED4[126];
Vincent Coubard 640:c90ae1400bf2 686 __IO uint32_t MODE; /*!< Timer Mode selection. */
Vincent Coubard 640:c90ae1400bf2 687 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
Vincent Coubard 640:c90ae1400bf2 688 __I uint32_t RESERVED5;
Vincent Coubard 640:c90ae1400bf2 689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
Vincent Coubard 640:c90ae1400bf2 690 clock frequency is divided by 2^SCALE. */
Vincent Coubard 640:c90ae1400bf2 691 __I uint32_t RESERVED6[11];
Vincent Coubard 640:c90ae1400bf2 692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Vincent Coubard 640:c90ae1400bf2 693 __I uint32_t RESERVED7[683];
Vincent Coubard 640:c90ae1400bf2 694 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 695 } NRF_TIMER_Type;
Vincent Coubard 640:c90ae1400bf2 696
Vincent Coubard 640:c90ae1400bf2 697
Vincent Coubard 640:c90ae1400bf2 698 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 699 /* ================ RTC ================ */
Vincent Coubard 640:c90ae1400bf2 700 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 701
Vincent Coubard 640:c90ae1400bf2 702
Vincent Coubard 640:c90ae1400bf2 703 /**
Vincent Coubard 640:c90ae1400bf2 704 * @brief Real time counter 0. (RTC)
Vincent Coubard 640:c90ae1400bf2 705 */
Vincent Coubard 640:c90ae1400bf2 706
Vincent Coubard 640:c90ae1400bf2 707 typedef struct { /*!< RTC Structure */
Vincent Coubard 640:c90ae1400bf2 708 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
Vincent Coubard 640:c90ae1400bf2 709 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
Vincent Coubard 640:c90ae1400bf2 710 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
Vincent Coubard 640:c90ae1400bf2 711 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
Vincent Coubard 640:c90ae1400bf2 712 __I uint32_t RESERVED0[60];
Vincent Coubard 640:c90ae1400bf2 713 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
Vincent Coubard 640:c90ae1400bf2 714 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
Vincent Coubard 640:c90ae1400bf2 715 __I uint32_t RESERVED1[14];
Vincent Coubard 640:c90ae1400bf2 716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Vincent Coubard 640:c90ae1400bf2 717 __I uint32_t RESERVED2[109];
Vincent Coubard 640:c90ae1400bf2 718 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 719 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 720 __I uint32_t RESERVED3[13];
Vincent Coubard 640:c90ae1400bf2 721 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
Vincent Coubard 640:c90ae1400bf2 722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
Vincent Coubard 640:c90ae1400bf2 723 the value of EVTEN. */
Vincent Coubard 640:c90ae1400bf2 724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
Vincent Coubard 640:c90ae1400bf2 725 gives the value of EVTEN. */
Vincent Coubard 640:c90ae1400bf2 726 __I uint32_t RESERVED4[110];
Vincent Coubard 640:c90ae1400bf2 727 __I uint32_t COUNTER; /*!< Current COUNTER value. */
Vincent Coubard 640:c90ae1400bf2 728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
Vincent Coubard 640:c90ae1400bf2 729 Must be written when RTC is STOPed. */
Vincent Coubard 640:c90ae1400bf2 730 __I uint32_t RESERVED5[13];
Vincent Coubard 640:c90ae1400bf2 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Vincent Coubard 640:c90ae1400bf2 732 __I uint32_t RESERVED6[683];
Vincent Coubard 640:c90ae1400bf2 733 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 734 } NRF_RTC_Type;
Vincent Coubard 640:c90ae1400bf2 735
Vincent Coubard 640:c90ae1400bf2 736
Vincent Coubard 640:c90ae1400bf2 737 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 738 /* ================ TEMP ================ */
Vincent Coubard 640:c90ae1400bf2 739 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 740
Vincent Coubard 640:c90ae1400bf2 741
Vincent Coubard 640:c90ae1400bf2 742 /**
Vincent Coubard 640:c90ae1400bf2 743 * @brief Temperature Sensor. (TEMP)
Vincent Coubard 640:c90ae1400bf2 744 */
Vincent Coubard 640:c90ae1400bf2 745
Vincent Coubard 640:c90ae1400bf2 746 typedef struct { /*!< TEMP Structure */
Vincent Coubard 640:c90ae1400bf2 747 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
Vincent Coubard 640:c90ae1400bf2 748 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
Vincent Coubard 640:c90ae1400bf2 749 __I uint32_t RESERVED0[62];
Vincent Coubard 640:c90ae1400bf2 750 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
Vincent Coubard 640:c90ae1400bf2 751 __I uint32_t RESERVED1[128];
Vincent Coubard 640:c90ae1400bf2 752 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 753 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 754 __I uint32_t RESERVED2[127];
Vincent Coubard 640:c90ae1400bf2 755 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
Vincent Coubard 640:c90ae1400bf2 756 __I uint32_t RESERVED3[700];
Vincent Coubard 640:c90ae1400bf2 757 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 758 } NRF_TEMP_Type;
Vincent Coubard 640:c90ae1400bf2 759
Vincent Coubard 640:c90ae1400bf2 760
Vincent Coubard 640:c90ae1400bf2 761 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 762 /* ================ RNG ================ */
Vincent Coubard 640:c90ae1400bf2 763 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 764
Vincent Coubard 640:c90ae1400bf2 765
Vincent Coubard 640:c90ae1400bf2 766 /**
Vincent Coubard 640:c90ae1400bf2 767 * @brief Random Number Generator. (RNG)
Vincent Coubard 640:c90ae1400bf2 768 */
Vincent Coubard 640:c90ae1400bf2 769
Vincent Coubard 640:c90ae1400bf2 770 typedef struct { /*!< RNG Structure */
Vincent Coubard 640:c90ae1400bf2 771 __O uint32_t TASKS_START; /*!< Start the random number generator. */
Vincent Coubard 640:c90ae1400bf2 772 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
Vincent Coubard 640:c90ae1400bf2 773 __I uint32_t RESERVED0[62];
Vincent Coubard 640:c90ae1400bf2 774 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
Vincent Coubard 640:c90ae1400bf2 775 __I uint32_t RESERVED1[63];
Vincent Coubard 640:c90ae1400bf2 776 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
Vincent Coubard 640:c90ae1400bf2 777 __I uint32_t RESERVED2[64];
Vincent Coubard 640:c90ae1400bf2 778 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
Vincent Coubard 640:c90ae1400bf2 779 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
Vincent Coubard 640:c90ae1400bf2 780 __I uint32_t RESERVED3[126];
Vincent Coubard 640:c90ae1400bf2 781 __IO uint32_t CONFIG; /*!< Configuration register. */
Vincent Coubard 640:c90ae1400bf2 782 __I uint32_t VALUE; /*!< RNG random number. */
Vincent Coubard 640:c90ae1400bf2 783 __I uint32_t RESERVED4[700];
Vincent Coubard 640:c90ae1400bf2 784 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 785 } NRF_RNG_Type;
Vincent Coubard 640:c90ae1400bf2 786
Vincent Coubard 640:c90ae1400bf2 787
Vincent Coubard 640:c90ae1400bf2 788 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 789 /* ================ ECB ================ */
Vincent Coubard 640:c90ae1400bf2 790 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 791
Vincent Coubard 640:c90ae1400bf2 792
Vincent Coubard 640:c90ae1400bf2 793 /**
Vincent Coubard 640:c90ae1400bf2 794 * @brief AES ECB Mode Encryption. (ECB)
Vincent Coubard 640:c90ae1400bf2 795 */
Vincent Coubard 640:c90ae1400bf2 796
Vincent Coubard 640:c90ae1400bf2 797 typedef struct { /*!< ECB Structure */
Vincent Coubard 640:c90ae1400bf2 798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
Vincent Coubard 640:c90ae1400bf2 799 will not initiate a new encryption and the ERRORECB event will
Vincent Coubard 640:c90ae1400bf2 800 be triggered. */
Vincent Coubard 640:c90ae1400bf2 801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
Vincent Coubard 640:c90ae1400bf2 802 this will will trigger the ERRORECB event. */
Vincent Coubard 640:c90ae1400bf2 803 __I uint32_t RESERVED0[62];
Vincent Coubard 640:c90ae1400bf2 804 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
Vincent Coubard 640:c90ae1400bf2 805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
Vincent Coubard 640:c90ae1400bf2 806 error. */
Vincent Coubard 640:c90ae1400bf2 807 __I uint32_t RESERVED1[127];
Vincent Coubard 640:c90ae1400bf2 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 810 __I uint32_t RESERVED2[126];
Vincent Coubard 640:c90ae1400bf2 811 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
Vincent Coubard 640:c90ae1400bf2 812 __I uint32_t RESERVED3[701];
Vincent Coubard 640:c90ae1400bf2 813 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 814 } NRF_ECB_Type;
Vincent Coubard 640:c90ae1400bf2 815
Vincent Coubard 640:c90ae1400bf2 816
Vincent Coubard 640:c90ae1400bf2 817 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 818 /* ================ AAR ================ */
Vincent Coubard 640:c90ae1400bf2 819 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 820
Vincent Coubard 640:c90ae1400bf2 821
Vincent Coubard 640:c90ae1400bf2 822 /**
Vincent Coubard 640:c90ae1400bf2 823 * @brief Accelerated Address Resolver. (AAR)
Vincent Coubard 640:c90ae1400bf2 824 */
Vincent Coubard 640:c90ae1400bf2 825
Vincent Coubard 640:c90ae1400bf2 826 typedef struct { /*!< AAR Structure */
Vincent Coubard 640:c90ae1400bf2 827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Vincent Coubard 640:c90ae1400bf2 828 data structure. */
Vincent Coubard 640:c90ae1400bf2 829 __I uint32_t RESERVED0;
Vincent Coubard 640:c90ae1400bf2 830 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
Vincent Coubard 640:c90ae1400bf2 831 __I uint32_t RESERVED1[61];
Vincent Coubard 640:c90ae1400bf2 832 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
Vincent Coubard 640:c90ae1400bf2 833 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
Vincent Coubard 640:c90ae1400bf2 834 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
Vincent Coubard 640:c90ae1400bf2 835 __I uint32_t RESERVED2[126];
Vincent Coubard 640:c90ae1400bf2 836 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 837 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 838 __I uint32_t RESERVED3[61];
Vincent Coubard 640:c90ae1400bf2 839 __I uint32_t STATUS; /*!< Resolution status. */
Vincent Coubard 640:c90ae1400bf2 840 __I uint32_t RESERVED4[63];
Vincent Coubard 640:c90ae1400bf2 841 __IO uint32_t ENABLE; /*!< Enable AAR. */
Vincent Coubard 640:c90ae1400bf2 842 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
Vincent Coubard 640:c90ae1400bf2 843 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
Vincent Coubard 640:c90ae1400bf2 844 __I uint32_t RESERVED5;
Vincent Coubard 640:c90ae1400bf2 845 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
Vincent Coubard 640:c90ae1400bf2 846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Vincent Coubard 640:c90ae1400bf2 847 during resolution. A minimum of 3 bytes must be reserved. */
Vincent Coubard 640:c90ae1400bf2 848 __I uint32_t RESERVED6[697];
Vincent Coubard 640:c90ae1400bf2 849 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 850 } NRF_AAR_Type;
Vincent Coubard 640:c90ae1400bf2 851
Vincent Coubard 640:c90ae1400bf2 852
Vincent Coubard 640:c90ae1400bf2 853 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 854 /* ================ CCM ================ */
Vincent Coubard 640:c90ae1400bf2 855 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 856
Vincent Coubard 640:c90ae1400bf2 857
Vincent Coubard 640:c90ae1400bf2 858 /**
Vincent Coubard 640:c90ae1400bf2 859 * @brief AES CCM Mode Encryption. (CCM)
Vincent Coubard 640:c90ae1400bf2 860 */
Vincent Coubard 640:c90ae1400bf2 861
Vincent Coubard 640:c90ae1400bf2 862 typedef struct { /*!< CCM Structure */
Vincent Coubard 640:c90ae1400bf2 863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Vincent Coubard 640:c90ae1400bf2 864 itself when completed. */
Vincent Coubard 640:c90ae1400bf2 865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
Vincent Coubard 640:c90ae1400bf2 866 completed. */
Vincent Coubard 640:c90ae1400bf2 867 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
Vincent Coubard 640:c90ae1400bf2 868 __I uint32_t RESERVED0[61];
Vincent Coubard 640:c90ae1400bf2 869 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
Vincent Coubard 640:c90ae1400bf2 870 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
Vincent Coubard 640:c90ae1400bf2 871 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
Vincent Coubard 640:c90ae1400bf2 872 __I uint32_t RESERVED1[61];
Vincent Coubard 640:c90ae1400bf2 873 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
Vincent Coubard 640:c90ae1400bf2 874 __I uint32_t RESERVED2[64];
Vincent Coubard 640:c90ae1400bf2 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 877 __I uint32_t RESERVED3[61];
Vincent Coubard 640:c90ae1400bf2 878 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
Vincent Coubard 640:c90ae1400bf2 879 __I uint32_t RESERVED4[63];
Vincent Coubard 640:c90ae1400bf2 880 __IO uint32_t ENABLE; /*!< CCM enable. */
Vincent Coubard 640:c90ae1400bf2 881 __IO uint32_t MODE; /*!< Operation mode. */
Vincent Coubard 640:c90ae1400bf2 882 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
Vincent Coubard 640:c90ae1400bf2 883 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
Vincent Coubard 640:c90ae1400bf2 884 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
Vincent Coubard 640:c90ae1400bf2 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Vincent Coubard 640:c90ae1400bf2 886 during resolution. A minimum of 43 bytes must be reserved. */
Vincent Coubard 640:c90ae1400bf2 887 __I uint32_t RESERVED5[697];
Vincent Coubard 640:c90ae1400bf2 888 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 889 } NRF_CCM_Type;
Vincent Coubard 640:c90ae1400bf2 890
Vincent Coubard 640:c90ae1400bf2 891
Vincent Coubard 640:c90ae1400bf2 892 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 893 /* ================ WDT ================ */
Vincent Coubard 640:c90ae1400bf2 894 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 895
Vincent Coubard 640:c90ae1400bf2 896
Vincent Coubard 640:c90ae1400bf2 897 /**
Vincent Coubard 640:c90ae1400bf2 898 * @brief Watchdog Timer. (WDT)
Vincent Coubard 640:c90ae1400bf2 899 */
Vincent Coubard 640:c90ae1400bf2 900
Vincent Coubard 640:c90ae1400bf2 901 typedef struct { /*!< WDT Structure */
Vincent Coubard 640:c90ae1400bf2 902 __O uint32_t TASKS_START; /*!< Start the watchdog. */
Vincent Coubard 640:c90ae1400bf2 903 __I uint32_t RESERVED0[63];
Vincent Coubard 640:c90ae1400bf2 904 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
Vincent Coubard 640:c90ae1400bf2 905 __I uint32_t RESERVED1[128];
Vincent Coubard 640:c90ae1400bf2 906 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 907 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 908 __I uint32_t RESERVED2[61];
Vincent Coubard 640:c90ae1400bf2 909 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
Vincent Coubard 640:c90ae1400bf2 910 __I uint32_t REQSTATUS; /*!< Request status. */
Vincent Coubard 640:c90ae1400bf2 911 __I uint32_t RESERVED3[63];
Vincent Coubard 640:c90ae1400bf2 912 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
Vincent Coubard 640:c90ae1400bf2 913 __IO uint32_t RREN; /*!< Reload request enable. */
Vincent Coubard 640:c90ae1400bf2 914 __IO uint32_t CONFIG; /*!< Configuration register. */
Vincent Coubard 640:c90ae1400bf2 915 __I uint32_t RESERVED4[60];
Vincent Coubard 640:c90ae1400bf2 916 __O uint32_t RR[8]; /*!< Reload requests registers. */
Vincent Coubard 640:c90ae1400bf2 917 __I uint32_t RESERVED5[631];
Vincent Coubard 640:c90ae1400bf2 918 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 919 } NRF_WDT_Type;
Vincent Coubard 640:c90ae1400bf2 920
Vincent Coubard 640:c90ae1400bf2 921
Vincent Coubard 640:c90ae1400bf2 922 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 923 /* ================ QDEC ================ */
Vincent Coubard 640:c90ae1400bf2 924 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 925
Vincent Coubard 640:c90ae1400bf2 926
Vincent Coubard 640:c90ae1400bf2 927 /**
Vincent Coubard 640:c90ae1400bf2 928 * @brief Rotary decoder. (QDEC)
Vincent Coubard 640:c90ae1400bf2 929 */
Vincent Coubard 640:c90ae1400bf2 930
Vincent Coubard 640:c90ae1400bf2 931 typedef struct { /*!< QDEC Structure */
Vincent Coubard 640:c90ae1400bf2 932 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
Vincent Coubard 640:c90ae1400bf2 933 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
Vincent Coubard 640:c90ae1400bf2 934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
Vincent Coubard 640:c90ae1400bf2 935 and clears the ACC registers. */
Vincent Coubard 640:c90ae1400bf2 936 __I uint32_t RESERVED0[61];
Vincent Coubard 640:c90ae1400bf2 937 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
Vincent Coubard 640:c90ae1400bf2 938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
Vincent Coubard 640:c90ae1400bf2 939 ACC register different than zero. */
Vincent Coubard 640:c90ae1400bf2 940 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
Vincent Coubard 640:c90ae1400bf2 941 __I uint32_t RESERVED1[61];
Vincent Coubard 640:c90ae1400bf2 942 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
Vincent Coubard 640:c90ae1400bf2 943 __I uint32_t RESERVED2[64];
Vincent Coubard 640:c90ae1400bf2 944 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 945 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 946 __I uint32_t RESERVED3[125];
Vincent Coubard 640:c90ae1400bf2 947 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
Vincent Coubard 640:c90ae1400bf2 948 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
Vincent Coubard 640:c90ae1400bf2 949 __IO uint32_t SAMPLEPER; /*!< Sample period. */
Vincent Coubard 640:c90ae1400bf2 950 __I int32_t SAMPLE; /*!< Motion sample value. */
Vincent Coubard 640:c90ae1400bf2 951 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
Vincent Coubard 640:c90ae1400bf2 952 __I int32_t ACC; /*!< Accumulated valid transitions register. */
Vincent Coubard 640:c90ae1400bf2 953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
Vincent Coubard 640:c90ae1400bf2 954 task. */
Vincent Coubard 640:c90ae1400bf2 955 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
Vincent Coubard 640:c90ae1400bf2 956 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
Vincent Coubard 640:c90ae1400bf2 957 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
Vincent Coubard 640:c90ae1400bf2 958 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
Vincent Coubard 640:c90ae1400bf2 959 __I uint32_t RESERVED4[5];
Vincent Coubard 640:c90ae1400bf2 960 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
Vincent Coubard 640:c90ae1400bf2 961 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
Vincent Coubard 640:c90ae1400bf2 962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
Vincent Coubard 640:c90ae1400bf2 963 task. */
Vincent Coubard 640:c90ae1400bf2 964 __I uint32_t RESERVED5[684];
Vincent Coubard 640:c90ae1400bf2 965 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 966 } NRF_QDEC_Type;
Vincent Coubard 640:c90ae1400bf2 967
Vincent Coubard 640:c90ae1400bf2 968
Vincent Coubard 640:c90ae1400bf2 969 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 970 /* ================ LPCOMP ================ */
Vincent Coubard 640:c90ae1400bf2 971 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 972
Vincent Coubard 640:c90ae1400bf2 973
Vincent Coubard 640:c90ae1400bf2 974 /**
Vincent Coubard 640:c90ae1400bf2 975 * @brief Low power comparator. (LPCOMP)
Vincent Coubard 640:c90ae1400bf2 976 */
Vincent Coubard 640:c90ae1400bf2 977
Vincent Coubard 640:c90ae1400bf2 978 typedef struct { /*!< LPCOMP Structure */
Vincent Coubard 640:c90ae1400bf2 979 __O uint32_t TASKS_START; /*!< Start the comparator. */
Vincent Coubard 640:c90ae1400bf2 980 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
Vincent Coubard 640:c90ae1400bf2 981 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
Vincent Coubard 640:c90ae1400bf2 982 __I uint32_t RESERVED0[61];
Vincent Coubard 640:c90ae1400bf2 983 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
Vincent Coubard 640:c90ae1400bf2 984 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
Vincent Coubard 640:c90ae1400bf2 985 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
Vincent Coubard 640:c90ae1400bf2 986 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
Vincent Coubard 640:c90ae1400bf2 987 __I uint32_t RESERVED1[60];
Vincent Coubard 640:c90ae1400bf2 988 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
Vincent Coubard 640:c90ae1400bf2 989 __I uint32_t RESERVED2[64];
Vincent Coubard 640:c90ae1400bf2 990 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Vincent Coubard 640:c90ae1400bf2 991 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Vincent Coubard 640:c90ae1400bf2 992 __I uint32_t RESERVED3[61];
Vincent Coubard 640:c90ae1400bf2 993 __I uint32_t RESULT; /*!< Result of last compare. */
Vincent Coubard 640:c90ae1400bf2 994 __I uint32_t RESERVED4[63];
Vincent Coubard 640:c90ae1400bf2 995 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
Vincent Coubard 640:c90ae1400bf2 996 __IO uint32_t PSEL; /*!< Input pin select. */
Vincent Coubard 640:c90ae1400bf2 997 __IO uint32_t REFSEL; /*!< Reference select. */
Vincent Coubard 640:c90ae1400bf2 998 __IO uint32_t EXTREFSEL; /*!< External reference select. */
Vincent Coubard 640:c90ae1400bf2 999 __I uint32_t RESERVED5[4];
Vincent Coubard 640:c90ae1400bf2 1000 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
Vincent Coubard 640:c90ae1400bf2 1001 __I uint32_t RESERVED6[694];
Vincent Coubard 640:c90ae1400bf2 1002 __IO uint32_t POWER; /*!< Peripheral power control. */
Vincent Coubard 640:c90ae1400bf2 1003 } NRF_LPCOMP_Type;
Vincent Coubard 640:c90ae1400bf2 1004
Vincent Coubard 640:c90ae1400bf2 1005
Vincent Coubard 640:c90ae1400bf2 1006 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1007 /* ================ SWI ================ */
Vincent Coubard 640:c90ae1400bf2 1008 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1009
Vincent Coubard 640:c90ae1400bf2 1010
Vincent Coubard 640:c90ae1400bf2 1011 /**
Vincent Coubard 640:c90ae1400bf2 1012 * @brief SW Interrupts. (SWI)
Vincent Coubard 640:c90ae1400bf2 1013 */
Vincent Coubard 640:c90ae1400bf2 1014
Vincent Coubard 640:c90ae1400bf2 1015 typedef struct { /*!< SWI Structure */
Vincent Coubard 640:c90ae1400bf2 1016 __I uint32_t UNUSED; /*!< Unused. */
Vincent Coubard 640:c90ae1400bf2 1017 } NRF_SWI_Type;
Vincent Coubard 640:c90ae1400bf2 1018
Vincent Coubard 640:c90ae1400bf2 1019
Vincent Coubard 640:c90ae1400bf2 1020 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1021 /* ================ NVMC ================ */
Vincent Coubard 640:c90ae1400bf2 1022 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1023
Vincent Coubard 640:c90ae1400bf2 1024
Vincent Coubard 640:c90ae1400bf2 1025 /**
Vincent Coubard 640:c90ae1400bf2 1026 * @brief Non Volatile Memory Controller. (NVMC)
Vincent Coubard 640:c90ae1400bf2 1027 */
Vincent Coubard 640:c90ae1400bf2 1028
Vincent Coubard 640:c90ae1400bf2 1029 typedef struct { /*!< NVMC Structure */
Vincent Coubard 640:c90ae1400bf2 1030 __I uint32_t RESERVED0[256];
Vincent Coubard 640:c90ae1400bf2 1031 __I uint32_t READY; /*!< Ready flag. */
Vincent Coubard 640:c90ae1400bf2 1032 __I uint32_t RESERVED1[64];
Vincent Coubard 640:c90ae1400bf2 1033 __IO uint32_t CONFIG; /*!< Configuration register. */
Vincent Coubard 640:c90ae1400bf2 1034
Vincent Coubard 640:c90ae1400bf2 1035 union {
Vincent Coubard 640:c90ae1400bf2 1036 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
Vincent Coubard 640:c90ae1400bf2 1037 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
Vincent Coubard 640:c90ae1400bf2 1038 };
Vincent Coubard 640:c90ae1400bf2 1039 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
Vincent Coubard 640:c90ae1400bf2 1040 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
Vincent Coubard 640:c90ae1400bf2 1041 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
Vincent Coubard 640:c90ae1400bf2 1042 } NRF_NVMC_Type;
Vincent Coubard 640:c90ae1400bf2 1043
Vincent Coubard 640:c90ae1400bf2 1044
Vincent Coubard 640:c90ae1400bf2 1045 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1046 /* ================ PPI ================ */
Vincent Coubard 640:c90ae1400bf2 1047 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1048
Vincent Coubard 640:c90ae1400bf2 1049
Vincent Coubard 640:c90ae1400bf2 1050 /**
Vincent Coubard 640:c90ae1400bf2 1051 * @brief PPI controller. (PPI)
Vincent Coubard 640:c90ae1400bf2 1052 */
Vincent Coubard 640:c90ae1400bf2 1053
Vincent Coubard 640:c90ae1400bf2 1054 typedef struct { /*!< PPI Structure */
Vincent Coubard 640:c90ae1400bf2 1055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
Vincent Coubard 640:c90ae1400bf2 1056 __I uint32_t RESERVED0[312];
Vincent Coubard 640:c90ae1400bf2 1057 __IO uint32_t CHEN; /*!< Channel enable. */
Vincent Coubard 640:c90ae1400bf2 1058 __IO uint32_t CHENSET; /*!< Channel enable set. */
Vincent Coubard 640:c90ae1400bf2 1059 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
Vincent Coubard 640:c90ae1400bf2 1060 __I uint32_t RESERVED1;
Vincent Coubard 640:c90ae1400bf2 1061 PPI_CH_Type CH[16]; /*!< PPI Channel. */
Vincent Coubard 640:c90ae1400bf2 1062 __I uint32_t RESERVED2[156];
Vincent Coubard 640:c90ae1400bf2 1063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
Vincent Coubard 640:c90ae1400bf2 1064 } NRF_PPI_Type;
Vincent Coubard 640:c90ae1400bf2 1065
Vincent Coubard 640:c90ae1400bf2 1066
Vincent Coubard 640:c90ae1400bf2 1067 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1068 /* ================ FICR ================ */
Vincent Coubard 640:c90ae1400bf2 1069 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1070
Vincent Coubard 640:c90ae1400bf2 1071
Vincent Coubard 640:c90ae1400bf2 1072 /**
Vincent Coubard 640:c90ae1400bf2 1073 * @brief Factory Information Configuration. (FICR)
Vincent Coubard 640:c90ae1400bf2 1074 */
Vincent Coubard 640:c90ae1400bf2 1075
Vincent Coubard 640:c90ae1400bf2 1076 typedef struct { /*!< FICR Structure */
Vincent Coubard 640:c90ae1400bf2 1077 __I uint32_t RESERVED0[4];
Vincent Coubard 640:c90ae1400bf2 1078 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
Vincent Coubard 640:c90ae1400bf2 1079 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
Vincent Coubard 640:c90ae1400bf2 1080 __I uint32_t RESERVED1[4];
Vincent Coubard 640:c90ae1400bf2 1081 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
Vincent Coubard 640:c90ae1400bf2 1082 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
Vincent Coubard 640:c90ae1400bf2 1083 __I uint32_t RESERVED2;
Vincent Coubard 640:c90ae1400bf2 1084 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
Vincent Coubard 640:c90ae1400bf2 1085
Vincent Coubard 640:c90ae1400bf2 1086 union {
Vincent Coubard 640:c90ae1400bf2 1087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Vincent Coubard 640:c90ae1400bf2 1088 kept for backward compatinility purposes. Use SIZERAMBLOCKS
Vincent Coubard 640:c90ae1400bf2 1089 instead. */
Vincent Coubard 640:c90ae1400bf2 1090 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
Vincent Coubard 640:c90ae1400bf2 1091 };
Vincent Coubard 640:c90ae1400bf2 1092 __I uint32_t RESERVED3[5];
Vincent Coubard 640:c90ae1400bf2 1093 __I uint32_t CONFIGID; /*!< Configuration identifier. */
Vincent Coubard 640:c90ae1400bf2 1094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
Vincent Coubard 640:c90ae1400bf2 1095 __I uint32_t RESERVED4[6];
Vincent Coubard 640:c90ae1400bf2 1096 __I uint32_t ER[4]; /*!< Encryption root. */
Vincent Coubard 640:c90ae1400bf2 1097 __I uint32_t IR[4]; /*!< Identity root. */
Vincent Coubard 640:c90ae1400bf2 1098 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
Vincent Coubard 640:c90ae1400bf2 1099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
Vincent Coubard 640:c90ae1400bf2 1100 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
Vincent Coubard 640:c90ae1400bf2 1101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Vincent Coubard 640:c90ae1400bf2 1102 mode. */
Vincent Coubard 640:c90ae1400bf2 1103 __I uint32_t RESERVED5[10];
Vincent Coubard 640:c90ae1400bf2 1104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
Vincent Coubard 640:c90ae1400bf2 1105 mode. */
Vincent Coubard 640:c90ae1400bf2 1106 } NRF_FICR_Type;
Vincent Coubard 640:c90ae1400bf2 1107
Vincent Coubard 640:c90ae1400bf2 1108
Vincent Coubard 640:c90ae1400bf2 1109 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1110 /* ================ UICR ================ */
Vincent Coubard 640:c90ae1400bf2 1111 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1112
Vincent Coubard 640:c90ae1400bf2 1113
Vincent Coubard 640:c90ae1400bf2 1114 /**
Vincent Coubard 640:c90ae1400bf2 1115 * @brief User Information Configuration. (UICR)
Vincent Coubard 640:c90ae1400bf2 1116 */
Vincent Coubard 640:c90ae1400bf2 1117
Vincent Coubard 640:c90ae1400bf2 1118 typedef struct { /*!< UICR Structure */
Vincent Coubard 640:c90ae1400bf2 1119 __IO uint32_t CLENR0; /*!< Length of code region 0. */
Vincent Coubard 640:c90ae1400bf2 1120 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
Vincent Coubard 640:c90ae1400bf2 1121 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
Vincent Coubard 640:c90ae1400bf2 1122 __I uint32_t RESERVED0;
Vincent Coubard 640:c90ae1400bf2 1123 __I uint32_t FWID; /*!< Firmware ID. */
Vincent Coubard 640:c90ae1400bf2 1124
Vincent Coubard 640:c90ae1400bf2 1125 union {
Vincent Coubard 640:c90ae1400bf2 1126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
Vincent Coubard 640:c90ae1400bf2 1127 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
Vincent Coubard 640:c90ae1400bf2 1128 };
Vincent Coubard 640:c90ae1400bf2 1129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
Vincent Coubard 640:c90ae1400bf2 1130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
Vincent Coubard 640:c90ae1400bf2 1131 } NRF_UICR_Type;
Vincent Coubard 640:c90ae1400bf2 1132
Vincent Coubard 640:c90ae1400bf2 1133
Vincent Coubard 640:c90ae1400bf2 1134 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1135 /* ================ GPIO ================ */
Vincent Coubard 640:c90ae1400bf2 1136 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1137
Vincent Coubard 640:c90ae1400bf2 1138
Vincent Coubard 640:c90ae1400bf2 1139 /**
Vincent Coubard 640:c90ae1400bf2 1140 * @brief General purpose input and output. (GPIO)
Vincent Coubard 640:c90ae1400bf2 1141 */
Vincent Coubard 640:c90ae1400bf2 1142
Vincent Coubard 640:c90ae1400bf2 1143 typedef struct { /*!< GPIO Structure */
Vincent Coubard 640:c90ae1400bf2 1144 __I uint32_t RESERVED0[321];
Vincent Coubard 640:c90ae1400bf2 1145 __IO uint32_t OUT; /*!< Write GPIO port. */
Vincent Coubard 640:c90ae1400bf2 1146 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
Vincent Coubard 640:c90ae1400bf2 1147 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
Vincent Coubard 640:c90ae1400bf2 1148 __I uint32_t IN; /*!< Read GPIO port. */
Vincent Coubard 640:c90ae1400bf2 1149 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
Vincent Coubard 640:c90ae1400bf2 1150 __IO uint32_t DIRSET; /*!< DIR set register. */
Vincent Coubard 640:c90ae1400bf2 1151 __IO uint32_t DIRCLR; /*!< DIR clear register. */
Vincent Coubard 640:c90ae1400bf2 1152 __I uint32_t RESERVED1[120];
Vincent Coubard 640:c90ae1400bf2 1153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
Vincent Coubard 640:c90ae1400bf2 1154 } NRF_GPIO_Type;
Vincent Coubard 640:c90ae1400bf2 1155
Vincent Coubard 640:c90ae1400bf2 1156
Vincent Coubard 640:c90ae1400bf2 1157 /* -------------------- End of section using anonymous unions ------------------- */
Vincent Coubard 640:c90ae1400bf2 1158 #if defined(__CC_ARM)
Vincent Coubard 640:c90ae1400bf2 1159 #pragma pop
Vincent Coubard 640:c90ae1400bf2 1160 #elif defined(__ICCARM__)
Vincent Coubard 640:c90ae1400bf2 1161 /* leave anonymous unions enabled */
Vincent Coubard 640:c90ae1400bf2 1162 #elif defined(__GNUC__)
Vincent Coubard 640:c90ae1400bf2 1163 /* anonymous unions are enabled by default */
Vincent Coubard 640:c90ae1400bf2 1164 #elif defined(__TMS470__)
Vincent Coubard 640:c90ae1400bf2 1165 /* anonymous unions are enabled by default */
Vincent Coubard 640:c90ae1400bf2 1166 #elif defined(__TASKING__)
Vincent Coubard 640:c90ae1400bf2 1167 #pragma warning restore
Vincent Coubard 640:c90ae1400bf2 1168 #else
Vincent Coubard 640:c90ae1400bf2 1169 #warning Not supported compiler type
Vincent Coubard 640:c90ae1400bf2 1170 #endif
Vincent Coubard 640:c90ae1400bf2 1171
Vincent Coubard 640:c90ae1400bf2 1172
Vincent Coubard 640:c90ae1400bf2 1173
Vincent Coubard 640:c90ae1400bf2 1174
Vincent Coubard 640:c90ae1400bf2 1175 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1176 /* ================ Peripheral memory map ================ */
Vincent Coubard 640:c90ae1400bf2 1177 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1178
Vincent Coubard 640:c90ae1400bf2 1179 #define NRF_POWER_BASE 0x40000000UL
Vincent Coubard 640:c90ae1400bf2 1180 #define NRF_CLOCK_BASE 0x40000000UL
Vincent Coubard 640:c90ae1400bf2 1181 #define NRF_MPU_BASE 0x40000000UL
Vincent Coubard 640:c90ae1400bf2 1182 #define NRF_AMLI_BASE 0x40000000UL
Vincent Coubard 640:c90ae1400bf2 1183 #define NRF_RADIO_BASE 0x40001000UL
Vincent Coubard 640:c90ae1400bf2 1184 #define NRF_UART0_BASE 0x40002000UL
Vincent Coubard 640:c90ae1400bf2 1185 #define NRF_SPI0_BASE 0x40003000UL
Vincent Coubard 640:c90ae1400bf2 1186 #define NRF_TWI0_BASE 0x40003000UL
Vincent Coubard 640:c90ae1400bf2 1187 #define NRF_SPI1_BASE 0x40004000UL
Vincent Coubard 640:c90ae1400bf2 1188 #define NRF_TWI1_BASE 0x40004000UL
Vincent Coubard 640:c90ae1400bf2 1189 #define NRF_SPIS1_BASE 0x40004000UL
Vincent Coubard 640:c90ae1400bf2 1190 #define NRF_SPIM1_BASE 0x40004000UL
Vincent Coubard 640:c90ae1400bf2 1191 #define NRF_GPIOTE_BASE 0x40006000UL
Vincent Coubard 640:c90ae1400bf2 1192 #define NRF_ADC_BASE 0x40007000UL
Vincent Coubard 640:c90ae1400bf2 1193 #define NRF_TIMER0_BASE 0x40008000UL
Vincent Coubard 640:c90ae1400bf2 1194 #define NRF_TIMER1_BASE 0x40009000UL
Vincent Coubard 640:c90ae1400bf2 1195 #define NRF_TIMER2_BASE 0x4000A000UL
Vincent Coubard 640:c90ae1400bf2 1196 #define NRF_RTC0_BASE 0x4000B000UL
Vincent Coubard 640:c90ae1400bf2 1197 #define NRF_TEMP_BASE 0x4000C000UL
Vincent Coubard 640:c90ae1400bf2 1198 #define NRF_RNG_BASE 0x4000D000UL
Vincent Coubard 640:c90ae1400bf2 1199 #define NRF_ECB_BASE 0x4000E000UL
Vincent Coubard 640:c90ae1400bf2 1200 #define NRF_AAR_BASE 0x4000F000UL
Vincent Coubard 640:c90ae1400bf2 1201 #define NRF_CCM_BASE 0x4000F000UL
Vincent Coubard 640:c90ae1400bf2 1202 #define NRF_WDT_BASE 0x40010000UL
Vincent Coubard 640:c90ae1400bf2 1203 #define NRF_RTC1_BASE 0x40011000UL
Vincent Coubard 640:c90ae1400bf2 1204 #define NRF_QDEC_BASE 0x40012000UL
Vincent Coubard 640:c90ae1400bf2 1205 #define NRF_LPCOMP_BASE 0x40013000UL
Vincent Coubard 640:c90ae1400bf2 1206 #define NRF_SWI_BASE 0x40014000UL
Vincent Coubard 640:c90ae1400bf2 1207 #define NRF_NVMC_BASE 0x4001E000UL
Vincent Coubard 640:c90ae1400bf2 1208 #define NRF_PPI_BASE 0x4001F000UL
Vincent Coubard 640:c90ae1400bf2 1209 #define NRF_FICR_BASE 0x10000000UL
Vincent Coubard 640:c90ae1400bf2 1210 #define NRF_UICR_BASE 0x10001000UL
Vincent Coubard 640:c90ae1400bf2 1211 #define NRF_GPIO_BASE 0x50000000UL
Vincent Coubard 640:c90ae1400bf2 1212
Vincent Coubard 640:c90ae1400bf2 1213
Vincent Coubard 640:c90ae1400bf2 1214 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1215 /* ================ Peripheral declaration ================ */
Vincent Coubard 640:c90ae1400bf2 1216 /* ================================================================================ */
Vincent Coubard 640:c90ae1400bf2 1217
Vincent Coubard 640:c90ae1400bf2 1218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Vincent Coubard 640:c90ae1400bf2 1219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Vincent Coubard 640:c90ae1400bf2 1220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
Vincent Coubard 640:c90ae1400bf2 1221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Vincent Coubard 640:c90ae1400bf2 1222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Vincent Coubard 640:c90ae1400bf2 1223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Vincent Coubard 640:c90ae1400bf2 1224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Vincent Coubard 640:c90ae1400bf2 1225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Vincent Coubard 640:c90ae1400bf2 1226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Vincent Coubard 640:c90ae1400bf2 1227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Vincent Coubard 640:c90ae1400bf2 1228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Vincent Coubard 640:c90ae1400bf2 1229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
Vincent Coubard 640:c90ae1400bf2 1230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Vincent Coubard 640:c90ae1400bf2 1231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
Vincent Coubard 640:c90ae1400bf2 1232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Vincent Coubard 640:c90ae1400bf2 1233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Vincent Coubard 640:c90ae1400bf2 1234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Vincent Coubard 640:c90ae1400bf2 1235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Vincent Coubard 640:c90ae1400bf2 1236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Vincent Coubard 640:c90ae1400bf2 1237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Vincent Coubard 640:c90ae1400bf2 1238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Vincent Coubard 640:c90ae1400bf2 1239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Vincent Coubard 640:c90ae1400bf2 1240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Vincent Coubard 640:c90ae1400bf2 1241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Vincent Coubard 640:c90ae1400bf2 1242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Vincent Coubard 640:c90ae1400bf2 1243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Vincent Coubard 640:c90ae1400bf2 1244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Vincent Coubard 640:c90ae1400bf2 1245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
Vincent Coubard 640:c90ae1400bf2 1246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Vincent Coubard 640:c90ae1400bf2 1247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Vincent Coubard 640:c90ae1400bf2 1248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Vincent Coubard 640:c90ae1400bf2 1249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Vincent Coubard 640:c90ae1400bf2 1250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
Vincent Coubard 640:c90ae1400bf2 1251
Vincent Coubard 640:c90ae1400bf2 1252
Vincent Coubard 640:c90ae1400bf2 1253 /** @} */ /* End of group Device_Peripheral_Registers */
Vincent Coubard 640:c90ae1400bf2 1254 /** @} */ /* End of group nrf51 */
Vincent Coubard 640:c90ae1400bf2 1255 /** @} */ /* End of group Nordic Semiconductor */
Vincent Coubard 640:c90ae1400bf2 1256
Vincent Coubard 640:c90ae1400bf2 1257 #ifdef __cplusplus
Vincent Coubard 640:c90ae1400bf2 1258 }
Vincent Coubard 640:c90ae1400bf2 1259 #endif
Vincent Coubard 640:c90ae1400bf2 1260
Vincent Coubard 640:c90ae1400bf2 1261
Vincent Coubard 640:c90ae1400bf2 1262 #endif /* nrf51_H */
Vincent Coubard 640:c90ae1400bf2 1263