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targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@617:d1b257119699, 2015-08-24 (annotated)

Committer:: kaizen
Date:: Mon Aug 24 00:12:39 2015 +0000
Revision:: 617:d1b257119699
Parent:: 294:78f9587bb26d

Added UART_2 of WIZwiki_W7500 for test

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	20:4263a77256ae	1	/*
mbed_official	256:76fd9a263045	2	* LPC43xx/LPC18xx MCU header
bogdanm	20:4263a77256ae	3	*
bogdanm	20:4263a77256ae	4	* Copyright(C) NXP Semiconductors, 2012
bogdanm	20:4263a77256ae	5	* All rights reserved.
bogdanm	20:4263a77256ae	6	*
bogdanm	20:4263a77256ae	7	* Software that is described herein is for illustrative purposes only
bogdanm	20:4263a77256ae	8	* which provides customers with programming information regarding the
bogdanm	20:4263a77256ae	9	* LPC products. This software is supplied "AS IS" without any warranties of
bogdanm	20:4263a77256ae	10	* any kind, and NXP Semiconductors and its licensor disclaim any and
bogdanm	20:4263a77256ae	11	* all warranties, express or implied, including all implied warranties of
bogdanm	20:4263a77256ae	12	* merchantability, fitness for a particular purpose and non-infringement of
bogdanm	20:4263a77256ae	13	* intellectual property rights. NXP Semiconductors assumes no responsibility
bogdanm	20:4263a77256ae	14	* or liability for the use of the software, conveys no license or rights under any
bogdanm	20:4263a77256ae	15	* patent, copyright, mask work right, or any other intellectual property rights in
bogdanm	20:4263a77256ae	16	* or to any products. NXP Semiconductors reserves the right to make changes
bogdanm	20:4263a77256ae	17	* in the software without notification. NXP Semiconductors also makes no
bogdanm	20:4263a77256ae	18	* representation or warranty that such application will be suitable for the
bogdanm	20:4263a77256ae	19	* specified use without further testing or modification.
bogdanm	20:4263a77256ae	20	*
bogdanm	20:4263a77256ae	21	* Permission to use, copy, modify, and distribute this software and its
bogdanm	20:4263a77256ae	22	* documentation is hereby granted, under NXP Semiconductors' and its
bogdanm	20:4263a77256ae	23	* licensor's relevant copyrights in the software, without fee, provided that it
bogdanm	20:4263a77256ae	24	* is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm	20:4263a77256ae	25	* copyright, permission, and disclaimer notice must appear in all copies of
bogdanm	20:4263a77256ae	26	* this code.
bogdanm	20:4263a77256ae	27	*
bogdanm	20:4263a77256ae	28	* Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
mbed_official	256:76fd9a263045	29	* 05/15/13 Micromint USA <support@micromint.com>
bogdanm	20:4263a77256ae	30	*/
bogdanm	20:4263a77256ae	31
bogdanm	20:4263a77256ae	32	#ifndef __LPC43XX_H
bogdanm	20:4263a77256ae	33	#define __LPC43XX_H
bogdanm	20:4263a77256ae	34
bogdanm	20:4263a77256ae	35	#ifdef __cplusplus
bogdanm	20:4263a77256ae	36	extern "C" {
bogdanm	20:4263a77256ae	37	#endif
bogdanm	20:4263a77256ae	38
mbed_official	256:76fd9a263045	39	/* Treat __CORE_Mx as CORE_Mx */
bogdanm	20:4263a77256ae	40	#if defined(__CORTEX_M0) && !defined(CORE_M0)
bogdanm	20:4263a77256ae	41	#define CORE_M0
bogdanm	20:4263a77256ae	42	#endif
bogdanm	20:4263a77256ae	43	#if defined(__CORTEX_M3) && !defined(CORE_M3)
bogdanm	20:4263a77256ae	44	#define CORE_M3
bogdanm	20:4263a77256ae	45	#endif
bogdanm	20:4263a77256ae	46	/* Default to M4 core if no core explicitly declared */
bogdanm	20:4263a77256ae	47	#if !defined(CORE_M0) && !defined(CORE_M3)
bogdanm	20:4263a77256ae	48	#define CORE_M4
bogdanm	20:4263a77256ae	49	#endif
bogdanm	20:4263a77256ae	50
mbed_official	256:76fd9a263045	51	/* Define LPC18XX or LPC43XX according to core type */
mbed_official	256:76fd9a263045	52	#if (defined(CORE_M4) \|\| defined(CORE_M0)) && !defined(__LPC43XX__)
mbed_official	256:76fd9a263045	53	#define __LPC43XX__
mbed_official	256:76fd9a263045	54	#endif
mbed_official	256:76fd9a263045	55	#if defined(CORE_M3) && !defined(__LPC18XX__)
mbed_official	256:76fd9a263045	56	#define __LPC18XX__
mbed_official	256:76fd9a263045	57	#endif
mbed_official	256:76fd9a263045	58
bogdanm	20:4263a77256ae	59	/* Start of section using anonymous unions */
bogdanm	20:4263a77256ae	60	#if defined(__ARMCC_VERSION)
bogdanm	20:4263a77256ae	61	// Kill warning "#pragma push with no matching #pragma pop"
bogdanm	20:4263a77256ae	62	#pragma diag_suppress 2525
bogdanm	20:4263a77256ae	63	#pragma push
bogdanm	20:4263a77256ae	64	#pragma anon_unions
bogdanm	20:4263a77256ae	65	#elif defined(__CWCC__)
bogdanm	20:4263a77256ae	66	#pragma push
bogdanm	20:4263a77256ae	67	#pragma cpp_extensions on
bogdanm	20:4263a77256ae	68	#elif defined(__IAR_SYSTEMS_ICC__)
bogdanm	20:4263a77256ae	69	//#pragma push // FIXME not usable for IAR
bogdanm	20:4263a77256ae	70	#pragma language=extended
bogdanm	20:4263a77256ae	71	#else /* defined(__GNUC__) and others */
bogdanm	20:4263a77256ae	72	/* Assume anonymous unions are enabled by default */
bogdanm	20:4263a77256ae	73	#endif
bogdanm	20:4263a77256ae	74
bogdanm	20:4263a77256ae	75	#if defined(CORE_M4)
mbed_official	256:76fd9a263045	76	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	77	* LPC43xx (M4 Core) Cortex CMSIS definitions
bogdanm	20:4263a77256ae	78	*/
bogdanm	20:4263a77256ae	79
mbed_official	256:76fd9a263045	80	#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
mbed_official	256:76fd9a263045	81	#define __MPU_PRESENT 1 /* MPU present or not */
mbed_official	256:76fd9a263045	82	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
mbed_official	256:76fd9a263045	83	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
mbed_official	256:76fd9a263045	84	#define __FPU_PRESENT 1 /* FPU present or not */
mbed_official	256:76fd9a263045	85	#define CHIP_LPC43XX /* LPCOPEN compatibility */
bogdanm	20:4263a77256ae	86
mbed_official	256:76fd9a263045	87	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	88	* LPC43xx peripheral interrupt numbers
bogdanm	20:4263a77256ae	89	*/
bogdanm	20:4263a77256ae	90
bogdanm	20:4263a77256ae	91	typedef enum {
mbed_official	256:76fd9a263045	92	/* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
mbed_official	256:76fd9a263045	93	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
mbed_official	256:76fd9a263045	94	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
mbed_official	256:76fd9a263045	95	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
mbed_official	256:76fd9a263045	96	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
mbed_official	256:76fd9a263045	97	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
mbed_official	256:76fd9a263045	98	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
mbed_official	256:76fd9a263045	99	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
mbed_official	256:76fd9a263045	100	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
mbed_official	256:76fd9a263045	101	PendSV_IRQn = -2,/* 14 Pendable request for system service */
mbed_official	256:76fd9a263045	102	SysTick_IRQn = -1,/* 15 System Tick Timer */
bogdanm	20:4263a77256ae	103
mbed_official	256:76fd9a263045	104	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
mbed_official	256:76fd9a263045	105	DAC_IRQn = 0,/* 0 DAC */
mbed_official	256:76fd9a263045	106	M0CORE_IRQn = 1,/* 1 M0a */
mbed_official	256:76fd9a263045	107	DMA_IRQn = 2,/* 2 DMA */
mbed_official	256:76fd9a263045	108	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
mbed_official	256:76fd9a263045	109	RESERVED2_IRQn = 4,
mbed_official	256:76fd9a263045	110	ETHERNET_IRQn = 5,/* 5 ETHERNET */
mbed_official	256:76fd9a263045	111	SDIO_IRQn = 6,/* 6 SDIO */
mbed_official	256:76fd9a263045	112	LCD_IRQn = 7,/* 7 LCD */
mbed_official	256:76fd9a263045	113	USB0_IRQn = 8,/* 8 USB0 */
mbed_official	256:76fd9a263045	114	USB1_IRQn = 9,/* 9 USB1 */
mbed_official	256:76fd9a263045	115	SCT_IRQn = 10,/* 10 SCT */
mbed_official	256:76fd9a263045	116	RITIMER_IRQn = 11,/* 11 RITIMER */
mbed_official	256:76fd9a263045	117	TIMER0_IRQn = 12,/* 12 TIMER0 */
mbed_official	256:76fd9a263045	118	TIMER1_IRQn = 13,/* 13 TIMER1 */
mbed_official	256:76fd9a263045	119	TIMER2_IRQn = 14,/* 14 TIMER2 */
mbed_official	256:76fd9a263045	120	TIMER3_IRQn = 15,/* 15 TIMER3 */
mbed_official	256:76fd9a263045	121	MCPWM_IRQn = 16,/* 16 MCPWM */
mbed_official	256:76fd9a263045	122	ADC0_IRQn = 17,/* 17 ADC0 */
mbed_official	256:76fd9a263045	123	I2C0_IRQn = 18,/* 18 I2C0 */
mbed_official	256:76fd9a263045	124	I2C1_IRQn = 19,/* 19 I2C1 */
mbed_official	256:76fd9a263045	125	SPI_INT_IRQn = 20,/* 20 SPI_INT */
mbed_official	256:76fd9a263045	126	ADC1_IRQn = 21,/* 21 ADC1 */
mbed_official	256:76fd9a263045	127	SSP0_IRQn = 22,/* 22 SSP0 */
mbed_official	256:76fd9a263045	128	SSP1_IRQn = 23,/* 23 SSP1 */
mbed_official	256:76fd9a263045	129	USART0_IRQn = 24,/* 24 USART0 */
mbed_official	256:76fd9a263045	130	UART1_IRQn = 25,/* 25 UART1 */
mbed_official	256:76fd9a263045	131	USART2_IRQn = 26,/* 26 USART2 */
mbed_official	256:76fd9a263045	132	USART3_IRQn = 27,/* 27 USART3 */
mbed_official	256:76fd9a263045	133	I2S0_IRQn = 28,/* 28 I2S0 */
mbed_official	256:76fd9a263045	134	I2S1_IRQn = 29,/* 29 I2S1 */
mbed_official	256:76fd9a263045	135	RESERVED4_IRQn = 30,
mbed_official	256:76fd9a263045	136	SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
mbed_official	256:76fd9a263045	137	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
mbed_official	256:76fd9a263045	138	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
mbed_official	256:76fd9a263045	139	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
mbed_official	256:76fd9a263045	140	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
mbed_official	256:76fd9a263045	141	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
mbed_official	256:76fd9a263045	142	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
mbed_official	256:76fd9a263045	143	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
mbed_official	256:76fd9a263045	144	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
mbed_official	256:76fd9a263045	145	GINT0_IRQn = 40,/* 40 GINT0 */
mbed_official	256:76fd9a263045	146	GINT1_IRQn = 41,/* 41 GINT1 */
mbed_official	256:76fd9a263045	147	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
mbed_official	256:76fd9a263045	148	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
mbed_official	256:76fd9a263045	149	RESERVED6_IRQn = 44,
mbed_official	256:76fd9a263045	150	RESERVED7_IRQn = 45,/* 45 VADC */
mbed_official	256:76fd9a263045	151	ATIMER_IRQn = 46,/* 46 ATIMER */
mbed_official	256:76fd9a263045	152	RTC_IRQn = 47,/* 47 RTC */
mbed_official	256:76fd9a263045	153	RESERVED8_IRQn = 48,
mbed_official	256:76fd9a263045	154	WWDT_IRQn = 49,/* 49 WWDT */
mbed_official	256:76fd9a263045	155	RESERVED9_IRQn = 50,
mbed_official	256:76fd9a263045	156	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
mbed_official	256:76fd9a263045	157	QEI_IRQn = 52,/* 52 QEI */
bogdanm	20:4263a77256ae	158	} IRQn_Type;
bogdanm	20:4263a77256ae	159
mbed_official	256:76fd9a263045	160	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
bogdanm	20:4263a77256ae	161
bogdanm	20:4263a77256ae	162	#elif defined(CORE_M3)
mbed_official	256:76fd9a263045	163	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	164	* LPC18xx (M3 Core) Cortex CMSIS definitions
bogdanm	20:4263a77256ae	165	*/
mbed_official	256:76fd9a263045	166	#define __MPU_PRESENT 1 /* MPU present or not */
mbed_official	256:76fd9a263045	167	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
mbed_official	256:76fd9a263045	168	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
mbed_official	256:76fd9a263045	169	#define __FPU_PRESENT 0 /* FPU present or not */
mbed_official	256:76fd9a263045	170	#define CHIP_LPC18XX /* LPCOPEN compatibility */
bogdanm	20:4263a77256ae	171
mbed_official	256:76fd9a263045	172	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	173	* LPC18xx peripheral interrupt numbers
bogdanm	20:4263a77256ae	174	*/
bogdanm	20:4263a77256ae	175
bogdanm	20:4263a77256ae	176	typedef enum {
mbed_official	256:76fd9a263045	177	/* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
mbed_official	256:76fd9a263045	178	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
mbed_official	256:76fd9a263045	179	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
mbed_official	256:76fd9a263045	180	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
mbed_official	256:76fd9a263045	181	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
mbed_official	256:76fd9a263045	182	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
mbed_official	256:76fd9a263045	183	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
mbed_official	256:76fd9a263045	184	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
mbed_official	256:76fd9a263045	185	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
mbed_official	256:76fd9a263045	186	PendSV_IRQn = -2,/* 14 Pendable request for system service */
mbed_official	256:76fd9a263045	187	SysTick_IRQn = -1,/* 15 System Tick Timer */
bogdanm	20:4263a77256ae	188
mbed_official	256:76fd9a263045	189	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
mbed_official	256:76fd9a263045	190	DAC_IRQn = 0,/* 0 DAC */
mbed_official	256:76fd9a263045	191	RESERVED0_IRQn = 1,
mbed_official	256:76fd9a263045	192	DMA_IRQn = 2,/* 2 DMA */
mbed_official	256:76fd9a263045	193	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
mbed_official	256:76fd9a263045	194	RESERVED2_IRQn = 4,
mbed_official	256:76fd9a263045	195	ETHERNET_IRQn = 5,/* 5 ETHERNET */
mbed_official	256:76fd9a263045	196	SDIO_IRQn = 6,/* 6 SDIO */
mbed_official	256:76fd9a263045	197	LCD_IRQn = 7,/* 7 LCD */
mbed_official	256:76fd9a263045	198	USB0_IRQn = 8,/* 8 USB0 */
mbed_official	256:76fd9a263045	199	USB1_IRQn = 9,/* 9 USB1 */
mbed_official	256:76fd9a263045	200	SCT_IRQn = 10,/* 10 SCT */
mbed_official	256:76fd9a263045	201	RITIMER_IRQn = 11,/* 11 RITIMER */
mbed_official	256:76fd9a263045	202	TIMER0_IRQn = 12,/* 12 TIMER0 */
mbed_official	256:76fd9a263045	203	TIMER1_IRQn = 13,/* 13 TIMER1 */
mbed_official	256:76fd9a263045	204	TIMER2_IRQn = 14,/* 14 TIMER2 */
mbed_official	256:76fd9a263045	205	TIMER3_IRQn = 15,/* 15 TIMER3 */
mbed_official	256:76fd9a263045	206	MCPWM_IRQn = 16,/* 16 MCPWM */
mbed_official	256:76fd9a263045	207	ADC0_IRQn = 17,/* 17 ADC0 */
mbed_official	256:76fd9a263045	208	I2C0_IRQn = 18,/* 18 I2C0 */
mbed_official	256:76fd9a263045	209	I2C1_IRQn = 19,/* 19 I2C1 */
mbed_official	256:76fd9a263045	210	RESERVED3_IRQn = 20,
mbed_official	256:76fd9a263045	211	ADC1_IRQn = 21,/* 21 ADC1 */
mbed_official	256:76fd9a263045	212	SSP0_IRQn = 22,/* 22 SSP0 */
mbed_official	256:76fd9a263045	213	SSP1_IRQn = 23,/* 23 SSP1 */
mbed_official	256:76fd9a263045	214	USART0_IRQn = 24,/* 24 USART0 */
mbed_official	256:76fd9a263045	215	UART1_IRQn = 25,/* 25 UART1 */
mbed_official	256:76fd9a263045	216	USART2_IRQn = 26,/* 26 USART2 */
mbed_official	256:76fd9a263045	217	USART3_IRQn = 27,/* 27 USART3 */
mbed_official	256:76fd9a263045	218	I2S0_IRQn = 28,/* 28 I2S0 */
mbed_official	256:76fd9a263045	219	I2S1_IRQn = 29,/* 29 I2S1 */
mbed_official	256:76fd9a263045	220	RESERVED4_IRQn = 30,
mbed_official	256:76fd9a263045	221	RESERVED5_IRQn = 31,
mbed_official	256:76fd9a263045	222	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
mbed_official	256:76fd9a263045	223	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
mbed_official	256:76fd9a263045	224	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
mbed_official	256:76fd9a263045	225	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
mbed_official	256:76fd9a263045	226	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
mbed_official	256:76fd9a263045	227	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
mbed_official	256:76fd9a263045	228	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
mbed_official	256:76fd9a263045	229	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
mbed_official	256:76fd9a263045	230	GINT0_IRQn = 40,/* 40 GINT0 */
mbed_official	256:76fd9a263045	231	GINT1_IRQn = 41,/* 41 GINT1 */
mbed_official	256:76fd9a263045	232	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
mbed_official	256:76fd9a263045	233	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
mbed_official	256:76fd9a263045	234	RESERVED6_IRQn = 44,
mbed_official	256:76fd9a263045	235	RESERVED7_IRQn = 45,/* 45 VADC */
mbed_official	256:76fd9a263045	236	ATIMER_IRQn = 46,/* 46 ATIMER */
mbed_official	256:76fd9a263045	237	RTC_IRQn = 47,/* 47 RTC */
mbed_official	256:76fd9a263045	238	RESERVED8_IRQn = 48,
mbed_official	256:76fd9a263045	239	WWDT_IRQn = 49,/* 49 WWDT */
mbed_official	256:76fd9a263045	240	RESERVED9_IRQn = 50,
mbed_official	256:76fd9a263045	241	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
mbed_official	256:76fd9a263045	242	QEI_IRQn = 52,/* 52 QEI */
bogdanm	20:4263a77256ae	243	} IRQn_Type;
bogdanm	20:4263a77256ae	244
mbed_official	256:76fd9a263045	245	#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
bogdanm	20:4263a77256ae	246
bogdanm	20:4263a77256ae	247	#elif defined(CORE_M0)
mbed_official	256:76fd9a263045	248	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	249	* LPC43xx (M0 Core) Cortex CMSIS definitions
bogdanm	20:4263a77256ae	250	*/
bogdanm	20:4263a77256ae	251
mbed_official	256:76fd9a263045	252	#define __MPU_PRESENT 0 /* MPU present or not */
mbed_official	256:76fd9a263045	253	#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
mbed_official	256:76fd9a263045	254	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
mbed_official	256:76fd9a263045	255	#define __FPU_PRESENT 0 /* FPU present or not */
mbed_official	256:76fd9a263045	256	#define CHIP_LPC43XX /* LPCOPEN compatibility */
bogdanm	20:4263a77256ae	257
mbed_official	256:76fd9a263045	258	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	259	* LPC43xx (M0 Core) peripheral interrupt numbers
bogdanm	20:4263a77256ae	260	*/
bogdanm	20:4263a77256ae	261
bogdanm	20:4263a77256ae	262	typedef enum {
mbed_official	256:76fd9a263045	263	/* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
mbed_official	256:76fd9a263045	264	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
mbed_official	256:76fd9a263045	265	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
mbed_official	256:76fd9a263045	266	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
mbed_official	256:76fd9a263045	267	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
mbed_official	256:76fd9a263045	268	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
mbed_official	256:76fd9a263045	269	PendSV_IRQn = -2,/* 14 Pendable request for system service */
mbed_official	256:76fd9a263045	270	SysTick_IRQn = -1,/* 15 System Tick Timer */
bogdanm	20:4263a77256ae	271
mbed_official	256:76fd9a263045	272	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
mbed_official	256:76fd9a263045	273	DAC_IRQn = 0,/* 0 DAC */
mbed_official	256:76fd9a263045	274	M0_M4CORE_IRQn = 1,/* 1 M0a */
mbed_official	256:76fd9a263045	275	DMA_IRQn = 2,/* 2 DMA r */
mbed_official	256:76fd9a263045	276	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
mbed_official	256:76fd9a263045	277	FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
mbed_official	256:76fd9a263045	278	ETHERNET_IRQn = 5,/* 5 ETHERNET */
mbed_official	256:76fd9a263045	279	SDIO_IRQn = 6,/* 6 SDIO */
mbed_official	256:76fd9a263045	280	LCD_IRQn = 7,/* 7 LCD */
mbed_official	256:76fd9a263045	281	USB0_IRQn = 8,/* 8 USB0 */
mbed_official	256:76fd9a263045	282	USB1_IRQn = 9,/* 9 USB1 */
mbed_official	256:76fd9a263045	283	SCT_IRQn = 10,/* 10 SCT */
mbed_official	256:76fd9a263045	284	RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
mbed_official	256:76fd9a263045	285	TIMER0_IRQn = 12,/* 12 TIMER0 */
mbed_official	256:76fd9a263045	286	GINT1_IRQn = 13,/* 13 GINT1 */
mbed_official	256:76fd9a263045	287	PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
mbed_official	256:76fd9a263045	288	TIMER3_IRQn = 15,/* 15 TIMER3 */
mbed_official	256:76fd9a263045	289	MCPWM_IRQn = 16,/* 16 MCPWM */
mbed_official	256:76fd9a263045	290	ADC0_IRQn = 17,/* 17 ADC0 */
mbed_official	256:76fd9a263045	291	I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
mbed_official	256:76fd9a263045	292	SGPIO_INT_IRQn = 19,/* 19 SGPIO */
mbed_official	256:76fd9a263045	293	SPI_INT_IRQn = 20,/* 20 SPI_INT */
mbed_official	256:76fd9a263045	294	ADC1_IRQn = 21,/* 21 ADC1 */
mbed_official	256:76fd9a263045	295	SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
mbed_official	256:76fd9a263045	296	EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
mbed_official	256:76fd9a263045	297	USART0_IRQn = 24,/* 24 USART0 */
mbed_official	256:76fd9a263045	298	UART1_IRQn = 25,/* 25 UART1 */
mbed_official	256:76fd9a263045	299	USART2_IRQn = 26,/* 26 USART2 */
mbed_official	256:76fd9a263045	300	USART3_IRQn = 27,/* 27 USART3 */
mbed_official	256:76fd9a263045	301	I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
mbed_official	256:76fd9a263045	302	C_CAN0_IRQn = 29,/* 29 C_CAN0 */
mbed_official	256:76fd9a263045	303	I2S1_IRQn = 29,/* 29 I2S1 */
mbed_official	256:76fd9a263045	304	RESERVED2_IRQn = 30,
mbed_official	256:76fd9a263045	305	RESERVED3_IRQn = 31,
bogdanm	20:4263a77256ae	306	} IRQn_Type;
bogdanm	20:4263a77256ae	307
mbed_official	256:76fd9a263045	308	#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
bogdanm	20:4263a77256ae	309	#else
bogdanm	20:4263a77256ae	310	#error Please #define CORE_M0, CORE_M3 or CORE_M4
bogdanm	20:4263a77256ae	311	#endif
bogdanm	20:4263a77256ae	312
mbed_official	258:2a0bf79294ef	313	#include "system_LPC43xx.h"
bogdanm	20:4263a77256ae	314
mbed_official	256:76fd9a263045	315	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	316	* State Configurable Timer register block structure
bogdanm	20:4263a77256ae	317	*/
bogdanm	20:4263a77256ae	318	#define LPC_SCT_BASE 0x40000000
mbed_official	256:76fd9a263045	319	#define CONFIG_SCT_nEV (16) /* Number of events */
mbed_official	256:76fd9a263045	320	#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
mbed_official	256:76fd9a263045	321	#define CONFIG_SCT_nOU (16) /* Number of outputs */
bogdanm	20:4263a77256ae	322
bogdanm	20:4263a77256ae	323	typedef struct {
mbed_official	256:76fd9a263045	324	__IO uint32_t CONFIG; /* Configuration Register */
mbed_official	256:76fd9a263045	325	union {
mbed_official	256:76fd9a263045	326	__IO uint32_t CTRL_U; /* Control Register */
mbed_official	256:76fd9a263045	327	struct {
mbed_official	256:76fd9a263045	328	__IO uint16_t CTRL_L; /* Low control register */
mbed_official	256:76fd9a263045	329	__IO uint16_t CTRL_H; /* High control register */
mbed_official	256:76fd9a263045	330	};
bogdanm	20:4263a77256ae	331
mbed_official	256:76fd9a263045	332	};
bogdanm	20:4263a77256ae	333
mbed_official	256:76fd9a263045	334	__IO uint16_t LIMIT_L; /* limit register for counter L */
mbed_official	256:76fd9a263045	335	__IO uint16_t LIMIT_H; /* limit register for counter H */
mbed_official	256:76fd9a263045	336	__IO uint16_t HALT_L; /* halt register for counter L */
mbed_official	256:76fd9a263045	337	__IO uint16_t HALT_H; /* halt register for counter H */
mbed_official	256:76fd9a263045	338	__IO uint16_t STOP_L; /* stop register for counter L */
mbed_official	256:76fd9a263045	339	__IO uint16_t STOP_H; /* stop register for counter H */
mbed_official	256:76fd9a263045	340	__IO uint16_t START_L; /* start register for counter L */
mbed_official	256:76fd9a263045	341	__IO uint16_t START_H; /* start register for counter H */
mbed_official	256:76fd9a263045	342	uint32_t RESERVED1[10]; /* 0x03C reserved */
mbed_official	256:76fd9a263045	343	union {
mbed_official	256:76fd9a263045	344	__IO uint32_t COUNT_U; /* counter register */
mbed_official	256:76fd9a263045	345	struct {
mbed_official	256:76fd9a263045	346	__IO uint16_t COUNT_L; /* counter register for counter L */
mbed_official	256:76fd9a263045	347	__IO uint16_t COUNT_H; /* counter register for counter H */
mbed_official	256:76fd9a263045	348	};
bogdanm	20:4263a77256ae	349
mbed_official	256:76fd9a263045	350	};
bogdanm	20:4263a77256ae	351
mbed_official	256:76fd9a263045	352	__IO uint16_t STATE_L; /* state register for counter L */
mbed_official	256:76fd9a263045	353	__IO uint16_t STATE_H; /* state register for counter H */
mbed_official	256:76fd9a263045	354	__I uint32_t INPUT; /* input register */
mbed_official	256:76fd9a263045	355	__IO uint16_t REGMODE_L; /* match - capture registers mode register L */
mbed_official	256:76fd9a263045	356	__IO uint16_t REGMODE_H; /* match - capture registers mode register H */
mbed_official	256:76fd9a263045	357	__IO uint32_t OUTPUT; /* output register */
mbed_official	256:76fd9a263045	358	__IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
mbed_official	256:76fd9a263045	359	__IO uint32_t RES; /* conflict resolution register */
mbed_official	256:76fd9a263045	360	__IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
mbed_official	256:76fd9a263045	361	__IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
mbed_official	256:76fd9a263045	362	uint32_t RESERVED2[35];
mbed_official	256:76fd9a263045	363	__IO uint32_t EVEN; /* event enable register */
mbed_official	256:76fd9a263045	364	__IO uint32_t EVFLAG; /* event flag register */
mbed_official	256:76fd9a263045	365	__IO uint32_t CONEN; /* conflict enable register */
mbed_official	256:76fd9a263045	366	__IO uint32_t CONFLAG; /* conflict flag register */
mbed_official	256:76fd9a263045	367	union {
mbed_official	256:76fd9a263045	368	__IO union { /* ... Match / Capture value */
mbed_official	256:76fd9a263045	369	uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
mbed_official	256:76fd9a263045	370	struct {
mbed_official	256:76fd9a263045	371	uint16_t L; /* SCTMATCH[i].L Access to L value */
mbed_official	256:76fd9a263045	372	uint16_t H; /* SCTMATCH[i].H Access to H value */
mbed_official	256:76fd9a263045	373	};
bogdanm	20:4263a77256ae	374
mbed_official	256:76fd9a263045	375	} MATCH[CONFIG_SCT_nRG];
bogdanm	20:4263a77256ae	376
mbed_official	256:76fd9a263045	377	__I union {
mbed_official	256:76fd9a263045	378	uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
mbed_official	256:76fd9a263045	379	struct {
mbed_official	256:76fd9a263045	380	uint16_t L; /* SCTCAP[i].L Access to L value */
mbed_official	256:76fd9a263045	381	uint16_t H; /* SCTCAP[i].H Access to H value */
mbed_official	256:76fd9a263045	382	};
bogdanm	20:4263a77256ae	383
mbed_official	256:76fd9a263045	384	} CAP[CONFIG_SCT_nRG];
bogdanm	20:4263a77256ae	385
mbed_official	256:76fd9a263045	386	};
bogdanm	20:4263a77256ae	387
mbed_official	256:76fd9a263045	388	uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
mbed_official	256:76fd9a263045	389	union {
mbed_official	256:76fd9a263045	390	__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
mbed_official	256:76fd9a263045	391	__I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
mbed_official	256:76fd9a263045	392	};
bogdanm	20:4263a77256ae	393
mbed_official	256:76fd9a263045	394	uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
mbed_official	256:76fd9a263045	395	union {
mbed_official	256:76fd9a263045	396	__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
mbed_official	256:76fd9a263045	397	__I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
mbed_official	256:76fd9a263045	398	};
bogdanm	20:4263a77256ae	399
mbed_official	256:76fd9a263045	400	uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
mbed_official	256:76fd9a263045	401	union {
mbed_official	256:76fd9a263045	402	__IO union { /* 0x200-... Match Reload / Capture Control value */
mbed_official	256:76fd9a263045	403	uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
mbed_official	256:76fd9a263045	404	struct {
mbed_official	256:76fd9a263045	405	uint16_t L; /* SCTMATCHREL[i].L Access to L value */
mbed_official	256:76fd9a263045	406	uint16_t H; /* SCTMATCHREL[i].H Access to H value */
mbed_official	256:76fd9a263045	407	};
bogdanm	20:4263a77256ae	408
mbed_official	256:76fd9a263045	409	} MATCHREL[CONFIG_SCT_nRG];
bogdanm	20:4263a77256ae	410
mbed_official	256:76fd9a263045	411	__IO union {
mbed_official	256:76fd9a263045	412	uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
mbed_official	256:76fd9a263045	413	struct {
mbed_official	256:76fd9a263045	414	uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
mbed_official	256:76fd9a263045	415	uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
mbed_official	256:76fd9a263045	416	};
bogdanm	20:4263a77256ae	417
mbed_official	256:76fd9a263045	418	} CAPCTRL[CONFIG_SCT_nRG];
bogdanm	20:4263a77256ae	419
mbed_official	256:76fd9a263045	420	};
bogdanm	20:4263a77256ae	421
mbed_official	256:76fd9a263045	422	uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
mbed_official	256:76fd9a263045	423	union {
mbed_official	256:76fd9a263045	424	__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
mbed_official	256:76fd9a263045	425	__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
mbed_official	256:76fd9a263045	426	};
bogdanm	20:4263a77256ae	427
mbed_official	256:76fd9a263045	428	uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
mbed_official	256:76fd9a263045	429	union {
mbed_official	256:76fd9a263045	430	__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
mbed_official	256:76fd9a263045	431	__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
mbed_official	256:76fd9a263045	432	};
bogdanm	20:4263a77256ae	433
mbed_official	256:76fd9a263045	434	uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
mbed_official	256:76fd9a263045	435	__IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
mbed_official	256:76fd9a263045	436	uint32_t STATE; /* Event State Register */
mbed_official	256:76fd9a263045	437	uint32_t CTRL; /* Event Control Register */
mbed_official	256:76fd9a263045	438	} EVENT[CONFIG_SCT_nEV];
bogdanm	20:4263a77256ae	439
mbed_official	256:76fd9a263045	440	uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
mbed_official	256:76fd9a263045	441	__IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
mbed_official	256:76fd9a263045	442	uint32_t SET; /* Output n Set Register */
mbed_official	256:76fd9a263045	443	uint32_t CLR; /* Output n Clear Register */
mbed_official	256:76fd9a263045	444	} OUT[CONFIG_SCT_nOU];
bogdanm	20:4263a77256ae	445
mbed_official	256:76fd9a263045	446	uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
mbed_official	256:76fd9a263045	447	__I uint32_t MODULECONTENT; /* 0x7FC Module Content */
bogdanm	20:4263a77256ae	448	} LPC_SCT_T;
bogdanm	20:4263a77256ae	449
mbed_official	256:76fd9a263045	450	/* Macro defines for SCT configuration register */
mbed_official	256:76fd9a263045	451	#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
mbed_official	256:76fd9a263045	452	#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
mbed_official	256:76fd9a263045	453
mbed_official	256:76fd9a263045	454	#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
mbed_official	256:76fd9a263045	455	#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
mbed_official	256:76fd9a263045	456	#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
mbed_official	256:76fd9a263045	457	#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
mbed_official	256:76fd9a263045	458
mbed_official	256:76fd9a263045	459	#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
mbed_official	256:76fd9a263045	460	#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
mbed_official	256:76fd9a263045	461
mbed_official	256:76fd9a263045	462	/* Macro defines for SCT control register */
mbed_official	256:76fd9a263045	463	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
mbed_official	256:76fd9a263045	464	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
mbed_official	256:76fd9a263045	465
mbed_official	256:76fd9a263045	466	#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
mbed_official	256:76fd9a263045	467	#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
mbed_official	256:76fd9a263045	468	#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
mbed_official	256:76fd9a263045	469	#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
mbed_official	256:76fd9a263045	470	#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
mbed_official	256:76fd9a263045	471
mbed_official	256:76fd9a263045	472	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
mbed_official	256:76fd9a263045	473	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
mbed_official	256:76fd9a263045	474	#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
mbed_official	256:76fd9a263045	475	#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
mbed_official	256:76fd9a263045	476	#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
mbed_official	256:76fd9a263045	477	#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
mbed_official	256:76fd9a263045	478	#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
mbed_official	256:76fd9a263045	479
mbed_official	256:76fd9a263045	480	/* Macro defines for SCT Conflict resolution register */
mbed_official	256:76fd9a263045	481	#define SCT_RES_NOCHANGE (0)
mbed_official	256:76fd9a263045	482	#define SCT_RES_SET_OUTPUT (1)
mbed_official	256:76fd9a263045	483	#define SCT_RES_CLEAR_OUTPUT (2)
mbed_official	256:76fd9a263045	484	#define SCT_RES_TOGGLE_OUTPUT (3)
mbed_official	256:76fd9a263045	485
mbed_official	256:76fd9a263045	486	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	487	* GPDMA Channel register block structure
bogdanm	20:4263a77256ae	488	*/
bogdanm	20:4263a77256ae	489	#define LPC_GPDMA_BASE 0x40002000
bogdanm	20:4263a77256ae	490
bogdanm	20:4263a77256ae	491	typedef struct {
mbed_official	256:76fd9a263045	492	__IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
mbed_official	256:76fd9a263045	493	__IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
mbed_official	256:76fd9a263045	494	__IO uint32_t LLI; /* DMA Channel Linked List Item Register */
mbed_official	256:76fd9a263045	495	__IO uint32_t CONTROL; /* DMA Channel Control Register */
mbed_official	256:76fd9a263045	496	__IO uint32_t CONFIG; /* DMA Channel Configuration Register */
mbed_official	256:76fd9a263045	497	__I uint32_t RESERVED1[3];
bogdanm	20:4263a77256ae	498	} LPC_GPDMA_CH_T;
bogdanm	20:4263a77256ae	499
bogdanm	20:4263a77256ae	500	#define GPDMA_CHANNELS 8
bogdanm	20:4263a77256ae	501
mbed_official	256:76fd9a263045	502	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	503	* GPDMA register block
bogdanm	20:4263a77256ae	504	*/
mbed_official	256:76fd9a263045	505	typedef struct { /* GPDMA Structure */
mbed_official	256:76fd9a263045	506	__I uint32_t INTSTAT; /* DMA Interrupt Status Register */
mbed_official	256:76fd9a263045	507	__I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
mbed_official	256:76fd9a263045	508	__O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
mbed_official	256:76fd9a263045	509	__I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
mbed_official	256:76fd9a263045	510	__O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
mbed_official	256:76fd9a263045	511	__I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
mbed_official	256:76fd9a263045	512	__I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
mbed_official	256:76fd9a263045	513	__I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
mbed_official	256:76fd9a263045	514	__IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
mbed_official	256:76fd9a263045	515	__IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
mbed_official	256:76fd9a263045	516	__IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
mbed_official	256:76fd9a263045	517	__IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
mbed_official	256:76fd9a263045	518	__IO uint32_t CONFIG; /* DMA Configuration Register */
mbed_official	256:76fd9a263045	519	__IO uint32_t SYNC; /* DMA Synchronization Register */
mbed_official	256:76fd9a263045	520	__I uint32_t RESERVED0[50];
mbed_official	256:76fd9a263045	521	LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
bogdanm	20:4263a77256ae	522	} LPC_GPDMA_T;
bogdanm	20:4263a77256ae	523
mbed_official	256:76fd9a263045	524	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	525	* SPIFI register block structure
mbed_official	256:76fd9a263045	526	*/
mbed_official	256:76fd9a263045	527	#define LPC_SPIFI_BASE 0x40003000
mbed_official	256:76fd9a263045	528
mbed_official	256:76fd9a263045	529	typedef struct { /* SPIFI Structure */
mbed_official	256:76fd9a263045	530	__IO uint32_t CTRL; /* Control register */
mbed_official	256:76fd9a263045	531	__IO uint32_t CMD; /* Command register */
mbed_official	256:76fd9a263045	532	__IO uint32_t ADDR; /* Address register */
mbed_official	256:76fd9a263045	533	__IO uint32_t IDATA; /* Intermediate data register */
mbed_official	256:76fd9a263045	534	__IO uint32_t CLIMIT; /* Cache limit register */
mbed_official	256:76fd9a263045	535	union {
mbed_official	256:76fd9a263045	536	__IO uint32_t DATA;
mbed_official	256:76fd9a263045	537	__IO uint16_t DATA_HWORD;
mbed_official	256:76fd9a263045	538	__IO uint8_t DATA_BYTE;
mbed_official	256:76fd9a263045	539	}; /* Data register */
mbed_official	256:76fd9a263045	540	__IO uint32_t MCMD; /* Memory command register */
mbed_official	256:76fd9a263045	541	__IO uint32_t STAT; /* Status register */
mbed_official	256:76fd9a263045	542	} LPC_SPIFI_T;
mbed_official	256:76fd9a263045	543
mbed_official	256:76fd9a263045	544	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	545	* SD/MMC & SDIO register block structure
bogdanm	20:4263a77256ae	546	*/
bogdanm	20:4263a77256ae	547	#define LPC_SDMMC_BASE 0x40004000
bogdanm	20:4263a77256ae	548
mbed_official	256:76fd9a263045	549	typedef struct { /* SDMMC Structure */
mbed_official	256:76fd9a263045	550	__IO uint32_t CTRL; /* Control Register */
mbed_official	256:76fd9a263045	551	__IO uint32_t PWREN; /* Power Enable Register */
mbed_official	256:76fd9a263045	552	__IO uint32_t CLKDIV; /* Clock Divider Register */
mbed_official	256:76fd9a263045	553	__IO uint32_t CLKSRC; /* SD Clock Source Register */
mbed_official	256:76fd9a263045	554	__IO uint32_t CLKENA; /* Clock Enable Register */
mbed_official	256:76fd9a263045	555	__IO uint32_t TMOUT; /* Timeout Register */
mbed_official	256:76fd9a263045	556	__IO uint32_t CTYPE; /* Card Type Register */
mbed_official	256:76fd9a263045	557	__IO uint32_t BLKSIZ; /* Block Size Register */
mbed_official	256:76fd9a263045	558	__IO uint32_t BYTCNT; /* Byte Count Register */
mbed_official	256:76fd9a263045	559	__IO uint32_t INTMASK; /* Interrupt Mask Register */
mbed_official	256:76fd9a263045	560	__IO uint32_t CMDARG; /* Command Argument Register */
mbed_official	256:76fd9a263045	561	__IO uint32_t CMD; /* Command Register */
mbed_official	256:76fd9a263045	562	__I uint32_t RESP0; /* Response Register 0 */
mbed_official	256:76fd9a263045	563	__I uint32_t RESP1; /* Response Register 1 */
mbed_official	256:76fd9a263045	564	__I uint32_t RESP2; /* Response Register 2 */
mbed_official	256:76fd9a263045	565	__I uint32_t RESP3; /* Response Register 3 */
mbed_official	256:76fd9a263045	566	__I uint32_t MINTSTS; /* Masked Interrupt Status Register */
mbed_official	256:76fd9a263045	567	__IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
mbed_official	256:76fd9a263045	568	__I uint32_t STATUS; /* Status Register */
mbed_official	256:76fd9a263045	569	__IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
mbed_official	256:76fd9a263045	570	__I uint32_t CDETECT; /* Card Detect Register */
mbed_official	256:76fd9a263045	571	__I uint32_t WRTPRT; /* Write Protect Register */
mbed_official	256:76fd9a263045	572	__IO uint32_t GPIO; /* General Purpose Input/Output Register */
mbed_official	256:76fd9a263045	573	__I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
mbed_official	256:76fd9a263045	574	__I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
mbed_official	256:76fd9a263045	575	__IO uint32_t DEBNCE; /* Debounce Count Register */
mbed_official	256:76fd9a263045	576	__IO uint32_t USRID; /* User ID Register */
mbed_official	256:76fd9a263045	577	__I uint32_t VERID; /* Version ID Register */
mbed_official	256:76fd9a263045	578	__I uint32_t RESERVED0;
mbed_official	256:76fd9a263045	579	__IO uint32_t UHS_REG; /* UHS-1 Register */
mbed_official	256:76fd9a263045	580	__IO uint32_t RST_N; /* Hardware Reset */
mbed_official	256:76fd9a263045	581	__I uint32_t RESERVED1;
mbed_official	256:76fd9a263045	582	__IO uint32_t BMOD; /* Bus Mode Register */
mbed_official	256:76fd9a263045	583	__O uint32_t PLDMND; /* Poll Demand Register */
mbed_official	256:76fd9a263045	584	__IO uint32_t DBADDR; /* Descriptor List Base Address Register */
mbed_official	256:76fd9a263045	585	__IO uint32_t IDSTS; /* Internal DMAC Status Register */
mbed_official	256:76fd9a263045	586	__IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
mbed_official	256:76fd9a263045	587	__I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
mbed_official	256:76fd9a263045	588	__I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
bogdanm	20:4263a77256ae	589	} LPC_SDMMC_T;
bogdanm	20:4263a77256ae	590
mbed_official	256:76fd9a263045	591	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	592	* External Memory Controller (EMC) register block structure
bogdanm	20:4263a77256ae	593	*/
bogdanm	20:4263a77256ae	594	#define LPC_EMC_BASE 0x40005000
bogdanm	20:4263a77256ae	595
mbed_official	256:76fd9a263045	596	typedef struct { /* EMC Structure */
mbed_official	256:76fd9a263045	597	__IO uint32_t CONTROL; /* Controls operation of the memory controller. */
mbed_official	256:76fd9a263045	598	__I uint32_t STATUS; /* Provides EMC status information. */
mbed_official	256:76fd9a263045	599	__IO uint32_t CONFIG; /* Configures operation of the memory controller. */
mbed_official	256:76fd9a263045	600	__I uint32_t RESERVED0[5];
mbed_official	256:76fd9a263045	601	__IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
mbed_official	256:76fd9a263045	602	__IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
mbed_official	256:76fd9a263045	603	__IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
mbed_official	256:76fd9a263045	604	__I uint32_t RESERVED1;
mbed_official	256:76fd9a263045	605	__IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
mbed_official	256:76fd9a263045	606	__IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
mbed_official	256:76fd9a263045	607	__IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
mbed_official	256:76fd9a263045	608	__IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
mbed_official	256:76fd9a263045	609	__IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
mbed_official	256:76fd9a263045	610	__IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
mbed_official	256:76fd9a263045	611	__IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
mbed_official	256:76fd9a263045	612	__IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
mbed_official	256:76fd9a263045	613	__IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
mbed_official	256:76fd9a263045	614	__IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
mbed_official	256:76fd9a263045	615	__IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
mbed_official	256:76fd9a263045	616	__I uint32_t RESERVED2[9];
mbed_official	256:76fd9a263045	617	__IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
mbed_official	256:76fd9a263045	618	__I uint32_t RESERVED3[31];
mbed_official	256:76fd9a263045	619	__IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
mbed_official	256:76fd9a263045	620	__IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
mbed_official	256:76fd9a263045	621	__I uint32_t RESERVED4[6];
mbed_official	256:76fd9a263045	622	__IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
mbed_official	256:76fd9a263045	623	__IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
mbed_official	256:76fd9a263045	624	__I uint32_t RESERVED5[6];
mbed_official	256:76fd9a263045	625	__IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
mbed_official	256:76fd9a263045	626	__IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
mbed_official	256:76fd9a263045	627	__I uint32_t RESERVED6[6];
mbed_official	256:76fd9a263045	628	__IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
mbed_official	256:76fd9a263045	629	__IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
mbed_official	256:76fd9a263045	630	__I uint32_t RESERVED7[38];
mbed_official	256:76fd9a263045	631	__IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
mbed_official	256:76fd9a263045	632	__IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
mbed_official	256:76fd9a263045	633	__IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
mbed_official	256:76fd9a263045	634	__IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
mbed_official	256:76fd9a263045	635	__IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
mbed_official	256:76fd9a263045	636	__IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
mbed_official	256:76fd9a263045	637	__IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
mbed_official	256:76fd9a263045	638	__I uint32_t RESERVED8;
mbed_official	256:76fd9a263045	639	__IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
mbed_official	256:76fd9a263045	640	__IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
mbed_official	256:76fd9a263045	641	__IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
mbed_official	256:76fd9a263045	642	__IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
mbed_official	256:76fd9a263045	643	__IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
mbed_official	256:76fd9a263045	644	__IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
mbed_official	256:76fd9a263045	645	__IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
mbed_official	256:76fd9a263045	646	__I uint32_t RESERVED9;
mbed_official	256:76fd9a263045	647	__IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
mbed_official	256:76fd9a263045	648	__IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
mbed_official	256:76fd9a263045	649	__IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
mbed_official	256:76fd9a263045	650	__IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
mbed_official	256:76fd9a263045	651	__IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
mbed_official	256:76fd9a263045	652	__IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
mbed_official	256:76fd9a263045	653	__IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
mbed_official	256:76fd9a263045	654	__I uint32_t RESERVED10;
mbed_official	256:76fd9a263045	655	__IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
mbed_official	256:76fd9a263045	656	__IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
mbed_official	256:76fd9a263045	657	__IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
mbed_official	256:76fd9a263045	658	__IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
mbed_official	256:76fd9a263045	659	__IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
mbed_official	256:76fd9a263045	660	__IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
mbed_official	256:76fd9a263045	661	__IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
bogdanm	20:4263a77256ae	662	} LPC_EMC_T;
bogdanm	20:4263a77256ae	663
mbed_official	256:76fd9a263045	664	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	665	* USB High-Speed register block structure
bogdanm	20:4263a77256ae	666	*/
bogdanm	20:4263a77256ae	667	#define LPC_USB0_BASE 0x40006000
bogdanm	20:4263a77256ae	668	#define LPC_USB1_BASE 0x40007000
bogdanm	20:4263a77256ae	669
mbed_official	256:76fd9a263045	670	typedef struct { /* USB Structure */
mbed_official	256:76fd9a263045	671	__I uint32_t RESERVED0[64];
mbed_official	256:76fd9a263045	672	__I uint32_t CAPLENGTH; /* Capability register length */
mbed_official	256:76fd9a263045	673	__I uint32_t HCSPARAMS; /* Host controller structural parameters */
mbed_official	256:76fd9a263045	674	__I uint32_t HCCPARAMS; /* Host controller capability parameters */
mbed_official	256:76fd9a263045	675	__I uint32_t RESERVED1[5];
mbed_official	256:76fd9a263045	676	__I uint32_t DCIVERSION; /* Device interface version number */
mbed_official	256:76fd9a263045	677	__I uint32_t RESERVED2[7];
mbed_official	256:76fd9a263045	678	union {
mbed_official	256:76fd9a263045	679	__IO uint32_t USBCMD_H; /* USB command (host mode) */
mbed_official	256:76fd9a263045	680	__IO uint32_t USBCMD_D; /* USB command (device mode) */
mbed_official	256:76fd9a263045	681	};
bogdanm	20:4263a77256ae	682
mbed_official	256:76fd9a263045	683	union {
mbed_official	256:76fd9a263045	684	__IO uint32_t USBSTS_H; /* USB status (host mode) */
mbed_official	256:76fd9a263045	685	__IO uint32_t USBSTS_D; /* USB status (device mode) */
mbed_official	256:76fd9a263045	686	};
bogdanm	20:4263a77256ae	687
mbed_official	256:76fd9a263045	688	union {
mbed_official	256:76fd9a263045	689	__IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
mbed_official	256:76fd9a263045	690	__IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
mbed_official	256:76fd9a263045	691	};
bogdanm	20:4263a77256ae	692
mbed_official	256:76fd9a263045	693	union {
mbed_official	256:76fd9a263045	694	__IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
mbed_official	256:76fd9a263045	695	__I uint32_t FRINDEX_D; /* USB frame index (device mode) */
mbed_official	256:76fd9a263045	696	};
bogdanm	20:4263a77256ae	697
mbed_official	256:76fd9a263045	698	__I uint32_t RESERVED3;
mbed_official	256:76fd9a263045	699	union {
mbed_official	256:76fd9a263045	700	__IO uint32_t PERIODICLISTBASE; /* Frame list base address */
mbed_official	256:76fd9a263045	701	__IO uint32_t DEVICEADDR; /* USB device address */
mbed_official	256:76fd9a263045	702	};
bogdanm	20:4263a77256ae	703
mbed_official	256:76fd9a263045	704	union {
mbed_official	256:76fd9a263045	705	__IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
mbed_official	256:76fd9a263045	706	__IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
mbed_official	256:76fd9a263045	707	};
bogdanm	20:4263a77256ae	708
mbed_official	256:76fd9a263045	709	__IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
mbed_official	256:76fd9a263045	710	__IO uint32_t BURSTSIZE; /* Programmable burst size */
mbed_official	256:76fd9a263045	711	__IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
mbed_official	256:76fd9a263045	712	__I uint32_t RESERVED4[2];
mbed_official	256:76fd9a263045	713	__IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
mbed_official	256:76fd9a263045	714	__IO uint32_t BINTERVAL; /* Length of virtual frame */
mbed_official	256:76fd9a263045	715	__IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
mbed_official	256:76fd9a263045	716	__IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
mbed_official	256:76fd9a263045	717	__I uint32_t RESERVED5;
mbed_official	256:76fd9a263045	718	union {
mbed_official	256:76fd9a263045	719	__IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
mbed_official	256:76fd9a263045	720	__IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
mbed_official	256:76fd9a263045	721	};
bogdanm	20:4263a77256ae	722
mbed_official	256:76fd9a263045	723	__I uint32_t RESERVED6[7];
mbed_official	256:76fd9a263045	724	__IO uint32_t OTGSC; /* OTG status and control */
mbed_official	256:76fd9a263045	725	union {
mbed_official	256:76fd9a263045	726	__IO uint32_t USBMODE_H; /* USB mode (host mode) */
mbed_official	256:76fd9a263045	727	__IO uint32_t USBMODE_D; /* USB mode (device mode) */
mbed_official	256:76fd9a263045	728	};
bogdanm	20:4263a77256ae	729
mbed_official	256:76fd9a263045	730	__IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
mbed_official	256:76fd9a263045	731	__IO uint32_t ENDPTPRIME; /* Endpoint initialization */
mbed_official	256:76fd9a263045	732	__IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
mbed_official	256:76fd9a263045	733	__I uint32_t ENDPTSTAT; /* Endpoint status */
mbed_official	256:76fd9a263045	734	__IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
mbed_official	256:76fd9a263045	735	__IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
bogdanm	20:4263a77256ae	736	} LPC_USBHS_T;
bogdanm	20:4263a77256ae	737
mbed_official	256:76fd9a263045	738	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	739	* LCD Controller register block structure
bogdanm	20:4263a77256ae	740	*/
bogdanm	20:4263a77256ae	741	#define LPC_LCD_BASE 0x40008000
bogdanm	20:4263a77256ae	742
mbed_official	256:76fd9a263045	743	typedef struct { /* LCD Structure */
mbed_official	256:76fd9a263045	744	__IO uint32_t TIMH; /* Horizontal Timing Control register */
mbed_official	256:76fd9a263045	745	__IO uint32_t TIMV; /* Vertical Timing Control register */
mbed_official	256:76fd9a263045	746	__IO uint32_t POL; /* Clock and Signal Polarity Control register */
mbed_official	256:76fd9a263045	747	__IO uint32_t LE; /* Line End Control register */
mbed_official	256:76fd9a263045	748	__IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
mbed_official	256:76fd9a263045	749	__IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
mbed_official	256:76fd9a263045	750	__IO uint32_t CTRL; /* LCD Control register */
mbed_official	256:76fd9a263045	751	__IO uint32_t INTMSK; /* Interrupt Mask register */
mbed_official	256:76fd9a263045	752	__I uint32_t INTRAW; /* Raw Interrupt Status register */
mbed_official	256:76fd9a263045	753	__I uint32_t INTSTAT; /* Masked Interrupt Status register */
mbed_official	256:76fd9a263045	754	__O uint32_t INTCLR; /* Interrupt Clear register */
mbed_official	256:76fd9a263045	755	__I uint32_t UPCURR; /* Upper Panel Current Address Value register */
mbed_official	256:76fd9a263045	756	__I uint32_t LPCURR; /* Lower Panel Current Address Value register */
mbed_official	256:76fd9a263045	757	__I uint32_t RESERVED0[115];
mbed_official	256:76fd9a263045	758	__IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
mbed_official	256:76fd9a263045	759	__I uint32_t RESERVED1[256];
mbed_official	256:76fd9a263045	760	__IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
mbed_official	256:76fd9a263045	761	__IO uint32_t CRSR_CTRL; /* Cursor Control register */
mbed_official	256:76fd9a263045	762	__IO uint32_t CRSR_CFG; /* Cursor Configuration register */
mbed_official	256:76fd9a263045	763	__IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
mbed_official	256:76fd9a263045	764	__IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
mbed_official	256:76fd9a263045	765	__IO uint32_t CRSR_XY; /* Cursor XY Position register */
mbed_official	256:76fd9a263045	766	__IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
mbed_official	256:76fd9a263045	767	__I uint32_t RESERVED2[2];
mbed_official	256:76fd9a263045	768	__IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
mbed_official	256:76fd9a263045	769	__O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
mbed_official	256:76fd9a263045	770	__I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
mbed_official	256:76fd9a263045	771	__I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
bogdanm	20:4263a77256ae	772	} LPC_LCD_T;
bogdanm	20:4263a77256ae	773
mbed_official	256:76fd9a263045	774	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	775	* EEPROM register block structure
bogdanm	20:4263a77256ae	776	*/
bogdanm	20:4263a77256ae	777	#define LPC_EEPROM_BASE 0x4000E000
bogdanm	20:4263a77256ae	778
mbed_official	256:76fd9a263045	779	typedef struct { /* EEPROM Structure */
mbed_official	256:76fd9a263045	780	__IO uint32_t CMD; /* EEPROM command register */
mbed_official	256:76fd9a263045	781	uint32_t RESERVED0;
mbed_official	256:76fd9a263045	782	__IO uint32_t RWSTATE; /* EEPROM read wait state register */
mbed_official	256:76fd9a263045	783	__IO uint32_t AUTOPROG; /* EEPROM auto programming register */
mbed_official	256:76fd9a263045	784	__IO uint32_t WSTATE; /* EEPROM wait state register */
mbed_official	256:76fd9a263045	785	__IO uint32_t CLKDIV; /* EEPROM clock divider register */
mbed_official	256:76fd9a263045	786	__IO uint32_t PWRDWN; /* EEPROM power-down register */
mbed_official	256:76fd9a263045	787	uint32_t RESERVED2[1007];
mbed_official	256:76fd9a263045	788	__O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
mbed_official	256:76fd9a263045	789	__O uint32_t INTENSET; /* EEPROM interrupt enable set */
mbed_official	256:76fd9a263045	790	__I uint32_t INTSTAT; /* EEPROM interrupt status */
mbed_official	256:76fd9a263045	791	__I uint32_t INTEN; /* EEPROM interrupt enable */
mbed_official	256:76fd9a263045	792	__O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
mbed_official	256:76fd9a263045	793	__O uint32_t INTSTATSET; /* EEPROM interrupt status set */
bogdanm	20:4263a77256ae	794	} LPC_EEPROM_T;
bogdanm	20:4263a77256ae	795
mbed_official	256:76fd9a263045	796	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	797	* 10/100 MII & RMII Ethernet with timestamping register block structure
bogdanm	20:4263a77256ae	798	*/
bogdanm	20:4263a77256ae	799	#define LPC_ETHERNET_BASE 0x40010000
bogdanm	20:4263a77256ae	800
mbed_official	256:76fd9a263045	801	typedef struct { /* ETHERNET Structure */
mbed_official	256:76fd9a263045	802	__IO uint32_t MAC_CONFIG; /* MAC configuration register */
mbed_official	256:76fd9a263045	803	__IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
mbed_official	256:76fd9a263045	804	__IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
mbed_official	256:76fd9a263045	805	__IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
mbed_official	256:76fd9a263045	806	__IO uint32_t MAC_MII_ADDR; /* MII address register */
mbed_official	256:76fd9a263045	807	__IO uint32_t MAC_MII_DATA; /* MII data register */
mbed_official	256:76fd9a263045	808	__IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
mbed_official	256:76fd9a263045	809	__IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
mbed_official	256:76fd9a263045	810	__I uint32_t RESERVED0;
mbed_official	256:76fd9a263045	811	__I uint32_t MAC_DEBUG; /* Debug register */
mbed_official	256:76fd9a263045	812	__IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
mbed_official	256:76fd9a263045	813	__IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
mbed_official	256:76fd9a263045	814	__I uint32_t RESERVED1[2];
mbed_official	256:76fd9a263045	815	__I uint32_t MAC_INTR; /* Interrupt status register */
mbed_official	256:76fd9a263045	816	__IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
mbed_official	256:76fd9a263045	817	__IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
mbed_official	256:76fd9a263045	818	__IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
mbed_official	256:76fd9a263045	819	__I uint32_t RESERVED2[430];
mbed_official	256:76fd9a263045	820	__IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
mbed_official	256:76fd9a263045	821	__IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
mbed_official	256:76fd9a263045	822	__I uint32_t SECONDS; /* System time seconds register */
mbed_official	256:76fd9a263045	823	__I uint32_t NANOSECONDS; /* System time nanoseconds register */
mbed_official	256:76fd9a263045	824	__IO uint32_t SECONDSUPDATE; /* System time seconds update register */
mbed_official	256:76fd9a263045	825	__IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
mbed_official	256:76fd9a263045	826	__IO uint32_t ADDEND; /* Time stamp addend register */
mbed_official	256:76fd9a263045	827	__IO uint32_t TARGETSECONDS; /* Target time seconds register */
mbed_official	256:76fd9a263045	828	__IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
mbed_official	256:76fd9a263045	829	__IO uint32_t HIGHWORD; /* System time higher word seconds register */
mbed_official	256:76fd9a263045	830	__I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
mbed_official	256:76fd9a263045	831	__IO uint32_t PPSCTRL; /* PPS control register */
mbed_official	256:76fd9a263045	832	__I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
mbed_official	256:76fd9a263045	833	__I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
mbed_official	256:76fd9a263045	834	__I uint32_t RESERVED3[562];
mbed_official	256:76fd9a263045	835	__IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
mbed_official	256:76fd9a263045	836	__IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
mbed_official	256:76fd9a263045	837	__IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
mbed_official	256:76fd9a263045	838	__IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
mbed_official	256:76fd9a263045	839	__IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
mbed_official	256:76fd9a263045	840	__IO uint32_t DMA_STAT; /* Status register */
mbed_official	256:76fd9a263045	841	__IO uint32_t DMA_OP_MODE; /* Operation mode register */
mbed_official	256:76fd9a263045	842	__IO uint32_t DMA_INT_EN; /* Interrupt enable register */
mbed_official	256:76fd9a263045	843	__I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
mbed_official	256:76fd9a263045	844	__IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
mbed_official	256:76fd9a263045	845	__I uint32_t RESERVED4[8];
mbed_official	256:76fd9a263045	846	__I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
mbed_official	256:76fd9a263045	847	__I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
mbed_official	256:76fd9a263045	848	__I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
mbed_official	256:76fd9a263045	849	__I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
bogdanm	20:4263a77256ae	850	} LPC_ENET_T;
bogdanm	20:4263a77256ae	851
mbed_official	256:76fd9a263045	852	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	853	* Alarm Timer register block structure
bogdanm	20:4263a77256ae	854	*/
bogdanm	20:4263a77256ae	855	#define LPC_ATIMER_BASE 0x40040000
bogdanm	20:4263a77256ae	856
mbed_official	256:76fd9a263045	857	typedef struct { /* ATIMER Structure */
mbed_official	256:76fd9a263045	858	__IO uint32_t DOWNCOUNTER; /* Downcounter register */
mbed_official	256:76fd9a263045	859	__IO uint32_t PRESET; /* Preset value register */
mbed_official	256:76fd9a263045	860	__I uint32_t RESERVED0[1012];
mbed_official	256:76fd9a263045	861	__O uint32_t CLR_EN; /* Interrupt clear enable register */
mbed_official	256:76fd9a263045	862	__O uint32_t SET_EN; /* Interrupt set enable register */
mbed_official	256:76fd9a263045	863	__I uint32_t STATUS; /* Status register */
mbed_official	256:76fd9a263045	864	__I uint32_t ENABLE; /* Enable register */
mbed_official	256:76fd9a263045	865	__O uint32_t CLR_STAT; /* Clear register */
mbed_official	256:76fd9a263045	866	__O uint32_t SET_STAT; /* Set register */
bogdanm	20:4263a77256ae	867	} LPC_ATIMER_T;
bogdanm	20:4263a77256ae	868
mbed_official	256:76fd9a263045	869	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	870	* Register File register block structure
bogdanm	20:4263a77256ae	871	*/
bogdanm	20:4263a77256ae	872	#define LPC_REGFILE_BASE 0x40041000
bogdanm	20:4263a77256ae	873
bogdanm	20:4263a77256ae	874	typedef struct {
mbed_official	256:76fd9a263045	875	__IO uint32_t REGFILE[64]; /* General purpose storage register */
bogdanm	20:4263a77256ae	876	} LPC_REGFILE_T;
bogdanm	20:4263a77256ae	877
mbed_official	256:76fd9a263045	878	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	879	* Power Management Controller register block structure
bogdanm	20:4263a77256ae	880	*/
bogdanm	20:4263a77256ae	881	#define LPC_PMC_BASE 0x40042000
bogdanm	20:4263a77256ae	882
mbed_official	256:76fd9a263045	883	typedef struct { /* PMC Structure */
mbed_official	256:76fd9a263045	884	__IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
mbed_official	256:76fd9a263045	885	__I uint32_t RESERVED0[6];
mbed_official	256:76fd9a263045	886	__IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
bogdanm	20:4263a77256ae	887	} LPC_PMC_T;
bogdanm	20:4263a77256ae	888
mbed_official	256:76fd9a263045	889	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	890	* CREG Register Block
bogdanm	20:4263a77256ae	891	*/
bogdanm	20:4263a77256ae	892	#define LPC_CREG_BASE 0x40043000
bogdanm	20:4263a77256ae	893
mbed_official	256:76fd9a263045	894	typedef struct { /* CREG Structure */
mbed_official	256:76fd9a263045	895	__I uint32_t RESERVED0;
mbed_official	256:76fd9a263045	896	__IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
mbed_official	256:76fd9a263045	897	__I uint32_t RESERVED1[62];
mbed_official	256:76fd9a263045	898	__IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
bogdanm	20:4263a77256ae	899	#if defined(CHIP_LPC18XX)
mbed_official	256:76fd9a263045	900	__I uint32_t RESERVED2[5];
bogdanm	20:4263a77256ae	901	#else
mbed_official	256:76fd9a263045	902	__I uint32_t RESERVED2;
mbed_official	256:76fd9a263045	903	__I uint32_t CREG1; /* Configuration Register 1 */
mbed_official	256:76fd9a263045	904	__I uint32_t CREG2; /* Configuration Register 2 */
mbed_official	256:76fd9a263045	905	__I uint32_t CREG3; /* Configuration Register 3 */
mbed_official	256:76fd9a263045	906	__I uint32_t CREG4; /* Configuration Register 4 */
bogdanm	20:4263a77256ae	907	#endif
mbed_official	256:76fd9a263045	908	__IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
mbed_official	256:76fd9a263045	909	__IO uint32_t DMAMUX; /* DMA muxing control */
mbed_official	256:76fd9a263045	910	__IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
mbed_official	256:76fd9a263045	911	__IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
mbed_official	256:76fd9a263045	912	__IO uint32_t ETBCFG; /* ETB RAM configuration */
mbed_official	256:76fd9a263045	913	__IO uint32_t CREG6; /* Chip configuration register 6. */
bogdanm	20:4263a77256ae	914	#if defined(CHIP_LPC18XX)
mbed_official	256:76fd9a263045	915	__I uint32_t RESERVED4[52];
bogdanm	20:4263a77256ae	916	#else
mbed_official	256:76fd9a263045	917	__IO uint32_t M4TXEVENT; /* M4 IPC event register */
mbed_official	256:76fd9a263045	918	__I uint32_t RESERVED4[51];
bogdanm	20:4263a77256ae	919	#endif
mbed_official	256:76fd9a263045	920	__I uint32_t CHIPID; /* Part ID */
bogdanm	20:4263a77256ae	921	#if defined(CHIP_LPC18XX)
mbed_official	256:76fd9a263045	922	__I uint32_t RESERVED5[191];
bogdanm	20:4263a77256ae	923	#else
mbed_official	256:76fd9a263045	924	__I uint32_t RESERVED5[127];
mbed_official	256:76fd9a263045	925	__IO uint32_t M0TXEVENT; /* M0 IPC Event register */
mbed_official	256:76fd9a263045	926	__IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
mbed_official	256:76fd9a263045	927	__I uint32_t RESERVED6[62];
bogdanm	20:4263a77256ae	928	#endif
mbed_official	256:76fd9a263045	929	__IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
mbed_official	256:76fd9a263045	930	__I uint32_t RESERVED7[63];
mbed_official	256:76fd9a263045	931	__IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
bogdanm	20:4263a77256ae	932	} LPC_CREG_T;
bogdanm	20:4263a77256ae	933
mbed_official	256:76fd9a263045	934	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	935	* Event Router register structure
bogdanm	20:4263a77256ae	936	*/
bogdanm	20:4263a77256ae	937	#define LPC_EVRT_BASE 0x40044000
bogdanm	20:4263a77256ae	938
mbed_official	256:76fd9a263045	939	typedef struct { /* EVENTROUTER Structure */
mbed_official	256:76fd9a263045	940	__IO uint32_t HILO; /* Level configuration register */
mbed_official	256:76fd9a263045	941	__IO uint32_t EDGE; /* Edge configuration */
mbed_official	256:76fd9a263045	942	__I uint32_t RESERVED0[1012];
mbed_official	256:76fd9a263045	943	__O uint32_t CLR_EN; /* Event clear enable register */
mbed_official	256:76fd9a263045	944	__O uint32_t SET_EN; /* Event set enable register */
mbed_official	256:76fd9a263045	945	__I uint32_t STATUS; /* Status register */
mbed_official	256:76fd9a263045	946	__I uint32_t ENABLE; /* Enable register */
mbed_official	256:76fd9a263045	947	__O uint32_t CLR_STAT; /* Clear register */
mbed_official	256:76fd9a263045	948	__O uint32_t SET_STAT; /* Set register */
bogdanm	20:4263a77256ae	949	} LPC_EVRT_T;
bogdanm	20:4263a77256ae	950
mbed_official	256:76fd9a263045	951	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	952	* Real Time Clock register block structure
bogdanm	20:4263a77256ae	953	*/
bogdanm	20:4263a77256ae	954	#define LPC_RTC_BASE 0x40046000
mbed_official	256:76fd9a263045	955	#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
bogdanm	20:4263a77256ae	956
mbed_official	256:76fd9a263045	957	typedef enum RTC_TIMEINDEX {
mbed_official	256:76fd9a263045	958	RTC_TIMETYPE_SECOND, /* Second */
mbed_official	256:76fd9a263045	959	RTC_TIMETYPE_MINUTE, /* Month */
mbed_official	256:76fd9a263045	960	RTC_TIMETYPE_HOUR, /* Hour */
mbed_official	256:76fd9a263045	961	RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
mbed_official	256:76fd9a263045	962	RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
mbed_official	256:76fd9a263045	963	RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
mbed_official	256:76fd9a263045	964	RTC_TIMETYPE_MONTH, /* Month */
mbed_official	256:76fd9a263045	965	RTC_TIMETYPE_YEAR, /* Year */
mbed_official	256:76fd9a263045	966	RTC_TIMETYPE_LAST
mbed_official	256:76fd9a263045	967	} RTC_TIMEINDEX_T;
bogdanm	20:4263a77256ae	968
bogdanm	20:4263a77256ae	969	#if RTC_EV_SUPPORT
bogdanm	20:4263a77256ae	970	typedef enum LPC_RTC_EV_CHANNEL {
mbed_official	256:76fd9a263045	971	RTC_EV_CHANNEL_1 = 0,
mbed_official	256:76fd9a263045	972	RTC_EV_CHANNEL_2,
mbed_official	256:76fd9a263045	973	RTC_EV_CHANNEL_3,
mbed_official	256:76fd9a263045	974	RTC_EV_CHANNEL_NUM,
bogdanm	20:4263a77256ae	975	} LPC_RTC_EV_CHANNEL_T;
bogdanm	20:4263a77256ae	976	#endif /RTC_EV_SUPPORT/
bogdanm	20:4263a77256ae	977
mbed_official	256:76fd9a263045	978	typedef struct { /* RTC Structure */
mbed_official	256:76fd9a263045	979	__IO uint32_t ILR; /* Interrupt Location Register */
mbed_official	256:76fd9a263045	980	__I uint32_t RESERVED0;
mbed_official	256:76fd9a263045	981	__IO uint32_t CCR; /* Clock Control Register */
mbed_official	256:76fd9a263045	982	__IO uint32_t CIIR; /* Counter Increment Interrupt Register */
mbed_official	256:76fd9a263045	983	__IO uint32_t AMR; /* Alarm Mask Register */
mbed_official	256:76fd9a263045	984	__I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
mbed_official	256:76fd9a263045	985	__IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
mbed_official	256:76fd9a263045	986	__IO uint32_t CALIBRATION; /* Calibration Value Register */
mbed_official	256:76fd9a263045	987	__I uint32_t RESERVED1[7];
mbed_official	256:76fd9a263045	988	__IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
bogdanm	20:4263a77256ae	989	#if RTC_EV_SUPPORT
mbed_official	256:76fd9a263045	990	__IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
mbed_official	256:76fd9a263045	991	__IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
mbed_official	256:76fd9a263045	992	__I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
mbed_official	256:76fd9a263045	993	__I uint32_t RESERVED2;
mbed_official	256:76fd9a263045	994	__I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
mbed_official	256:76fd9a263045	995	__I uint32_t RESERVED3;
mbed_official	256:76fd9a263045	996	__I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
bogdanm	20:4263a77256ae	997	#endif /RTC_EV_SUPPORT/
bogdanm	20:4263a77256ae	998	} LPC_RTC_T;
bogdanm	20:4263a77256ae	999
mbed_official	256:76fd9a263045	1000	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1001	* LPC18XX/43XX CGU register block structure
bogdanm	20:4263a77256ae	1002	*/
bogdanm	20:4263a77256ae	1003	#define LPC_CGU_BASE 0x40050000
bogdanm	20:4263a77256ae	1004	#define LPC_CCU1_BASE 0x40051000
bogdanm	20:4263a77256ae	1005	#define LPC_CCU2_BASE 0x40052000
mbed_official	256:76fd9a263045	1006	/*
mbed_official	256:76fd9a263045	1007	* Input clocks for the CGU and can come from both external (crystal) and
mbed_official	256:76fd9a263045	1008	* internal (PLL) sources. Can be routed to the base clocks.
bogdanm	20:4263a77256ae	1009	*/
bogdanm	20:4263a77256ae	1010	typedef enum CGU_CLKIN {
mbed_official	256:76fd9a263045	1011	CLKIN_32K, /* External 32KHz input */
mbed_official	256:76fd9a263045	1012	CLKIN_IRC, /* Internal IRC (12MHz) input */
mbed_official	256:76fd9a263045	1013	CLKIN_ENET_RX, /* External ENET_RX pin input */
mbed_official	256:76fd9a263045	1014	CLKIN_ENET_TX, /* External ENET_TX pin input */
mbed_official	256:76fd9a263045	1015	CLKIN_CLKIN, /* External GPCLKIN pin input */
mbed_official	256:76fd9a263045	1016	CLKIN_RESERVED1,
mbed_official	256:76fd9a263045	1017	CLKIN_CRYSTAL, /* External (main) crystal pin input */
mbed_official	256:76fd9a263045	1018	CLKIN_USBPLL, /* Internal USB PLL input */
mbed_official	256:76fd9a263045	1019	CLKIN_AUDIOPLL, /* Internal Audio PLL input */
mbed_official	256:76fd9a263045	1020	CLKIN_MAINPLL, /* Internal Main PLL input */
mbed_official	256:76fd9a263045	1021	CLKIN_RESERVED2,
mbed_official	256:76fd9a263045	1022	CLKIN_RESERVED3,
mbed_official	256:76fd9a263045	1023	CLKIN_IDIVA, /* Internal divider A input */
mbed_official	256:76fd9a263045	1024	CLKIN_IDIVB, /* Internal divider B input */
mbed_official	256:76fd9a263045	1025	CLKIN_IDIVC, /* Internal divider C input */
mbed_official	256:76fd9a263045	1026	CLKIN_IDIVD, /* Internal divider D input */
mbed_official	256:76fd9a263045	1027	CLKIN_IDIVE, /* Internal divider E input */
mbed_official	256:76fd9a263045	1028	CLKINPUT_PD /* External 32KHz input */
bogdanm	20:4263a77256ae	1029	} CGU_CLKIN_T;
bogdanm	20:4263a77256ae	1030
bogdanm	20:4263a77256ae	1031	#define CLKIN_PLL0USB CLKIN_USBPLL
bogdanm	20:4263a77256ae	1032	#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
bogdanm	20:4263a77256ae	1033	#define CLKIN_PLL1 CLKIN_MAINPLL
bogdanm	20:4263a77256ae	1034
mbed_official	256:76fd9a263045	1035	/*
bogdanm	20:4263a77256ae	1036	* CGU base clocks are clocks that are associated with a single input clock
bogdanm	20:4263a77256ae	1037	* and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
bogdanm	20:4263a77256ae	1038	* clock can be configured to use the CLKIN_MAINPLL input clock, which will in
bogdanm	20:4263a77256ae	1039	* turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
bogdanm	20:4263a77256ae	1040	* CLK_PERIPH_SGPIO periphral clocks.
bogdanm	20:4263a77256ae	1041	*/
bogdanm	20:4263a77256ae	1042	typedef enum CGU_BASE_CLK {
mbed_official	256:76fd9a263045	1043	CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
mbed_official	256:76fd9a263045	1044	CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
bogdanm	20:4263a77256ae	1045	#if defined(CHIP_LPC43XX)
mbed_official	256:76fd9a263045	1046	CLK_BASE_PERIPH, /* Base clock for SGPIO */
bogdanm	20:4263a77256ae	1047	#else
mbed_official	256:76fd9a263045	1048	CLK_BASE_RESERVED1,
bogdanm	20:4263a77256ae	1049	#endif
mbed_official	256:76fd9a263045	1050	CLK_BASE_USB1, /* Base USB clock for USB1 */
mbed_official	256:76fd9a263045	1051	CLK_BASE_MX, /* Base clock for CPU core */
mbed_official	256:76fd9a263045	1052	CLK_BASE_SPIFI, /* Base clock for SPIFI */
bogdanm	20:4263a77256ae	1053	#if defined(CHIP_LPC43XX)
mbed_official	256:76fd9a263045	1054	CLK_BASE_SPI, /* Base clock for SPI */
bogdanm	20:4263a77256ae	1055	#else
mbed_official	256:76fd9a263045	1056	CLK_BASE_RESERVED2,
bogdanm	20:4263a77256ae	1057	#endif
mbed_official	256:76fd9a263045	1058	CLK_BASE_PHY_RX, /* Base clock for PHY RX */
mbed_official	256:76fd9a263045	1059	CLK_BASE_PHY_TX, /* Base clock for PHY TX */
mbed_official	256:76fd9a263045	1060	CLK_BASE_APB1, /* Base clock for APB1 group */
mbed_official	256:76fd9a263045	1061	CLK_BASE_APB3, /* Base clock for APB3 group */
mbed_official	256:76fd9a263045	1062	CLK_BASE_LCD, /* Base clock for LCD pixel clock */
bogdanm	20:4263a77256ae	1063	#if defined(CHIP_LPC43XX)
mbed_official	256:76fd9a263045	1064	CLK_BASE_VADC, /* Base clock for VADC */
bogdanm	20:4263a77256ae	1065	#else
mbed_official	256:76fd9a263045	1066	CLK_BASE_RESERVED3,
bogdanm	20:4263a77256ae	1067	#endif
mbed_official	256:76fd9a263045	1068	CLK_BASE_SDIO, /* Base clock for SDIO */
mbed_official	256:76fd9a263045	1069	CLK_BASE_SSP0, /* Base clock for SSP0 */
mbed_official	256:76fd9a263045	1070	CLK_BASE_SSP1, /* Base clock for SSP1 */
mbed_official	256:76fd9a263045	1071	CLK_BASE_UART0, /* Base clock for UART0 */
mbed_official	256:76fd9a263045	1072	CLK_BASE_UART1, /* Base clock for UART1 */
mbed_official	256:76fd9a263045	1073	CLK_BASE_UART2, /* Base clock for UART2 */
mbed_official	256:76fd9a263045	1074	CLK_BASE_UART3, /* Base clock for UART3 */
mbed_official	256:76fd9a263045	1075	CLK_BASE_OUT, /* Base clock for CLKOUT pin */
mbed_official	256:76fd9a263045	1076	CLK_BASE_RESERVED4,
mbed_official	256:76fd9a263045	1077	CLK_BASE_RESERVED5,
mbed_official	256:76fd9a263045	1078	CLK_BASE_RESERVED6,
mbed_official	256:76fd9a263045	1079	CLK_BASE_RESERVED7,
mbed_official	256:76fd9a263045	1080	CLK_BASE_APLL, /* Base clock for audio PLL */
mbed_official	256:76fd9a263045	1081	CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
mbed_official	256:76fd9a263045	1082	CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
mbed_official	256:76fd9a263045	1083	CLK_BASE_LAST,
mbed_official	256:76fd9a263045	1084	CLK_BASE_NONE = CLK_BASE_LAST
bogdanm	20:4263a77256ae	1085	} CGU_BASE_CLK_T;
bogdanm	20:4263a77256ae	1086
mbed_official	256:76fd9a263045	1087	/*
bogdanm	20:4263a77256ae	1088	* CGU dividers provide an extra clock state where a specific clock can be
bogdanm	20:4263a77256ae	1089	* divided before being routed to a peripheral group. A divider accepts an
bogdanm	20:4263a77256ae	1090	* input clock and then divides it. To use the divided clock for a base clock
bogdanm	20:4263a77256ae	1091	* group, use the divider as the input clock for the base clock (for example,
bogdanm	20:4263a77256ae	1092	* use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
bogdanm	20:4263a77256ae	1093	*/
bogdanm	20:4263a77256ae	1094	typedef enum CGU_IDIV {
mbed_official	256:76fd9a263045	1095	CLK_IDIV_A, /* CGU clock divider A */
mbed_official	256:76fd9a263045	1096	CLK_IDIV_B, /* CGU clock divider B */
mbed_official	256:76fd9a263045	1097	CLK_IDIV_C, /* CGU clock divider A */
mbed_official	256:76fd9a263045	1098	CLK_IDIV_D, /* CGU clock divider D */
mbed_official	256:76fd9a263045	1099	CLK_IDIV_E, /* CGU clock divider E */
mbed_official	256:76fd9a263045	1100	CLK_IDIV_LAST
bogdanm	20:4263a77256ae	1101	} CGU_IDIV_T;
bogdanm	20:4263a77256ae	1102
mbed_official	256:76fd9a263045	1103	/*
bogdanm	20:4263a77256ae	1104	* Peripheral clocks are individual clocks routed to peripherals. Although
bogdanm	20:4263a77256ae	1105	* multiple peripherals may share a same base clock, each peripheral's clock
bogdanm	20:4263a77256ae	1106	* can be enabled or disabled individually. Some peripheral clocks also have
bogdanm	20:4263a77256ae	1107	* additional dividers associated with them.
bogdanm	20:4263a77256ae	1108	*/
bogdanm	20:4263a77256ae	1109	typedef enum CCU_CLK {
mbed_official	256:76fd9a263045	1110	/* CCU1 clocks */
mbed_official	256:76fd9a263045	1111	CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
mbed_official	256:76fd9a263045	1112	CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
mbed_official	256:76fd9a263045	1113	CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
mbed_official	256:76fd9a263045	1114	CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
mbed_official	256:76fd9a263045	1115	CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
mbed_official	256:76fd9a263045	1116	CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
mbed_official	256:76fd9a263045	1117	CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
mbed_official	256:76fd9a263045	1118	CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
mbed_official	256:76fd9a263045	1119	CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
mbed_official	256:76fd9a263045	1120	CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
mbed_official	256:76fd9a263045	1121	CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
mbed_official	256:76fd9a263045	1122	CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
mbed_official	256:76fd9a263045	1123	CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1124	CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1125	CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1126	CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1127	CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1128	CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1129	CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1130	CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1131	CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1132	CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1133	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
mbed_official	256:76fd9a263045	1134	CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1135	CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1136	CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1137	CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1138	CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
bogdanm	20:4263a77256ae	1139	#if defined(CHIP_LPC43XX)
mbed_official	256:76fd9a263045	1140	CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1141	CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
bogdanm	20:4263a77256ae	1142	#else
mbed_official	256:76fd9a263045	1143	CLK_RESERVED1,
mbed_official	256:76fd9a263045	1144	CLK_RESERVED2,
bogdanm	20:4263a77256ae	1145	#endif
mbed_official	256:76fd9a263045	1146	CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1147	CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1148	CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1149	CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1150	CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1151	CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1152	CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1153	CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1154	CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1155	CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1156	CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1157	CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1158	CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1159	CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1160	CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
mbed_official	256:76fd9a263045	1161	CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
bogdanm	20:4263a77256ae	1162	#if defined(CHIP_LPC43XX)
mbed_official	256:76fd9a263045	1163	CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
mbed_official	256:76fd9a263045	1164	CLK_RESERVED3,
mbed_official	256:76fd9a263045	1165	CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
mbed_official	256:76fd9a263045	1166	CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
bogdanm	20:4263a77256ae	1167	#else
mbed_official	256:76fd9a263045	1168	CLK_RESERVED3 = 192,
mbed_official	256:76fd9a263045	1169	CLK_RESERVED3A,
mbed_official	256:76fd9a263045	1170	CLK_RESERVED4,
mbed_official	256:76fd9a263045	1171	CLK_RESERVED5,
bogdanm	20:4263a77256ae	1172	#endif
mbed_official	256:76fd9a263045	1173	CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
mbed_official	256:76fd9a263045	1174	CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
bogdanm	20:4263a77256ae	1175	#if defined(CHIP_LPC43XX)
mbed_official	256:76fd9a263045	1176	CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
mbed_official	256:76fd9a263045	1177	CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
bogdanm	20:4263a77256ae	1178	#else
mbed_official	256:76fd9a263045	1179	CLK_RESERVED7 = 320,
mbed_official	256:76fd9a263045	1180	CLK_RESERVED8,
bogdanm	20:4263a77256ae	1181	#endif
mbed_official	256:76fd9a263045	1182	CLK_CCU1_LAST,
bogdanm	20:4263a77256ae	1183
mbed_official	256:76fd9a263045	1184	/* CCU2 clocks */
mbed_official	256:76fd9a263045	1185	CLK_CCU2_START,
mbed_official	256:76fd9a263045	1186	CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
mbed_official	256:76fd9a263045	1187	RESERVED_ALIGNB = CLK_CCU2_START + 31,
mbed_official	256:76fd9a263045	1188	CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
mbed_official	256:76fd9a263045	1189	RESERVED_ALIGNC = CLK_CCU2_START + 63,
mbed_official	256:76fd9a263045	1190	CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
mbed_official	256:76fd9a263045	1191	RESERVED_ALIGND = CLK_CCU2_START + 95,
mbed_official	256:76fd9a263045	1192	CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
mbed_official	256:76fd9a263045	1193	RESERVED_ALIGNE = CLK_CCU2_START + 127,
mbed_official	256:76fd9a263045	1194	CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
mbed_official	256:76fd9a263045	1195	RESERVED_ALIGNF = CLK_CCU2_START + 159,
mbed_official	256:76fd9a263045	1196	CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
mbed_official	256:76fd9a263045	1197	RESERVED_ALIGNG = CLK_CCU2_START + 191,
mbed_official	256:76fd9a263045	1198	CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
mbed_official	256:76fd9a263045	1199	RESERVED_ALIGNH = CLK_CCU2_START + 223,
mbed_official	256:76fd9a263045	1200	CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
mbed_official	256:76fd9a263045	1201	CLK_CCU2_LAST
bogdanm	20:4263a77256ae	1202	} CCU_CLK_T;
bogdanm	20:4263a77256ae	1203
mbed_official	256:76fd9a263045	1204	/*
bogdanm	20:4263a77256ae	1205	* Audio or USB PLL selection
bogdanm	20:4263a77256ae	1206	*/
mbed_official	294:78f9587bb26d	1207	typedef enum CGU_USB_AUDIO_PLL {
mbed_official	256:76fd9a263045	1208	CGU_USB_PLL,
mbed_official	256:76fd9a263045	1209	CGU_AUDIO_PLL
mbed_official	294:78f9587bb26d	1210	} CGU_USB_AUDIO_PLL_T;
bogdanm	20:4263a77256ae	1211
mbed_official	256:76fd9a263045	1212	/*
bogdanm	20:4263a77256ae	1213	* PLL register block
bogdanm	20:4263a77256ae	1214	*/
bogdanm	20:4263a77256ae	1215	typedef struct {
mbed_official	256:76fd9a263045	1216	__I uint32_t PLL_STAT; /* PLL status register */
mbed_official	256:76fd9a263045	1217	__IO uint32_t PLL_CTRL; /* PLL control register */
mbed_official	256:76fd9a263045	1218	__IO uint32_t PLL_MDIV; /* PLL M-divider register */
mbed_official	256:76fd9a263045	1219	__IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
bogdanm	20:4263a77256ae	1220	} CGU_PLL_REG_T;
bogdanm	20:4263a77256ae	1221
mbed_official	256:76fd9a263045	1222	typedef struct { /* (@ 0x40050000) CGU Structure */
mbed_official	256:76fd9a263045	1223	__I uint32_t RESERVED0[5];
mbed_official	256:76fd9a263045	1224	__IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
mbed_official	256:76fd9a263045	1225	__IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
mbed_official	256:76fd9a263045	1226	CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
mbed_official	256:76fd9a263045	1227	__IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
mbed_official	256:76fd9a263045	1228	__I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
mbed_official	256:76fd9a263045	1229	__IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
mbed_official	256:76fd9a263045	1230	__IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
mbed_official	256:76fd9a263045	1231	__IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
bogdanm	20:4263a77256ae	1232	} LPC_CGU_T;
bogdanm	20:4263a77256ae	1233
mbed_official	256:76fd9a263045	1234	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1235	* CCU clock config/status register pair
bogdanm	20:4263a77256ae	1236	*/
bogdanm	20:4263a77256ae	1237	typedef struct {
mbed_official	256:76fd9a263045	1238	__IO uint32_t CFG; /* CCU clock configuration register */
mbed_official	256:76fd9a263045	1239	__I uint32_t STAT; /* CCU clock status register */
bogdanm	20:4263a77256ae	1240	} CCU_CFGSTAT_T;
bogdanm	20:4263a77256ae	1241
mbed_official	256:76fd9a263045	1242	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1243	* CCU1 register block structure
bogdanm	20:4263a77256ae	1244	*/
mbed_official	256:76fd9a263045	1245	typedef struct { /* (@ 0x40051000) CCU1 Structure */
mbed_official	256:76fd9a263045	1246	__IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
mbed_official	256:76fd9a263045	1247	__I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
mbed_official	256:76fd9a263045	1248	__I uint32_t RESERVED0[62];
mbed_official	256:76fd9a263045	1249	CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
bogdanm	20:4263a77256ae	1250	} LPC_CCU1_T;
bogdanm	20:4263a77256ae	1251
mbed_official	256:76fd9a263045	1252	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1253	* CCU2 register block structure
bogdanm	20:4263a77256ae	1254	*/
mbed_official	256:76fd9a263045	1255	typedef struct { /* (@ 0x40052000) CCU2 Structure */
mbed_official	256:76fd9a263045	1256	__IO uint32_t PM; /* (@ 0x40052000) Power mode register */
mbed_official	256:76fd9a263045	1257	__I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
mbed_official	256:76fd9a263045	1258	__I uint32_t RESERVED0[62];
mbed_official	256:76fd9a263045	1259	CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
bogdanm	20:4263a77256ae	1260	} LPC_CCU2_T;
bogdanm	20:4263a77256ae	1261
mbed_official	256:76fd9a263045	1262	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1263	* RGU register structure
bogdanm	20:4263a77256ae	1264	*/
bogdanm	20:4263a77256ae	1265	#define LPC_RGU_BASE 0x40053000
bogdanm	20:4263a77256ae	1266
mbed_official	294:78f9587bb26d	1267	typedef enum RGU_RST {
mbed_official	256:76fd9a263045	1268	RGU_CORE_RST,
mbed_official	256:76fd9a263045	1269	RGU_PERIPH_RST,
mbed_official	256:76fd9a263045	1270	RGU_MASTER_RST,
mbed_official	256:76fd9a263045	1271	RGU_WWDT_RST = 4,
mbed_official	256:76fd9a263045	1272	RGU_CREG_RST,
mbed_official	256:76fd9a263045	1273	RGU_BUS_RST = 8,
mbed_official	256:76fd9a263045	1274	RGU_SCU_RST,
mbed_official	256:76fd9a263045	1275	RGU_M3_RST = 13,
mbed_official	256:76fd9a263045	1276	RGU_LCD_RST = 16,
mbed_official	256:76fd9a263045	1277	RGU_USB0_RST,
mbed_official	256:76fd9a263045	1278	RGU_USB1_RST,
mbed_official	256:76fd9a263045	1279	RGU_DMA_RST,
mbed_official	256:76fd9a263045	1280	RGU_SDIO_RST,
mbed_official	256:76fd9a263045	1281	RGU_EMC_RST,
mbed_official	256:76fd9a263045	1282	RGU_ETHERNET_RST,
mbed_official	256:76fd9a263045	1283	RGU_FLASHA_RST = 25,
mbed_official	256:76fd9a263045	1284	RGU_EEPROM_RST = 27,
mbed_official	256:76fd9a263045	1285	RGU_GPIO_RST,
mbed_official	256:76fd9a263045	1286	RGU_FLASHB_RST,
mbed_official	256:76fd9a263045	1287	RGU_TIMER0_RST = 32,
mbed_official	256:76fd9a263045	1288	RGU_TIMER1_RST,
mbed_official	256:76fd9a263045	1289	RGU_TIMER2_RST,
mbed_official	256:76fd9a263045	1290	RGU_TIMER3_RST,
mbed_official	256:76fd9a263045	1291	RGU_RITIMER_RST,
mbed_official	256:76fd9a263045	1292	RGU_SCT_RST,
mbed_official	256:76fd9a263045	1293	RGU_MOTOCONPWM_RST,
mbed_official	256:76fd9a263045	1294	RGU_QEI_RST,
mbed_official	256:76fd9a263045	1295	RGU_ADC0_RST,
mbed_official	256:76fd9a263045	1296	RGU_ADC1_RST,
mbed_official	256:76fd9a263045	1297	RGU_DAC_RST,
mbed_official	256:76fd9a263045	1298	RGU_UART0_RST = 44,
mbed_official	256:76fd9a263045	1299	RGU_UART1_RST,
mbed_official	256:76fd9a263045	1300	RGU_UART2_RST,
mbed_official	256:76fd9a263045	1301	RGU_UART3_RST,
mbed_official	256:76fd9a263045	1302	RGU_I2C0_RST,
mbed_official	256:76fd9a263045	1303	RGU_I2C1_RST,
mbed_official	256:76fd9a263045	1304	RGU_SSP0_RST,
mbed_official	256:76fd9a263045	1305	RGU_SSP1_RST,
mbed_official	256:76fd9a263045	1306	RGU_I2S_RST,
mbed_official	256:76fd9a263045	1307	RGU_SPIFI_RST,
mbed_official	256:76fd9a263045	1308	RGU_CAN1_RST,
mbed_official	256:76fd9a263045	1309	RGU_CAN0_RST,
bogdanm	20:4263a77256ae	1310	#ifdef CHIP_LPC43XX
mbed_official	256:76fd9a263045	1311	RGU_M0APP_RST,
mbed_official	256:76fd9a263045	1312	RGU_SGPIO_RST,
mbed_official	256:76fd9a263045	1313	RGU_SPI_RST,
bogdanm	20:4263a77256ae	1314	#endif
mbed_official	256:76fd9a263045	1315	RGU_LAST_RST = 63,
mbed_official	294:78f9587bb26d	1316	} RGU_RST_T;
bogdanm	20:4263a77256ae	1317
mbed_official	256:76fd9a263045	1318	typedef struct { /* RGU Structure */
mbed_official	256:76fd9a263045	1319	__I uint32_t RESERVED0[64];
mbed_official	256:76fd9a263045	1320	__O uint32_t RESET_CTRL0; /* Reset control register 0 */
mbed_official	256:76fd9a263045	1321	__O uint32_t RESET_CTRL1; /* Reset control register 1 */
mbed_official	256:76fd9a263045	1322	__I uint32_t RESERVED1[2];
mbed_official	256:76fd9a263045	1323	__IO uint32_t RESET_STATUS0; /* Reset status register 0 */
mbed_official	256:76fd9a263045	1324	__IO uint32_t RESET_STATUS1; /* Reset status register 1 */
mbed_official	256:76fd9a263045	1325	__IO uint32_t RESET_STATUS2; /* Reset status register 2 */
mbed_official	256:76fd9a263045	1326	__IO uint32_t RESET_STATUS3; /* Reset status register 3 */
mbed_official	256:76fd9a263045	1327	__I uint32_t RESERVED2[12];
mbed_official	256:76fd9a263045	1328	__I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
mbed_official	256:76fd9a263045	1329	__I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
mbed_official	256:76fd9a263045	1330	__I uint32_t RESERVED3[170];
mbed_official	256:76fd9a263045	1331	__IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
bogdanm	20:4263a77256ae	1332	} LPC_RGU_T;
bogdanm	20:4263a77256ae	1333
mbed_official	256:76fd9a263045	1334	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1335	* Windowed Watchdog register block structure
bogdanm	20:4263a77256ae	1336	*/
bogdanm	20:4263a77256ae	1337	#define LPC_WWDT_BASE 0x40080000
bogdanm	20:4263a77256ae	1338
mbed_official	256:76fd9a263045	1339	typedef struct { /* WWDT Structure */
mbed_official	256:76fd9a263045	1340	__IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
mbed_official	256:76fd9a263045	1341	__IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
mbed_official	256:76fd9a263045	1342	__O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
mbed_official	256:76fd9a263045	1343	__I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
bogdanm	20:4263a77256ae	1344	#ifdef WATCHDOG_CLKSEL_SUPPORT
mbed_official	256:76fd9a263045	1345	__IO uint32_t CLKSEL; /* Watchdog clock select register. */
bogdanm	20:4263a77256ae	1346	#else
mbed_official	256:76fd9a263045	1347	__I uint32_t RESERVED0;
bogdanm	20:4263a77256ae	1348	#endif
bogdanm	20:4263a77256ae	1349	#ifdef WATCHDOG_WINDOW_SUPPORT
mbed_official	256:76fd9a263045	1350	__IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
mbed_official	256:76fd9a263045	1351	__IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
bogdanm	20:4263a77256ae	1352	#endif
bogdanm	20:4263a77256ae	1353	} LPC_WWDT_T;
bogdanm	20:4263a77256ae	1354
mbed_official	256:76fd9a263045	1355	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1356	* USART register block structure
bogdanm	20:4263a77256ae	1357	*/
bogdanm	20:4263a77256ae	1358	#define LPC_USART0_BASE 0x40081000
bogdanm	20:4263a77256ae	1359	#define LPC_UART1_BASE 0x40082000
bogdanm	20:4263a77256ae	1360	#define LPC_USART2_BASE 0x400C1000
bogdanm	20:4263a77256ae	1361	#define LPC_USART3_BASE 0x400C2000
bogdanm	20:4263a77256ae	1362
mbed_official	256:76fd9a263045	1363	typedef struct { /* USARTn Structure */
bogdanm	20:4263a77256ae	1364
mbed_official	256:76fd9a263045	1365	union {
mbed_official	256:76fd9a263045	1366	__IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
mbed_official	256:76fd9a263045	1367	__O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
mbed_official	256:76fd9a263045	1368	__I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
mbed_official	256:76fd9a263045	1369	};
bogdanm	20:4263a77256ae	1370
mbed_official	256:76fd9a263045	1371	union {
mbed_official	256:76fd9a263045	1372	__IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
mbed_official	256:76fd9a263045	1373	__IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
mbed_official	256:76fd9a263045	1374	};
bogdanm	20:4263a77256ae	1375
mbed_official	256:76fd9a263045	1376	union {
mbed_official	256:76fd9a263045	1377	__O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
mbed_official	256:76fd9a263045	1378	__I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
mbed_official	256:76fd9a263045	1379	};
bogdanm	20:4263a77256ae	1380
mbed_official	256:76fd9a263045	1381	__IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
mbed_official	256:76fd9a263045	1382	__IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
mbed_official	256:76fd9a263045	1383	__I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
mbed_official	256:76fd9a263045	1384	__I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
mbed_official	256:76fd9a263045	1385	__IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
mbed_official	256:76fd9a263045	1386	__IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
mbed_official	256:76fd9a263045	1387	__IO uint32_t ICR; /* IrDA control register (not all UARTS) */
mbed_official	256:76fd9a263045	1388	__IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
mbed_official	256:76fd9a263045	1389	__IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
mbed_official	256:76fd9a263045	1390	__IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
mbed_official	256:76fd9a263045	1391	uint32_t RESERVED0[3];
mbed_official	256:76fd9a263045	1392	__IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
mbed_official	256:76fd9a263045	1393	__I uint32_t RESERVED1[1];
mbed_official	256:76fd9a263045	1394	__IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
mbed_official	256:76fd9a263045	1395	__IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
mbed_official	256:76fd9a263045	1396	__IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
mbed_official	256:76fd9a263045	1397	__IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
mbed_official	256:76fd9a263045	1398	union {
mbed_official	256:76fd9a263045	1399	__IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
mbed_official	256:76fd9a263045	1400	__I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
mbed_official	256:76fd9a263045	1401	};
bogdanm	20:4263a77256ae	1402
mbed_official	256:76fd9a263045	1403	__IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
bogdanm	20:4263a77256ae	1404	} LPC_USART_T;
bogdanm	20:4263a77256ae	1405
mbed_official	256:76fd9a263045	1406	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1407	* SSP register block structure
bogdanm	20:4263a77256ae	1408	*/
bogdanm	20:4263a77256ae	1409	#define LPC_SSP0_BASE 0x40083000
bogdanm	20:4263a77256ae	1410	#define LPC_SSP1_BASE 0x400C5000
bogdanm	20:4263a77256ae	1411
mbed_official	256:76fd9a263045	1412	typedef struct { /* SSPn Structure */
mbed_official	256:76fd9a263045	1413	__IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
mbed_official	256:76fd9a263045	1414	__IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
mbed_official	256:76fd9a263045	1415	__IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
mbed_official	256:76fd9a263045	1416	__I uint32_t SR; /* Status Register */
mbed_official	256:76fd9a263045	1417	__IO uint32_t CPSR; /* Clock Prescale Register */
mbed_official	256:76fd9a263045	1418	__IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
mbed_official	256:76fd9a263045	1419	__I uint32_t RIS; /* Raw Interrupt Status Register */
mbed_official	256:76fd9a263045	1420	__I uint32_t MIS; /* Masked Interrupt Status Register */
mbed_official	256:76fd9a263045	1421	__O uint32_t ICR; /* SSPICR Interrupt Clear Register */
mbed_official	256:76fd9a263045	1422	__IO uint32_t DMACR; /* SSPn DMA control register */
bogdanm	20:4263a77256ae	1423	} LPC_SSP_T;
bogdanm	20:4263a77256ae	1424
mbed_official	256:76fd9a263045	1425	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1426	* 32-bit Standard timer register block structure
bogdanm	20:4263a77256ae	1427	*/
bogdanm	20:4263a77256ae	1428	#define LPC_TIMER0_BASE 0x40084000
bogdanm	20:4263a77256ae	1429	#define LPC_TIMER1_BASE 0x40085000
bogdanm	20:4263a77256ae	1430	#define LPC_TIMER2_BASE 0x400C3000
bogdanm	20:4263a77256ae	1431	#define LPC_TIMER3_BASE 0x400C4000
bogdanm	20:4263a77256ae	1432
mbed_official	256:76fd9a263045	1433	typedef struct { /* TIMERn Structure */
mbed_official	256:76fd9a263045	1434	__IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
mbed_official	256:76fd9a263045	1435	__IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
mbed_official	256:76fd9a263045	1436	__IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
mbed_official	256:76fd9a263045	1437	__IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
mbed_official	256:76fd9a263045	1438	__IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
mbed_official	256:76fd9a263045	1439	__IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
mbed_official	256:76fd9a263045	1440	__IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
mbed_official	256:76fd9a263045	1441	__IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
mbed_official	256:76fd9a263045	1442	__IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
mbed_official	256:76fd9a263045	1443	__IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
mbed_official	256:76fd9a263045	1444	__I uint32_t RESERVED0[12];
mbed_official	256:76fd9a263045	1445	__IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
mbed_official	256:76fd9a263045	1446	} LPC_TIMER_T;
mbed_official	256:76fd9a263045	1447
mbed_official	256:76fd9a263045	1448	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1449	* System Control Unit register block
bogdanm	20:4263a77256ae	1450	*/
bogdanm	20:4263a77256ae	1451	#define LPC_SCU_BASE 0x40086000
bogdanm	20:4263a77256ae	1452
bogdanm	20:4263a77256ae	1453	typedef struct {
mbed_official	256:76fd9a263045	1454	__IO uint32_t SFSP[16][32];
mbed_official	256:76fd9a263045	1455	__I uint32_t RESERVED0[256];
mbed_official	256:76fd9a263045	1456	__IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
mbed_official	256:76fd9a263045	1457	__I uint32_t RESERVED16[28];
mbed_official	256:76fd9a263045	1458	__IO uint32_t SFSUSB; /* Pin configuration register for USB */
mbed_official	256:76fd9a263045	1459	__IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
mbed_official	256:76fd9a263045	1460	__IO uint32_t ENAIO[3]; /* Analog function select registers */
mbed_official	256:76fd9a263045	1461	__I uint32_t RESERVED17[27];
mbed_official	256:76fd9a263045	1462	__IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
mbed_official	256:76fd9a263045	1463	__I uint32_t RESERVED18[63];
mbed_official	256:76fd9a263045	1464	__IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
mbed_official	256:76fd9a263045	1465	__IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
bogdanm	20:4263a77256ae	1466	} LPC_SCU_T;
bogdanm	20:4263a77256ae	1467
mbed_official	256:76fd9a263045	1468	/*
bogdanm	20:4263a77256ae	1469	* SCU function and mode selection definitions
bogdanm	20:4263a77256ae	1470	* See the User Manual for specific modes and functions supoprted by the
bogdanm	20:4263a77256ae	1471	* various LPC18xx/43xx devices. Functionality can vary per device.
bogdanm	20:4263a77256ae	1472	*/
mbed_official	256:76fd9a263045	1473	#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
mbed_official	256:76fd9a263045	1474	#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
mbed_official	256:76fd9a263045	1475	#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
mbed_official	256:76fd9a263045	1476	#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
mbed_official	256:76fd9a263045	1477	#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
mbed_official	256:76fd9a263045	1478	#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
mbed_official	256:76fd9a263045	1479	#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
mbed_official	256:76fd9a263045	1480	#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
mbed_official	256:76fd9a263045	1481	#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
mbed_official	256:76fd9a263045	1482	#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
mbed_official	256:76fd9a263045	1483	#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
mbed_official	256:76fd9a263045	1484
mbed_official	256:76fd9a263045	1485	#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
mbed_official	256:76fd9a263045	1486	#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
mbed_official	256:76fd9a263045	1487	#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
mbed_official	256:76fd9a263045	1488	#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
mbed_official	256:76fd9a263045	1489	#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
mbed_official	256:76fd9a263045	1490	#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
mbed_official	256:76fd9a263045	1491	#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
mbed_official	256:76fd9a263045	1492	#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
bogdanm	20:4263a77256ae	1493
bogdanm	20:4263a77256ae	1494	/* Common SCU configurations */
mbed_official	256:76fd9a263045	1495	#define SCU_PINIO_FAST (SCU_MODE_INACT \| SCU_MODE_HIGHSPEEDSLEW_EN \| SCU_MODE_INBUFF_EN \| SCU_MODE_ZIF_DIS)
bogdanm	20:4263a77256ae	1496	#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
mbed_official	256:76fd9a263045	1497	#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN \| SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
mbed_official	256:76fd9a263045	1498	#define SCU_PINIO_PULLNONE (SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
bogdanm	20:4263a77256ae	1499
bogdanm	20:4263a77256ae	1500	/* Calculate SCU offset and register address from group and pin number */
mbed_official	294:78f9587bb26d	1501	#define SCU_OFF(group, num) ((group << 7) + (num << 2))
bogdanm	20:4263a77256ae	1502	#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
bogdanm	20:4263a77256ae	1503
bogdanm	20:4263a77256ae	1504	/**
mbed_official	256:76fd9a263045	1505	* SCU function and mode selection definitions (old)
mbed_official	256:76fd9a263045	1506	* For backwards compatibility.
mbed_official	256:76fd9a263045	1507	*/
mbed_official	256:76fd9a263045	1508	#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
mbed_official	256:76fd9a263045	1509	#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
mbed_official	256:76fd9a263045	1510	#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
mbed_official	256:76fd9a263045	1511	#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
mbed_official	256:76fd9a263045	1512	#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
mbed_official	256:76fd9a263045	1513	#define MD_EZI (0x1 << 6) /* Input buffer enable */
mbed_official	256:76fd9a263045	1514	#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
mbed_official	256:76fd9a263045	1515	#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
mbed_official	256:76fd9a263045	1516	#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
mbed_official	256:76fd9a263045	1517	#define MD_PLN_FAST (MD_PLN \| MD_EZI \| MD_ZI \| MD_EHS)
mbed_official	256:76fd9a263045	1518	#define I2C0_STANDARD_FAST_MODE (1 << 3 \| 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
mbed_official	256:76fd9a263045	1519	#define I2C0_FAST_MODE_PLUS (2 << 1 \| 1 << 3 \| 1 << 7 \| 1 << 10 \| 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
mbed_official	256:76fd9a263045	1520
mbed_official	256:76fd9a263045	1521	#define FUNC0 0x0 /* Pin function 0 */
mbed_official	256:76fd9a263045	1522	#define FUNC1 0x1 /* Pin function 1 */
mbed_official	256:76fd9a263045	1523	#define FUNC2 0x2 /* Pin function 2 */
mbed_official	256:76fd9a263045	1524	#define FUNC3 0x3 /* Pin function 3 */
mbed_official	256:76fd9a263045	1525	#define FUNC4 0x4 /* Pin function 4 */
mbed_official	256:76fd9a263045	1526	#define FUNC5 0x5 /* Pin function 5 */
mbed_official	256:76fd9a263045	1527	#define FUNC6 0x6 /* Pin function 6 */
mbed_official	256:76fd9a263045	1528	#define FUNC7 0x7 /* Pin function 7 */
mbed_official	256:76fd9a263045	1529
mbed_official	256:76fd9a263045	1530	#define PORT_OFFSET 0x80 /* Port offset definition */
mbed_official	256:76fd9a263045	1531	#define PIN_OFFSET 0x04 /* Pin offset definition */
mbed_official	256:76fd9a263045	1532
mbed_official	256:76fd9a263045	1533	/* Returns the SFSP register address in the SCU for a pin and port,
mbed_official	256:76fd9a263045	1534	recommend using ((volatile int ) &LPC_SCU->SFSP[po][pi];) */
mbed_official	256:76fd9a263045	1535	#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
mbed_official	256:76fd9a263045	1536	((volatile int ) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
mbed_official	256:76fd9a263045	1537
mbed_official	256:76fd9a263045	1538	/* Returns the address in the SCU for a SFSCLK clock register,
mbed_official	256:76fd9a263045	1539	recommend using ((volatile int ) &LPC_SCU->SFSCLK[c];) */
mbed_official	256:76fd9a263045	1540	#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
mbed_official	256:76fd9a263045	1541	((volatile int ) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
mbed_official	256:76fd9a263045	1542
mbed_official	256:76fd9a263045	1543	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1544	* GPIO pin interrupt register block structure
bogdanm	20:4263a77256ae	1545	*/
bogdanm	20:4263a77256ae	1546	#define LPC_GPIO_PIN_INT_BASE 0x40087000
bogdanm	20:4263a77256ae	1547
mbed_official	256:76fd9a263045	1548	typedef struct { /* GPIO_PIN_INT Structure */
mbed_official	256:76fd9a263045	1549	__IO uint32_t ISEL; /* Pin Interrupt Mode register */
mbed_official	256:76fd9a263045	1550	__IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
mbed_official	256:76fd9a263045	1551	__O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
mbed_official	256:76fd9a263045	1552	__O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
mbed_official	256:76fd9a263045	1553	__IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
mbed_official	256:76fd9a263045	1554	__O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
mbed_official	256:76fd9a263045	1555	__O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
mbed_official	256:76fd9a263045	1556	__IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
mbed_official	256:76fd9a263045	1557	__IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
mbed_official	256:76fd9a263045	1558	__IO uint32_t IST; /* Pin Interrupt Status register */
bogdanm	20:4263a77256ae	1559	} LPC_GPIOPININT_T;
bogdanm	20:4263a77256ae	1560
bogdanm	20:4263a77256ae	1561	typedef enum LPC_GPIOPININT_MODE {
mbed_official	256:76fd9a263045	1562	GPIOPININT_RISING_EDGE = 0x01,
mbed_official	256:76fd9a263045	1563	GPIOPININT_FALLING_EDGE = 0x02,
mbed_official	256:76fd9a263045	1564	GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
mbed_official	256:76fd9a263045	1565	GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
bogdanm	20:4263a77256ae	1566	} LPC_GPIOPININT_MODE_T;
bogdanm	20:4263a77256ae	1567
mbed_official	256:76fd9a263045	1568	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1569	* GPIO grouped interrupt register block structure
bogdanm	20:4263a77256ae	1570	*/
bogdanm	20:4263a77256ae	1571	#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
bogdanm	20:4263a77256ae	1572	#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
bogdanm	20:4263a77256ae	1573
mbed_official	256:76fd9a263045	1574	typedef struct { /* GPIO_GROUP_INTn Structure */
mbed_official	256:76fd9a263045	1575	__IO uint32_t CTRL; /* GPIO grouped interrupt control register */
mbed_official	256:76fd9a263045	1576	__I uint32_t RESERVED0[7];
mbed_official	256:76fd9a263045	1577	__IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
mbed_official	256:76fd9a263045	1578	__IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
bogdanm	20:4263a77256ae	1579	} LPC_GPIOGROUPINT_T;
bogdanm	20:4263a77256ae	1580
mbed_official	256:76fd9a263045	1581	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1582	* Motor Control PWM register block structure
bogdanm	20:4263a77256ae	1583	*/
bogdanm	20:4263a77256ae	1584	#define LPC_MCPWM_BASE 0x400A0000
bogdanm	20:4263a77256ae	1585
mbed_official	256:76fd9a263045	1586	typedef struct { /* MCPWM Structure */
mbed_official	256:76fd9a263045	1587	__I uint32_t CON; /* PWM Control read address */
mbed_official	256:76fd9a263045	1588	__O uint32_t CON_SET; /* PWM Control set address */
mbed_official	256:76fd9a263045	1589	__O uint32_t CON_CLR; /* PWM Control clear address */
mbed_official	256:76fd9a263045	1590	__I uint32_t CAPCON; /* Capture Control read address */
mbed_official	256:76fd9a263045	1591	__O uint32_t CAPCON_SET; /* Capture Control set address */
mbed_official	256:76fd9a263045	1592	__O uint32_t CAPCON_CLR; /* Event Control clear address */
mbed_official	256:76fd9a263045	1593	__IO uint32_t TC[3]; /* Timer Counter register */
mbed_official	256:76fd9a263045	1594	__IO uint32_t LIM[3]; /* Limit register */
mbed_official	256:76fd9a263045	1595	__IO uint32_t MAT[3]; /* Match register */
mbed_official	256:76fd9a263045	1596	__IO uint32_t DT; /* Dead time register */
mbed_official	256:76fd9a263045	1597	__IO uint32_t CCP; /* Communication Pattern register */
mbed_official	256:76fd9a263045	1598	__I uint32_t CAP[3]; /* Capture register */
mbed_official	256:76fd9a263045	1599	__I uint32_t INTEN; /* Interrupt Enable read address */
mbed_official	256:76fd9a263045	1600	__O uint32_t INTEN_SET; /* Interrupt Enable set address */
mbed_official	256:76fd9a263045	1601	__O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
mbed_official	256:76fd9a263045	1602	__I uint32_t CNTCON; /* Count Control read address */
mbed_official	256:76fd9a263045	1603	__O uint32_t CNTCON_SET; /* Count Control set address */
mbed_official	256:76fd9a263045	1604	__O uint32_t CNTCON_CLR; /* Count Control clear address */
mbed_official	256:76fd9a263045	1605	__I uint32_t INTF; /* Interrupt flags read address */
mbed_official	256:76fd9a263045	1606	__O uint32_t INTF_SET; /* Interrupt flags set address */
mbed_official	256:76fd9a263045	1607	__O uint32_t INTF_CLR; /* Interrupt flags clear address */
mbed_official	256:76fd9a263045	1608	__O uint32_t CAP_CLR; /* Capture clear address */
bogdanm	20:4263a77256ae	1609	} LPC_MCPWM_T;
bogdanm	20:4263a77256ae	1610
mbed_official	256:76fd9a263045	1611	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1612	* I2C register block structure
bogdanm	20:4263a77256ae	1613	*/
bogdanm	20:4263a77256ae	1614	#define LPC_I2C0_BASE 0x400A1000
bogdanm	20:4263a77256ae	1615	#define LPC_I2C1_BASE 0x400E0000
bogdanm	20:4263a77256ae	1616
mbed_official	256:76fd9a263045	1617	typedef struct { /* I2C0 Structure */
mbed_official	256:76fd9a263045	1618	__IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
mbed_official	256:76fd9a263045	1619	__I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
mbed_official	256:76fd9a263045	1620	__IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
mbed_official	256:76fd9a263045	1621	__IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
mbed_official	256:76fd9a263045	1622	__IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
mbed_official	256:76fd9a263045	1623	__IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
mbed_official	256:76fd9a263045	1624	__O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
mbed_official	256:76fd9a263045	1625	__IO uint32_t MMCTRL; /* Monitor mode control register. */
mbed_official	256:76fd9a263045	1626	__IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
mbed_official	256:76fd9a263045	1627	__IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
mbed_official	256:76fd9a263045	1628	__IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
mbed_official	256:76fd9a263045	1629	__I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
mbed_official	256:76fd9a263045	1630	__IO uint32_t MASK[4]; /* I2C Slave address mask register */
bogdanm	20:4263a77256ae	1631	} LPC_I2C_T;
bogdanm	20:4263a77256ae	1632
mbed_official	256:76fd9a263045	1633	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1634	* I2S register block structure
bogdanm	20:4263a77256ae	1635	*/
bogdanm	20:4263a77256ae	1636	#define LPC_I2S0_BASE 0x400A2000
bogdanm	20:4263a77256ae	1637	#define LPC_I2S1_BASE 0x400A3000
bogdanm	20:4263a77256ae	1638
mbed_official	256:76fd9a263045	1639	typedef struct { /* I2S Structure */
mbed_official	256:76fd9a263045	1640	__IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
mbed_official	256:76fd9a263045	1641	__IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
mbed_official	256:76fd9a263045	1642	__O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
mbed_official	256:76fd9a263045	1643	__I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
mbed_official	256:76fd9a263045	1644	__I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
mbed_official	256:76fd9a263045	1645	__IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
mbed_official	256:76fd9a263045	1646	__IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
mbed_official	256:76fd9a263045	1647	__IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
mbed_official	256:76fd9a263045	1648	__IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
mbed_official	256:76fd9a263045	1649	__IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
mbed_official	256:76fd9a263045	1650	__IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
mbed_official	256:76fd9a263045	1651	__IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
mbed_official	256:76fd9a263045	1652	__IO uint32_t TXMODE; /* I2S Transmit mode control */
mbed_official	256:76fd9a263045	1653	__IO uint32_t RXMODE; /* I2S Receive mode control */
bogdanm	20:4263a77256ae	1654	} LPC_I2S_T;
bogdanm	20:4263a77256ae	1655
mbed_official	256:76fd9a263045	1656	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1657	* CCAN Controller Area Network register block structure
bogdanm	20:4263a77256ae	1658	*/
bogdanm	20:4263a77256ae	1659	#define LPC_C_CAN1_BASE 0x400A4000
bogdanm	20:4263a77256ae	1660	#define LPC_C_CAN0_BASE 0x400E2000
bogdanm	20:4263a77256ae	1661
mbed_official	256:76fd9a263045	1662	typedef struct { /* C_CAN message interface Structure */
mbed_official	256:76fd9a263045	1663	__IO uint32_t IF_CMDREQ; /* Message interface command request */
mbed_official	256:76fd9a263045	1664	union {
mbed_official	256:76fd9a263045	1665	__IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
mbed_official	256:76fd9a263045	1666	__IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
mbed_official	256:76fd9a263045	1667	};
bogdanm	20:4263a77256ae	1668
mbed_official	256:76fd9a263045	1669	__IO uint32_t IF_MSK1; /* Message interface mask 1 */
mbed_official	256:76fd9a263045	1670	__IO uint32_t IF_MSK2; /* Message interface mask 2 */
mbed_official	256:76fd9a263045	1671	__IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
mbed_official	256:76fd9a263045	1672	__IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
mbed_official	256:76fd9a263045	1673	__IO uint32_t IF_MCTRL; /* Message interface message control */
mbed_official	256:76fd9a263045	1674	__IO uint32_t IF_DA1; /* Message interface data A1 */
mbed_official	256:76fd9a263045	1675	__IO uint32_t IF_DA2; /* Message interface data A2 */
mbed_official	256:76fd9a263045	1676	__IO uint32_t IF_DB1; /* Message interface data B1 */
mbed_official	256:76fd9a263045	1677	__IO uint32_t IF_DB2; /* Message interface data B2 */
mbed_official	256:76fd9a263045	1678	__I uint32_t RESERVED[13];
bogdanm	20:4263a77256ae	1679	} LPC_CCAN_IF_T;
bogdanm	20:4263a77256ae	1680
mbed_official	256:76fd9a263045	1681	typedef struct { /* C_CAN Structure */
mbed_official	256:76fd9a263045	1682	__IO uint32_t CNTL; /* CAN control */
mbed_official	256:76fd9a263045	1683	__IO uint32_t STAT; /* Status register */
mbed_official	256:76fd9a263045	1684	__I uint32_t EC; /* Error counter */
mbed_official	256:76fd9a263045	1685	__IO uint32_t BT; /* Bit timing register */
mbed_official	256:76fd9a263045	1686	__I uint32_t INT; /* Interrupt register */
mbed_official	256:76fd9a263045	1687	__IO uint32_t TEST; /* Test register */
mbed_official	256:76fd9a263045	1688	__IO uint32_t BRPE; /* Baud rate prescaler extension register */
mbed_official	256:76fd9a263045	1689	__I uint32_t RESERVED0;
mbed_official	256:76fd9a263045	1690	LPC_CCAN_IF_T IF[2];
mbed_official	256:76fd9a263045	1691	__I uint32_t RESERVED2[8];
mbed_official	256:76fd9a263045	1692	__I uint32_t TXREQ1; /* Transmission request 1 */
mbed_official	256:76fd9a263045	1693	__I uint32_t TXREQ2; /* Transmission request 2 */
mbed_official	256:76fd9a263045	1694	__I uint32_t RESERVED3[6];
mbed_official	256:76fd9a263045	1695	__I uint32_t ND1; /* New data 1 */
mbed_official	256:76fd9a263045	1696	__I uint32_t ND2; /* New data 2 */
mbed_official	256:76fd9a263045	1697	__I uint32_t RESERVED4[6];
mbed_official	256:76fd9a263045	1698	__I uint32_t IR1; /* Interrupt pending 1 */
mbed_official	256:76fd9a263045	1699	__I uint32_t IR2; /* Interrupt pending 2 */
mbed_official	256:76fd9a263045	1700	__I uint32_t RESERVED5[6];
mbed_official	256:76fd9a263045	1701	__I uint32_t MSGV1; /* Message valid 1 */
mbed_official	256:76fd9a263045	1702	__I uint32_t MSGV2; /* Message valid 2 */
mbed_official	256:76fd9a263045	1703	__I uint32_t RESERVED6[6];
mbed_official	256:76fd9a263045	1704	__IO uint32_t CLKDIV; /* CAN clock divider register */
bogdanm	20:4263a77256ae	1705	} LPC_CCAN_T;
bogdanm	20:4263a77256ae	1706
mbed_official	256:76fd9a263045	1707	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1708	* Repetitive Interrupt Timer register block structure
bogdanm	20:4263a77256ae	1709	*/
bogdanm	20:4263a77256ae	1710	#define LPC_RITIMER_BASE 0x400C0000
bogdanm	20:4263a77256ae	1711
mbed_official	256:76fd9a263045	1712	typedef struct { /* RITIMER Structure */
mbed_official	256:76fd9a263045	1713	__IO uint32_t COMPVAL; /* Compare register */
mbed_official	256:76fd9a263045	1714	__IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
mbed_official	256:76fd9a263045	1715	__IO uint32_t CTRL; /* Control register. */
mbed_official	256:76fd9a263045	1716	__IO uint32_t COUNTER; /* 32-bit counter */
bogdanm	20:4263a77256ae	1717	} LPC_RITIMER_T;
bogdanm	20:4263a77256ae	1718
mbed_official	256:76fd9a263045	1719	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1720	* Quadrature Encoder Interface register block structure
bogdanm	20:4263a77256ae	1721	*/
bogdanm	20:4263a77256ae	1722	#define LPC_QEI_BASE 0x400C6000
bogdanm	20:4263a77256ae	1723
mbed_official	256:76fd9a263045	1724	typedef struct { /* QEI Structure */
mbed_official	256:76fd9a263045	1725	__O uint32_t CON; /* Control register */
mbed_official	256:76fd9a263045	1726	__I uint32_t STAT; /* Encoder status register */
mbed_official	256:76fd9a263045	1727	__IO uint32_t CONF; /* Configuration register */
mbed_official	256:76fd9a263045	1728	__I uint32_t POS; /* Position register */
mbed_official	256:76fd9a263045	1729	__IO uint32_t MAXPOS; /* Maximum position register */
mbed_official	256:76fd9a263045	1730	__IO uint32_t CMPOS0; /* position compare register 0 */
mbed_official	256:76fd9a263045	1731	__IO uint32_t CMPOS1; /* position compare register 1 */
mbed_official	256:76fd9a263045	1732	__IO uint32_t CMPOS2; /* position compare register 2 */
mbed_official	256:76fd9a263045	1733	__I uint32_t INXCNT; /* Index count register */
mbed_official	256:76fd9a263045	1734	__IO uint32_t INXCMP0; /* Index compare register 0 */
mbed_official	256:76fd9a263045	1735	__IO uint32_t LOAD; /* Velocity timer reload register */
mbed_official	256:76fd9a263045	1736	__I uint32_t TIME; /* Velocity timer register */
mbed_official	256:76fd9a263045	1737	__I uint32_t VEL; /* Velocity counter register */
mbed_official	256:76fd9a263045	1738	__I uint32_t CAP; /* Velocity capture register */
mbed_official	256:76fd9a263045	1739	__IO uint32_t VELCOMP; /* Velocity compare register */
mbed_official	256:76fd9a263045	1740	__IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
mbed_official	256:76fd9a263045	1741	__IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
mbed_official	256:76fd9a263045	1742	__IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
mbed_official	256:76fd9a263045	1743	__IO uint32_t WINDOW; /* Index acceptance window register */
mbed_official	256:76fd9a263045	1744	__IO uint32_t INXCMP1; /* Index compare register 1 */
mbed_official	256:76fd9a263045	1745	__IO uint32_t INXCMP2; /* Index compare register 2 */
mbed_official	256:76fd9a263045	1746	__I uint32_t RESERVED0[993];
mbed_official	256:76fd9a263045	1747	__O uint32_t IEC; /* Interrupt enable clear register */
mbed_official	256:76fd9a263045	1748	__O uint32_t IES; /* Interrupt enable set register */
mbed_official	256:76fd9a263045	1749	__I uint32_t INTSTAT; /* Interrupt status register */
mbed_official	256:76fd9a263045	1750	__I uint32_t IE; /* Interrupt enable register */
mbed_official	256:76fd9a263045	1751	__O uint32_t CLR; /* Interrupt status clear register */
mbed_official	256:76fd9a263045	1752	__O uint32_t SET; /* Interrupt status set register */
bogdanm	20:4263a77256ae	1753	} LPC_QEI_T;
bogdanm	20:4263a77256ae	1754
mbed_official	256:76fd9a263045	1755	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1756	* Global Input Multiplexer Array (GIMA) register block structure
bogdanm	20:4263a77256ae	1757	*/
bogdanm	20:4263a77256ae	1758	#define LPC_GIMA_BASE 0x400C7000
bogdanm	20:4263a77256ae	1759
mbed_official	256:76fd9a263045	1760	typedef struct { /* GIMA Structure */
mbed_official	256:76fd9a263045	1761	__IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x4)+y)) /
mbed_official	256:76fd9a263045	1762	__IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
mbed_official	256:76fd9a263045	1763	__IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
mbed_official	256:76fd9a263045	1764	__IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
mbed_official	256:76fd9a263045	1765	__IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
mbed_official	256:76fd9a263045	1766	__IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
mbed_official	256:76fd9a263045	1767	__IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
mbed_official	256:76fd9a263045	1768	__IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
bogdanm	20:4263a77256ae	1769	} LPC_GIMA_T;
bogdanm	20:4263a77256ae	1770
mbed_official	256:76fd9a263045	1771	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1772	* DAC register block structure
bogdanm	20:4263a77256ae	1773	*/
bogdanm	20:4263a77256ae	1774	#define LPC_DAC_BASE 0x400E1000
bogdanm	20:4263a77256ae	1775
mbed_official	256:76fd9a263045	1776	typedef struct { /* DAC Structure */
mbed_official	256:76fd9a263045	1777	__IO uint32_t CR; /* DAC register. Holds the conversion data. */
mbed_official	256:76fd9a263045	1778	__IO uint32_t CTRL; /* DAC control register. */
mbed_official	256:76fd9a263045	1779	__IO uint32_t CNTVAL; /* DAC counter value register. */
bogdanm	20:4263a77256ae	1780	} LPC_DAC_T;
bogdanm	20:4263a77256ae	1781
bogdanm	20:4263a77256ae	1782	/* After the selected settling time after this field is written with a
bogdanm	20:4263a77256ae	1783	* new VALUE, the voltage on the AOUT pin (with respect to VSSA)
bogdanm	20:4263a77256ae	1784	* is VALUE/1024 ? VREF
bogdanm	20:4263a77256ae	1785	*/
bogdanm	20:4263a77256ae	1786	#define DAC_RANGE 0x3FF
mbed_official	256:76fd9a263045	1787	#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
mbed_official	256:76fd9a263045	1788	#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
mbed_official	256:76fd9a263045	1789	#define DAC_VALUE(n) DAC_SET(n)
bogdanm	20:4263a77256ae	1790	/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
bogdanm	20:4263a77256ae	1791	* and the maximum current is 700 microAmpere
bogdanm	20:4263a77256ae	1792	* If this bit = 1: The settling time of the DAC is 2.5 microsecond
bogdanm	20:4263a77256ae	1793	* and the maximum current is 350 microAmpere
bogdanm	20:4263a77256ae	1794	*/
bogdanm	20:4263a77256ae	1795	#define DAC_BIAS_EN ((uint32_t) (1 << 16))
bogdanm	20:4263a77256ae	1796	/* Value to reload interrupt DMA counter */
bogdanm	20:4263a77256ae	1797	#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
bogdanm	20:4263a77256ae	1798
bogdanm	20:4263a77256ae	1799	#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
bogdanm	20:4263a77256ae	1800	#define DAC_CNT_ENA ((uint32_t) (1 << 2))
bogdanm	20:4263a77256ae	1801	#define DAC_DMA_ENA ((uint32_t) (1 << 3))
bogdanm	20:4263a77256ae	1802	#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
bogdanm	20:4263a77256ae	1803
bogdanm	20:4263a77256ae	1804	/* Current option in DAC configuration option */
mbed_official	256:76fd9a263045	1805	typedef enum DAC_CURRENT_OPT {
mbed_official	256:76fd9a263045	1806	DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
mbed_official	256:76fd9a263045	1807	allows for a maximum update rate of 1 MHz */
mbed_official	256:76fd9a263045	1808	DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
mbed_official	256:76fd9a263045	1809	allows for a maximum update rate of 400 kHz */
mbed_official	256:76fd9a263045	1810	} DAC_CURRENT_OPT_T;
bogdanm	20:4263a77256ae	1811
mbed_official	256:76fd9a263045	1812	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1813	* ADC register block structure
bogdanm	20:4263a77256ae	1814	*/
bogdanm	20:4263a77256ae	1815	#define LPC_ADC0_BASE 0x400E3000
bogdanm	20:4263a77256ae	1816	#define LPC_ADC1_BASE 0x400E4000
bogdanm	20:4263a77256ae	1817	#define ADC_ACC_10BITS
bogdanm	20:4263a77256ae	1818
mbed_official	256:76fd9a263045	1819	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1820	* 10 or 12-bit ADC register block structure
bogdanm	20:4263a77256ae	1821	*/
mbed_official	256:76fd9a263045	1822	typedef struct { /* ADCn Structure */
mbed_official	256:76fd9a263045	1823	__IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
mbed_official	256:76fd9a263045	1824	__I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
mbed_official	256:76fd9a263045	1825	__I uint32_t RESERVED0;
mbed_official	256:76fd9a263045	1826	__IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
mbed_official	256:76fd9a263045	1827	__I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
mbed_official	256:76fd9a263045	1828	__I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
bogdanm	20:4263a77256ae	1829	} LPC_ADC_T;
bogdanm	20:4263a77256ae	1830
bogdanm	20:4263a77256ae	1831	/* ADC register support bitfields and mask */
bogdanm	20:4263a77256ae	1832	#define ADC_RANGE 0x3FF
mbed_official	256:76fd9a263045	1833	#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
mbed_official	256:76fd9a263045	1834	#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
mbed_official	256:76fd9a263045	1835	#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
mbed_official	256:76fd9a263045	1836	#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
mbed_official	256:76fd9a263045	1837	#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
mbed_official	256:76fd9a263045	1838	#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
mbed_official	256:76fd9a263045	1839	#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
mbed_official	256:76fd9a263045	1840	#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
mbed_official	256:76fd9a263045	1841	#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
mbed_official	256:76fd9a263045	1842	#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
mbed_official	256:76fd9a263045	1843	#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
mbed_official	256:76fd9a263045	1844	#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
mbed_official	256:76fd9a263045	1845	#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
mbed_official	256:76fd9a263045	1846	#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
mbed_official	256:76fd9a263045	1847	#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
mbed_official	256:76fd9a263045	1848	#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
mbed_official	256:76fd9a263045	1849	#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
bogdanm	20:4263a77256ae	1850	#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) \| ADC_CR_BITACC(0x07) \| ADC_CR_PDN)
bogdanm	20:4263a77256ae	1851
mbed_official	256:76fd9a263045	1852	/* ADC status register used for IP drivers */
mbed_official	256:76fd9a263045	1853	typedef enum ADC_STATUS {
mbed_official	256:76fd9a263045	1854	ADC_DR_DONE_STAT, /* ADC data register staus */
mbed_official	256:76fd9a263045	1855	ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
mbed_official	256:76fd9a263045	1856	ADC_DR_ADINT_STAT /* ADC interrupt status */
mbed_official	256:76fd9a263045	1857	} ADC_STATUS_T;
bogdanm	20:4263a77256ae	1858
mbed_official	256:76fd9a263045	1859	/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
mbed_official	256:76fd9a263045	1860	typedef enum ADC_START_MODE {
mbed_official	256:76fd9a263045	1861	ADC_NO_START = 0,
mbed_official	256:76fd9a263045	1862	ADC_START_NOW, /* Start conversion now */
mbed_official	256:76fd9a263045	1863	ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
mbed_official	256:76fd9a263045	1864	ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
mbed_official	256:76fd9a263045	1865	ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
mbed_official	256:76fd9a263045	1866	ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
mbed_official	256:76fd9a263045	1867	ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
mbed_official	256:76fd9a263045	1868	} ADC_START_MODE_T;
mbed_official	256:76fd9a263045	1869
mbed_official	256:76fd9a263045	1870	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1871	* GPIO port register block structure
bogdanm	20:4263a77256ae	1872	*/
bogdanm	20:4263a77256ae	1873	#define LPC_GPIO_PORT_BASE 0x400F4000
mbed_official	256:76fd9a263045	1874	#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
mbed_official	256:76fd9a263045	1875	#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
mbed_official	256:76fd9a263045	1876	#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
mbed_official	256:76fd9a263045	1877	#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
mbed_official	256:76fd9a263045	1878	#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
mbed_official	256:76fd9a263045	1879	#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
mbed_official	256:76fd9a263045	1880	#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
mbed_official	256:76fd9a263045	1881	#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
bogdanm	20:4263a77256ae	1882
mbed_official	256:76fd9a263045	1883	typedef struct { /* GPIO_PORT Structure */
mbed_official	256:76fd9a263045	1884	__IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
mbed_official	256:76fd9a263045	1885	__IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
mbed_official	256:76fd9a263045	1886	__IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
mbed_official	256:76fd9a263045	1887	__IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
mbed_official	256:76fd9a263045	1888	__IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
mbed_official	256:76fd9a263045	1889	__IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
mbed_official	256:76fd9a263045	1890	__IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
mbed_official	256:76fd9a263045	1891	__O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
mbed_official	256:76fd9a263045	1892	__O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
bogdanm	20:4263a77256ae	1893	} LPC_GPIO_T;
bogdanm	20:4263a77256ae	1894
bogdanm	20:4263a77256ae	1895	/* Calculate GPIO offset and port register address from group and pin number */
bogdanm	20:4263a77256ae	1896	#define GPIO_OFF(port, pin) ((port << 5) + pin)
bogdanm	20:4263a77256ae	1897	#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
bogdanm	20:4263a77256ae	1898
mbed_official	256:76fd9a263045	1899	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1900	* SPI register block structure
bogdanm	20:4263a77256ae	1901	*/
bogdanm	20:4263a77256ae	1902	#define LPC_SPI_BASE 0x40100000
bogdanm	20:4263a77256ae	1903
mbed_official	256:76fd9a263045	1904	typedef struct { /* SPI Structure */
mbed_official	256:76fd9a263045	1905	__IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
mbed_official	256:76fd9a263045	1906	__I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
mbed_official	256:76fd9a263045	1907	__IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
mbed_official	256:76fd9a263045	1908	__IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
mbed_official	256:76fd9a263045	1909	__I uint32_t RESERVED0[3];
mbed_official	256:76fd9a263045	1910	__IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
bogdanm	20:4263a77256ae	1911	} LPC_SPI_T;
bogdanm	20:4263a77256ae	1912
bogdanm	20:4263a77256ae	1913	/* SPI CFG Register BitMask */
bogdanm	20:4263a77256ae	1914	#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
bogdanm	20:4263a77256ae	1915	/* Enable of controlling the number of bits per transfer */
bogdanm	20:4263a77256ae	1916	#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
bogdanm	20:4263a77256ae	1917	/* Mask of field of bit controlling */
bogdanm	20:4263a77256ae	1918	#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
bogdanm	20:4263a77256ae	1919	/* Set the number of bits per a transfer */
mbed_official	256:76fd9a263045	1920	#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
bogdanm	20:4263a77256ae	1921	/* SPI Clock Phase Select*/
mbed_official	256:76fd9a263045	1922	#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /Capture data on the first edge, Change data on the following edge/
mbed_official	256:76fd9a263045	1923	#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
bogdanm	20:4263a77256ae	1924	/* SPI Clock Polarity Select*/
mbed_official	256:76fd9a263045	1925	#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
mbed_official	256:76fd9a263045	1926	#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
bogdanm	20:4263a77256ae	1927	/* SPI Slave Mode Select */
bogdanm	20:4263a77256ae	1928	#define SPI_CR_SLAVE_EN ((uint32_t) 0)
bogdanm	20:4263a77256ae	1929	/* SPI Master Mode Select */
bogdanm	20:4263a77256ae	1930	#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
bogdanm	20:4263a77256ae	1931	/* SPI MSB First mode enable */
mbed_official	256:76fd9a263045	1932	#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
bogdanm	20:4263a77256ae	1933	/* SPI LSB First mode enable */
mbed_official	256:76fd9a263045	1934	#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
bogdanm	20:4263a77256ae	1935	/* SPI interrupt enable */
bogdanm	20:4263a77256ae	1936	#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
bogdanm	20:4263a77256ae	1937	/* SPI STAT Register BitMask */
bogdanm	20:4263a77256ae	1938	#define SPI_SR_BITMASK ((uint32_t) 0xF8)
bogdanm	20:4263a77256ae	1939	/* Slave abort Flag */
mbed_official	256:76fd9a263045	1940	#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
bogdanm	20:4263a77256ae	1941	/* Mode fault Flag */
mbed_official	256:76fd9a263045	1942	#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
bogdanm	20:4263a77256ae	1943	/* Read overrun flag*/
mbed_official	256:76fd9a263045	1944	#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
bogdanm	20:4263a77256ae	1945	/* Write collision flag. */
mbed_official	256:76fd9a263045	1946	#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
bogdanm	20:4263a77256ae	1947	/* SPI transfer complete flag. */
mbed_official	256:76fd9a263045	1948	#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
mbed_official	256:76fd9a263045	1949	/* SPI error flag */
bogdanm	20:4263a77256ae	1950	#define SPI_SR_ERROR (SPI_SR_ABRT \| SPI_SR_MODF \| SPI_SR_ROVR \| SPI_SR_WCOL)
bogdanm	20:4263a77256ae	1951	/* Enable SPI Test Mode */
bogdanm	20:4263a77256ae	1952	#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
bogdanm	20:4263a77256ae	1953	/* SPI interrupt flag */
bogdanm	20:4263a77256ae	1954	#define SPI_INT_SPIF ((uint32_t) (1 << 0))
bogdanm	20:4263a77256ae	1955	/* Receiver Data */
bogdanm	20:4263a77256ae	1956	#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
bogdanm	20:4263a77256ae	1957
bogdanm	20:4263a77256ae	1958	/* SPI Mode*/
bogdanm	20:4263a77256ae	1959	typedef enum LPC_SPI_MODE {
mbed_official	256:76fd9a263045	1960	SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
mbed_official	256:76fd9a263045	1961	SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
bogdanm	20:4263a77256ae	1962	} LPC_SPI_MODE_T;
bogdanm	20:4263a77256ae	1963
bogdanm	20:4263a77256ae	1964	/* SPI Clock Mode*/
bogdanm	20:4263a77256ae	1965	typedef enum LPC_SPI_CLOCK_MODE {
mbed_official	256:76fd9a263045	1966	SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
mbed_official	256:76fd9a263045	1967	SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
mbed_official	256:76fd9a263045	1968	SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
mbed_official	256:76fd9a263045	1969	SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
mbed_official	256:76fd9a263045	1970	SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
mbed_official	256:76fd9a263045	1971	SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
mbed_official	256:76fd9a263045	1972	SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
mbed_official	256:76fd9a263045	1973	SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
bogdanm	20:4263a77256ae	1974	} LPC_SPI_CLOCK_MODE_T;
bogdanm	20:4263a77256ae	1975
bogdanm	20:4263a77256ae	1976	/* SPI Data Order Mode*/
bogdanm	20:4263a77256ae	1977	typedef enum LPC_SPI_DATA_ORDER {
mbed_official	256:76fd9a263045	1978	SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
mbed_official	256:76fd9a263045	1979	SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
bogdanm	20:4263a77256ae	1980	} LPC_SPI_DATA_ORDER_T;
bogdanm	20:4263a77256ae	1981
mbed_official	256:76fd9a263045	1982	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	1983	* Serial GPIO register block structure
bogdanm	20:4263a77256ae	1984	*/
bogdanm	20:4263a77256ae	1985	#define LPC_SGPIO_BASE 0x40101000
bogdanm	20:4263a77256ae	1986
mbed_official	256:76fd9a263045	1987	typedef struct { /* SGPIO Structure */
mbed_official	256:76fd9a263045	1988	__IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
mbed_official	256:76fd9a263045	1989	__IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
mbed_official	256:76fd9a263045	1990	__IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
mbed_official	256:76fd9a263045	1991	__IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
mbed_official	256:76fd9a263045	1992	__IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
mbed_official	256:76fd9a263045	1993	__IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
mbed_official	256:76fd9a263045	1994	__IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
mbed_official	256:76fd9a263045	1995	__IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
mbed_official	256:76fd9a263045	1996	__IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
mbed_official	256:76fd9a263045	1997	__IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
mbed_official	256:76fd9a263045	1998	__IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
mbed_official	256:76fd9a263045	1999	__IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
mbed_official	256:76fd9a263045	2000	__I uint32_t GPIO_INREG; /* GPIO input status register */
mbed_official	256:76fd9a263045	2001	__IO uint32_t GPIO_OUTREG; /* GPIO output control register */
mbed_official	256:76fd9a263045	2002	__IO uint32_t GPIO_OENREG; /* GPIO OE control register */
mbed_official	256:76fd9a263045	2003	__IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
mbed_official	256:76fd9a263045	2004	__IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
mbed_official	256:76fd9a263045	2005	__I uint32_t RESERVED0[823];
mbed_official	256:76fd9a263045	2006	__O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
mbed_official	256:76fd9a263045	2007	__O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
mbed_official	256:76fd9a263045	2008	__I uint32_t ENABLE_0; /* Shift clock interrupt enable */
mbed_official	256:76fd9a263045	2009	__I uint32_t STATUS_0; /* Shift clock interrupt status */
mbed_official	256:76fd9a263045	2010	__O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
mbed_official	256:76fd9a263045	2011	__O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
mbed_official	256:76fd9a263045	2012	__I uint32_t RESERVED1[2];
mbed_official	256:76fd9a263045	2013	__O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
mbed_official	256:76fd9a263045	2014	__O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
mbed_official	256:76fd9a263045	2015	__I uint32_t ENABLE_1; /* Capture clock interrupt enable */
mbed_official	256:76fd9a263045	2016	__I uint32_t STATUS_1; /* Capture clock interrupt status */
mbed_official	256:76fd9a263045	2017	__O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
mbed_official	256:76fd9a263045	2018	__O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
mbed_official	256:76fd9a263045	2019	__I uint32_t RESERVED2[2];
mbed_official	256:76fd9a263045	2020	__O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
mbed_official	256:76fd9a263045	2021	__O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
mbed_official	256:76fd9a263045	2022	__I uint32_t ENABLE_2; /* Pattern match interrupt enable */
mbed_official	256:76fd9a263045	2023	__I uint32_t STATUS_2; /* Pattern match interrupt status */
mbed_official	256:76fd9a263045	2024	__O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
mbed_official	256:76fd9a263045	2025	__O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
mbed_official	256:76fd9a263045	2026	__I uint32_t RESERVED3[2];
mbed_official	256:76fd9a263045	2027	__O uint32_t CLR_EN_3; /* Input interrupt clear mask */
mbed_official	256:76fd9a263045	2028	__O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
mbed_official	256:76fd9a263045	2029	__I uint32_t ENABLE_3; /* Input bit match interrupt enable */
mbed_official	256:76fd9a263045	2030	__I uint32_t STATUS_3; /* Input bit match interrupt status */
mbed_official	256:76fd9a263045	2031	__O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
mbed_official	256:76fd9a263045	2032	__O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
bogdanm	20:4263a77256ae	2033	} LPC_SGPIO_T;
bogdanm	20:4263a77256ae	2034
bogdanm	20:4263a77256ae	2035	/* End of section using anonymous unions */
bogdanm	20:4263a77256ae	2036	#if defined(__ARMCC_VERSION)
bogdanm	20:4263a77256ae	2037	#pragma pop
bogdanm	20:4263a77256ae	2038	#elif defined(__CWCC__)
bogdanm	20:4263a77256ae	2039	#pragma pop
bogdanm	20:4263a77256ae	2040	#elif defined(__IAR_SYSTEMS_ICC__)
bogdanm	20:4263a77256ae	2041	//#pragma pop // FIXME not usable for IAR
bogdanm	20:4263a77256ae	2042	#else /* defined(__GNUC__) and others */
bogdanm	20:4263a77256ae	2043	/* Leave anonymous unions enabled */
bogdanm	20:4263a77256ae	2044	#endif
bogdanm	20:4263a77256ae	2045
mbed_official	256:76fd9a263045	2046	/* ---------------------------------------------------------------------------
mbed_official	256:76fd9a263045	2047	* LPC43xx Peripheral register set declarations
bogdanm	20:4263a77256ae	2048	*/
mbed_official	256:76fd9a263045	2049	#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
mbed_official	256:76fd9a263045	2050	#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
mbed_official	256:76fd9a263045	2051	#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
mbed_official	256:76fd9a263045	2052	#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
mbed_official	256:76fd9a263045	2053	#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
mbed_official	256:76fd9a263045	2054	#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
mbed_official	256:76fd9a263045	2055	#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
mbed_official	256:76fd9a263045	2056	#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
mbed_official	256:76fd9a263045	2057	#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
mbed_official	256:76fd9a263045	2058	#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
mbed_official	256:76fd9a263045	2059	#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
mbed_official	256:76fd9a263045	2060	#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
mbed_official	256:76fd9a263045	2061	#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
mbed_official	256:76fd9a263045	2062	#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
mbed_official	256:76fd9a263045	2063	#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
mbed_official	256:76fd9a263045	2064	#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
mbed_official	256:76fd9a263045	2065	#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
mbed_official	256:76fd9a263045	2066	#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
mbed_official	256:76fd9a263045	2067	#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
mbed_official	256:76fd9a263045	2068	#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
mbed_official	256:76fd9a263045	2069	#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
mbed_official	256:76fd9a263045	2070	#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
mbed_official	256:76fd9a263045	2071	#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
mbed_official	256:76fd9a263045	2072	#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
mbed_official	256:76fd9a263045	2073	#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
mbed_official	256:76fd9a263045	2074	#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
mbed_official	256:76fd9a263045	2075	#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
mbed_official	256:76fd9a263045	2076	#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
mbed_official	256:76fd9a263045	2077	#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
mbed_official	256:76fd9a263045	2078	#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
mbed_official	256:76fd9a263045	2079	#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
mbed_official	256:76fd9a263045	2080	#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
mbed_official	256:76fd9a263045	2081	#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
mbed_official	256:76fd9a263045	2082	#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
mbed_official	256:76fd9a263045	2083	#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
mbed_official	256:76fd9a263045	2084	#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
mbed_official	256:76fd9a263045	2085	#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
mbed_official	256:76fd9a263045	2086	#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
mbed_official	256:76fd9a263045	2087	#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
mbed_official	256:76fd9a263045	2088	#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
mbed_official	256:76fd9a263045	2089	#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
mbed_official	256:76fd9a263045	2090	#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
mbed_official	256:76fd9a263045	2091	#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
mbed_official	256:76fd9a263045	2092	#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
mbed_official	256:76fd9a263045	2093	#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
mbed_official	256:76fd9a263045	2094	#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
mbed_official	256:76fd9a263045	2095	#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
mbed_official	256:76fd9a263045	2096	#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
mbed_official	256:76fd9a263045	2097	#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
mbed_official	256:76fd9a263045	2098	#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
mbed_official	256:76fd9a263045	2099	#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
mbed_official	256:76fd9a263045	2100	#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
mbed_official	256:76fd9a263045	2101	#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
mbed_official	256:76fd9a263045	2102	#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
mbed_official	256:76fd9a263045	2103	#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
mbed_official	256:76fd9a263045	2104	#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
mbed_official	256:76fd9a263045	2105	#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
mbed_official	256:76fd9a263045	2106	#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
mbed_official	256:76fd9a263045	2107	#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
bogdanm	20:4263a77256ae	2108
bogdanm	20:4263a77256ae	2109	#ifdef __cplusplus
bogdanm	20:4263a77256ae	2110	}
bogdanm	20:4263a77256ae	2111	#endif
bogdanm	20:4263a77256ae	2112
bogdanm	20:4263a77256ae	2113	#endif /* __LPC43XX_H */

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Type:	Library
Created:	09 Sep 2015
Imports:	0
Forks:	0
Commits:	618
Dependents:	1
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h@617:d1b257119699, 2015-08-24 (annotated)

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