Minsu Lee / mbed-src

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Dependents:   WizFi250_AP_HelloWorld

Fork of mbed-src by DongEun Koak

vendor/Freescale/KL25Z/hal/rtc_api.c@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include "rtc_api.h"
emilmont 10:3bc89ef62ce7 17
emilmont 10:3bc89ef62ce7 18 #if DEVICE_RTC
emilmont 10:3bc89ef62ce7 19
emilmont 10:3bc89ef62ce7 20 static void init(void) {
emilmont 10:3bc89ef62ce7 21 // enable PORTC clock
emilmont 10:3bc89ef62ce7 22 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
emilmont 10:3bc89ef62ce7 23
emilmont 10:3bc89ef62ce7 24 // enable RTC clock
emilmont 10:3bc89ef62ce7 25 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
emilmont 10:3bc89ef62ce7 26
emilmont 10:3bc89ef62ce7 27 /*
emilmont 10:3bc89ef62ce7 28 * configure PTC1 with alternate function 1: RTC_CLKIN
emilmont 10:3bc89ef62ce7 29 * As the kl25z board does not have a 32kHz osc,
emilmont 10:3bc89ef62ce7 30 * we use an external clock generated by the
emilmont 10:3bc89ef62ce7 31 * interface chip
emilmont 10:3bc89ef62ce7 32 */
emilmont 10:3bc89ef62ce7 33 PORTC->PCR[1] &= ~PORT_PCR_MUX_MASK;
emilmont 10:3bc89ef62ce7 34 PORTC->PCR[1] = PORT_PCR_MUX(1);
emilmont 10:3bc89ef62ce7 35
emilmont 10:3bc89ef62ce7 36 // select RTC_CLKIN as RTC clock source
emilmont 10:3bc89ef62ce7 37 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
emilmont 10:3bc89ef62ce7 38 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(2);
emilmont 10:3bc89ef62ce7 39 }
emilmont 10:3bc89ef62ce7 40
emilmont 10:3bc89ef62ce7 41 void rtc_init(void) {
emilmont 10:3bc89ef62ce7 42 init();
emilmont 10:3bc89ef62ce7 43
emilmont 10:3bc89ef62ce7 44 //Configure the TSR. default value: 1
emilmont 10:3bc89ef62ce7 45 RTC->TSR = 1;
emilmont 10:3bc89ef62ce7 46
emilmont 10:3bc89ef62ce7 47 // enable counter
emilmont 10:3bc89ef62ce7 48 RTC->SR |= RTC_SR_TCE_MASK;
emilmont 10:3bc89ef62ce7 49 }
emilmont 10:3bc89ef62ce7 50
emilmont 10:3bc89ef62ce7 51 void rtc_free(void) {
emilmont 10:3bc89ef62ce7 52 // [TODO]
emilmont 10:3bc89ef62ce7 53 }
emilmont 10:3bc89ef62ce7 54
emilmont 10:3bc89ef62ce7 55 /*
emilmont 10:3bc89ef62ce7 56 * Little check routine to see if the RTC has been enabled
emilmont 10:3bc89ef62ce7 57 * 0 = Disabled, 1 = Enabled
emilmont 10:3bc89ef62ce7 58 */
emilmont 10:3bc89ef62ce7 59 int rtc_isenabled(void) {
emilmont 10:3bc89ef62ce7 60 // even if the RTC module is enabled,
emilmont 10:3bc89ef62ce7 61 // as we use RTC_CLKIN and an external clock,
emilmont 10:3bc89ef62ce7 62 // we need to reconfigure the pins. That is why we
emilmont 10:3bc89ef62ce7 63 // call init() if the rtc is enabled
emilmont 10:3bc89ef62ce7 64
emilmont 10:3bc89ef62ce7 65 // if RTC not enabled return 0
emilmont 10:3bc89ef62ce7 66 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
emilmont 10:3bc89ef62ce7 67 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
emilmont 10:3bc89ef62ce7 68 if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
emilmont 10:3bc89ef62ce7 69 return 0;
emilmont 10:3bc89ef62ce7 70
emilmont 10:3bc89ef62ce7 71 init();
emilmont 10:3bc89ef62ce7 72 return 1;
emilmont 10:3bc89ef62ce7 73 }
emilmont 10:3bc89ef62ce7 74
emilmont 10:3bc89ef62ce7 75 time_t rtc_read(void) {
emilmont 10:3bc89ef62ce7 76 return RTC->TSR;
emilmont 10:3bc89ef62ce7 77 }
emilmont 10:3bc89ef62ce7 78
emilmont 10:3bc89ef62ce7 79 void rtc_write(time_t t) {
emilmont 10:3bc89ef62ce7 80 // disable counter
emilmont 10:3bc89ef62ce7 81 RTC->SR &= ~RTC_SR_TCE_MASK;
emilmont 10:3bc89ef62ce7 82
emilmont 10:3bc89ef62ce7 83 // we do not write 0 into TSR
emilmont 10:3bc89ef62ce7 84 // to avoid invalid time
emilmont 10:3bc89ef62ce7 85 if (t == 0)
emilmont 10:3bc89ef62ce7 86 t = 1;
emilmont 10:3bc89ef62ce7 87
emilmont 10:3bc89ef62ce7 88 // write seconds
emilmont 10:3bc89ef62ce7 89 RTC->TSR = t;
emilmont 10:3bc89ef62ce7 90
emilmont 10:3bc89ef62ce7 91 // re-enable counter
emilmont 10:3bc89ef62ce7 92 RTC->SR |= RTC_SR_TCE_MASK;
emilmont 10:3bc89ef62ce7 93 }
emilmont 10:3bc89ef62ce7 94
emilmont 10:3bc89ef62ce7 95 #endif