Minato Shoji / PowerControl

PowerControl

Dependents:   mbed_2019_rx3

EthernetPowerControl.cpp@0:8599d485662f, 2012-03-28 (annotated)

Committer:
JST2011
Date:
Wed Mar 28 10:49:14 2012 +0000
Revision:
0:8599d485662f
change \"LPC1768/LPC17xx.h\" to  \"LPC1768/ARM/LPC17xx.h\"

Who changed what in which revision?

UserRevisionLine numberNew contents of line
JST2011 0:8599d485662f 1 #include "EthernetPowerControl.h"
JST2011 0:8599d485662f 2
JST2011 0:8599d485662f 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
JST2011 0:8599d485662f 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
JST2011 0:8599d485662f 5 unsigned int tout;
JST2011 0:8599d485662f 6 /* Hardware MII Management for LPC176x devices. */
JST2011 0:8599d485662f 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
JST2011 0:8599d485662f 8 LPC_EMAC->MWTD = Value;
JST2011 0:8599d485662f 9
JST2011 0:8599d485662f 10 /* Wait utill operation completed */
JST2011 0:8599d485662f 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
JST2011 0:8599d485662f 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
JST2011 0:8599d485662f 13 break;
JST2011 0:8599d485662f 14 }
JST2011 0:8599d485662f 15 }
JST2011 0:8599d485662f 16 }
JST2011 0:8599d485662f 17
JST2011 0:8599d485662f 18 static unsigned short read_PHY (unsigned int PhyReg) {
JST2011 0:8599d485662f 19 /* Read a PHY register 'PhyReg'. */
JST2011 0:8599d485662f 20 unsigned int tout, val;
JST2011 0:8599d485662f 21
JST2011 0:8599d485662f 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
JST2011 0:8599d485662f 23 LPC_EMAC->MCMD = MCMD_READ;
JST2011 0:8599d485662f 24
JST2011 0:8599d485662f 25 /* Wait until operation completed */
JST2011 0:8599d485662f 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
JST2011 0:8599d485662f 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
JST2011 0:8599d485662f 28 break;
JST2011 0:8599d485662f 29 }
JST2011 0:8599d485662f 30 }
JST2011 0:8599d485662f 31 LPC_EMAC->MCMD = 0;
JST2011 0:8599d485662f 32 val = LPC_EMAC->MRDD;
JST2011 0:8599d485662f 33
JST2011 0:8599d485662f 34 return (val);
JST2011 0:8599d485662f 35 }
JST2011 0:8599d485662f 36
JST2011 0:8599d485662f 37 void EMAC_Init()
JST2011 0:8599d485662f 38 {
JST2011 0:8599d485662f 39 unsigned int tout,regv;
JST2011 0:8599d485662f 40 /* Power Up the EMAC controller. */
JST2011 0:8599d485662f 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
JST2011 0:8599d485662f 42
JST2011 0:8599d485662f 43 LPC_PINCON->PINSEL2 = 0x50150105;
JST2011 0:8599d485662f 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
JST2011 0:8599d485662f 45 LPC_PINCON->PINSEL3 |= 0x00000005;
JST2011 0:8599d485662f 46
JST2011 0:8599d485662f 47 /* Reset all EMAC internal modules. */
JST2011 0:8599d485662f 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
JST2011 0:8599d485662f 49 MAC1_SIM_RES | MAC1_SOFT_RES;
JST2011 0:8599d485662f 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
JST2011 0:8599d485662f 51
JST2011 0:8599d485662f 52 /* A short delay after reset. */
JST2011 0:8599d485662f 53 for (tout = 100; tout; tout--);
JST2011 0:8599d485662f 54
JST2011 0:8599d485662f 55 /* Initialize MAC control registers. */
JST2011 0:8599d485662f 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
JST2011 0:8599d485662f 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
JST2011 0:8599d485662f 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
JST2011 0:8599d485662f 59 LPC_EMAC->CLRT = CLRT_DEF;
JST2011 0:8599d485662f 60 LPC_EMAC->IPGR = IPGR_DEF;
JST2011 0:8599d485662f 61
JST2011 0:8599d485662f 62 /* Enable Reduced MII interface. */
JST2011 0:8599d485662f 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
JST2011 0:8599d485662f 64
JST2011 0:8599d485662f 65 /* Reset Reduced MII Logic. */
JST2011 0:8599d485662f 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
JST2011 0:8599d485662f 67 for (tout = 100; tout; tout--);
JST2011 0:8599d485662f 68 LPC_EMAC->SUPP = 0;
JST2011 0:8599d485662f 69
JST2011 0:8599d485662f 70 /* Put the DP83848C in reset mode */
JST2011 0:8599d485662f 71 write_PHY (PHY_REG_BMCR, 0x8000);
JST2011 0:8599d485662f 72
JST2011 0:8599d485662f 73 /* Wait for hardware reset to end. */
JST2011 0:8599d485662f 74 for (tout = 0; tout < 0x100000; tout++) {
JST2011 0:8599d485662f 75 regv = read_PHY (PHY_REG_BMCR);
JST2011 0:8599d485662f 76 if (!(regv & 0x8000)) {
JST2011 0:8599d485662f 77 /* Reset complete */
JST2011 0:8599d485662f 78 break;
JST2011 0:8599d485662f 79 }
JST2011 0:8599d485662f 80 }
JST2011 0:8599d485662f 81 }
JST2011 0:8599d485662f 82
JST2011 0:8599d485662f 83
JST2011 0:8599d485662f 84 void PHY_PowerDown()
JST2011 0:8599d485662f 85 {
JST2011 0:8599d485662f 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
JST2011 0:8599d485662f 87 EMAC_Init(); //init EMAC if it is not already init'd
JST2011 0:8599d485662f 88
JST2011 0:8599d485662f 89 unsigned int regv;
JST2011 0:8599d485662f 90 regv = read_PHY(PHY_REG_BMCR);
JST2011 0:8599d485662f 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
JST2011 0:8599d485662f 92 regv = read_PHY(PHY_REG_BMCR);
JST2011 0:8599d485662f 93
JST2011 0:8599d485662f 94 //shouldn't need the EMAC now.
JST2011 0:8599d485662f 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
JST2011 0:8599d485662f 96
JST2011 0:8599d485662f 97 //and turn off the PHY OSC
JST2011 0:8599d485662f 98 LPC_GPIO1->FIODIR |= 0x8000000;
JST2011 0:8599d485662f 99 LPC_GPIO1->FIOCLR = 0x8000000;
JST2011 0:8599d485662f 100 }
JST2011 0:8599d485662f 101
JST2011 0:8599d485662f 102 void PHY_PowerUp()
JST2011 0:8599d485662f 103 {
JST2011 0:8599d485662f 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
JST2011 0:8599d485662f 105 EMAC_Init(); //init EMAC if it is not already init'd
JST2011 0:8599d485662f 106
JST2011 0:8599d485662f 107 LPC_GPIO1->FIODIR |= 0x8000000;
JST2011 0:8599d485662f 108 LPC_GPIO1->FIOSET = 0x8000000;
JST2011 0:8599d485662f 109
JST2011 0:8599d485662f 110 //wait for osc to be stable
JST2011 0:8599d485662f 111 wait_ms(200);
JST2011 0:8599d485662f 112
JST2011 0:8599d485662f 113 unsigned int regv;
JST2011 0:8599d485662f 114 regv = read_PHY(PHY_REG_BMCR);
JST2011 0:8599d485662f 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
JST2011 0:8599d485662f 116 regv = read_PHY(PHY_REG_BMCR);
JST2011 0:8599d485662f 117 }
JST2011 0:8599d485662f 118
JST2011 0:8599d485662f 119 void PHY_EnergyDetect_Enable()
JST2011 0:8599d485662f 120 {
JST2011 0:8599d485662f 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
JST2011 0:8599d485662f 122 EMAC_Init(); //init EMAC if it is not already init'd
JST2011 0:8599d485662f 123
JST2011 0:8599d485662f 124 unsigned int regv;
JST2011 0:8599d485662f 125 regv = read_PHY(PHY_REG_EDCR);
JST2011 0:8599d485662f 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
JST2011 0:8599d485662f 127 regv = read_PHY(PHY_REG_EDCR);
JST2011 0:8599d485662f 128 }
JST2011 0:8599d485662f 129
JST2011 0:8599d485662f 130 void PHY_EnergyDetect_Disable()
JST2011 0:8599d485662f 131 {
JST2011 0:8599d485662f 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
JST2011 0:8599d485662f 133 EMAC_Init(); //init EMAC if it is not already init'd
JST2011 0:8599d485662f 134 unsigned int regv;
JST2011 0:8599d485662f 135 regv = read_PHY(PHY_REG_EDCR);
JST2011 0:8599d485662f 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
JST2011 0:8599d485662f 137 regv = read_PHY(PHY_REG_EDCR);
JST2011 0:8599d485662f 138 }