Diff: TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct

Revision:

92:4fc01daae5a5

Child:

93:e188a91d3eaa

diff -r 031413cf7a89 -r 4fc01daae5a5 TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct	Thu Nov 27 13:33:22 2014 +0000
@@ -0,0 +1,46 @@
+
+
+LOAD_TTB    0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+{
+    TTB     +0 EMPTY 0x4000            
+    { }                           ; Level-1 Translation Table for MMU
+}
+
+SFLASH 0x18000000 (0x08000000)
+{
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+    ; S-Flash ROM : Executable cached region
+    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+    BOOT_LOADER_BEGIN 0x18000000 FIXED
+    {
+        *   ( BOOT_LOADER )
+    }
+
+    VECTORS 0x18004000 FIXED
+    {
+        * (RESET, +FIRST)         ; Vector table and other (assembler) startup code
+        * (InRoot$$Sections)      ; All (library) code that must be in a root region
+        * (+RO-CODE)              ; Application RO code (.text)
+    }
+
+    RO_DATA          +0
+    { * (+RO-DATA) }              ; Application RO data (.constdata)
+
+    RW_DATA 0x20600000 0x00100000 ; Page 1 of On-Chip Large-Capacity RAM (0x20060000 to 0x206FFFFF)
+    { * (+RW) }                   ; Application RW data (.data)
+
+    ZI_DATA 0x20100000 0x00100000 ; Page 1 of On-Chip Large-Capacity RAM (0x20010000 to 0x201FFFFF)
+    { * (+ZI) }                   ; Application ZI data (.bss)
+
+    RW_DATA_NC 0x60900000 0x00100000
+    { * (NC_DATA) }              ; Application RW data Non cached area
+
+    ZI_DATA_NC +0
+    { * (NC_BSS) }               ; Application ZI data Non cached area
+    
+    ;HEAP    0x90000000 
+    ;{ * (HEAP) }
+}
+
+