Diff: TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h

Revision:

85:024bf7f99721

Parent:

81:7d30d6019079

Child:

90:cb3d968589d8

diff -r 0b3ab51c8877 -r 024bf7f99721 TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h
--- a/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h	Mon May 19 18:14:09 2014 +0100
+++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h	Wed Jun 11 15:14:05 2014 +0100
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f4xx_hal_nor.h
   * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    18-February-2014
+  * @version V1.1.0RC2
+  * @date    14-May-2014
   * @brief   Header file of NOR HAL module.
   ******************************************************************************
   * @attention
@@ -62,7 +62,7 @@
 
 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
 
-/* Exported typedef ----------------------------------------------------------*/ 
+/* Exported typedef ----------------------------------------------------------*/
 /** 
   * @brief  HAL SRAM State structures definition  
   */ 
@@ -71,10 +71,9 @@
   HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
   HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
   HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
-  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */ 
-  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected  */
-
-}HAL_NOR_StateTypeDef;    
+  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
+  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
+}HAL_NOR_StateTypeDef;
 
 /**
   * @brief  FMC NOR Status typedef
@@ -85,8 +84,7 @@
   NOR_ONGOING,
   NOR_ERROR,
   NOR_TIMEOUT
-
-}NOR_StatusTypedef; 
+}NOR_StatusTypedef;
 
 /**
   * @brief  FMC NOR ID typedef
@@ -94,19 +92,17 @@
 typedef struct
 {
   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
-  
-  uint16_t Device_Code1;  
-  
-  uint16_t Device_Code2;                      
-        
-  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory. 
+
+  uint16_t Device_Code1;
+
+  uint16_t Device_Code2;
+
+  uint16_t Device_Code3;       /*!< Defines the devices' codes used to identify the memory. 
                                     These codes can be accessed by performing read operations with specific 
                                     control signals and addresses set.They can also be accessed by issuing 
-                                    an Auto Select command                                                   */    
-  
+                                    an Auto Select command                                                   */
 }NOR_IDTypeDef;
 
-
 /**
   * @brief  FMC NOR CFI typedef
   */
@@ -115,32 +111,31 @@
   /*!< Defines the information stored in the memory's Common flash interface
        which contains a description of various electrical and timing parameters, 
        density information and functions supported by the memory                   */
-  
-  uint16_t CFI_1;            
-  
-  uint16_t CFI_2;          
-  
-  uint16_t CFI_3;                      
-  
-  uint16_t CFI_4;                     
-  
+
+  uint16_t CFI_1;
+
+  uint16_t CFI_2;
+
+  uint16_t CFI_3;
+
+  uint16_t CFI_4;
 }NOR_CFITypeDef;
 
 /** 
-  * @brief  NOR handle Structure definition  
+  * @brief  NOR handle Structure definition
   */ 
 typedef struct
 {
-  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */ 
-  
+  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
+
   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
-  
+
   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
 
-  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */ 
-  
+  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
+
   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
-   
+
 }NOR_HandleTypeDef; 
 
 /* Exported constants --------------------------------------------------------*/
@@ -173,6 +168,13 @@
   */
 
 /* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset NOR handle state
+  * @param  __HANDLE__: specifies the NOR handle.
+  * @retval None
+  */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+
 /**
   * @brief  NOR memory address shifting.
   * @param  __ADDRESS__: NOR memory address 
@@ -194,14 +196,14 @@
 
 /* Exported functions --------------------------------------------------------*/
 
-/* Initialization/de-initialization functions  **********************************/  
+/* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
 
-/* I/O operation functions  *****************************************************/
+/* I/O operation functions  ***************************************************/
 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
@@ -214,11 +216,11 @@
 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
 
-/* NOR Control functions  *******************************************************/
+/* NOR Control functions  *****************************************************/
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
 
-/* NOR State functions **********************************************************/
+/* NOR State functions ********************************************************/
 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
 NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);