Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f401xe.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Parent:
85:024bf7f99721 
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f401xe.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V2.1.0
Kojto 90:cb3d968589d8 6 * @date 19-June-2014
emilmont 77:869cf507173a 7 * @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
emilmont 77:869cf507173a 8 *
emilmont 77:869cf507173a 9 * This file contains:
emilmont 77:869cf507173a 10 * - Data structures and the address mapping for all peripherals
emilmont 77:869cf507173a 11 * - Peripheral's registers declarations and bits definition
emilmont 77:869cf507173a 12 * - Macros to access peripheral’s registers hardware
emilmont 77:869cf507173a 13 *
emilmont 77:869cf507173a 14 ******************************************************************************
emilmont 77:869cf507173a 15 * @attention
emilmont 77:869cf507173a 16 *
emilmont 77:869cf507173a 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 18 *
emilmont 77:869cf507173a 19 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 20 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 21 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 22 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 24 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 25 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 27 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 28 * without specific prior written permission.
emilmont 77:869cf507173a 29 *
emilmont 77:869cf507173a 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 40 *
emilmont 77:869cf507173a 41 ******************************************************************************
emilmont 77:869cf507173a 42 */
emilmont 77:869cf507173a 43
emilmont 77:869cf507173a 44 /** @addtogroup CMSIS
emilmont 77:869cf507173a 45 * @{
emilmont 77:869cf507173a 46 */
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 /** @addtogroup stm32f401xe
emilmont 77:869cf507173a 49 * @{
emilmont 77:869cf507173a 50 */
emilmont 77:869cf507173a 51
emilmont 77:869cf507173a 52 #ifndef __STM32F401xE_H
emilmont 77:869cf507173a 53 #define __STM32F401xE_H
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55 #ifdef __cplusplus
emilmont 77:869cf507173a 56 extern "C" {
emilmont 77:869cf507173a 57 #endif /* __cplusplus */
emilmont 77:869cf507173a 58
emilmont 77:869cf507173a 59
emilmont 77:869cf507173a 60 /** @addtogroup Configuration_section_for_CMSIS
emilmont 77:869cf507173a 61 * @{
emilmont 77:869cf507173a 62 */
emilmont 77:869cf507173a 63
emilmont 77:869cf507173a 64 /**
emilmont 77:869cf507173a 65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
emilmont 77:869cf507173a 66 */
emilmont 77:869cf507173a 67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
emilmont 77:869cf507173a 68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
emilmont 77:869cf507173a 69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
emilmont 77:869cf507173a 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 77:869cf507173a 71 #define __FPU_PRESENT 1 /*!< FPU present */
emilmont 77:869cf507173a 72
emilmont 77:869cf507173a 73 /**
emilmont 77:869cf507173a 74 * @}
emilmont 77:869cf507173a 75 */
emilmont 77:869cf507173a 76
emilmont 77:869cf507173a 77 /** @addtogroup Peripheral_interrupt_number_definition
emilmont 77:869cf507173a 78 * @{
emilmont 77:869cf507173a 79 */
emilmont 77:869cf507173a 80
emilmont 77:869cf507173a 81 /**
emilmont 77:869cf507173a 82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
emilmont 77:869cf507173a 83 * in @ref Library_configuration_section
emilmont 77:869cf507173a 84 */
emilmont 77:869cf507173a 85 typedef enum
emilmont 77:869cf507173a 86 {
emilmont 77:869cf507173a 87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
emilmont 77:869cf507173a 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
emilmont 77:869cf507173a 89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
emilmont 77:869cf507173a 90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
emilmont 77:869cf507173a 91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
emilmont 77:869cf507173a 92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
emilmont 77:869cf507173a 93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
emilmont 77:869cf507173a 94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
emilmont 77:869cf507173a 95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
emilmont 77:869cf507173a 96 /****** STM32 specific Interrupt Numbers **********************************************************************/
emilmont 77:869cf507173a 97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
emilmont 77:869cf507173a 98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
emilmont 77:869cf507173a 99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
emilmont 77:869cf507173a 100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
emilmont 77:869cf507173a 101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
emilmont 77:869cf507173a 102 RCC_IRQn = 5, /*!< RCC global Interrupt */
emilmont 77:869cf507173a 103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
emilmont 77:869cf507173a 104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
emilmont 77:869cf507173a 105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
emilmont 77:869cf507173a 106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
emilmont 77:869cf507173a 107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
emilmont 77:869cf507173a 108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
emilmont 77:869cf507173a 109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
emilmont 77:869cf507173a 110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
emilmont 77:869cf507173a 111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
emilmont 77:869cf507173a 112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
emilmont 77:869cf507173a 113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
emilmont 77:869cf507173a 114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
emilmont 77:869cf507173a 115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
emilmont 77:869cf507173a 116 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
emilmont 77:869cf507173a 117 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
emilmont 77:869cf507173a 118 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
emilmont 77:869cf507173a 119 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
emilmont 77:869cf507173a 120 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
emilmont 77:869cf507173a 121 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
emilmont 77:869cf507173a 122 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
emilmont 77:869cf507173a 123 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
emilmont 77:869cf507173a 124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
emilmont 77:869cf507173a 125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
emilmont 77:869cf507173a 126 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
emilmont 77:869cf507173a 127 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
emilmont 77:869cf507173a 128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
emilmont 77:869cf507173a 129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
emilmont 77:869cf507173a 130 USART1_IRQn = 37, /*!< USART1 global Interrupt */
emilmont 77:869cf507173a 131 USART2_IRQn = 38, /*!< USART2 global Interrupt */
emilmont 77:869cf507173a 132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
emilmont 77:869cf507173a 133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
emilmont 77:869cf507173a 134 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
emilmont 77:869cf507173a 135 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
emilmont 77:869cf507173a 136 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
emilmont 77:869cf507173a 137 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
emilmont 77:869cf507173a 138 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
emilmont 77:869cf507173a 139 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
emilmont 77:869cf507173a 140 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
emilmont 77:869cf507173a 141 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
emilmont 77:869cf507173a 142 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
emilmont 77:869cf507173a 143 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
emilmont 77:869cf507173a 144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
emilmont 77:869cf507173a 145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
emilmont 77:869cf507173a 146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
emilmont 77:869cf507173a 147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
emilmont 77:869cf507173a 148 USART6_IRQn = 71, /*!< USART6 global interrupt */
emilmont 77:869cf507173a 149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
emilmont 77:869cf507173a 150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
emilmont 77:869cf507173a 151 FPU_IRQn = 81, /*!< FPU global interrupt */
emilmont 77:869cf507173a 152 SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
emilmont 77:869cf507173a 153 } IRQn_Type;
emilmont 77:869cf507173a 154
emilmont 77:869cf507173a 155 /**
emilmont 77:869cf507173a 156 * @}
emilmont 77:869cf507173a 157 */
emilmont 77:869cf507173a 158
emilmont 77:869cf507173a 159 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
emilmont 77:869cf507173a 160 #include "system_stm32f4xx.h"
emilmont 77:869cf507173a 161 #include <stdint.h>
emilmont 77:869cf507173a 162
emilmont 77:869cf507173a 163 /** @addtogroup Peripheral_registers_structures
emilmont 77:869cf507173a 164 * @{
emilmont 77:869cf507173a 165 */
emilmont 77:869cf507173a 166
emilmont 77:869cf507173a 167 /**
emilmont 77:869cf507173a 168 * @brief Analog to Digital Converter
emilmont 77:869cf507173a 169 */
emilmont 77:869cf507173a 170
emilmont 77:869cf507173a 171 typedef struct
emilmont 77:869cf507173a 172 {
emilmont 77:869cf507173a 173 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
emilmont 77:869cf507173a 174 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
emilmont 77:869cf507173a 175 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
emilmont 77:869cf507173a 176 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
emilmont 77:869cf507173a 177 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
emilmont 77:869cf507173a 178 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
emilmont 77:869cf507173a 179 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
emilmont 77:869cf507173a 180 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
emilmont 77:869cf507173a 181 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
emilmont 77:869cf507173a 182 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
emilmont 77:869cf507173a 183 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
emilmont 77:869cf507173a 184 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
emilmont 77:869cf507173a 185 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
emilmont 77:869cf507173a 186 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
emilmont 77:869cf507173a 187 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
emilmont 77:869cf507173a 188 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
emilmont 77:869cf507173a 189 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
emilmont 77:869cf507173a 190 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
emilmont 77:869cf507173a 191 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
emilmont 77:869cf507173a 192 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
emilmont 77:869cf507173a 193 } ADC_TypeDef;
emilmont 77:869cf507173a 194
emilmont 77:869cf507173a 195 typedef struct
emilmont 77:869cf507173a 196 {
emilmont 77:869cf507173a 197 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
emilmont 77:869cf507173a 198 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
emilmont 77:869cf507173a 199 __IO uint32_t CDR; /*!< ADC common regular data register for dual
emilmont 77:869cf507173a 200 AND triple modes, Address offset: ADC1 base address + 0x308 */
emilmont 77:869cf507173a 201 } ADC_Common_TypeDef;
emilmont 77:869cf507173a 202
emilmont 77:869cf507173a 203 /**
emilmont 77:869cf507173a 204 * @brief CRC calculation unit
emilmont 77:869cf507173a 205 */
emilmont 77:869cf507173a 206
emilmont 77:869cf507173a 207 typedef struct
emilmont 77:869cf507173a 208 {
emilmont 77:869cf507173a 209 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
emilmont 77:869cf507173a 210 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
emilmont 77:869cf507173a 211 uint8_t RESERVED0; /*!< Reserved, 0x05 */
emilmont 77:869cf507173a 212 uint16_t RESERVED1; /*!< Reserved, 0x06 */
emilmont 77:869cf507173a 213 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
emilmont 77:869cf507173a 214 } CRC_TypeDef;
emilmont 77:869cf507173a 215
emilmont 77:869cf507173a 216 /**
emilmont 77:869cf507173a 217 * @brief Debug MCU
emilmont 77:869cf507173a 218 */
emilmont 77:869cf507173a 219
emilmont 77:869cf507173a 220 typedef struct
emilmont 77:869cf507173a 221 {
emilmont 77:869cf507173a 222 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
emilmont 77:869cf507173a 223 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
emilmont 77:869cf507173a 224 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
emilmont 77:869cf507173a 225 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
emilmont 77:869cf507173a 226 }DBGMCU_TypeDef;
emilmont 77:869cf507173a 227
emilmont 77:869cf507173a 228
emilmont 77:869cf507173a 229 /**
emilmont 77:869cf507173a 230 * @brief DMA Controller
emilmont 77:869cf507173a 231 */
emilmont 77:869cf507173a 232
emilmont 77:869cf507173a 233 typedef struct
emilmont 77:869cf507173a 234 {
emilmont 77:869cf507173a 235 __IO uint32_t CR; /*!< DMA stream x configuration register */
emilmont 77:869cf507173a 236 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
emilmont 77:869cf507173a 237 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
emilmont 77:869cf507173a 238 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
emilmont 77:869cf507173a 239 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
emilmont 77:869cf507173a 240 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
emilmont 77:869cf507173a 241 } DMA_Stream_TypeDef;
emilmont 77:869cf507173a 242
emilmont 77:869cf507173a 243 typedef struct
emilmont 77:869cf507173a 244 {
emilmont 77:869cf507173a 245 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
emilmont 77:869cf507173a 246 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
emilmont 77:869cf507173a 247 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
emilmont 77:869cf507173a 248 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
emilmont 77:869cf507173a 249 } DMA_TypeDef;
emilmont 77:869cf507173a 250
emilmont 77:869cf507173a 251
emilmont 77:869cf507173a 252 /**
emilmont 77:869cf507173a 253 * @brief External Interrupt/Event Controller
emilmont 77:869cf507173a 254 */
emilmont 77:869cf507173a 255
emilmont 77:869cf507173a 256 typedef struct
emilmont 77:869cf507173a 257 {
emilmont 77:869cf507173a 258 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
emilmont 77:869cf507173a 259 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
emilmont 77:869cf507173a 260 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
emilmont 77:869cf507173a 261 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
emilmont 77:869cf507173a 262 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
emilmont 77:869cf507173a 263 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
emilmont 77:869cf507173a 264 } EXTI_TypeDef;
emilmont 77:869cf507173a 265
emilmont 77:869cf507173a 266 /**
emilmont 77:869cf507173a 267 * @brief FLASH Registers
emilmont 77:869cf507173a 268 */
emilmont 77:869cf507173a 269
emilmont 77:869cf507173a 270 typedef struct
emilmont 77:869cf507173a 271 {
emilmont 77:869cf507173a 272 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
emilmont 77:869cf507173a 273 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
emilmont 77:869cf507173a 274 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
emilmont 77:869cf507173a 275 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
emilmont 77:869cf507173a 276 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
emilmont 77:869cf507173a 277 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
emilmont 77:869cf507173a 278 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
emilmont 77:869cf507173a 279 } FLASH_TypeDef;
emilmont 77:869cf507173a 280
emilmont 77:869cf507173a 281 /**
emilmont 77:869cf507173a 282 * @brief General Purpose I/O
emilmont 77:869cf507173a 283 */
emilmont 77:869cf507173a 284
emilmont 77:869cf507173a 285 typedef struct
emilmont 77:869cf507173a 286 {
emilmont 77:869cf507173a 287 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
emilmont 77:869cf507173a 288 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
emilmont 77:869cf507173a 289 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
emilmont 77:869cf507173a 290 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
emilmont 77:869cf507173a 291 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
emilmont 77:869cf507173a 292 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
emilmont 77:869cf507173a 293 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
emilmont 77:869cf507173a 294 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
emilmont 77:869cf507173a 295 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
emilmont 77:869cf507173a 296 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
emilmont 77:869cf507173a 297 } GPIO_TypeDef;
emilmont 77:869cf507173a 298
emilmont 77:869cf507173a 299 /**
emilmont 77:869cf507173a 300 * @brief System configuration controller
emilmont 77:869cf507173a 301 */
emilmont 77:869cf507173a 302
emilmont 77:869cf507173a 303 typedef struct
emilmont 77:869cf507173a 304 {
emilmont 77:869cf507173a 305 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
emilmont 77:869cf507173a 306 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
emilmont 77:869cf507173a 307 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
emilmont 77:869cf507173a 308 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
emilmont 77:869cf507173a 309 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
emilmont 77:869cf507173a 310 } SYSCFG_TypeDef;
emilmont 77:869cf507173a 311
emilmont 77:869cf507173a 312 /**
emilmont 77:869cf507173a 313 * @brief Inter-integrated Circuit Interface
emilmont 77:869cf507173a 314 */
emilmont 77:869cf507173a 315
emilmont 77:869cf507173a 316 typedef struct
emilmont 77:869cf507173a 317 {
emilmont 77:869cf507173a 318 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
emilmont 77:869cf507173a 319 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
emilmont 77:869cf507173a 320 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
emilmont 77:869cf507173a 321 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
emilmont 77:869cf507173a 322 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
emilmont 77:869cf507173a 323 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
emilmont 77:869cf507173a 324 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
emilmont 77:869cf507173a 325 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
emilmont 77:869cf507173a 326 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
emilmont 77:869cf507173a 327 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
emilmont 77:869cf507173a 328 } I2C_TypeDef;
emilmont 77:869cf507173a 329
emilmont 77:869cf507173a 330 /**
emilmont 77:869cf507173a 331 * @brief Independent WATCHDOG
emilmont 77:869cf507173a 332 */
emilmont 77:869cf507173a 333
emilmont 77:869cf507173a 334 typedef struct
emilmont 77:869cf507173a 335 {
emilmont 77:869cf507173a 336 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
emilmont 77:869cf507173a 337 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
emilmont 77:869cf507173a 338 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
emilmont 77:869cf507173a 339 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
emilmont 77:869cf507173a 340 } IWDG_TypeDef;
emilmont 77:869cf507173a 341
emilmont 77:869cf507173a 342 /**
emilmont 77:869cf507173a 343 * @brief Power Control
emilmont 77:869cf507173a 344 */
emilmont 77:869cf507173a 345
emilmont 77:869cf507173a 346 typedef struct
emilmont 77:869cf507173a 347 {
emilmont 77:869cf507173a 348 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
emilmont 77:869cf507173a 349 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
emilmont 77:869cf507173a 350 } PWR_TypeDef;
emilmont 77:869cf507173a 351
emilmont 77:869cf507173a 352 /**
emilmont 77:869cf507173a 353 * @brief Reset and Clock Control
emilmont 77:869cf507173a 354 */
emilmont 77:869cf507173a 355
emilmont 77:869cf507173a 356 typedef struct
emilmont 77:869cf507173a 357 {
emilmont 77:869cf507173a 358 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
emilmont 77:869cf507173a 359 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
emilmont 77:869cf507173a 360 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
emilmont 77:869cf507173a 361 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
emilmont 77:869cf507173a 362 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
emilmont 77:869cf507173a 363 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
emilmont 77:869cf507173a 364 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
emilmont 77:869cf507173a 365 uint32_t RESERVED0; /*!< Reserved, 0x1C */
emilmont 77:869cf507173a 366 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
emilmont 77:869cf507173a 367 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
emilmont 77:869cf507173a 368 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
emilmont 77:869cf507173a 369 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
emilmont 77:869cf507173a 370 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
emilmont 77:869cf507173a 371 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
emilmont 77:869cf507173a 372 uint32_t RESERVED2; /*!< Reserved, 0x3C */
emilmont 77:869cf507173a 373 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
emilmont 77:869cf507173a 374 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
emilmont 77:869cf507173a 375 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
emilmont 77:869cf507173a 376 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
emilmont 77:869cf507173a 377 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
emilmont 77:869cf507173a 378 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
emilmont 77:869cf507173a 379 uint32_t RESERVED4; /*!< Reserved, 0x5C */
emilmont 77:869cf507173a 380 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
emilmont 77:869cf507173a 381 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
emilmont 77:869cf507173a 382 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
emilmont 77:869cf507173a 383 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
emilmont 77:869cf507173a 384 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
emilmont 77:869cf507173a 385 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
emilmont 77:869cf507173a 386 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
emilmont 77:869cf507173a 387 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
emilmont 77:869cf507173a 388
emilmont 77:869cf507173a 389 } RCC_TypeDef;
emilmont 77:869cf507173a 390
emilmont 77:869cf507173a 391 /**
emilmont 77:869cf507173a 392 * @brief Real-Time Clock
emilmont 77:869cf507173a 393 */
emilmont 77:869cf507173a 394
emilmont 77:869cf507173a 395 typedef struct
emilmont 77:869cf507173a 396 {
emilmont 77:869cf507173a 397 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
emilmont 77:869cf507173a 398 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
emilmont 77:869cf507173a 399 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
emilmont 77:869cf507173a 400 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
emilmont 77:869cf507173a 401 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
emilmont 77:869cf507173a 402 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
emilmont 77:869cf507173a 403 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
emilmont 77:869cf507173a 404 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
emilmont 77:869cf507173a 405 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
emilmont 77:869cf507173a 406 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
emilmont 77:869cf507173a 407 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
emilmont 77:869cf507173a 408 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
emilmont 77:869cf507173a 409 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
emilmont 77:869cf507173a 410 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
emilmont 77:869cf507173a 411 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
emilmont 77:869cf507173a 412 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
emilmont 77:869cf507173a 413 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
emilmont 77:869cf507173a 414 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
emilmont 77:869cf507173a 415 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
emilmont 77:869cf507173a 416 uint32_t RESERVED7; /*!< Reserved, 0x4C */
emilmont 77:869cf507173a 417 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
emilmont 77:869cf507173a 418 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
emilmont 77:869cf507173a 419 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
emilmont 77:869cf507173a 420 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
emilmont 77:869cf507173a 421 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
emilmont 77:869cf507173a 422 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
emilmont 77:869cf507173a 423 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
emilmont 77:869cf507173a 424 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
emilmont 77:869cf507173a 425 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
emilmont 77:869cf507173a 426 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
emilmont 77:869cf507173a 427 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
emilmont 77:869cf507173a 428 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
emilmont 77:869cf507173a 429 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
emilmont 77:869cf507173a 430 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
emilmont 77:869cf507173a 431 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
emilmont 77:869cf507173a 432 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
emilmont 77:869cf507173a 433 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
emilmont 77:869cf507173a 434 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
emilmont 77:869cf507173a 435 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
emilmont 77:869cf507173a 436 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
emilmont 77:869cf507173a 437 } RTC_TypeDef;
emilmont 77:869cf507173a 438
emilmont 77:869cf507173a 439
emilmont 77:869cf507173a 440 /**
emilmont 77:869cf507173a 441 * @brief SD host Interface
emilmont 77:869cf507173a 442 */
emilmont 77:869cf507173a 443
emilmont 77:869cf507173a 444 typedef struct
emilmont 77:869cf507173a 445 {
emilmont 77:869cf507173a 446 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
emilmont 77:869cf507173a 447 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
emilmont 77:869cf507173a 448 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
emilmont 77:869cf507173a 449 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
emilmont 77:869cf507173a 450 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
emilmont 77:869cf507173a 451 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
emilmont 77:869cf507173a 452 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
emilmont 77:869cf507173a 453 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
emilmont 77:869cf507173a 454 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
emilmont 77:869cf507173a 455 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
emilmont 77:869cf507173a 456 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
emilmont 77:869cf507173a 457 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
emilmont 77:869cf507173a 458 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
emilmont 77:869cf507173a 459 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
emilmont 77:869cf507173a 460 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
emilmont 77:869cf507173a 461 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
emilmont 77:869cf507173a 462 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
emilmont 77:869cf507173a 463 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
emilmont 77:869cf507173a 464 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
emilmont 77:869cf507173a 465 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
emilmont 77:869cf507173a 466 } SDIO_TypeDef;
emilmont 77:869cf507173a 467
emilmont 77:869cf507173a 468 /**
emilmont 77:869cf507173a 469 * @brief Serial Peripheral Interface
emilmont 77:869cf507173a 470 */
emilmont 77:869cf507173a 471
emilmont 77:869cf507173a 472 typedef struct
emilmont 77:869cf507173a 473 {
emilmont 77:869cf507173a 474 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
emilmont 77:869cf507173a 475 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
emilmont 77:869cf507173a 476 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
emilmont 77:869cf507173a 477 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
emilmont 77:869cf507173a 478 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
emilmont 77:869cf507173a 479 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
emilmont 77:869cf507173a 480 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
emilmont 77:869cf507173a 481 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
emilmont 77:869cf507173a 482 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
emilmont 77:869cf507173a 483 } SPI_TypeDef;
emilmont 77:869cf507173a 484
emilmont 77:869cf507173a 485 /**
emilmont 77:869cf507173a 486 * @brief TIM
emilmont 77:869cf507173a 487 */
emilmont 77:869cf507173a 488
emilmont 77:869cf507173a 489 typedef struct
emilmont 77:869cf507173a 490 {
emilmont 77:869cf507173a 491 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
emilmont 77:869cf507173a 492 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
emilmont 77:869cf507173a 493 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
emilmont 77:869cf507173a 494 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
emilmont 77:869cf507173a 495 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
emilmont 77:869cf507173a 496 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
emilmont 77:869cf507173a 497 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
emilmont 77:869cf507173a 498 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
emilmont 77:869cf507173a 499 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
emilmont 77:869cf507173a 500 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
emilmont 77:869cf507173a 501 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
emilmont 77:869cf507173a 502 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
emilmont 77:869cf507173a 503 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
emilmont 77:869cf507173a 504 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
emilmont 77:869cf507173a 505 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
emilmont 77:869cf507173a 506 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
emilmont 77:869cf507173a 507 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
emilmont 77:869cf507173a 508 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
emilmont 77:869cf507173a 509 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
emilmont 77:869cf507173a 510 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
emilmont 77:869cf507173a 511 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
emilmont 77:869cf507173a 512 } TIM_TypeDef;
emilmont 77:869cf507173a 513
emilmont 77:869cf507173a 514 /**
emilmont 77:869cf507173a 515 * @brief Universal Synchronous Asynchronous Receiver Transmitter
emilmont 77:869cf507173a 516 */
emilmont 77:869cf507173a 517
emilmont 77:869cf507173a 518 typedef struct
emilmont 77:869cf507173a 519 {
emilmont 77:869cf507173a 520 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
emilmont 77:869cf507173a 521 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
emilmont 77:869cf507173a 522 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
emilmont 77:869cf507173a 523 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
emilmont 77:869cf507173a 524 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
emilmont 77:869cf507173a 525 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
emilmont 77:869cf507173a 526 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
emilmont 77:869cf507173a 527 } USART_TypeDef;
emilmont 77:869cf507173a 528
emilmont 77:869cf507173a 529 /**
emilmont 77:869cf507173a 530 * @brief Window WATCHDOG
emilmont 77:869cf507173a 531 */
emilmont 77:869cf507173a 532
emilmont 77:869cf507173a 533 typedef struct
emilmont 77:869cf507173a 534 {
emilmont 77:869cf507173a 535 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
emilmont 77:869cf507173a 536 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
emilmont 77:869cf507173a 537 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
emilmont 77:869cf507173a 538 } WWDG_TypeDef;
emilmont 77:869cf507173a 539
emilmont 77:869cf507173a 540 /**
emilmont 77:869cf507173a 541 * @brief __USB_OTG_Core_register
emilmont 77:869cf507173a 542 */
emilmont 77:869cf507173a 543 typedef struct
emilmont 77:869cf507173a 544 {
emilmont 77:869cf507173a 545 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
emilmont 77:869cf507173a 546 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
emilmont 77:869cf507173a 547 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
emilmont 77:869cf507173a 548 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
emilmont 77:869cf507173a 549 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
emilmont 77:869cf507173a 550 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
emilmont 77:869cf507173a 551 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
emilmont 77:869cf507173a 552 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
emilmont 77:869cf507173a 553 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
emilmont 77:869cf507173a 554 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
emilmont 77:869cf507173a 555 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
emilmont 77:869cf507173a 556 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
emilmont 77:869cf507173a 557 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
emilmont 77:869cf507173a 558 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
emilmont 77:869cf507173a 559 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
emilmont 77:869cf507173a 560 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
emilmont 77:869cf507173a 561 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
emilmont 77:869cf507173a 562 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
emilmont 77:869cf507173a 563 }
emilmont 77:869cf507173a 564 USB_OTG_GlobalTypeDef;
emilmont 77:869cf507173a 565
emilmont 77:869cf507173a 566
emilmont 77:869cf507173a 567
emilmont 77:869cf507173a 568 /**
emilmont 77:869cf507173a 569 * @brief __device_Registers
emilmont 77:869cf507173a 570 */
emilmont 77:869cf507173a 571 typedef struct
emilmont 77:869cf507173a 572 {
emilmont 77:869cf507173a 573 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
emilmont 77:869cf507173a 574 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
emilmont 77:869cf507173a 575 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
emilmont 77:869cf507173a 576 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
emilmont 77:869cf507173a 577 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
emilmont 77:869cf507173a 578 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
emilmont 77:869cf507173a 579 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
emilmont 77:869cf507173a 580 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
emilmont 77:869cf507173a 581 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
emilmont 77:869cf507173a 582 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
emilmont 77:869cf507173a 583 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
emilmont 77:869cf507173a 584 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
emilmont 77:869cf507173a 585 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
emilmont 77:869cf507173a 586 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
emilmont 77:869cf507173a 587 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
emilmont 77:869cf507173a 588 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
emilmont 77:869cf507173a 589 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
emilmont 77:869cf507173a 590 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
emilmont 77:869cf507173a 591 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
emilmont 77:869cf507173a 592 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
emilmont 77:869cf507173a 593 }
emilmont 77:869cf507173a 594 USB_OTG_DeviceTypeDef;
emilmont 77:869cf507173a 595
emilmont 77:869cf507173a 596
emilmont 77:869cf507173a 597 /**
emilmont 77:869cf507173a 598 * @brief __IN_Endpoint-Specific_Register
emilmont 77:869cf507173a 599 */
emilmont 77:869cf507173a 600 typedef struct
emilmont 77:869cf507173a 601 {
emilmont 77:869cf507173a 602 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
emilmont 77:869cf507173a 603 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
emilmont 77:869cf507173a 604 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
emilmont 77:869cf507173a 605 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
emilmont 77:869cf507173a 606 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
emilmont 77:869cf507173a 607 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
emilmont 77:869cf507173a 608 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
emilmont 77:869cf507173a 609 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
emilmont 77:869cf507173a 610 }
emilmont 77:869cf507173a 611 USB_OTG_INEndpointTypeDef;
emilmont 77:869cf507173a 612
emilmont 77:869cf507173a 613
emilmont 77:869cf507173a 614 /**
emilmont 77:869cf507173a 615 * @brief __OUT_Endpoint-Specific_Registers
emilmont 77:869cf507173a 616 */
emilmont 77:869cf507173a 617 typedef struct
emilmont 77:869cf507173a 618 {
emilmont 77:869cf507173a 619 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
emilmont 77:869cf507173a 620 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
emilmont 77:869cf507173a 621 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
emilmont 77:869cf507173a 622 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
emilmont 77:869cf507173a 623 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
emilmont 77:869cf507173a 624 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
emilmont 77:869cf507173a 625 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
emilmont 77:869cf507173a 626 }
emilmont 77:869cf507173a 627 USB_OTG_OUTEndpointTypeDef;
emilmont 77:869cf507173a 628
emilmont 77:869cf507173a 629
emilmont 77:869cf507173a 630 /**
emilmont 77:869cf507173a 631 * @brief __Host_Mode_Register_Structures
emilmont 77:869cf507173a 632 */
emilmont 77:869cf507173a 633 typedef struct
emilmont 77:869cf507173a 634 {
emilmont 77:869cf507173a 635 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
emilmont 77:869cf507173a 636 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
emilmont 77:869cf507173a 637 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
emilmont 77:869cf507173a 638 uint32_t Reserved40C; /* Reserved 40Ch*/
emilmont 77:869cf507173a 639 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
emilmont 77:869cf507173a 640 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
emilmont 77:869cf507173a 641 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
emilmont 77:869cf507173a 642 }
emilmont 77:869cf507173a 643 USB_OTG_HostTypeDef;
emilmont 77:869cf507173a 644
emilmont 77:869cf507173a 645
emilmont 77:869cf507173a 646 /**
emilmont 77:869cf507173a 647 * @brief __Host_Channel_Specific_Registers
emilmont 77:869cf507173a 648 */
emilmont 77:869cf507173a 649 typedef struct
emilmont 77:869cf507173a 650 {
emilmont 77:869cf507173a 651 __IO uint32_t HCCHAR;
emilmont 77:869cf507173a 652 __IO uint32_t HCSPLT;
emilmont 77:869cf507173a 653 __IO uint32_t HCINT;
emilmont 77:869cf507173a 654 __IO uint32_t HCINTMSK;
emilmont 77:869cf507173a 655 __IO uint32_t HCTSIZ;
emilmont 77:869cf507173a 656 __IO uint32_t HCDMA;
emilmont 77:869cf507173a 657 uint32_t Reserved[2];
emilmont 77:869cf507173a 658 }
emilmont 77:869cf507173a 659 USB_OTG_HostChannelTypeDef;
emilmont 77:869cf507173a 660
emilmont 77:869cf507173a 661
emilmont 77:869cf507173a 662 /**
emilmont 77:869cf507173a 663 * @brief Peripheral_memory_map
emilmont 77:869cf507173a 664 */
emilmont 77:869cf507173a 665 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
emilmont 77:869cf507173a 666 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
bogdanm 85:024bf7f99721 667 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
bogdanm 85:024bf7f99721 668 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
bogdanm 85:024bf7f99721 669 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
emilmont 77:869cf507173a 670 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
emilmont 77:869cf507173a 671 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
emilmont 77:869cf507173a 672 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
bogdanm 85:024bf7f99721 673 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
bogdanm 85:024bf7f99721 674 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
bogdanm 85:024bf7f99721 675 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
emilmont 77:869cf507173a 676 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
emilmont 77:869cf507173a 677 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
Kojto 90:cb3d968589d8 678 #define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
emilmont 77:869cf507173a 679
emilmont 77:869cf507173a 680 /* Legacy defines */
emilmont 77:869cf507173a 681 #define SRAM_BASE SRAM1_BASE
emilmont 77:869cf507173a 682 #define SRAM_BB_BASE SRAM1_BB_BASE
emilmont 77:869cf507173a 683
emilmont 77:869cf507173a 684
emilmont 77:869cf507173a 685 /*!< Peripheral memory map */
emilmont 77:869cf507173a 686 #define APB1PERIPH_BASE PERIPH_BASE
emilmont 77:869cf507173a 687 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
emilmont 77:869cf507173a 688 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
emilmont 77:869cf507173a 689 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
emilmont 77:869cf507173a 690
emilmont 77:869cf507173a 691 /*!< APB1 peripherals */
emilmont 77:869cf507173a 692 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
emilmont 77:869cf507173a 693 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
emilmont 77:869cf507173a 694 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
emilmont 77:869cf507173a 695 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
emilmont 77:869cf507173a 696 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
emilmont 77:869cf507173a 697 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
emilmont 77:869cf507173a 698 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
emilmont 77:869cf507173a 699 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
emilmont 77:869cf507173a 700 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
emilmont 77:869cf507173a 701 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
emilmont 77:869cf507173a 702 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
emilmont 77:869cf507173a 703 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
emilmont 77:869cf507173a 704 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
emilmont 77:869cf507173a 705 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
emilmont 77:869cf507173a 706 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
emilmont 77:869cf507173a 707 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
emilmont 77:869cf507173a 708
emilmont 77:869cf507173a 709 /*!< APB2 peripherals */
emilmont 77:869cf507173a 710 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
emilmont 77:869cf507173a 711 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
emilmont 77:869cf507173a 712 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
emilmont 77:869cf507173a 713 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
emilmont 77:869cf507173a 714 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
emilmont 77:869cf507173a 715 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
emilmont 77:869cf507173a 716 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
emilmont 77:869cf507173a 717 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
emilmont 77:869cf507173a 718 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
emilmont 77:869cf507173a 719 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
emilmont 77:869cf507173a 720 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
emilmont 77:869cf507173a 721 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
emilmont 77:869cf507173a 722 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
emilmont 77:869cf507173a 723
emilmont 77:869cf507173a 724 /*!< AHB1 peripherals */
emilmont 77:869cf507173a 725 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
emilmont 77:869cf507173a 726 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
emilmont 77:869cf507173a 727 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
emilmont 77:869cf507173a 728 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
emilmont 77:869cf507173a 729 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
emilmont 77:869cf507173a 730 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
emilmont 77:869cf507173a 731 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
emilmont 77:869cf507173a 732 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
emilmont 77:869cf507173a 733 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
emilmont 77:869cf507173a 734 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
emilmont 77:869cf507173a 735 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
emilmont 77:869cf507173a 736 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
emilmont 77:869cf507173a 737 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
emilmont 77:869cf507173a 738 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
emilmont 77:869cf507173a 739 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
emilmont 77:869cf507173a 740 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
emilmont 77:869cf507173a 741 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
emilmont 77:869cf507173a 742 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
emilmont 77:869cf507173a 743 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
emilmont 77:869cf507173a 744 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
emilmont 77:869cf507173a 745 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
emilmont 77:869cf507173a 746 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
emilmont 77:869cf507173a 747 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
emilmont 77:869cf507173a 748 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
emilmont 77:869cf507173a 749 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
emilmont 77:869cf507173a 750 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
emilmont 77:869cf507173a 751 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
emilmont 77:869cf507173a 752
emilmont 77:869cf507173a 753 /* Debug MCU registers base address */
emilmont 77:869cf507173a 754 #define DBGMCU_BASE ((uint32_t )0xE0042000)
emilmont 77:869cf507173a 755
emilmont 77:869cf507173a 756 /*!< USB registers base address */
emilmont 77:869cf507173a 757 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
emilmont 77:869cf507173a 758
emilmont 77:869cf507173a 759 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
emilmont 77:869cf507173a 760 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
emilmont 77:869cf507173a 761 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
emilmont 77:869cf507173a 762 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
emilmont 77:869cf507173a 763 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
emilmont 77:869cf507173a 764 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
emilmont 77:869cf507173a 765 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
emilmont 77:869cf507173a 766 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
emilmont 77:869cf507173a 767 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
emilmont 77:869cf507173a 768 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
emilmont 77:869cf507173a 769 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
emilmont 77:869cf507173a 770 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
emilmont 77:869cf507173a 771
emilmont 77:869cf507173a 772 /**
emilmont 77:869cf507173a 773 * @}
emilmont 77:869cf507173a 774 */
emilmont 77:869cf507173a 775
emilmont 77:869cf507173a 776 /** @addtogroup Peripheral_declaration
emilmont 77:869cf507173a 777 * @{
emilmont 77:869cf507173a 778 */
emilmont 77:869cf507173a 779 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
emilmont 77:869cf507173a 780 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
emilmont 77:869cf507173a 781 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
emilmont 77:869cf507173a 782 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
emilmont 77:869cf507173a 783 #define RTC ((RTC_TypeDef *) RTC_BASE)
emilmont 77:869cf507173a 784 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
emilmont 77:869cf507173a 785 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
emilmont 77:869cf507173a 786 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
emilmont 77:869cf507173a 787 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
emilmont 77:869cf507173a 788 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
emilmont 77:869cf507173a 789 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
emilmont 77:869cf507173a 790 #define USART2 ((USART_TypeDef *) USART2_BASE)
emilmont 77:869cf507173a 791 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
emilmont 77:869cf507173a 792 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
emilmont 77:869cf507173a 793 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
emilmont 77:869cf507173a 794 #define PWR ((PWR_TypeDef *) PWR_BASE)
emilmont 77:869cf507173a 795 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
emilmont 77:869cf507173a 796 #define USART1 ((USART_TypeDef *) USART1_BASE)
emilmont 77:869cf507173a 797 #define USART6 ((USART_TypeDef *) USART6_BASE)
emilmont 77:869cf507173a 798 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
emilmont 77:869cf507173a 799 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
emilmont 77:869cf507173a 800 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
emilmont 77:869cf507173a 801 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
emilmont 77:869cf507173a 802 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
emilmont 77:869cf507173a 803 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
emilmont 77:869cf507173a 804 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
emilmont 77:869cf507173a 805 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
emilmont 77:869cf507173a 806 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
emilmont 77:869cf507173a 807 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
emilmont 77:869cf507173a 808 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
emilmont 77:869cf507173a 809 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
emilmont 77:869cf507173a 810 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
emilmont 77:869cf507173a 811 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
emilmont 77:869cf507173a 812 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
emilmont 77:869cf507173a 813 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
emilmont 77:869cf507173a 814 #define CRC ((CRC_TypeDef *) CRC_BASE)
emilmont 77:869cf507173a 815 #define RCC ((RCC_TypeDef *) RCC_BASE)
emilmont 77:869cf507173a 816 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
emilmont 77:869cf507173a 817 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
emilmont 77:869cf507173a 818 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
emilmont 77:869cf507173a 819 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
emilmont 77:869cf507173a 820 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
emilmont 77:869cf507173a 821 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
emilmont 77:869cf507173a 822 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
emilmont 77:869cf507173a 823 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
emilmont 77:869cf507173a 824 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
emilmont 77:869cf507173a 825 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
emilmont 77:869cf507173a 826 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
emilmont 77:869cf507173a 827 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
emilmont 77:869cf507173a 828 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
emilmont 77:869cf507173a 829 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
emilmont 77:869cf507173a 830 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
emilmont 77:869cf507173a 831 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
emilmont 77:869cf507173a 832 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
emilmont 77:869cf507173a 833 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
bogdanm 85:024bf7f99721 834 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
emilmont 77:869cf507173a 835
emilmont 77:869cf507173a 836 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
emilmont 77:869cf507173a 837
emilmont 77:869cf507173a 838 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
emilmont 77:869cf507173a 839
emilmont 77:869cf507173a 840 /**
emilmont 77:869cf507173a 841 * @}
emilmont 77:869cf507173a 842 */
emilmont 77:869cf507173a 843
emilmont 77:869cf507173a 844 /** @addtogroup Exported_constants
emilmont 77:869cf507173a 845 * @{
emilmont 77:869cf507173a 846 */
emilmont 77:869cf507173a 847
emilmont 77:869cf507173a 848 /** @addtogroup Peripheral_Registers_Bits_Definition
emilmont 77:869cf507173a 849 * @{
emilmont 77:869cf507173a 850 */
emilmont 77:869cf507173a 851
emilmont 77:869cf507173a 852 /******************************************************************************/
emilmont 77:869cf507173a 853 /* Peripheral Registers_Bits_Definition */
emilmont 77:869cf507173a 854 /******************************************************************************/
emilmont 77:869cf507173a 855
emilmont 77:869cf507173a 856 /******************************************************************************/
emilmont 77:869cf507173a 857 /* */
emilmont 77:869cf507173a 858 /* Analog to Digital Converter */
emilmont 77:869cf507173a 859 /* */
emilmont 77:869cf507173a 860 /******************************************************************************/
emilmont 77:869cf507173a 861 /******************** Bit definition for ADC_SR register ********************/
emilmont 77:869cf507173a 862 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
emilmont 77:869cf507173a 863 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
emilmont 77:869cf507173a 864 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
emilmont 77:869cf507173a 865 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
emilmont 77:869cf507173a 866 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
emilmont 77:869cf507173a 867 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
emilmont 77:869cf507173a 868
emilmont 77:869cf507173a 869 /******************* Bit definition for ADC_CR1 register ********************/
emilmont 77:869cf507173a 870 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
emilmont 77:869cf507173a 871 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 872 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 873 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 874 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 875 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 876 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
emilmont 77:869cf507173a 877 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
emilmont 77:869cf507173a 878 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
emilmont 77:869cf507173a 879 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
emilmont 77:869cf507173a 880 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
emilmont 77:869cf507173a 881 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
emilmont 77:869cf507173a 882 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
emilmont 77:869cf507173a 883 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
emilmont 77:869cf507173a 884 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
emilmont 77:869cf507173a 885 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
emilmont 77:869cf507173a 886 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
emilmont 77:869cf507173a 887 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
emilmont 77:869cf507173a 888 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
emilmont 77:869cf507173a 889 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
emilmont 77:869cf507173a 890 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
emilmont 77:869cf507173a 891 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
emilmont 77:869cf507173a 892 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
emilmont 77:869cf507173a 893 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
emilmont 77:869cf507173a 894
emilmont 77:869cf507173a 895 /******************* Bit definition for ADC_CR2 register ********************/
emilmont 77:869cf507173a 896 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
emilmont 77:869cf507173a 897 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
emilmont 77:869cf507173a 898 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
emilmont 77:869cf507173a 899 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
emilmont 77:869cf507173a 900 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
emilmont 77:869cf507173a 901 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
emilmont 77:869cf507173a 902 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
emilmont 77:869cf507173a 903 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
emilmont 77:869cf507173a 904 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
emilmont 77:869cf507173a 905 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
emilmont 77:869cf507173a 906 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
emilmont 77:869cf507173a 907 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
emilmont 77:869cf507173a 908 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
emilmont 77:869cf507173a 909 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
emilmont 77:869cf507173a 910 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
emilmont 77:869cf507173a 911 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
emilmont 77:869cf507173a 912 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
emilmont 77:869cf507173a 913 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
emilmont 77:869cf507173a 914 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
emilmont 77:869cf507173a 915 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
emilmont 77:869cf507173a 916 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
emilmont 77:869cf507173a 917 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
emilmont 77:869cf507173a 918 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
emilmont 77:869cf507173a 919 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
emilmont 77:869cf507173a 920
emilmont 77:869cf507173a 921 /****************** Bit definition for ADC_SMPR1 register *******************/
emilmont 77:869cf507173a 922 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
emilmont 77:869cf507173a 923 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 924 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 925 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 926 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
emilmont 77:869cf507173a 927 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
emilmont 77:869cf507173a 928 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
emilmont 77:869cf507173a 929 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
emilmont 77:869cf507173a 930 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
emilmont 77:869cf507173a 931 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
emilmont 77:869cf507173a 932 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
emilmont 77:869cf507173a 933 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
emilmont 77:869cf507173a 934 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
emilmont 77:869cf507173a 935 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
emilmont 77:869cf507173a 936 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
emilmont 77:869cf507173a 937 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
emilmont 77:869cf507173a 938 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
emilmont 77:869cf507173a 939 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
emilmont 77:869cf507173a 940 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
emilmont 77:869cf507173a 941 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
emilmont 77:869cf507173a 942 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
emilmont 77:869cf507173a 943 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
emilmont 77:869cf507173a 944 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
emilmont 77:869cf507173a 945 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
emilmont 77:869cf507173a 946 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
emilmont 77:869cf507173a 947 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
emilmont 77:869cf507173a 948 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
emilmont 77:869cf507173a 949 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
emilmont 77:869cf507173a 950 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
emilmont 77:869cf507173a 951 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
emilmont 77:869cf507173a 952 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
emilmont 77:869cf507173a 953 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
emilmont 77:869cf507173a 954 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
emilmont 77:869cf507173a 955 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
emilmont 77:869cf507173a 956 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
emilmont 77:869cf507173a 957 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
emilmont 77:869cf507173a 958
emilmont 77:869cf507173a 959 /****************** Bit definition for ADC_SMPR2 register *******************/
emilmont 77:869cf507173a 960 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
emilmont 77:869cf507173a 961 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 962 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 963 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 964 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
emilmont 77:869cf507173a 965 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
emilmont 77:869cf507173a 966 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
emilmont 77:869cf507173a 967 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
emilmont 77:869cf507173a 968 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
emilmont 77:869cf507173a 969 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
emilmont 77:869cf507173a 970 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
emilmont 77:869cf507173a 971 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
emilmont 77:869cf507173a 972 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
emilmont 77:869cf507173a 973 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
emilmont 77:869cf507173a 974 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
emilmont 77:869cf507173a 975 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
emilmont 77:869cf507173a 976 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
emilmont 77:869cf507173a 977 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
emilmont 77:869cf507173a 978 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
emilmont 77:869cf507173a 979 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
emilmont 77:869cf507173a 980 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
emilmont 77:869cf507173a 981 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
emilmont 77:869cf507173a 982 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
emilmont 77:869cf507173a 983 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
emilmont 77:869cf507173a 984 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
emilmont 77:869cf507173a 985 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
emilmont 77:869cf507173a 986 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
emilmont 77:869cf507173a 987 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
emilmont 77:869cf507173a 988 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
emilmont 77:869cf507173a 989 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
emilmont 77:869cf507173a 990 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
emilmont 77:869cf507173a 991 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
emilmont 77:869cf507173a 992 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
emilmont 77:869cf507173a 993 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
emilmont 77:869cf507173a 994 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
emilmont 77:869cf507173a 995 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
emilmont 77:869cf507173a 996 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
emilmont 77:869cf507173a 997 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
emilmont 77:869cf507173a 998 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
emilmont 77:869cf507173a 999 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
emilmont 77:869cf507173a 1000
emilmont 77:869cf507173a 1001 /****************** Bit definition for ADC_JOFR1 register *******************/
emilmont 77:869cf507173a 1002 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
emilmont 77:869cf507173a 1003
emilmont 77:869cf507173a 1004 /****************** Bit definition for ADC_JOFR2 register *******************/
emilmont 77:869cf507173a 1005 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
emilmont 77:869cf507173a 1006
emilmont 77:869cf507173a 1007 /****************** Bit definition for ADC_JOFR3 register *******************/
emilmont 77:869cf507173a 1008 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
emilmont 77:869cf507173a 1009
emilmont 77:869cf507173a 1010 /****************** Bit definition for ADC_JOFR4 register *******************/
emilmont 77:869cf507173a 1011 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
emilmont 77:869cf507173a 1012
emilmont 77:869cf507173a 1013 /******************* Bit definition for ADC_HTR register ********************/
emilmont 77:869cf507173a 1014 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
emilmont 77:869cf507173a 1015
emilmont 77:869cf507173a 1016 /******************* Bit definition for ADC_LTR register ********************/
emilmont 77:869cf507173a 1017 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
emilmont 77:869cf507173a 1018
emilmont 77:869cf507173a 1019 /******************* Bit definition for ADC_SQR1 register *******************/
emilmont 77:869cf507173a 1020 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
emilmont 77:869cf507173a 1021 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 1022 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 1023 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 1024 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 1025 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 1026 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
emilmont 77:869cf507173a 1027 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
emilmont 77:869cf507173a 1028 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
emilmont 77:869cf507173a 1029 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
emilmont 77:869cf507173a 1030 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
emilmont 77:869cf507173a 1031 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
emilmont 77:869cf507173a 1032 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
emilmont 77:869cf507173a 1033 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
emilmont 77:869cf507173a 1034 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
emilmont 77:869cf507173a 1035 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
emilmont 77:869cf507173a 1036 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
emilmont 77:869cf507173a 1037 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
emilmont 77:869cf507173a 1038 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
emilmont 77:869cf507173a 1039 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
emilmont 77:869cf507173a 1040 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
emilmont 77:869cf507173a 1041 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
emilmont 77:869cf507173a 1042 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
emilmont 77:869cf507173a 1043 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
emilmont 77:869cf507173a 1044 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
emilmont 77:869cf507173a 1045 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
emilmont 77:869cf507173a 1046 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
emilmont 77:869cf507173a 1047 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
emilmont 77:869cf507173a 1048 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
emilmont 77:869cf507173a 1049
emilmont 77:869cf507173a 1050 /******************* Bit definition for ADC_SQR2 register *******************/
emilmont 77:869cf507173a 1051 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
emilmont 77:869cf507173a 1052 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 1053 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 1054 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 1055 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 1056 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 1057 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
emilmont 77:869cf507173a 1058 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
emilmont 77:869cf507173a 1059 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
emilmont 77:869cf507173a 1060 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
emilmont 77:869cf507173a 1061 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
emilmont 77:869cf507173a 1062 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
emilmont 77:869cf507173a 1063 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
emilmont 77:869cf507173a 1064 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
emilmont 77:869cf507173a 1065 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
emilmont 77:869cf507173a 1066 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
emilmont 77:869cf507173a 1067 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
emilmont 77:869cf507173a 1068 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
emilmont 77:869cf507173a 1069 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
emilmont 77:869cf507173a 1070 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
emilmont 77:869cf507173a 1071 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
emilmont 77:869cf507173a 1072 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
emilmont 77:869cf507173a 1073 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
emilmont 77:869cf507173a 1074 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
emilmont 77:869cf507173a 1075 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
emilmont 77:869cf507173a 1076 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
emilmont 77:869cf507173a 1077 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
emilmont 77:869cf507173a 1078 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
emilmont 77:869cf507173a 1079 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
emilmont 77:869cf507173a 1080 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
emilmont 77:869cf507173a 1081 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
emilmont 77:869cf507173a 1082 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
emilmont 77:869cf507173a 1083 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
emilmont 77:869cf507173a 1084 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
emilmont 77:869cf507173a 1085 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
emilmont 77:869cf507173a 1086 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
emilmont 77:869cf507173a 1087
emilmont 77:869cf507173a 1088 /******************* Bit definition for ADC_SQR3 register *******************/
emilmont 77:869cf507173a 1089 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
emilmont 77:869cf507173a 1090 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 1091 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 1092 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 1093 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 1094 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 1095 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
emilmont 77:869cf507173a 1096 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
emilmont 77:869cf507173a 1097 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
emilmont 77:869cf507173a 1098 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
emilmont 77:869cf507173a 1099 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
emilmont 77:869cf507173a 1100 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
emilmont 77:869cf507173a 1101 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
emilmont 77:869cf507173a 1102 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
emilmont 77:869cf507173a 1103 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
emilmont 77:869cf507173a 1104 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
emilmont 77:869cf507173a 1105 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
emilmont 77:869cf507173a 1106 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
emilmont 77:869cf507173a 1107 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
emilmont 77:869cf507173a 1108 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
emilmont 77:869cf507173a 1109 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
emilmont 77:869cf507173a 1110 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
emilmont 77:869cf507173a 1111 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
emilmont 77:869cf507173a 1112 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
emilmont 77:869cf507173a 1113 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
emilmont 77:869cf507173a 1114 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
emilmont 77:869cf507173a 1115 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
emilmont 77:869cf507173a 1116 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
emilmont 77:869cf507173a 1117 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
emilmont 77:869cf507173a 1118 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
emilmont 77:869cf507173a 1119 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
emilmont 77:869cf507173a 1120 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
emilmont 77:869cf507173a 1121 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
emilmont 77:869cf507173a 1122 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
emilmont 77:869cf507173a 1123 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
emilmont 77:869cf507173a 1124 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
emilmont 77:869cf507173a 1125
emilmont 77:869cf507173a 1126 /******************* Bit definition for ADC_JSQR register *******************/
emilmont 77:869cf507173a 1127 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
emilmont 77:869cf507173a 1128 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 1129 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 1130 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 1131 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 1132 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 1133 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
emilmont 77:869cf507173a 1134 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
emilmont 77:869cf507173a 1135 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
emilmont 77:869cf507173a 1136 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
emilmont 77:869cf507173a 1137 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
emilmont 77:869cf507173a 1138 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
emilmont 77:869cf507173a 1139 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
emilmont 77:869cf507173a 1140 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
emilmont 77:869cf507173a 1141 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
emilmont 77:869cf507173a 1142 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
emilmont 77:869cf507173a 1143 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
emilmont 77:869cf507173a 1144 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
emilmont 77:869cf507173a 1145 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
emilmont 77:869cf507173a 1146 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
emilmont 77:869cf507173a 1147 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
emilmont 77:869cf507173a 1148 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
emilmont 77:869cf507173a 1149 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
emilmont 77:869cf507173a 1150 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
emilmont 77:869cf507173a 1151 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
emilmont 77:869cf507173a 1152 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
emilmont 77:869cf507173a 1153 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
emilmont 77:869cf507173a 1154
emilmont 77:869cf507173a 1155 /******************* Bit definition for ADC_JDR1 register *******************/
emilmont 77:869cf507173a 1156 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
emilmont 77:869cf507173a 1157
emilmont 77:869cf507173a 1158 /******************* Bit definition for ADC_JDR2 register *******************/
emilmont 77:869cf507173a 1159 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
emilmont 77:869cf507173a 1160
emilmont 77:869cf507173a 1161 /******************* Bit definition for ADC_JDR3 register *******************/
emilmont 77:869cf507173a 1162 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
emilmont 77:869cf507173a 1163
emilmont 77:869cf507173a 1164 /******************* Bit definition for ADC_JDR4 register *******************/
emilmont 77:869cf507173a 1165 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
emilmont 77:869cf507173a 1166
emilmont 77:869cf507173a 1167 /******************** Bit definition for ADC_DR register ********************/
emilmont 77:869cf507173a 1168 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
emilmont 77:869cf507173a 1169 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
emilmont 77:869cf507173a 1170
emilmont 77:869cf507173a 1171 /******************* Bit definition for ADC_CSR register ********************/
emilmont 77:869cf507173a 1172 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
emilmont 77:869cf507173a 1173 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
emilmont 77:869cf507173a 1174 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
emilmont 77:869cf507173a 1175 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
emilmont 77:869cf507173a 1176 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
emilmont 77:869cf507173a 1177 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
emilmont 77:869cf507173a 1178 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
emilmont 77:869cf507173a 1179 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
emilmont 77:869cf507173a 1180 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
emilmont 77:869cf507173a 1181 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
emilmont 77:869cf507173a 1182 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
emilmont 77:869cf507173a 1183 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
emilmont 77:869cf507173a 1184 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
emilmont 77:869cf507173a 1185 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
emilmont 77:869cf507173a 1186 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
emilmont 77:869cf507173a 1187 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
emilmont 77:869cf507173a 1188 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
emilmont 77:869cf507173a 1189 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
emilmont 77:869cf507173a 1190
emilmont 77:869cf507173a 1191 /******************* Bit definition for ADC_CCR register ********************/
emilmont 77:869cf507173a 1192 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
emilmont 77:869cf507173a 1193 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 1194 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 1195 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 1196 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 1197 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 1198 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
emilmont 77:869cf507173a 1199 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
emilmont 77:869cf507173a 1200 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
emilmont 77:869cf507173a 1201 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
emilmont 77:869cf507173a 1202 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
emilmont 77:869cf507173a 1203 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
emilmont 77:869cf507173a 1204 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
emilmont 77:869cf507173a 1205 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
emilmont 77:869cf507173a 1206 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
emilmont 77:869cf507173a 1207 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
emilmont 77:869cf507173a 1208 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
emilmont 77:869cf507173a 1209 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
emilmont 77:869cf507173a 1210 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
emilmont 77:869cf507173a 1211 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
emilmont 77:869cf507173a 1212
emilmont 77:869cf507173a 1213 /******************* Bit definition for ADC_CDR register ********************/
emilmont 77:869cf507173a 1214 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
emilmont 77:869cf507173a 1215 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
emilmont 77:869cf507173a 1216
emilmont 77:869cf507173a 1217 /******************************************************************************/
emilmont 77:869cf507173a 1218 /* */
emilmont 77:869cf507173a 1219 /* CRC calculation unit */
emilmont 77:869cf507173a 1220 /* */
emilmont 77:869cf507173a 1221 /******************************************************************************/
emilmont 77:869cf507173a 1222 /******************* Bit definition for CRC_DR register *********************/
emilmont 77:869cf507173a 1223 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
emilmont 77:869cf507173a 1224
emilmont 77:869cf507173a 1225
emilmont 77:869cf507173a 1226 /******************* Bit definition for CRC_IDR register ********************/
emilmont 77:869cf507173a 1227 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
emilmont 77:869cf507173a 1228
emilmont 77:869cf507173a 1229
emilmont 77:869cf507173a 1230 /******************** Bit definition for CRC_CR register ********************/
emilmont 77:869cf507173a 1231 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
emilmont 77:869cf507173a 1232
emilmont 77:869cf507173a 1233 /******************************************************************************/
emilmont 77:869cf507173a 1234 /* */
emilmont 77:869cf507173a 1235 /* Debug MCU */
emilmont 77:869cf507173a 1236 /* */
emilmont 77:869cf507173a 1237 /******************************************************************************/
emilmont 77:869cf507173a 1238
emilmont 77:869cf507173a 1239 /******************************************************************************/
emilmont 77:869cf507173a 1240 /* */
emilmont 77:869cf507173a 1241 /* DMA Controller */
emilmont 77:869cf507173a 1242 /* */
emilmont 77:869cf507173a 1243 /******************************************************************************/
emilmont 77:869cf507173a 1244 /******************** Bits definition for DMA_SxCR register *****************/
emilmont 77:869cf507173a 1245 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
emilmont 77:869cf507173a 1246 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1247 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1248 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1249 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
emilmont 77:869cf507173a 1250 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 1251 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1252 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
emilmont 77:869cf507173a 1253 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1254 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1255 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1256 #define DMA_SxCR_CT ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1257 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1258 #define DMA_SxCR_PL ((uint32_t)0x00030000)
emilmont 77:869cf507173a 1259 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1260 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 1261 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1262 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
emilmont 77:869cf507173a 1263 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1264 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1265 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
emilmont 77:869cf507173a 1266 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1267 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1268 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1269 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1270 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1271 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
emilmont 77:869cf507173a 1272 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1273 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1274 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1275 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1276 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1277 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1278 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1279 #define DMA_SxCR_EN ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1280
emilmont 77:869cf507173a 1281 /******************** Bits definition for DMA_SxCNDTR register **************/
emilmont 77:869cf507173a 1282 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
emilmont 77:869cf507173a 1283 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1284 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1285 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1286 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1287 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1288 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1289 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1290 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1291 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1292 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1293 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1294 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1295 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1296 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1297 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1298 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1299
emilmont 77:869cf507173a 1300 /******************** Bits definition for DMA_SxFCR register ****************/
emilmont 77:869cf507173a 1301 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1302 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
emilmont 77:869cf507173a 1303 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1304 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1305 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1306 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1307 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
emilmont 77:869cf507173a 1308 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1309 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1310
emilmont 77:869cf507173a 1311 /******************** Bits definition for DMA_LISR register *****************/
emilmont 77:869cf507173a 1312 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1313 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1314 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1315 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1316 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1317 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1318 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1319 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1320 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1321 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1322 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1323 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1324 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1325 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1326 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1327 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1328 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1329 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1330 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1331 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1332
emilmont 77:869cf507173a 1333 /******************** Bits definition for DMA_HISR register *****************/
emilmont 77:869cf507173a 1334 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1335 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1336 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1337 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1338 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1339 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1340 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1341 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1342 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1343 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1344 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1345 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1346 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1347 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1348 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1349 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1350 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1351 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1352 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1353 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1354
emilmont 77:869cf507173a 1355 /******************** Bits definition for DMA_LIFCR register ****************/
emilmont 77:869cf507173a 1356 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1357 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1358 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1359 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1360 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1361 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1362 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1363 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1364 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1365 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1366 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1367 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1368 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1369 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1370 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1371 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1372 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1373 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1374 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1375 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1376
emilmont 77:869cf507173a 1377 /******************** Bits definition for DMA_HIFCR register ****************/
emilmont 77:869cf507173a 1378 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1379 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1380 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1381 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1382 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1383 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1384 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1385 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1386 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1387 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1388 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1389 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1390 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1391 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1392 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1393 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1394 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1395 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1396 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1397 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1398
emilmont 77:869cf507173a 1399
emilmont 77:869cf507173a 1400 /******************************************************************************/
emilmont 77:869cf507173a 1401 /* */
emilmont 77:869cf507173a 1402 /* External Interrupt/Event Controller */
emilmont 77:869cf507173a 1403 /* */
emilmont 77:869cf507173a 1404 /******************************************************************************/
emilmont 77:869cf507173a 1405 /******************* Bit definition for EXTI_IMR register *******************/
emilmont 77:869cf507173a 1406 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
emilmont 77:869cf507173a 1407 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
emilmont 77:869cf507173a 1408 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
emilmont 77:869cf507173a 1409 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
emilmont 77:869cf507173a 1410 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
emilmont 77:869cf507173a 1411 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
emilmont 77:869cf507173a 1412 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
emilmont 77:869cf507173a 1413 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
emilmont 77:869cf507173a 1414 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
emilmont 77:869cf507173a 1415 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
emilmont 77:869cf507173a 1416 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
emilmont 77:869cf507173a 1417 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
emilmont 77:869cf507173a 1418 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
emilmont 77:869cf507173a 1419 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
emilmont 77:869cf507173a 1420 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
emilmont 77:869cf507173a 1421 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
emilmont 77:869cf507173a 1422 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
emilmont 77:869cf507173a 1423 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
emilmont 77:869cf507173a 1424 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
emilmont 77:869cf507173a 1425 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
emilmont 77:869cf507173a 1426
emilmont 77:869cf507173a 1427 /******************* Bit definition for EXTI_EMR register *******************/
emilmont 77:869cf507173a 1428 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
emilmont 77:869cf507173a 1429 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
emilmont 77:869cf507173a 1430 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
emilmont 77:869cf507173a 1431 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
emilmont 77:869cf507173a 1432 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
emilmont 77:869cf507173a 1433 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
emilmont 77:869cf507173a 1434 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
emilmont 77:869cf507173a 1435 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
emilmont 77:869cf507173a 1436 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
emilmont 77:869cf507173a 1437 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
emilmont 77:869cf507173a 1438 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
emilmont 77:869cf507173a 1439 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
emilmont 77:869cf507173a 1440 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
emilmont 77:869cf507173a 1441 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
emilmont 77:869cf507173a 1442 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
emilmont 77:869cf507173a 1443 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
emilmont 77:869cf507173a 1444 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
emilmont 77:869cf507173a 1445 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
emilmont 77:869cf507173a 1446 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
emilmont 77:869cf507173a 1447 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
emilmont 77:869cf507173a 1448
emilmont 77:869cf507173a 1449 /****************** Bit definition for EXTI_RTSR register *******************/
emilmont 77:869cf507173a 1450 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
emilmont 77:869cf507173a 1451 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
emilmont 77:869cf507173a 1452 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
emilmont 77:869cf507173a 1453 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
emilmont 77:869cf507173a 1454 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
emilmont 77:869cf507173a 1455 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
emilmont 77:869cf507173a 1456 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
emilmont 77:869cf507173a 1457 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
emilmont 77:869cf507173a 1458 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
emilmont 77:869cf507173a 1459 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
emilmont 77:869cf507173a 1460 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
emilmont 77:869cf507173a 1461 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
emilmont 77:869cf507173a 1462 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
emilmont 77:869cf507173a 1463 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
emilmont 77:869cf507173a 1464 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
emilmont 77:869cf507173a 1465 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
emilmont 77:869cf507173a 1466 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
emilmont 77:869cf507173a 1467 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
emilmont 77:869cf507173a 1468 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
emilmont 77:869cf507173a 1469 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
emilmont 77:869cf507173a 1470
emilmont 77:869cf507173a 1471 /****************** Bit definition for EXTI_FTSR register *******************/
emilmont 77:869cf507173a 1472 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
emilmont 77:869cf507173a 1473 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
emilmont 77:869cf507173a 1474 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
emilmont 77:869cf507173a 1475 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
emilmont 77:869cf507173a 1476 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
emilmont 77:869cf507173a 1477 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
emilmont 77:869cf507173a 1478 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
emilmont 77:869cf507173a 1479 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
emilmont 77:869cf507173a 1480 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
emilmont 77:869cf507173a 1481 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
emilmont 77:869cf507173a 1482 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
emilmont 77:869cf507173a 1483 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
emilmont 77:869cf507173a 1484 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
emilmont 77:869cf507173a 1485 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
emilmont 77:869cf507173a 1486 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
emilmont 77:869cf507173a 1487 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
emilmont 77:869cf507173a 1488 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
emilmont 77:869cf507173a 1489 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
emilmont 77:869cf507173a 1490 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
emilmont 77:869cf507173a 1491 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
emilmont 77:869cf507173a 1492
emilmont 77:869cf507173a 1493 /****************** Bit definition for EXTI_SWIER register ******************/
emilmont 77:869cf507173a 1494 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
emilmont 77:869cf507173a 1495 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
emilmont 77:869cf507173a 1496 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
emilmont 77:869cf507173a 1497 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
emilmont 77:869cf507173a 1498 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
emilmont 77:869cf507173a 1499 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
emilmont 77:869cf507173a 1500 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
emilmont 77:869cf507173a 1501 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
emilmont 77:869cf507173a 1502 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
emilmont 77:869cf507173a 1503 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
emilmont 77:869cf507173a 1504 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
emilmont 77:869cf507173a 1505 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
emilmont 77:869cf507173a 1506 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
emilmont 77:869cf507173a 1507 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
emilmont 77:869cf507173a 1508 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
emilmont 77:869cf507173a 1509 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
emilmont 77:869cf507173a 1510 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
emilmont 77:869cf507173a 1511 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
emilmont 77:869cf507173a 1512 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
emilmont 77:869cf507173a 1513 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
emilmont 77:869cf507173a 1514
emilmont 77:869cf507173a 1515 /******************* Bit definition for EXTI_PR register ********************/
emilmont 77:869cf507173a 1516 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
emilmont 77:869cf507173a 1517 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
emilmont 77:869cf507173a 1518 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
emilmont 77:869cf507173a 1519 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
emilmont 77:869cf507173a 1520 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
emilmont 77:869cf507173a 1521 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
emilmont 77:869cf507173a 1522 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
emilmont 77:869cf507173a 1523 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
emilmont 77:869cf507173a 1524 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
emilmont 77:869cf507173a 1525 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
emilmont 77:869cf507173a 1526 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
emilmont 77:869cf507173a 1527 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
emilmont 77:869cf507173a 1528 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
emilmont 77:869cf507173a 1529 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
emilmont 77:869cf507173a 1530 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
emilmont 77:869cf507173a 1531 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
emilmont 77:869cf507173a 1532 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
emilmont 77:869cf507173a 1533 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
emilmont 77:869cf507173a 1534 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
emilmont 77:869cf507173a 1535 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
emilmont 77:869cf507173a 1536
emilmont 77:869cf507173a 1537 /******************************************************************************/
emilmont 77:869cf507173a 1538 /* */
emilmont 77:869cf507173a 1539 /* FLASH */
emilmont 77:869cf507173a 1540 /* */
emilmont 77:869cf507173a 1541 /******************************************************************************/
emilmont 77:869cf507173a 1542 /******************* Bits definition for FLASH_ACR register *****************/
emilmont 77:869cf507173a 1543 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 1544 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
emilmont 77:869cf507173a 1545 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1546 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1547 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
emilmont 77:869cf507173a 1548 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1549 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
emilmont 77:869cf507173a 1550 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
emilmont 77:869cf507173a 1551 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
emilmont 77:869cf507173a 1552
emilmont 77:869cf507173a 1553 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1554 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1555 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1556 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1557 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1558 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
emilmont 77:869cf507173a 1559 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
emilmont 77:869cf507173a 1560
emilmont 77:869cf507173a 1561 /******************* Bits definition for FLASH_SR register ******************/
emilmont 77:869cf507173a 1562 #define FLASH_SR_EOP ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1563 #define FLASH_SR_SOP ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1564 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1565 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1566 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1567 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1568 #define FLASH_SR_BSY ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1569
emilmont 77:869cf507173a 1570 /******************* Bits definition for FLASH_CR register ******************/
emilmont 77:869cf507173a 1571 #define FLASH_CR_PG ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1572 #define FLASH_CR_SER ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1573 #define FLASH_CR_MER ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1574 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
emilmont 77:869cf507173a 1575 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1576 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1577 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1578 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1579 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1580 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
emilmont 77:869cf507173a 1581 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1582 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1583 #define FLASH_CR_STRT ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1584 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1585 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
emilmont 77:869cf507173a 1586
emilmont 77:869cf507173a 1587 /******************* Bits definition for FLASH_OPTCR register ***************/
emilmont 77:869cf507173a 1588 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1589 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1590 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1591 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1592 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
emilmont 77:869cf507173a 1593
emilmont 77:869cf507173a 1594 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1595 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1596 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1597 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
emilmont 77:869cf507173a 1598 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1599 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1600 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1601 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1602 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1603 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1604 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1605 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1606 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
emilmont 77:869cf507173a 1607 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1608 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 1609 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1610 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1611 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1612 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1613 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1614 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 1615 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1616 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1617 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1618 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1619
emilmont 77:869cf507173a 1620 /****************** Bits definition for FLASH_OPTCR1 register ***************/
emilmont 77:869cf507173a 1621 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
emilmont 77:869cf507173a 1622 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1623 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 1624 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1625 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1626 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1627 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1628 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1629 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 1630 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1631 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1632 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1633 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1634
emilmont 77:869cf507173a 1635 /******************************************************************************/
emilmont 77:869cf507173a 1636 /* */
emilmont 77:869cf507173a 1637 /* General Purpose I/O */
emilmont 77:869cf507173a 1638 /* */
emilmont 77:869cf507173a 1639 /******************************************************************************/
emilmont 77:869cf507173a 1640 /****************** Bits definition for GPIO_MODER register *****************/
emilmont 77:869cf507173a 1641 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
emilmont 77:869cf507173a 1642 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1643 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1644
emilmont 77:869cf507173a 1645 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
emilmont 77:869cf507173a 1646 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1647 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1648
emilmont 77:869cf507173a 1649 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
emilmont 77:869cf507173a 1650 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1651 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1652
emilmont 77:869cf507173a 1653 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
emilmont 77:869cf507173a 1654 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1655 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1656
emilmont 77:869cf507173a 1657 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
emilmont 77:869cf507173a 1658 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1659 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1660
emilmont 77:869cf507173a 1661 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
emilmont 77:869cf507173a 1662 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1663 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1664
emilmont 77:869cf507173a 1665 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
emilmont 77:869cf507173a 1666 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1667 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1668
emilmont 77:869cf507173a 1669 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
emilmont 77:869cf507173a 1670 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1671 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1672
emilmont 77:869cf507173a 1673 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
emilmont 77:869cf507173a 1674 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1675 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 1676
emilmont 77:869cf507173a 1677 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
emilmont 77:869cf507173a 1678 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1679 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1680
emilmont 77:869cf507173a 1681 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
emilmont 77:869cf507173a 1682 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1683 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1684
emilmont 77:869cf507173a 1685 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
emilmont 77:869cf507173a 1686 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1687 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 1688
emilmont 77:869cf507173a 1689 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
emilmont 77:869cf507173a 1690 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1691 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1692
emilmont 77:869cf507173a 1693 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
emilmont 77:869cf507173a 1694 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1695 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1696
emilmont 77:869cf507173a 1697 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
emilmont 77:869cf507173a 1698 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 1699 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 1700
emilmont 77:869cf507173a 1701 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
emilmont 77:869cf507173a 1702 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 1703 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 1704
emilmont 77:869cf507173a 1705 /****************** Bits definition for GPIO_OTYPER register ****************/
emilmont 77:869cf507173a 1706 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1707 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1708 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1709 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1710 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1711 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1712 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1713 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1714 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1715 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1716 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1717 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1718 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1719 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1720 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1721 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1722
emilmont 77:869cf507173a 1723 /****************** Bits definition for GPIO_OSPEEDR register ***************/
emilmont 77:869cf507173a 1724 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
emilmont 77:869cf507173a 1725 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1726 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1727
emilmont 77:869cf507173a 1728 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
emilmont 77:869cf507173a 1729 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1730 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1731
emilmont 77:869cf507173a 1732 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
emilmont 77:869cf507173a 1733 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1734 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1735
emilmont 77:869cf507173a 1736 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
emilmont 77:869cf507173a 1737 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1738 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1739
emilmont 77:869cf507173a 1740 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
emilmont 77:869cf507173a 1741 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1742 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1743
emilmont 77:869cf507173a 1744 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
emilmont 77:869cf507173a 1745 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1746 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1747
emilmont 77:869cf507173a 1748 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
emilmont 77:869cf507173a 1749 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1750 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1751
emilmont 77:869cf507173a 1752 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
emilmont 77:869cf507173a 1753 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1754 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1755
emilmont 77:869cf507173a 1756 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
emilmont 77:869cf507173a 1757 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1758 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 1759
emilmont 77:869cf507173a 1760 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
emilmont 77:869cf507173a 1761 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1762 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1763
emilmont 77:869cf507173a 1764 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
emilmont 77:869cf507173a 1765 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1766 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1767
emilmont 77:869cf507173a 1768 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
emilmont 77:869cf507173a 1769 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1770 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 1771
emilmont 77:869cf507173a 1772 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
emilmont 77:869cf507173a 1773 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1774 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1775
emilmont 77:869cf507173a 1776 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
emilmont 77:869cf507173a 1777 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1778 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1779
emilmont 77:869cf507173a 1780 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
emilmont 77:869cf507173a 1781 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 1782 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 1783
emilmont 77:869cf507173a 1784 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
emilmont 77:869cf507173a 1785 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 1786 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 1787
emilmont 77:869cf507173a 1788 /****************** Bits definition for GPIO_PUPDR register *****************/
emilmont 77:869cf507173a 1789 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
emilmont 77:869cf507173a 1790 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1791 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1792
emilmont 77:869cf507173a 1793 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
emilmont 77:869cf507173a 1794 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1795 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1796
emilmont 77:869cf507173a 1797 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
emilmont 77:869cf507173a 1798 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1799 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1800
emilmont 77:869cf507173a 1801 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
emilmont 77:869cf507173a 1802 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1803 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1804
emilmont 77:869cf507173a 1805 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
emilmont 77:869cf507173a 1806 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1807 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1808
emilmont 77:869cf507173a 1809 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
emilmont 77:869cf507173a 1810 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1811 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1812
emilmont 77:869cf507173a 1813 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
emilmont 77:869cf507173a 1814 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1815 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1816
emilmont 77:869cf507173a 1817 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
emilmont 77:869cf507173a 1818 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1819 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1820
emilmont 77:869cf507173a 1821 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
emilmont 77:869cf507173a 1822 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1823 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 1824
emilmont 77:869cf507173a 1825 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
emilmont 77:869cf507173a 1826 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1827 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1828
emilmont 77:869cf507173a 1829 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
emilmont 77:869cf507173a 1830 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1831 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1832
emilmont 77:869cf507173a 1833 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
emilmont 77:869cf507173a 1834 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1835 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 1836
emilmont 77:869cf507173a 1837 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
emilmont 77:869cf507173a 1838 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1839 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1840
emilmont 77:869cf507173a 1841 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
emilmont 77:869cf507173a 1842 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1843 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1844
emilmont 77:869cf507173a 1845 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
emilmont 77:869cf507173a 1846 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 1847 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 1848
emilmont 77:869cf507173a 1849 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
emilmont 77:869cf507173a 1850 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 1851 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 1852
emilmont 77:869cf507173a 1853 /****************** Bits definition for GPIO_IDR register *******************/
emilmont 77:869cf507173a 1854 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1855 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1856 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1857 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1858 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1859 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1860 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1861 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1862 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1863 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1864 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1865 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1866 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1867 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1868 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1869 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1870 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
emilmont 77:869cf507173a 1871 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
emilmont 77:869cf507173a 1872 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
emilmont 77:869cf507173a 1873 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
emilmont 77:869cf507173a 1874 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
emilmont 77:869cf507173a 1875 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
emilmont 77:869cf507173a 1876 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
emilmont 77:869cf507173a 1877 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
emilmont 77:869cf507173a 1878 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
emilmont 77:869cf507173a 1879 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
emilmont 77:869cf507173a 1880 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
emilmont 77:869cf507173a 1881 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
emilmont 77:869cf507173a 1882 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
emilmont 77:869cf507173a 1883 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
emilmont 77:869cf507173a 1884 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
emilmont 77:869cf507173a 1885 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
emilmont 77:869cf507173a 1886 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
emilmont 77:869cf507173a 1887
emilmont 77:869cf507173a 1888 /****************** Bits definition for GPIO_ODR register *******************/
emilmont 77:869cf507173a 1889 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1890 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1891 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1892 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1893 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1894 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1895 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1896 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1897 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1898 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1899 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1900 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1901 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1902 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1903 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1904 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1905 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
emilmont 77:869cf507173a 1906 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
emilmont 77:869cf507173a 1907 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
emilmont 77:869cf507173a 1908 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
emilmont 77:869cf507173a 1909 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
emilmont 77:869cf507173a 1910 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
emilmont 77:869cf507173a 1911 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
emilmont 77:869cf507173a 1912 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
emilmont 77:869cf507173a 1913 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
emilmont 77:869cf507173a 1914 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
emilmont 77:869cf507173a 1915 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
emilmont 77:869cf507173a 1916 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
emilmont 77:869cf507173a 1917 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
emilmont 77:869cf507173a 1918 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
emilmont 77:869cf507173a 1919 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
emilmont 77:869cf507173a 1920 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
emilmont 77:869cf507173a 1921 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
emilmont 77:869cf507173a 1922
emilmont 77:869cf507173a 1923 /****************** Bits definition for GPIO_BSRR register ******************/
emilmont 77:869cf507173a 1924 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 1925 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 1926 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 1927 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 1928 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 1929 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 1930 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 1931 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 1932 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 1933 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 1934 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 1935 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 1936 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 1937 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 1938 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 1939 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 1940 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1941 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 1942 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 1943 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 1944 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 1945 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 1946 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 1947 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 1948 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 1949 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 1950 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 1951 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 1952 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 1953 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 1954 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 1955 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 1956
bogdanm 85:024bf7f99721 1957 /****************** Bit definition for GPIO_LCKR register ********************/
bogdanm 85:024bf7f99721 1958 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm 85:024bf7f99721 1959 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm 85:024bf7f99721 1960 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm 85:024bf7f99721 1961 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm 85:024bf7f99721 1962 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm 85:024bf7f99721 1963 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm 85:024bf7f99721 1964 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm 85:024bf7f99721 1965 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm 85:024bf7f99721 1966 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm 85:024bf7f99721 1967 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm 85:024bf7f99721 1968 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm 85:024bf7f99721 1969 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm 85:024bf7f99721 1970 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm 85:024bf7f99721 1971 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm 85:024bf7f99721 1972 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm 85:024bf7f99721 1973 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm 85:024bf7f99721 1974 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
emilmont 77:869cf507173a 1975
emilmont 77:869cf507173a 1976 /******************************************************************************/
emilmont 77:869cf507173a 1977 /* */
emilmont 77:869cf507173a 1978 /* Inter-integrated Circuit Interface */
emilmont 77:869cf507173a 1979 /* */
emilmont 77:869cf507173a 1980 /******************************************************************************/
emilmont 77:869cf507173a 1981 /******************* Bit definition for I2C_CR1 register ********************/
emilmont 77:869cf507173a 1982 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
emilmont 77:869cf507173a 1983 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
emilmont 77:869cf507173a 1984 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
emilmont 77:869cf507173a 1985 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
emilmont 77:869cf507173a 1986 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
emilmont 77:869cf507173a 1987 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
emilmont 77:869cf507173a 1988 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
emilmont 77:869cf507173a 1989 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
emilmont 77:869cf507173a 1990 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
emilmont 77:869cf507173a 1991 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
emilmont 77:869cf507173a 1992 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
emilmont 77:869cf507173a 1993 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
emilmont 77:869cf507173a 1994 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
emilmont 77:869cf507173a 1995 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
emilmont 77:869cf507173a 1996
emilmont 77:869cf507173a 1997 /******************* Bit definition for I2C_CR2 register ********************/
emilmont 77:869cf507173a 1998 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
emilmont 77:869cf507173a 1999 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 2000 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 2001 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 2002 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 2003 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 2004 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
emilmont 77:869cf507173a 2005
emilmont 77:869cf507173a 2006 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
emilmont 77:869cf507173a 2007 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
emilmont 77:869cf507173a 2008 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
emilmont 77:869cf507173a 2009 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
emilmont 77:869cf507173a 2010 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
emilmont 77:869cf507173a 2011
emilmont 77:869cf507173a 2012 /******************* Bit definition for I2C_OAR1 register *******************/
emilmont 77:869cf507173a 2013 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
emilmont 77:869cf507173a 2014 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
emilmont 77:869cf507173a 2015
emilmont 77:869cf507173a 2016 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 2017 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 2018 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 2019 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 2020 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 2021 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
emilmont 77:869cf507173a 2022 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
emilmont 77:869cf507173a 2023 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
emilmont 77:869cf507173a 2024 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
emilmont 77:869cf507173a 2025 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
emilmont 77:869cf507173a 2026
emilmont 77:869cf507173a 2027 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
emilmont 77:869cf507173a 2028
emilmont 77:869cf507173a 2029 /******************* Bit definition for I2C_OAR2 register *******************/
emilmont 77:869cf507173a 2030 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
emilmont 77:869cf507173a 2031 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
emilmont 77:869cf507173a 2032
emilmont 77:869cf507173a 2033 /******************** Bit definition for I2C_DR register ********************/
emilmont 77:869cf507173a 2034 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
emilmont 77:869cf507173a 2035
emilmont 77:869cf507173a 2036 /******************* Bit definition for I2C_SR1 register ********************/
emilmont 77:869cf507173a 2037 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
emilmont 77:869cf507173a 2038 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
emilmont 77:869cf507173a 2039 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
emilmont 77:869cf507173a 2040 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
emilmont 77:869cf507173a 2041 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
emilmont 77:869cf507173a 2042 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
emilmont 77:869cf507173a 2043 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
emilmont 77:869cf507173a 2044 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
emilmont 77:869cf507173a 2045 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
emilmont 77:869cf507173a 2046 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
emilmont 77:869cf507173a 2047 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
emilmont 77:869cf507173a 2048 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
emilmont 77:869cf507173a 2049 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
emilmont 77:869cf507173a 2050 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
emilmont 77:869cf507173a 2051
emilmont 77:869cf507173a 2052 /******************* Bit definition for I2C_SR2 register ********************/
emilmont 77:869cf507173a 2053 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
emilmont 77:869cf507173a 2054 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
emilmont 77:869cf507173a 2055 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
emilmont 77:869cf507173a 2056 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
emilmont 77:869cf507173a 2057 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
emilmont 77:869cf507173a 2058 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
emilmont 77:869cf507173a 2059 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
emilmont 77:869cf507173a 2060 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
emilmont 77:869cf507173a 2061
emilmont 77:869cf507173a 2062 /******************* Bit definition for I2C_CCR register ********************/
emilmont 77:869cf507173a 2063 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
emilmont 77:869cf507173a 2064 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
emilmont 77:869cf507173a 2065 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
emilmont 77:869cf507173a 2066
emilmont 77:869cf507173a 2067 /****************** Bit definition for I2C_TRISE register *******************/
emilmont 77:869cf507173a 2068 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
emilmont 77:869cf507173a 2069
emilmont 77:869cf507173a 2070 /****************** Bit definition for I2C_FLTR register *******************/
emilmont 77:869cf507173a 2071 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
emilmont 77:869cf507173a 2072 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
emilmont 77:869cf507173a 2073
emilmont 77:869cf507173a 2074 /******************************************************************************/
emilmont 77:869cf507173a 2075 /* */
emilmont 77:869cf507173a 2076 /* Independent WATCHDOG */
emilmont 77:869cf507173a 2077 /* */
emilmont 77:869cf507173a 2078 /******************************************************************************/
emilmont 77:869cf507173a 2079 /******************* Bit definition for IWDG_KR register ********************/
emilmont 77:869cf507173a 2080 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
emilmont 77:869cf507173a 2081
emilmont 77:869cf507173a 2082 /******************* Bit definition for IWDG_PR register ********************/
emilmont 77:869cf507173a 2083 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
emilmont 77:869cf507173a 2084 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
emilmont 77:869cf507173a 2085 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
emilmont 77:869cf507173a 2086 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
emilmont 77:869cf507173a 2087
emilmont 77:869cf507173a 2088 /******************* Bit definition for IWDG_RLR register *******************/
emilmont 77:869cf507173a 2089 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
emilmont 77:869cf507173a 2090
emilmont 77:869cf507173a 2091 /******************* Bit definition for IWDG_SR register ********************/
emilmont 77:869cf507173a 2092 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
emilmont 77:869cf507173a 2093 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
emilmont 77:869cf507173a 2094
emilmont 77:869cf507173a 2095
emilmont 77:869cf507173a 2096 /******************************************************************************/
emilmont 77:869cf507173a 2097 /* */
emilmont 77:869cf507173a 2098 /* Power Control */
emilmont 77:869cf507173a 2099 /* */
emilmont 77:869cf507173a 2100 /******************************************************************************/
emilmont 77:869cf507173a 2101 /******************** Bit definition for PWR_CR register ********************/
emilmont 77:869cf507173a 2102 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
emilmont 77:869cf507173a 2103 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
emilmont 77:869cf507173a 2104 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
emilmont 77:869cf507173a 2105 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
emilmont 77:869cf507173a 2106 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
emilmont 77:869cf507173a 2107
emilmont 77:869cf507173a 2108 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
emilmont 77:869cf507173a 2109 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
emilmont 77:869cf507173a 2110 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
emilmont 77:869cf507173a 2111 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
emilmont 77:869cf507173a 2112
emilmont 77:869cf507173a 2113 /*!< PVD level configuration */
emilmont 77:869cf507173a 2114 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
emilmont 77:869cf507173a 2115 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
emilmont 77:869cf507173a 2116 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
emilmont 77:869cf507173a 2117 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
emilmont 77:869cf507173a 2118 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
emilmont 77:869cf507173a 2119 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
emilmont 77:869cf507173a 2120 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
emilmont 77:869cf507173a 2121 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
emilmont 77:869cf507173a 2122
emilmont 77:869cf507173a 2123 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
emilmont 77:869cf507173a 2124 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
bogdanm 85:024bf7f99721 2125 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
bogdanm 85:024bf7f99721 2126 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
bogdanm 85:024bf7f99721 2127 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
bogdanm 85:024bf7f99721 2128 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
emilmont 77:869cf507173a 2129 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
emilmont 77:869cf507173a 2130 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
emilmont 77:869cf507173a 2131
emilmont 77:869cf507173a 2132 /* Legacy define */
emilmont 77:869cf507173a 2133 #define PWR_CR_PMODE PWR_CR_VOS
emilmont 77:869cf507173a 2134
emilmont 77:869cf507173a 2135 /******************* Bit definition for PWR_CSR register ********************/
emilmont 77:869cf507173a 2136 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
emilmont 77:869cf507173a 2137 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
emilmont 77:869cf507173a 2138 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
emilmont 77:869cf507173a 2139 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
emilmont 77:869cf507173a 2140 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
emilmont 77:869cf507173a 2141 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
emilmont 77:869cf507173a 2142 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
emilmont 77:869cf507173a 2143
emilmont 77:869cf507173a 2144 /* Legacy define */
emilmont 77:869cf507173a 2145 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
emilmont 77:869cf507173a 2146
emilmont 77:869cf507173a 2147 /******************************************************************************/
emilmont 77:869cf507173a 2148 /* */
emilmont 77:869cf507173a 2149 /* Reset and Clock Control */
emilmont 77:869cf507173a 2150 /* */
emilmont 77:869cf507173a 2151 /******************************************************************************/
emilmont 77:869cf507173a 2152 /******************** Bit definition for RCC_CR register ********************/
emilmont 77:869cf507173a 2153 #define RCC_CR_HSION ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2154 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2155
emilmont 77:869cf507173a 2156 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
emilmont 77:869cf507173a 2157 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
emilmont 77:869cf507173a 2158 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
emilmont 77:869cf507173a 2159 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
emilmont 77:869cf507173a 2160 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
emilmont 77:869cf507173a 2161 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
emilmont 77:869cf507173a 2162
emilmont 77:869cf507173a 2163 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
emilmont 77:869cf507173a 2164 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
emilmont 77:869cf507173a 2165 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
emilmont 77:869cf507173a 2166 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
emilmont 77:869cf507173a 2167 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
emilmont 77:869cf507173a 2168 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
emilmont 77:869cf507173a 2169 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
emilmont 77:869cf507173a 2170 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
emilmont 77:869cf507173a 2171 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
emilmont 77:869cf507173a 2172
emilmont 77:869cf507173a 2173 #define RCC_CR_HSEON ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2174 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2175 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2176 #define RCC_CR_CSSON ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2177 #define RCC_CR_PLLON ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2178 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2179 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2180 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2181
emilmont 77:869cf507173a 2182 /******************** Bit definition for RCC_PLLCFGR register ***************/
emilmont 77:869cf507173a 2183 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
emilmont 77:869cf507173a 2184 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2185 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2186 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2187 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2188 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2189 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2190
emilmont 77:869cf507173a 2191 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
emilmont 77:869cf507173a 2192 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2193 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2194 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2195 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2196 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2197 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2198 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2199 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2200 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2201
emilmont 77:869cf507173a 2202 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
emilmont 77:869cf507173a 2203 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2204 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2205
emilmont 77:869cf507173a 2206 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2207 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2208 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
emilmont 77:869cf507173a 2209
emilmont 77:869cf507173a 2210 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 2211 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2212 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2213 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2214 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2215
emilmont 77:869cf507173a 2216 /******************** Bit definition for RCC_CFGR register ******************/
emilmont 77:869cf507173a 2217 /*!< SW configuration */
emilmont 77:869cf507173a 2218 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
emilmont 77:869cf507173a 2219 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2220 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2221
emilmont 77:869cf507173a 2222 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
emilmont 77:869cf507173a 2223 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
emilmont 77:869cf507173a 2224 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
emilmont 77:869cf507173a 2225
emilmont 77:869cf507173a 2226 /*!< SWS configuration */
emilmont 77:869cf507173a 2227 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
emilmont 77:869cf507173a 2228 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
emilmont 77:869cf507173a 2229 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
emilmont 77:869cf507173a 2230
emilmont 77:869cf507173a 2231 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
emilmont 77:869cf507173a 2232 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
emilmont 77:869cf507173a 2233 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
emilmont 77:869cf507173a 2234
emilmont 77:869cf507173a 2235 /*!< HPRE configuration */
emilmont 77:869cf507173a 2236 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
emilmont 77:869cf507173a 2237 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2238 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2239 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2240 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2241
emilmont 77:869cf507173a 2242 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
emilmont 77:869cf507173a 2243 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
emilmont 77:869cf507173a 2244 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
emilmont 77:869cf507173a 2245 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
emilmont 77:869cf507173a 2246 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
emilmont 77:869cf507173a 2247 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
emilmont 77:869cf507173a 2248 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
emilmont 77:869cf507173a 2249 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
emilmont 77:869cf507173a 2250 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
emilmont 77:869cf507173a 2251
emilmont 77:869cf507173a 2252 /*!< PPRE1 configuration */
emilmont 77:869cf507173a 2253 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
emilmont 77:869cf507173a 2254 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 2255 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 2256 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 2257
emilmont 77:869cf507173a 2258 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
emilmont 77:869cf507173a 2259 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
emilmont 77:869cf507173a 2260 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
emilmont 77:869cf507173a 2261 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
emilmont 77:869cf507173a 2262 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
emilmont 77:869cf507173a 2263
emilmont 77:869cf507173a 2264 /*!< PPRE2 configuration */
emilmont 77:869cf507173a 2265 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
emilmont 77:869cf507173a 2266 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
emilmont 77:869cf507173a 2267 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
emilmont 77:869cf507173a 2268 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
emilmont 77:869cf507173a 2269
emilmont 77:869cf507173a 2270 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
emilmont 77:869cf507173a 2271 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
emilmont 77:869cf507173a 2272 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
emilmont 77:869cf507173a 2273 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
emilmont 77:869cf507173a 2274 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
emilmont 77:869cf507173a 2275
emilmont 77:869cf507173a 2276 /*!< RTCPRE configuration */
emilmont 77:869cf507173a 2277 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
emilmont 77:869cf507173a 2278 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2279 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2280 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2281 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2282 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2283
emilmont 77:869cf507173a 2284 /*!< MCO1 configuration */
emilmont 77:869cf507173a 2285 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
emilmont 77:869cf507173a 2286 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2287 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2288
emilmont 77:869cf507173a 2289 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2290
emilmont 77:869cf507173a 2291 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
emilmont 77:869cf507173a 2292 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2293 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2294 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2295
emilmont 77:869cf507173a 2296 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
emilmont 77:869cf507173a 2297 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2298 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2299 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 2300
emilmont 77:869cf507173a 2301 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
emilmont 77:869cf507173a 2302 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 2303 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 2304
emilmont 77:869cf507173a 2305 /******************** Bit definition for RCC_CIR register *******************/
emilmont 77:869cf507173a 2306 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2307 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2308 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2309 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2310 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2311 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2312
emilmont 77:869cf507173a 2313 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2314 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2315 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2316 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2317 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2318 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2319 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2320
emilmont 77:869cf507173a 2321 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2322 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2323 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2324 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2325 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2326 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2327
emilmont 77:869cf507173a 2328 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2329
emilmont 77:869cf507173a 2330 /******************** Bit definition for RCC_AHB1RSTR register **************/
emilmont 77:869cf507173a 2331 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2332 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2333 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2334 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2335 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2336 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2337 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2338 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2339 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2340
emilmont 77:869cf507173a 2341 /******************** Bit definition for RCC_AHB2RSTR register **************/
emilmont 77:869cf507173a 2342 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2343
emilmont 77:869cf507173a 2344 /******************** Bit definition for RCC_AHB3RSTR register **************/
emilmont 77:869cf507173a 2345
emilmont 77:869cf507173a 2346 /******************** Bit definition for RCC_APB1RSTR register **************/
emilmont 77:869cf507173a 2347 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2348 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2349 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2350 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2351 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2352 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2353 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2354 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2355 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2356 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2357 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2358 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2359
emilmont 77:869cf507173a 2360 /******************** Bit definition for RCC_APB2RSTR register **************/
emilmont 77:869cf507173a 2361 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2362 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2363 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2364 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2365 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2366 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2367 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2368 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2369 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2370 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2371 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2372
emilmont 77:869cf507173a 2373 /* Old SPI1RST bit definition, maintained for legacy purpose */
emilmont 77:869cf507173a 2374 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
emilmont 77:869cf507173a 2375
emilmont 77:869cf507173a 2376 /******************** Bit definition for RCC_AHB1ENR register ***************/
emilmont 77:869cf507173a 2377 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2378 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2379 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2380 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2381 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2382 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2383 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2384 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2385 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2386 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2387 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2388
emilmont 77:869cf507173a 2389 /******************** Bit definition for RCC_AHB2ENR register ***************/
emilmont 77:869cf507173a 2390 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2391
emilmont 77:869cf507173a 2392 /******************** Bit definition for RCC_AHB3ENR register ***************/
emilmont 77:869cf507173a 2393
emilmont 77:869cf507173a 2394 /******************** Bit definition for RCC_APB1ENR register ***************/
emilmont 77:869cf507173a 2395 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2396 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2397 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2398 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2399 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2400 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2401 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2402 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2403 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2404 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2405 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2406 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2407
emilmont 77:869cf507173a 2408 /******************** Bit definition for RCC_APB2ENR register ***************/
emilmont 77:869cf507173a 2409 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2410 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2411 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2412 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2413 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2414 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2415 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2416 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2417 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2418 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2419 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2420
emilmont 77:869cf507173a 2421 /******************** Bit definition for RCC_AHB1LPENR register *************/
emilmont 77:869cf507173a 2422 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2423 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2424 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2425 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2426 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2427 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2428 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2429 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2430 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2431 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2432 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2433 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2434 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2435 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2436
emilmont 77:869cf507173a 2437 /******************** Bit definition for RCC_AHB2LPENR register *************/
emilmont 77:869cf507173a 2438 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2439
emilmont 77:869cf507173a 2440 /******************** Bit definition for RCC_AHB3LPENR register *************/
emilmont 77:869cf507173a 2441
emilmont 77:869cf507173a 2442 /******************** Bit definition for RCC_APB1LPENR register *************/
emilmont 77:869cf507173a 2443 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2444 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2445 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2446 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2447 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2448 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2449 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2450 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2451 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2452 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2453 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2454 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2455 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
emilmont 77:869cf507173a 2456
emilmont 77:869cf507173a 2457 /******************** Bit definition for RCC_APB2LPENR register *************/
emilmont 77:869cf507173a 2458 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2459 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2460 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2461 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2462 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2463 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2464 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2465 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2466 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2467 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2468 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2469
emilmont 77:869cf507173a 2470 /******************** Bit definition for RCC_BDCR register ******************/
emilmont 77:869cf507173a 2471 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2472 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2473 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2474
emilmont 77:869cf507173a 2475 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
emilmont 77:869cf507173a 2476 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2477 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2478
emilmont 77:869cf507173a 2479 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2480 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2481
emilmont 77:869cf507173a 2482 /******************** Bit definition for RCC_CSR register *******************/
emilmont 77:869cf507173a 2483 #define RCC_CSR_LSION ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2484 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2485 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2486 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2487 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2488 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2489 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2490 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
emilmont 77:869cf507173a 2491 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
emilmont 77:869cf507173a 2492 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
emilmont 77:869cf507173a 2493
emilmont 77:869cf507173a 2494 /******************** Bit definition for RCC_SSCGR register *****************/
emilmont 77:869cf507173a 2495 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
emilmont 77:869cf507173a 2496 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
emilmont 77:869cf507173a 2497 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
emilmont 77:869cf507173a 2498 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
emilmont 77:869cf507173a 2499
emilmont 77:869cf507173a 2500 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
emilmont 77:869cf507173a 2501 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
emilmont 77:869cf507173a 2502 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2503 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2504 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2505 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2506 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2507 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2508 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2509 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2510 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2511
emilmont 77:869cf507173a 2512 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
emilmont 77:869cf507173a 2513 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2514 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 2515 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 2516
emilmont 77:869cf507173a 2517 /******************************************************************************/
emilmont 77:869cf507173a 2518 /* */
emilmont 77:869cf507173a 2519 /* Real-Time Clock (RTC) */
emilmont 77:869cf507173a 2520 /* */
emilmont 77:869cf507173a 2521 /******************************************************************************/
emilmont 77:869cf507173a 2522 /******************** Bits definition for RTC_TR register *******************/
emilmont 77:869cf507173a 2523 #define RTC_TR_PM ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2524 #define RTC_TR_HT ((uint32_t)0x00300000)
emilmont 77:869cf507173a 2525 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2526 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2527 #define RTC_TR_HU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 2528 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2529 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2530 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2531 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2532 #define RTC_TR_MNT ((uint32_t)0x00007000)
emilmont 77:869cf507173a 2533 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2534 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2535 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2536 #define RTC_TR_MNU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 2537 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2538 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2539 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2540 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2541 #define RTC_TR_ST ((uint32_t)0x00000070)
emilmont 77:869cf507173a 2542 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2543 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2544 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2545 #define RTC_TR_SU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 2546 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2547 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2548 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2549 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2550
emilmont 77:869cf507173a 2551 /******************** Bits definition for RTC_DR register *******************/
emilmont 77:869cf507173a 2552 #define RTC_DR_YT ((uint32_t)0x00F00000)
emilmont 77:869cf507173a 2553 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2554 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2555 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2556 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2557 #define RTC_DR_YU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 2558 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2559 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2560 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2561 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2562 #define RTC_DR_WDU ((uint32_t)0x0000E000)
emilmont 77:869cf507173a 2563 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2564 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2565 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2566 #define RTC_DR_MT ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2567 #define RTC_DR_MU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 2568 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2569 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2570 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2571 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2572 #define RTC_DR_DT ((uint32_t)0x00000030)
emilmont 77:869cf507173a 2573 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2574 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2575 #define RTC_DR_DU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 2576 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2577 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2578 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2579 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2580
emilmont 77:869cf507173a 2581 /******************** Bits definition for RTC_CR register *******************/
emilmont 77:869cf507173a 2582 #define RTC_CR_COE ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2583 #define RTC_CR_OSEL ((uint32_t)0x00600000)
emilmont 77:869cf507173a 2584 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2585 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2586 #define RTC_CR_POL ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2587 #define RTC_CR_COSEL ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2588 #define RTC_CR_BCK ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2589 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2590 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2591 #define RTC_CR_TSIE ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2592 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2593 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2594 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2595 #define RTC_CR_TSE ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2596 #define RTC_CR_WUTE ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2597 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2598 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2599 #define RTC_CR_DCE ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2600 #define RTC_CR_FMT ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2601 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2602 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2603 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2604 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
emilmont 77:869cf507173a 2605 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2606 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2607 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2608
emilmont 77:869cf507173a 2609 /******************** Bits definition for RTC_ISR register ******************/
emilmont 77:869cf507173a 2610 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2611 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2612 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2613 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2614 #define RTC_ISR_TSF ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2615 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2616 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2617 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2618 #define RTC_ISR_INIT ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2619 #define RTC_ISR_INITF ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2620 #define RTC_ISR_RSF ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2621 #define RTC_ISR_INITS ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2622 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2623 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2624 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2625 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2626
emilmont 77:869cf507173a 2627 /******************** Bits definition for RTC_PRER register *****************/
emilmont 77:869cf507173a 2628 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
emilmont 77:869cf507173a 2629 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
emilmont 77:869cf507173a 2630
emilmont 77:869cf507173a 2631 /******************** Bits definition for RTC_WUTR register *****************/
emilmont 77:869cf507173a 2632 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
emilmont 77:869cf507173a 2633
emilmont 77:869cf507173a 2634 /******************** Bits definition for RTC_CALIBR register ***************/
emilmont 77:869cf507173a 2635 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2636 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
emilmont 77:869cf507173a 2637
emilmont 77:869cf507173a 2638 /******************** Bits definition for RTC_ALRMAR register ***************/
emilmont 77:869cf507173a 2639 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 2640 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
emilmont 77:869cf507173a 2641 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
emilmont 77:869cf507173a 2642 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2643 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 2644 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 2645 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2646 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2647 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2648 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2649 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2650 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2651 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
emilmont 77:869cf507173a 2652 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2653 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2654 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 2655 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2656 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2657 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2658 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2659 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2660 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
emilmont 77:869cf507173a 2661 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2662 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2663 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2664 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 2665 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2666 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2667 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2668 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2669 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2670 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
emilmont 77:869cf507173a 2671 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2672 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2673 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2674 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 2675 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2676 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2677 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2678 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2679
emilmont 77:869cf507173a 2680 /******************** Bits definition for RTC_ALRMBR register ***************/
emilmont 77:869cf507173a 2681 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 2682 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
emilmont 77:869cf507173a 2683 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
emilmont 77:869cf507173a 2684 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2685 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 2686 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 2687 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2688 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2689 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2690 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2691 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2692 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2693 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
emilmont 77:869cf507173a 2694 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2695 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2696 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 2697 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2698 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2699 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2700 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2701 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2702 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
emilmont 77:869cf507173a 2703 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2704 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2705 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2706 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 2707 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2708 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2709 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2710 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2711 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2712 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
emilmont 77:869cf507173a 2713 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2714 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2715 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2716 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 2717 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2718 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2719 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2720 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2721
emilmont 77:869cf507173a 2722 /******************** Bits definition for RTC_WPR register ******************/
emilmont 77:869cf507173a 2723 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
emilmont 77:869cf507173a 2724
emilmont 77:869cf507173a 2725 /******************** Bits definition for RTC_SSR register ******************/
emilmont 77:869cf507173a 2726 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
emilmont 77:869cf507173a 2727
emilmont 77:869cf507173a 2728 /******************** Bits definition for RTC_SHIFTR register ***************/
emilmont 77:869cf507173a 2729 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
emilmont 77:869cf507173a 2730 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
emilmont 77:869cf507173a 2731
emilmont 77:869cf507173a 2732 /******************** Bits definition for RTC_TSTR register *****************/
emilmont 77:869cf507173a 2733 #define RTC_TSTR_PM ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2734 #define RTC_TSTR_HT ((uint32_t)0x00300000)
emilmont 77:869cf507173a 2735 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2736 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2737 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 2738 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2739 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2740 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2741 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2742 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
emilmont 77:869cf507173a 2743 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2744 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2745 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2746 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 2747 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2748 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2749 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2750 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2751 #define RTC_TSTR_ST ((uint32_t)0x00000070)
emilmont 77:869cf507173a 2752 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2753 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2754 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2755 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 2756 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2757 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2758 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2759 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2760
emilmont 77:869cf507173a 2761 /******************** Bits definition for RTC_TSDR register *****************/
emilmont 77:869cf507173a 2762 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
emilmont 77:869cf507173a 2763 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2764 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2765 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2766 #define RTC_TSDR_MT ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2767 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 2768 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2769 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2770 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2771 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2772 #define RTC_TSDR_DT ((uint32_t)0x00000030)
emilmont 77:869cf507173a 2773 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2774 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2775 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 2776 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2777 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2778 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2779 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2780
emilmont 77:869cf507173a 2781 /******************** Bits definition for RTC_TSSSR register ****************/
emilmont 77:869cf507173a 2782 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
emilmont 77:869cf507173a 2783
emilmont 77:869cf507173a 2784 /******************** Bits definition for RTC_CAL register *****************/
emilmont 77:869cf507173a 2785 #define RTC_CALR_CALP ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2786 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2787 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2788 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
emilmont 77:869cf507173a 2789 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2790 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2791 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2792 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2793 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2794 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2795 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2796 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2797 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2798
emilmont 77:869cf507173a 2799 /******************** Bits definition for RTC_TAFCR register ****************/
emilmont 77:869cf507173a 2800 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2801 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2802 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2803 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2804 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
emilmont 77:869cf507173a 2805 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2806 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2807 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
emilmont 77:869cf507173a 2808 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2809 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2810 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
emilmont 77:869cf507173a 2811 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2812 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2813 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2814 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2815 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2816 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2817 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2818 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2819 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2820
emilmont 77:869cf507173a 2821 /******************** Bits definition for RTC_ALRMASSR register *************/
emilmont 77:869cf507173a 2822 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 2823 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2824 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2825 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2826 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2827 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
emilmont 77:869cf507173a 2828
emilmont 77:869cf507173a 2829 /******************** Bits definition for RTC_ALRMBSSR register *************/
emilmont 77:869cf507173a 2830 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 2831 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2832 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2833 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2834 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2835 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
emilmont 77:869cf507173a 2836
emilmont 77:869cf507173a 2837 /******************** Bits definition for RTC_BKP0R register ****************/
emilmont 77:869cf507173a 2838 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2839
emilmont 77:869cf507173a 2840 /******************** Bits definition for RTC_BKP1R register ****************/
emilmont 77:869cf507173a 2841 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2842
emilmont 77:869cf507173a 2843 /******************** Bits definition for RTC_BKP2R register ****************/
emilmont 77:869cf507173a 2844 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2845
emilmont 77:869cf507173a 2846 /******************** Bits definition for RTC_BKP3R register ****************/
emilmont 77:869cf507173a 2847 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2848
emilmont 77:869cf507173a 2849 /******************** Bits definition for RTC_BKP4R register ****************/
emilmont 77:869cf507173a 2850 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2851
emilmont 77:869cf507173a 2852 /******************** Bits definition for RTC_BKP5R register ****************/
emilmont 77:869cf507173a 2853 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2854
emilmont 77:869cf507173a 2855 /******************** Bits definition for RTC_BKP6R register ****************/
emilmont 77:869cf507173a 2856 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2857
emilmont 77:869cf507173a 2858 /******************** Bits definition for RTC_BKP7R register ****************/
emilmont 77:869cf507173a 2859 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2860
emilmont 77:869cf507173a 2861 /******************** Bits definition for RTC_BKP8R register ****************/
emilmont 77:869cf507173a 2862 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2863
emilmont 77:869cf507173a 2864 /******************** Bits definition for RTC_BKP9R register ****************/
emilmont 77:869cf507173a 2865 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2866
emilmont 77:869cf507173a 2867 /******************** Bits definition for RTC_BKP10R register ***************/
emilmont 77:869cf507173a 2868 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2869
emilmont 77:869cf507173a 2870 /******************** Bits definition for RTC_BKP11R register ***************/
emilmont 77:869cf507173a 2871 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2872
emilmont 77:869cf507173a 2873 /******************** Bits definition for RTC_BKP12R register ***************/
emilmont 77:869cf507173a 2874 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2875
emilmont 77:869cf507173a 2876 /******************** Bits definition for RTC_BKP13R register ***************/
emilmont 77:869cf507173a 2877 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2878
emilmont 77:869cf507173a 2879 /******************** Bits definition for RTC_BKP14R register ***************/
emilmont 77:869cf507173a 2880 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2881
emilmont 77:869cf507173a 2882 /******************** Bits definition for RTC_BKP15R register ***************/
emilmont 77:869cf507173a 2883 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2884
emilmont 77:869cf507173a 2885 /******************** Bits definition for RTC_BKP16R register ***************/
emilmont 77:869cf507173a 2886 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2887
emilmont 77:869cf507173a 2888 /******************** Bits definition for RTC_BKP17R register ***************/
emilmont 77:869cf507173a 2889 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2890
emilmont 77:869cf507173a 2891 /******************** Bits definition for RTC_BKP18R register ***************/
emilmont 77:869cf507173a 2892 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2893
emilmont 77:869cf507173a 2894 /******************** Bits definition for RTC_BKP19R register ***************/
emilmont 77:869cf507173a 2895 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 2896
emilmont 77:869cf507173a 2897
emilmont 77:869cf507173a 2898
emilmont 77:869cf507173a 2899 /******************************************************************************/
emilmont 77:869cf507173a 2900 /* */
emilmont 77:869cf507173a 2901 /* SD host Interface */
emilmont 77:869cf507173a 2902 /* */
emilmont 77:869cf507173a 2903 /******************************************************************************/
emilmont 77:869cf507173a 2904 /****************** Bit definition for SDIO_POWER register ******************/
emilmont 77:869cf507173a 2905 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
emilmont 77:869cf507173a 2906 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
emilmont 77:869cf507173a 2907 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
emilmont 77:869cf507173a 2908
emilmont 77:869cf507173a 2909 /****************** Bit definition for SDIO_CLKCR register ******************/
emilmont 77:869cf507173a 2910 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
emilmont 77:869cf507173a 2911 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
emilmont 77:869cf507173a 2912 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
emilmont 77:869cf507173a 2913 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
emilmont 77:869cf507173a 2914
emilmont 77:869cf507173a 2915 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
emilmont 77:869cf507173a 2916 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
emilmont 77:869cf507173a 2917 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
emilmont 77:869cf507173a 2918
emilmont 77:869cf507173a 2919 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
emilmont 77:869cf507173a 2920 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
emilmont 77:869cf507173a 2921
emilmont 77:869cf507173a 2922 /******************* Bit definition for SDIO_ARG register *******************/
emilmont 77:869cf507173a 2923 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
emilmont 77:869cf507173a 2924
emilmont 77:869cf507173a 2925 /******************* Bit definition for SDIO_CMD register *******************/
emilmont 77:869cf507173a 2926 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
emilmont 77:869cf507173a 2927
emilmont 77:869cf507173a 2928 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
emilmont 77:869cf507173a 2929 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
emilmont 77:869cf507173a 2930 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
emilmont 77:869cf507173a 2931
emilmont 77:869cf507173a 2932 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
emilmont 77:869cf507173a 2933 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
emilmont 77:869cf507173a 2934 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
emilmont 77:869cf507173a 2935 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
emilmont 77:869cf507173a 2936 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
emilmont 77:869cf507173a 2937 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
emilmont 77:869cf507173a 2938 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
emilmont 77:869cf507173a 2939
emilmont 77:869cf507173a 2940 /***************** Bit definition for SDIO_RESPCMD register *****************/
emilmont 77:869cf507173a 2941 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
emilmont 77:869cf507173a 2942
emilmont 77:869cf507173a 2943 /****************** Bit definition for SDIO_RESP0 register ******************/
emilmont 77:869cf507173a 2944 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
emilmont 77:869cf507173a 2945
emilmont 77:869cf507173a 2946 /****************** Bit definition for SDIO_RESP1 register ******************/
emilmont 77:869cf507173a 2947 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
emilmont 77:869cf507173a 2948
emilmont 77:869cf507173a 2949 /****************** Bit definition for SDIO_RESP2 register ******************/
emilmont 77:869cf507173a 2950 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
emilmont 77:869cf507173a 2951
emilmont 77:869cf507173a 2952 /****************** Bit definition for SDIO_RESP3 register ******************/
emilmont 77:869cf507173a 2953 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
emilmont 77:869cf507173a 2954
emilmont 77:869cf507173a 2955 /****************** Bit definition for SDIO_RESP4 register ******************/
emilmont 77:869cf507173a 2956 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
emilmont 77:869cf507173a 2957
emilmont 77:869cf507173a 2958 /****************** Bit definition for SDIO_DTIMER register *****************/
emilmont 77:869cf507173a 2959 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
emilmont 77:869cf507173a 2960
emilmont 77:869cf507173a 2961 /****************** Bit definition for SDIO_DLEN register *******************/
emilmont 77:869cf507173a 2962 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
emilmont 77:869cf507173a 2963
emilmont 77:869cf507173a 2964 /****************** Bit definition for SDIO_DCTRL register ******************/
emilmont 77:869cf507173a 2965 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
emilmont 77:869cf507173a 2966 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
emilmont 77:869cf507173a 2967 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
emilmont 77:869cf507173a 2968 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
emilmont 77:869cf507173a 2969
emilmont 77:869cf507173a 2970 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
emilmont 77:869cf507173a 2971 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 2972 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 2973 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 2974 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
emilmont 77:869cf507173a 2975
emilmont 77:869cf507173a 2976 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
emilmont 77:869cf507173a 2977 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
emilmont 77:869cf507173a 2978 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
emilmont 77:869cf507173a 2979 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
emilmont 77:869cf507173a 2980
emilmont 77:869cf507173a 2981 /****************** Bit definition for SDIO_DCOUNT register *****************/
emilmont 77:869cf507173a 2982 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
emilmont 77:869cf507173a 2983
emilmont 77:869cf507173a 2984 /****************** Bit definition for SDIO_STA register ********************/
emilmont 77:869cf507173a 2985 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
emilmont 77:869cf507173a 2986 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
emilmont 77:869cf507173a 2987 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
emilmont 77:869cf507173a 2988 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
emilmont 77:869cf507173a 2989 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
emilmont 77:869cf507173a 2990 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
emilmont 77:869cf507173a 2991 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
emilmont 77:869cf507173a 2992 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
emilmont 77:869cf507173a 2993 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
emilmont 77:869cf507173a 2994 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
emilmont 77:869cf507173a 2995 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
emilmont 77:869cf507173a 2996 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
emilmont 77:869cf507173a 2997 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
emilmont 77:869cf507173a 2998 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
emilmont 77:869cf507173a 2999 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
emilmont 77:869cf507173a 3000 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
emilmont 77:869cf507173a 3001 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
emilmont 77:869cf507173a 3002 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
emilmont 77:869cf507173a 3003 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
emilmont 77:869cf507173a 3004 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
emilmont 77:869cf507173a 3005 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
emilmont 77:869cf507173a 3006 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
emilmont 77:869cf507173a 3007 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
emilmont 77:869cf507173a 3008 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
emilmont 77:869cf507173a 3009
emilmont 77:869cf507173a 3010 /******************* Bit definition for SDIO_ICR register *******************/
emilmont 77:869cf507173a 3011 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
emilmont 77:869cf507173a 3012 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
emilmont 77:869cf507173a 3013 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
emilmont 77:869cf507173a 3014 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
emilmont 77:869cf507173a 3015 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
emilmont 77:869cf507173a 3016 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
emilmont 77:869cf507173a 3017 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
emilmont 77:869cf507173a 3018 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
emilmont 77:869cf507173a 3019 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
emilmont 77:869cf507173a 3020 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
emilmont 77:869cf507173a 3021 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
emilmont 77:869cf507173a 3022 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
emilmont 77:869cf507173a 3023 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
emilmont 77:869cf507173a 3024
emilmont 77:869cf507173a 3025 /****************** Bit definition for SDIO_MASK register *******************/
emilmont 77:869cf507173a 3026 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
emilmont 77:869cf507173a 3027 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
emilmont 77:869cf507173a 3028 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
emilmont 77:869cf507173a 3029 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
emilmont 77:869cf507173a 3030 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
emilmont 77:869cf507173a 3031 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
emilmont 77:869cf507173a 3032 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
emilmont 77:869cf507173a 3033 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
emilmont 77:869cf507173a 3034 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
emilmont 77:869cf507173a 3035 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
emilmont 77:869cf507173a 3036 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
emilmont 77:869cf507173a 3037 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
emilmont 77:869cf507173a 3038 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
emilmont 77:869cf507173a 3039 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
emilmont 77:869cf507173a 3040 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
emilmont 77:869cf507173a 3041 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
emilmont 77:869cf507173a 3042 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
emilmont 77:869cf507173a 3043 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
emilmont 77:869cf507173a 3044 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
emilmont 77:869cf507173a 3045 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
emilmont 77:869cf507173a 3046 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
emilmont 77:869cf507173a 3047 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
emilmont 77:869cf507173a 3048 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
emilmont 77:869cf507173a 3049 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
emilmont 77:869cf507173a 3050
emilmont 77:869cf507173a 3051 /***************** Bit definition for SDIO_FIFOCNT register *****************/
emilmont 77:869cf507173a 3052 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
emilmont 77:869cf507173a 3053
emilmont 77:869cf507173a 3054 /****************** Bit definition for SDIO_FIFO register *******************/
emilmont 77:869cf507173a 3055 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
emilmont 77:869cf507173a 3056
emilmont 77:869cf507173a 3057 /******************************************************************************/
emilmont 77:869cf507173a 3058 /* */
emilmont 77:869cf507173a 3059 /* Serial Peripheral Interface */
emilmont 77:869cf507173a 3060 /* */
emilmont 77:869cf507173a 3061 /******************************************************************************/
emilmont 77:869cf507173a 3062 /******************* Bit definition for SPI_CR1 register ********************/
emilmont 77:869cf507173a 3063 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
emilmont 77:869cf507173a 3064 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
emilmont 77:869cf507173a 3065 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
emilmont 77:869cf507173a 3066
emilmont 77:869cf507173a 3067 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
emilmont 77:869cf507173a 3068 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
emilmont 77:869cf507173a 3069 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
emilmont 77:869cf507173a 3070 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
emilmont 77:869cf507173a 3071
emilmont 77:869cf507173a 3072 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
emilmont 77:869cf507173a 3073 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
emilmont 77:869cf507173a 3074 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
emilmont 77:869cf507173a 3075 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
emilmont 77:869cf507173a 3076 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
emilmont 77:869cf507173a 3077 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
emilmont 77:869cf507173a 3078 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
emilmont 77:869cf507173a 3079 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
emilmont 77:869cf507173a 3080 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
emilmont 77:869cf507173a 3081 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
emilmont 77:869cf507173a 3082
emilmont 77:869cf507173a 3083 /******************* Bit definition for SPI_CR2 register ********************/
emilmont 77:869cf507173a 3084 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
emilmont 77:869cf507173a 3085 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
emilmont 77:869cf507173a 3086 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
emilmont 77:869cf507173a 3087 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
emilmont 77:869cf507173a 3088 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
emilmont 77:869cf507173a 3089 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
emilmont 77:869cf507173a 3090 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
emilmont 77:869cf507173a 3091
emilmont 77:869cf507173a 3092 /******************** Bit definition for SPI_SR register ********************/
emilmont 77:869cf507173a 3093 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
emilmont 77:869cf507173a 3094 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
emilmont 77:869cf507173a 3095 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
emilmont 77:869cf507173a 3096 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
emilmont 77:869cf507173a 3097 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
emilmont 77:869cf507173a 3098 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
emilmont 77:869cf507173a 3099 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
emilmont 77:869cf507173a 3100 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
emilmont 77:869cf507173a 3101 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
emilmont 77:869cf507173a 3102
emilmont 77:869cf507173a 3103 /******************** Bit definition for SPI_DR register ********************/
emilmont 77:869cf507173a 3104 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
emilmont 77:869cf507173a 3105
emilmont 77:869cf507173a 3106 /******************* Bit definition for SPI_CRCPR register ******************/
emilmont 77:869cf507173a 3107 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
emilmont 77:869cf507173a 3108
emilmont 77:869cf507173a 3109 /****************** Bit definition for SPI_RXCRCR register ******************/
emilmont 77:869cf507173a 3110 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
emilmont 77:869cf507173a 3111
emilmont 77:869cf507173a 3112 /****************** Bit definition for SPI_TXCRCR register ******************/
emilmont 77:869cf507173a 3113 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
emilmont 77:869cf507173a 3114
emilmont 77:869cf507173a 3115 /****************** Bit definition for SPI_I2SCFGR register *****************/
emilmont 77:869cf507173a 3116 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
emilmont 77:869cf507173a 3117
emilmont 77:869cf507173a 3118 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
emilmont 77:869cf507173a 3119 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
emilmont 77:869cf507173a 3120 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
emilmont 77:869cf507173a 3121
emilmont 77:869cf507173a 3122 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
emilmont 77:869cf507173a 3123
emilmont 77:869cf507173a 3124 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
emilmont 77:869cf507173a 3125 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
emilmont 77:869cf507173a 3126 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
emilmont 77:869cf507173a 3127
emilmont 77:869cf507173a 3128 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
emilmont 77:869cf507173a 3129
emilmont 77:869cf507173a 3130 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
emilmont 77:869cf507173a 3131 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
emilmont 77:869cf507173a 3132 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
emilmont 77:869cf507173a 3133
emilmont 77:869cf507173a 3134 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
emilmont 77:869cf507173a 3135 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
emilmont 77:869cf507173a 3136
emilmont 77:869cf507173a 3137 /****************** Bit definition for SPI_I2SPR register *******************/
emilmont 77:869cf507173a 3138 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
emilmont 77:869cf507173a 3139 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
emilmont 77:869cf507173a 3140 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
emilmont 77:869cf507173a 3141
emilmont 77:869cf507173a 3142 /******************************************************************************/
emilmont 77:869cf507173a 3143 /* */
emilmont 77:869cf507173a 3144 /* SYSCFG */
emilmont 77:869cf507173a 3145 /* */
emilmont 77:869cf507173a 3146 /******************************************************************************/
emilmont 77:869cf507173a 3147 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
emilmont 77:869cf507173a 3148 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
emilmont 77:869cf507173a 3149 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3150 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3151 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3152
emilmont 77:869cf507173a 3153 /****************** Bit definition for SYSCFG_PMC register ******************/
emilmont 77:869cf507173a 3154 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
emilmont 77:869cf507173a 3155
emilmont 77:869cf507173a 3156 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
emilmont 77:869cf507173a 3157 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
emilmont 77:869cf507173a 3158 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
emilmont 77:869cf507173a 3159 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
emilmont 77:869cf507173a 3160 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
emilmont 77:869cf507173a 3161 /**
emilmont 77:869cf507173a 3162 * @brief EXTI0 configuration
emilmont 77:869cf507173a 3163 */
emilmont 77:869cf507173a 3164 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
emilmont 77:869cf507173a 3165 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
emilmont 77:869cf507173a 3166 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
emilmont 77:869cf507173a 3167 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
emilmont 77:869cf507173a 3168 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
emilmont 77:869cf507173a 3169 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
emilmont 77:869cf507173a 3170
emilmont 77:869cf507173a 3171 /**
emilmont 77:869cf507173a 3172 * @brief EXTI1 configuration
emilmont 77:869cf507173a 3173 */
emilmont 77:869cf507173a 3174 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
emilmont 77:869cf507173a 3175 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
emilmont 77:869cf507173a 3176 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
emilmont 77:869cf507173a 3177 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
emilmont 77:869cf507173a 3178 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
emilmont 77:869cf507173a 3179 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
emilmont 77:869cf507173a 3180
emilmont 77:869cf507173a 3181 /**
emilmont 77:869cf507173a 3182 * @brief EXTI2 configuration
emilmont 77:869cf507173a 3183 */
emilmont 77:869cf507173a 3184 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
emilmont 77:869cf507173a 3185 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
emilmont 77:869cf507173a 3186 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
emilmont 77:869cf507173a 3187 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
emilmont 77:869cf507173a 3188 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
emilmont 77:869cf507173a 3189 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
emilmont 77:869cf507173a 3190
emilmont 77:869cf507173a 3191 /**
emilmont 77:869cf507173a 3192 * @brief EXTI3 configuration
emilmont 77:869cf507173a 3193 */
emilmont 77:869cf507173a 3194 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
emilmont 77:869cf507173a 3195 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
emilmont 77:869cf507173a 3196 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
emilmont 77:869cf507173a 3197 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
emilmont 77:869cf507173a 3198 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
emilmont 77:869cf507173a 3199 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
emilmont 77:869cf507173a 3200
emilmont 77:869cf507173a 3201 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
emilmont 77:869cf507173a 3202 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
emilmont 77:869cf507173a 3203 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
emilmont 77:869cf507173a 3204 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
emilmont 77:869cf507173a 3205 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
emilmont 77:869cf507173a 3206 /**
emilmont 77:869cf507173a 3207 * @brief EXTI4 configuration
emilmont 77:869cf507173a 3208 */
emilmont 77:869cf507173a 3209 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
emilmont 77:869cf507173a 3210 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
emilmont 77:869cf507173a 3211 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
emilmont 77:869cf507173a 3212 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
emilmont 77:869cf507173a 3213 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
emilmont 77:869cf507173a 3214 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
emilmont 77:869cf507173a 3215
emilmont 77:869cf507173a 3216 /**
emilmont 77:869cf507173a 3217 * @brief EXTI5 configuration
emilmont 77:869cf507173a 3218 */
emilmont 77:869cf507173a 3219 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
emilmont 77:869cf507173a 3220 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
emilmont 77:869cf507173a 3221 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
emilmont 77:869cf507173a 3222 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
emilmont 77:869cf507173a 3223 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
emilmont 77:869cf507173a 3224 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
emilmont 77:869cf507173a 3225
emilmont 77:869cf507173a 3226 /**
emilmont 77:869cf507173a 3227 * @brief EXTI6 configuration
emilmont 77:869cf507173a 3228 */
emilmont 77:869cf507173a 3229 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
emilmont 77:869cf507173a 3230 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
emilmont 77:869cf507173a 3231 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
emilmont 77:869cf507173a 3232 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
emilmont 77:869cf507173a 3233 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
emilmont 77:869cf507173a 3234 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
emilmont 77:869cf507173a 3235
emilmont 77:869cf507173a 3236 /**
emilmont 77:869cf507173a 3237 * @brief EXTI7 configuration
emilmont 77:869cf507173a 3238 */
emilmont 77:869cf507173a 3239 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
emilmont 77:869cf507173a 3240 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
emilmont 77:869cf507173a 3241 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
emilmont 77:869cf507173a 3242 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
emilmont 77:869cf507173a 3243 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
emilmont 77:869cf507173a 3244 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
emilmont 77:869cf507173a 3245
emilmont 77:869cf507173a 3246
emilmont 77:869cf507173a 3247 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
emilmont 77:869cf507173a 3248 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
emilmont 77:869cf507173a 3249 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
emilmont 77:869cf507173a 3250 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
emilmont 77:869cf507173a 3251 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
emilmont 77:869cf507173a 3252
emilmont 77:869cf507173a 3253 /**
emilmont 77:869cf507173a 3254 * @brief EXTI8 configuration
emilmont 77:869cf507173a 3255 */
emilmont 77:869cf507173a 3256 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
emilmont 77:869cf507173a 3257 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
emilmont 77:869cf507173a 3258 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
emilmont 77:869cf507173a 3259 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
emilmont 77:869cf507173a 3260 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
emilmont 77:869cf507173a 3261 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
emilmont 77:869cf507173a 3262
emilmont 77:869cf507173a 3263 /**
emilmont 77:869cf507173a 3264 * @brief EXTI9 configuration
emilmont 77:869cf507173a 3265 */
emilmont 77:869cf507173a 3266 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
emilmont 77:869cf507173a 3267 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
emilmont 77:869cf507173a 3268 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
emilmont 77:869cf507173a 3269 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
emilmont 77:869cf507173a 3270 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
emilmont 77:869cf507173a 3271 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
emilmont 77:869cf507173a 3272
emilmont 77:869cf507173a 3273 /**
emilmont 77:869cf507173a 3274 * @brief EXTI10 configuration
emilmont 77:869cf507173a 3275 */
emilmont 77:869cf507173a 3276 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
emilmont 77:869cf507173a 3277 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
emilmont 77:869cf507173a 3278 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
emilmont 77:869cf507173a 3279 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
emilmont 77:869cf507173a 3280 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
emilmont 77:869cf507173a 3281 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
emilmont 77:869cf507173a 3282
emilmont 77:869cf507173a 3283 /**
emilmont 77:869cf507173a 3284 * @brief EXTI11 configuration
emilmont 77:869cf507173a 3285 */
emilmont 77:869cf507173a 3286 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
emilmont 77:869cf507173a 3287 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
emilmont 77:869cf507173a 3288 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
emilmont 77:869cf507173a 3289 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
emilmont 77:869cf507173a 3290 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
emilmont 77:869cf507173a 3291 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
emilmont 77:869cf507173a 3292
emilmont 77:869cf507173a 3293 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
emilmont 77:869cf507173a 3294 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
emilmont 77:869cf507173a 3295 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
emilmont 77:869cf507173a 3296 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
emilmont 77:869cf507173a 3297 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
emilmont 77:869cf507173a 3298 /**
emilmont 77:869cf507173a 3299 * @brief EXTI12 configuration
emilmont 77:869cf507173a 3300 */
emilmont 77:869cf507173a 3301 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
emilmont 77:869cf507173a 3302 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
emilmont 77:869cf507173a 3303 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
emilmont 77:869cf507173a 3304 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
emilmont 77:869cf507173a 3305 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
emilmont 77:869cf507173a 3306 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
emilmont 77:869cf507173a 3307
emilmont 77:869cf507173a 3308 /**
emilmont 77:869cf507173a 3309 * @brief EXTI13 configuration
emilmont 77:869cf507173a 3310 */
emilmont 77:869cf507173a 3311 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
emilmont 77:869cf507173a 3312 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
emilmont 77:869cf507173a 3313 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
emilmont 77:869cf507173a 3314 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
emilmont 77:869cf507173a 3315 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
emilmont 77:869cf507173a 3316 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
emilmont 77:869cf507173a 3317
emilmont 77:869cf507173a 3318 /**
emilmont 77:869cf507173a 3319 * @brief EXTI14 configuration
emilmont 77:869cf507173a 3320 */
emilmont 77:869cf507173a 3321 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
emilmont 77:869cf507173a 3322 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
emilmont 77:869cf507173a 3323 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
emilmont 77:869cf507173a 3324 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
emilmont 77:869cf507173a 3325 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
emilmont 77:869cf507173a 3326 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
emilmont 77:869cf507173a 3327
emilmont 77:869cf507173a 3328 /**
emilmont 77:869cf507173a 3329 * @brief EXTI15 configuration
emilmont 77:869cf507173a 3330 */
emilmont 77:869cf507173a 3331 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
emilmont 77:869cf507173a 3332 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
emilmont 77:869cf507173a 3333 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
emilmont 77:869cf507173a 3334 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
emilmont 77:869cf507173a 3335 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
emilmont 77:869cf507173a 3336 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
emilmont 77:869cf507173a 3337
emilmont 77:869cf507173a 3338 /****************** Bit definition for SYSCFG_CMPCR register ****************/
emilmont 77:869cf507173a 3339 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
emilmont 77:869cf507173a 3340 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
emilmont 77:869cf507173a 3341
emilmont 77:869cf507173a 3342 /******************************************************************************/
emilmont 77:869cf507173a 3343 /* */
emilmont 77:869cf507173a 3344 /* TIM */
emilmont 77:869cf507173a 3345 /* */
emilmont 77:869cf507173a 3346 /******************************************************************************/
emilmont 77:869cf507173a 3347 /******************* Bit definition for TIM_CR1 register ********************/
emilmont 77:869cf507173a 3348 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
emilmont 77:869cf507173a 3349 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
emilmont 77:869cf507173a 3350 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
emilmont 77:869cf507173a 3351 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
emilmont 77:869cf507173a 3352 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
emilmont 77:869cf507173a 3353
emilmont 77:869cf507173a 3354 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
emilmont 77:869cf507173a 3355 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
emilmont 77:869cf507173a 3356 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
emilmont 77:869cf507173a 3357
emilmont 77:869cf507173a 3358 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
emilmont 77:869cf507173a 3359
emilmont 77:869cf507173a 3360 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
emilmont 77:869cf507173a 3361 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 3362 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 3363
emilmont 77:869cf507173a 3364 /******************* Bit definition for TIM_CR2 register ********************/
emilmont 77:869cf507173a 3365 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
emilmont 77:869cf507173a 3366 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
emilmont 77:869cf507173a 3367 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
emilmont 77:869cf507173a 3368
emilmont 77:869cf507173a 3369 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
emilmont 77:869cf507173a 3370 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 3371 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 3372 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 3373
emilmont 77:869cf507173a 3374 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
emilmont 77:869cf507173a 3375 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
emilmont 77:869cf507173a 3376 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
emilmont 77:869cf507173a 3377 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
emilmont 77:869cf507173a 3378 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
emilmont 77:869cf507173a 3379 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
emilmont 77:869cf507173a 3380 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
emilmont 77:869cf507173a 3381 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
emilmont 77:869cf507173a 3382
emilmont 77:869cf507173a 3383 /******************* Bit definition for TIM_SMCR register *******************/
emilmont 77:869cf507173a 3384 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
emilmont 77:869cf507173a 3385 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 3386 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 3387 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
emilmont 77:869cf507173a 3388
emilmont 77:869cf507173a 3389 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
emilmont 77:869cf507173a 3390 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 3391 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 3392 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 3393
emilmont 77:869cf507173a 3394 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
emilmont 77:869cf507173a 3395
emilmont 77:869cf507173a 3396 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
emilmont 77:869cf507173a 3397 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 3398 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 3399 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
emilmont 77:869cf507173a 3400 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
emilmont 77:869cf507173a 3401
emilmont 77:869cf507173a 3402 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
emilmont 77:869cf507173a 3403 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 3404 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 3405
emilmont 77:869cf507173a 3406 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
emilmont 77:869cf507173a 3407 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
emilmont 77:869cf507173a 3408
emilmont 77:869cf507173a 3409 /******************* Bit definition for TIM_DIER register *******************/
emilmont 77:869cf507173a 3410 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
emilmont 77:869cf507173a 3411 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
emilmont 77:869cf507173a 3412 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
emilmont 77:869cf507173a 3413 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
emilmont 77:869cf507173a 3414 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
emilmont 77:869cf507173a 3415 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
emilmont 77:869cf507173a 3416 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
emilmont 77:869cf507173a 3417 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
emilmont 77:869cf507173a 3418 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
emilmont 77:869cf507173a 3419 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
emilmont 77:869cf507173a 3420 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
emilmont 77:869cf507173a 3421 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
emilmont 77:869cf507173a 3422 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
emilmont 77:869cf507173a 3423 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
emilmont 77:869cf507173a 3424 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
emilmont 77:869cf507173a 3425
emilmont 77:869cf507173a 3426 /******************** Bit definition for TIM_SR register ********************/
emilmont 77:869cf507173a 3427 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
emilmont 77:869cf507173a 3428 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
emilmont 77:869cf507173a 3429 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
emilmont 77:869cf507173a 3430 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
emilmont 77:869cf507173a 3431 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
emilmont 77:869cf507173a 3432 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
emilmont 77:869cf507173a 3433 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
emilmont 77:869cf507173a 3434 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
emilmont 77:869cf507173a 3435 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
emilmont 77:869cf507173a 3436 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
emilmont 77:869cf507173a 3437 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
emilmont 77:869cf507173a 3438 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
emilmont 77:869cf507173a 3439
emilmont 77:869cf507173a 3440 /******************* Bit definition for TIM_EGR register ********************/
emilmont 77:869cf507173a 3441 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
emilmont 77:869cf507173a 3442 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
emilmont 77:869cf507173a 3443 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
emilmont 77:869cf507173a 3444 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
emilmont 77:869cf507173a 3445 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
emilmont 77:869cf507173a 3446 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
emilmont 77:869cf507173a 3447 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
emilmont 77:869cf507173a 3448 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
emilmont 77:869cf507173a 3449
emilmont 77:869cf507173a 3450 /****************** Bit definition for TIM_CCMR1 register *******************/
emilmont 77:869cf507173a 3451 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
emilmont 77:869cf507173a 3452 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 3453 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 3454
emilmont 77:869cf507173a 3455 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
emilmont 77:869cf507173a 3456 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
emilmont 77:869cf507173a 3457
emilmont 77:869cf507173a 3458 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
emilmont 77:869cf507173a 3459 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 3460 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 3461 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 3462
emilmont 77:869cf507173a 3463 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
emilmont 77:869cf507173a 3464
emilmont 77:869cf507173a 3465 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
emilmont 77:869cf507173a 3466 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 3467 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 3468
emilmont 77:869cf507173a 3469 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
emilmont 77:869cf507173a 3470 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
emilmont 77:869cf507173a 3471
emilmont 77:869cf507173a 3472 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
emilmont 77:869cf507173a 3473 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 3474 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 3475 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
emilmont 77:869cf507173a 3476
emilmont 77:869cf507173a 3477 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
emilmont 77:869cf507173a 3478
emilmont 77:869cf507173a 3479 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 3480
emilmont 77:869cf507173a 3481 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
emilmont 77:869cf507173a 3482 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
emilmont 77:869cf507173a 3483 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
emilmont 77:869cf507173a 3484
emilmont 77:869cf507173a 3485 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
emilmont 77:869cf507173a 3486 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 3487 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 3488 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 3489 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
emilmont 77:869cf507173a 3490
emilmont 77:869cf507173a 3491 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
emilmont 77:869cf507173a 3492 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
emilmont 77:869cf507173a 3493 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
emilmont 77:869cf507173a 3494
emilmont 77:869cf507173a 3495 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
emilmont 77:869cf507173a 3496 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 3497 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 3498 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
emilmont 77:869cf507173a 3499 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
emilmont 77:869cf507173a 3500
emilmont 77:869cf507173a 3501 /****************** Bit definition for TIM_CCMR2 register *******************/
emilmont 77:869cf507173a 3502 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
emilmont 77:869cf507173a 3503 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 3504 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 3505
emilmont 77:869cf507173a 3506 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
emilmont 77:869cf507173a 3507 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
emilmont 77:869cf507173a 3508
emilmont 77:869cf507173a 3509 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
emilmont 77:869cf507173a 3510 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 3511 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 3512 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 3513
emilmont 77:869cf507173a 3514 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
emilmont 77:869cf507173a 3515
emilmont 77:869cf507173a 3516 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
emilmont 77:869cf507173a 3517 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 3518 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 3519
emilmont 77:869cf507173a 3520 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
emilmont 77:869cf507173a 3521 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
emilmont 77:869cf507173a 3522
emilmont 77:869cf507173a 3523 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
emilmont 77:869cf507173a 3524 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 3525 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 3526 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
emilmont 77:869cf507173a 3527
emilmont 77:869cf507173a 3528 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
emilmont 77:869cf507173a 3529
emilmont 77:869cf507173a 3530 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 3531
emilmont 77:869cf507173a 3532 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
emilmont 77:869cf507173a 3533 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
emilmont 77:869cf507173a 3534 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
emilmont 77:869cf507173a 3535
emilmont 77:869cf507173a 3536 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
emilmont 77:869cf507173a 3537 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 3538 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 3539 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 3540 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
emilmont 77:869cf507173a 3541
emilmont 77:869cf507173a 3542 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
emilmont 77:869cf507173a 3543 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
emilmont 77:869cf507173a 3544 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
emilmont 77:869cf507173a 3545
emilmont 77:869cf507173a 3546 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
emilmont 77:869cf507173a 3547 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 3548 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 3549 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
emilmont 77:869cf507173a 3550 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
emilmont 77:869cf507173a 3551
emilmont 77:869cf507173a 3552 /******************* Bit definition for TIM_CCER register *******************/
emilmont 77:869cf507173a 3553 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
emilmont 77:869cf507173a 3554 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
emilmont 77:869cf507173a 3555 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
emilmont 77:869cf507173a 3556 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
emilmont 77:869cf507173a 3557 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
emilmont 77:869cf507173a 3558 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
emilmont 77:869cf507173a 3559 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
emilmont 77:869cf507173a 3560 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
emilmont 77:869cf507173a 3561 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
emilmont 77:869cf507173a 3562 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
emilmont 77:869cf507173a 3563 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
emilmont 77:869cf507173a 3564 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
emilmont 77:869cf507173a 3565 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
emilmont 77:869cf507173a 3566 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
emilmont 77:869cf507173a 3567 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
emilmont 77:869cf507173a 3568
emilmont 77:869cf507173a 3569 /******************* Bit definition for TIM_CNT register ********************/
emilmont 77:869cf507173a 3570 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
emilmont 77:869cf507173a 3571
emilmont 77:869cf507173a 3572 /******************* Bit definition for TIM_PSC register ********************/
emilmont 77:869cf507173a 3573 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
emilmont 77:869cf507173a 3574
emilmont 77:869cf507173a 3575 /******************* Bit definition for TIM_ARR register ********************/
emilmont 77:869cf507173a 3576 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
emilmont 77:869cf507173a 3577
emilmont 77:869cf507173a 3578 /******************* Bit definition for TIM_RCR register ********************/
emilmont 77:869cf507173a 3579 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
emilmont 77:869cf507173a 3580
emilmont 77:869cf507173a 3581 /******************* Bit definition for TIM_CCR1 register *******************/
emilmont 77:869cf507173a 3582 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
emilmont 77:869cf507173a 3583
emilmont 77:869cf507173a 3584 /******************* Bit definition for TIM_CCR2 register *******************/
emilmont 77:869cf507173a 3585 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
emilmont 77:869cf507173a 3586
emilmont 77:869cf507173a 3587 /******************* Bit definition for TIM_CCR3 register *******************/
emilmont 77:869cf507173a 3588 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
emilmont 77:869cf507173a 3589
emilmont 77:869cf507173a 3590 /******************* Bit definition for TIM_CCR4 register *******************/
emilmont 77:869cf507173a 3591 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
emilmont 77:869cf507173a 3592
emilmont 77:869cf507173a 3593 /******************* Bit definition for TIM_BDTR register *******************/
emilmont 77:869cf507173a 3594 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
emilmont 77:869cf507173a 3595 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 3596 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 3597 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
emilmont 77:869cf507173a 3598 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
emilmont 77:869cf507173a 3599 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
emilmont 77:869cf507173a 3600 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
emilmont 77:869cf507173a 3601 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
emilmont 77:869cf507173a 3602 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
emilmont 77:869cf507173a 3603
emilmont 77:869cf507173a 3604 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
emilmont 77:869cf507173a 3605 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 3606 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 3607
emilmont 77:869cf507173a 3608 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
emilmont 77:869cf507173a 3609 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
emilmont 77:869cf507173a 3610 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
emilmont 77:869cf507173a 3611 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
emilmont 77:869cf507173a 3612 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
emilmont 77:869cf507173a 3613 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
emilmont 77:869cf507173a 3614
emilmont 77:869cf507173a 3615 /******************* Bit definition for TIM_DCR register ********************/
emilmont 77:869cf507173a 3616 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
emilmont 77:869cf507173a 3617 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 3618 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 3619 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
emilmont 77:869cf507173a 3620 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
emilmont 77:869cf507173a 3621 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
emilmont 77:869cf507173a 3622
emilmont 77:869cf507173a 3623 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
emilmont 77:869cf507173a 3624 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 3625 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 3626 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
emilmont 77:869cf507173a 3627 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
emilmont 77:869cf507173a 3628 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
emilmont 77:869cf507173a 3629
emilmont 77:869cf507173a 3630 /******************* Bit definition for TIM_DMAR register *******************/
emilmont 77:869cf507173a 3631 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
emilmont 77:869cf507173a 3632
emilmont 77:869cf507173a 3633 /******************* Bit definition for TIM_OR register *********************/
emilmont 77:869cf507173a 3634 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
emilmont 77:869cf507173a 3635 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
emilmont 77:869cf507173a 3636 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
emilmont 77:869cf507173a 3637 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
emilmont 77:869cf507173a 3638 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
emilmont 77:869cf507173a 3639 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
emilmont 77:869cf507173a 3640
emilmont 77:869cf507173a 3641
emilmont 77:869cf507173a 3642 /******************************************************************************/
emilmont 77:869cf507173a 3643 /* */
emilmont 77:869cf507173a 3644 /* Universal Synchronous Asynchronous Receiver Transmitter */
emilmont 77:869cf507173a 3645 /* */
emilmont 77:869cf507173a 3646 /******************************************************************************/
emilmont 77:869cf507173a 3647 /******************* Bit definition for USART_SR register *******************/
emilmont 77:869cf507173a 3648 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
emilmont 77:869cf507173a 3649 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
emilmont 77:869cf507173a 3650 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
emilmont 77:869cf507173a 3651 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
emilmont 77:869cf507173a 3652 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
emilmont 77:869cf507173a 3653 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
emilmont 77:869cf507173a 3654 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
emilmont 77:869cf507173a 3655 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
emilmont 77:869cf507173a 3656 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
emilmont 77:869cf507173a 3657 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
emilmont 77:869cf507173a 3658
emilmont 77:869cf507173a 3659 /******************* Bit definition for USART_DR register *******************/
emilmont 77:869cf507173a 3660 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
emilmont 77:869cf507173a 3661
emilmont 77:869cf507173a 3662 /****************** Bit definition for USART_BRR register *******************/
emilmont 77:869cf507173a 3663 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
emilmont 77:869cf507173a 3664 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
emilmont 77:869cf507173a 3665
emilmont 77:869cf507173a 3666 /****************** Bit definition for USART_CR1 register *******************/
emilmont 77:869cf507173a 3667 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
emilmont 77:869cf507173a 3668 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
emilmont 77:869cf507173a 3669 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
emilmont 77:869cf507173a 3670 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
emilmont 77:869cf507173a 3671 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
emilmont 77:869cf507173a 3672 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
emilmont 77:869cf507173a 3673 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
emilmont 77:869cf507173a 3674 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
emilmont 77:869cf507173a 3675 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
emilmont 77:869cf507173a 3676 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
emilmont 77:869cf507173a 3677 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
emilmont 77:869cf507173a 3678 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
emilmont 77:869cf507173a 3679 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
emilmont 77:869cf507173a 3680 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
emilmont 77:869cf507173a 3681 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
emilmont 77:869cf507173a 3682
emilmont 77:869cf507173a 3683 /****************** Bit definition for USART_CR2 register *******************/
emilmont 77:869cf507173a 3684 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
emilmont 77:869cf507173a 3685 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
emilmont 77:869cf507173a 3686 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
emilmont 77:869cf507173a 3687 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
emilmont 77:869cf507173a 3688 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
emilmont 77:869cf507173a 3689 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
emilmont 77:869cf507173a 3690 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
emilmont 77:869cf507173a 3691
emilmont 77:869cf507173a 3692 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
emilmont 77:869cf507173a 3693 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 3694 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 3695
emilmont 77:869cf507173a 3696 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
emilmont 77:869cf507173a 3697
emilmont 77:869cf507173a 3698 /****************** Bit definition for USART_CR3 register *******************/
emilmont 77:869cf507173a 3699 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
emilmont 77:869cf507173a 3700 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
emilmont 77:869cf507173a 3701 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
emilmont 77:869cf507173a 3702 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
emilmont 77:869cf507173a 3703 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
emilmont 77:869cf507173a 3704 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
emilmont 77:869cf507173a 3705 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
emilmont 77:869cf507173a 3706 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
emilmont 77:869cf507173a 3707 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
emilmont 77:869cf507173a 3708 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
emilmont 77:869cf507173a 3709 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
emilmont 77:869cf507173a 3710 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
emilmont 77:869cf507173a 3711
emilmont 77:869cf507173a 3712 /****************** Bit definition for USART_GTPR register ******************/
emilmont 77:869cf507173a 3713 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
emilmont 77:869cf507173a 3714 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 3715 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 3716 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
emilmont 77:869cf507173a 3717 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
emilmont 77:869cf507173a 3718 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
emilmont 77:869cf507173a 3719 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
emilmont 77:869cf507173a 3720 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
emilmont 77:869cf507173a 3721 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
emilmont 77:869cf507173a 3722
emilmont 77:869cf507173a 3723 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
emilmont 77:869cf507173a 3724
emilmont 77:869cf507173a 3725 /******************************************************************************/
emilmont 77:869cf507173a 3726 /* */
emilmont 77:869cf507173a 3727 /* Window WATCHDOG */
emilmont 77:869cf507173a 3728 /* */
emilmont 77:869cf507173a 3729 /******************************************************************************/
emilmont 77:869cf507173a 3730 /******************* Bit definition for WWDG_CR register ********************/
emilmont 77:869cf507173a 3731 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
emilmont 77:869cf507173a 3732 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
emilmont 77:869cf507173a 3733 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
emilmont 77:869cf507173a 3734 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
emilmont 77:869cf507173a 3735 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
emilmont 77:869cf507173a 3736 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
emilmont 77:869cf507173a 3737 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
emilmont 77:869cf507173a 3738 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
emilmont 77:869cf507173a 3739
emilmont 77:869cf507173a 3740 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
emilmont 77:869cf507173a 3741
emilmont 77:869cf507173a 3742 /******************* Bit definition for WWDG_CFR register *******************/
emilmont 77:869cf507173a 3743 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
emilmont 77:869cf507173a 3744 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 3745 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 3746 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
emilmont 77:869cf507173a 3747 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
emilmont 77:869cf507173a 3748 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
emilmont 77:869cf507173a 3749 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
emilmont 77:869cf507173a 3750 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
emilmont 77:869cf507173a 3751
emilmont 77:869cf507173a 3752 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
emilmont 77:869cf507173a 3753 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
emilmont 77:869cf507173a 3754 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
emilmont 77:869cf507173a 3755
emilmont 77:869cf507173a 3756 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
emilmont 77:869cf507173a 3757
emilmont 77:869cf507173a 3758 /******************* Bit definition for WWDG_SR register ********************/
emilmont 77:869cf507173a 3759 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
emilmont 77:869cf507173a 3760
emilmont 77:869cf507173a 3761
emilmont 77:869cf507173a 3762 /******************************************************************************/
emilmont 77:869cf507173a 3763 /* */
emilmont 77:869cf507173a 3764 /* DBG */
emilmont 77:869cf507173a 3765 /* */
emilmont 77:869cf507173a 3766 /******************************************************************************/
emilmont 77:869cf507173a 3767 /******************** Bit definition for DBGMCU_IDCODE register *************/
emilmont 77:869cf507173a 3768 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
emilmont 77:869cf507173a 3769 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
emilmont 77:869cf507173a 3770
emilmont 77:869cf507173a 3771 /******************** Bit definition for DBGMCU_CR register *****************/
emilmont 77:869cf507173a 3772 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3773 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3774 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3775 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3776
emilmont 77:869cf507173a 3777 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
emilmont 77:869cf507173a 3778 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
emilmont 77:869cf507173a 3779 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
emilmont 77:869cf507173a 3780
emilmont 77:869cf507173a 3781 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
emilmont 77:869cf507173a 3782 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3783 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3784 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3785 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3786 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3787 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3788 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3789 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3790 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3791 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3792 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3793 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3794 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
emilmont 77:869cf507173a 3795 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3796 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
emilmont 77:869cf507173a 3797 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
emilmont 77:869cf507173a 3798 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
emilmont 77:869cf507173a 3799 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
emilmont 77:869cf507173a 3800 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
emilmont 77:869cf507173a 3801
emilmont 77:869cf507173a 3802 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
emilmont 77:869cf507173a 3803 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3804 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3805 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3806 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
emilmont 77:869cf507173a 3807 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
emilmont 77:869cf507173a 3808
emilmont 77:869cf507173a 3809 /******************************************************************************/
emilmont 77:869cf507173a 3810 /* */
emilmont 77:869cf507173a 3811 /* USB_OTG */
emilmont 77:869cf507173a 3812 /* */
emilmont 77:869cf507173a 3813 /******************************************************************************/
emilmont 77:869cf507173a 3814 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
emilmont 77:869cf507173a 3815 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
emilmont 77:869cf507173a 3816 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
emilmont 77:869cf507173a 3817 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
emilmont 77:869cf507173a 3818 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
emilmont 77:869cf507173a 3819 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
emilmont 77:869cf507173a 3820 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
emilmont 77:869cf507173a 3821 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
emilmont 77:869cf507173a 3822 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
emilmont 77:869cf507173a 3823 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
emilmont 77:869cf507173a 3824 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
emilmont 77:869cf507173a 3825
emilmont 77:869cf507173a 3826 /******************** Bit definition forUSB_OTG_HCFG register ********************/
emilmont 77:869cf507173a 3827
emilmont 77:869cf507173a 3828 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
emilmont 77:869cf507173a 3829 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 3830 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 3831 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
emilmont 77:869cf507173a 3832
emilmont 77:869cf507173a 3833 /******************** Bit definition forUSB_OTG_DCFG register ********************/
emilmont 77:869cf507173a 3834
emilmont 77:869cf507173a 3835 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
emilmont 77:869cf507173a 3836 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 3837 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 3838 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
emilmont 77:869cf507173a 3839
emilmont 77:869cf507173a 3840 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
emilmont 77:869cf507173a 3841 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
emilmont 77:869cf507173a 3842 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
emilmont 77:869cf507173a 3843 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
emilmont 77:869cf507173a 3844 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
emilmont 77:869cf507173a 3845 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
emilmont 77:869cf507173a 3846 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
emilmont 77:869cf507173a 3847 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
emilmont 77:869cf507173a 3848
emilmont 77:869cf507173a 3849 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
emilmont 77:869cf507173a 3850 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
emilmont 77:869cf507173a 3851 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
emilmont 77:869cf507173a 3852
emilmont 77:869cf507173a 3853 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
emilmont 77:869cf507173a 3854 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
emilmont 77:869cf507173a 3855 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
emilmont 77:869cf507173a 3856
emilmont 77:869cf507173a 3857 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
emilmont 77:869cf507173a 3858 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
emilmont 77:869cf507173a 3859 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
emilmont 77:869cf507173a 3860 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
emilmont 77:869cf507173a 3861
emilmont 77:869cf507173a 3862 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
emilmont 77:869cf507173a 3863 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
emilmont 77:869cf507173a 3864 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
emilmont 77:869cf507173a 3865 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
emilmont 77:869cf507173a 3866 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
emilmont 77:869cf507173a 3867 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
emilmont 77:869cf507173a 3868 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
emilmont 77:869cf507173a 3869
emilmont 77:869cf507173a 3870 /******************** Bit definition forUSB_OTG_DCTL register ********************/
emilmont 77:869cf507173a 3871 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
emilmont 77:869cf507173a 3872 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
emilmont 77:869cf507173a 3873 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
emilmont 77:869cf507173a 3874 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
emilmont 77:869cf507173a 3875
emilmont 77:869cf507173a 3876 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
emilmont 77:869cf507173a 3877 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
emilmont 77:869cf507173a 3878 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
emilmont 77:869cf507173a 3879 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
emilmont 77:869cf507173a 3880 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
emilmont 77:869cf507173a 3881 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
emilmont 77:869cf507173a 3882 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
emilmont 77:869cf507173a 3883 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
emilmont 77:869cf507173a 3884 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
emilmont 77:869cf507173a 3885
emilmont 77:869cf507173a 3886 /******************** Bit definition forUSB_OTG_HFIR register ********************/
emilmont 77:869cf507173a 3887 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
emilmont 77:869cf507173a 3888
emilmont 77:869cf507173a 3889 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
emilmont 77:869cf507173a 3890 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
emilmont 77:869cf507173a 3891 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
emilmont 77:869cf507173a 3892
emilmont 77:869cf507173a 3893 /******************** Bit definition forUSB_OTG_DSTS register ********************/
emilmont 77:869cf507173a 3894 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
emilmont 77:869cf507173a 3895
emilmont 77:869cf507173a 3896 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
emilmont 77:869cf507173a 3897 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
emilmont 77:869cf507173a 3898 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
emilmont 77:869cf507173a 3899 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
emilmont 77:869cf507173a 3900 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
emilmont 77:869cf507173a 3901
emilmont 77:869cf507173a 3902 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
emilmont 77:869cf507173a 3903 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
emilmont 77:869cf507173a 3904
emilmont 77:869cf507173a 3905 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
emilmont 77:869cf507173a 3906 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
emilmont 77:869cf507173a 3907 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
emilmont 77:869cf507173a 3908 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
emilmont 77:869cf507173a 3909 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
emilmont 77:869cf507173a 3910 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
emilmont 77:869cf507173a 3911 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
emilmont 77:869cf507173a 3912 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
emilmont 77:869cf507173a 3913
emilmont 77:869cf507173a 3914 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
emilmont 77:869cf507173a 3915
emilmont 77:869cf507173a 3916 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
emilmont 77:869cf507173a 3917 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 3918 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 3919 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 3920 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
emilmont 77:869cf507173a 3921 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
emilmont 77:869cf507173a 3922 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
emilmont 77:869cf507173a 3923
emilmont 77:869cf507173a 3924 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
emilmont 77:869cf507173a 3925 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
emilmont 77:869cf507173a 3926 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
emilmont 77:869cf507173a 3927 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
emilmont 77:869cf507173a 3928 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
emilmont 77:869cf507173a 3929 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
emilmont 77:869cf507173a 3930 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
emilmont 77:869cf507173a 3931 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
emilmont 77:869cf507173a 3932 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
emilmont 77:869cf507173a 3933 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
emilmont 77:869cf507173a 3934 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
emilmont 77:869cf507173a 3935 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
emilmont 77:869cf507173a 3936 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
emilmont 77:869cf507173a 3937 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
emilmont 77:869cf507173a 3938 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
emilmont 77:869cf507173a 3939 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
emilmont 77:869cf507173a 3940 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
emilmont 77:869cf507173a 3941 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
emilmont 77:869cf507173a 3942
emilmont 77:869cf507173a 3943 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
emilmont 77:869cf507173a 3944 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
emilmont 77:869cf507173a 3945 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
emilmont 77:869cf507173a 3946 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
emilmont 77:869cf507173a 3947 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
emilmont 77:869cf507173a 3948 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
emilmont 77:869cf507173a 3949
emilmont 77:869cf507173a 3950 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
emilmont 77:869cf507173a 3951 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
emilmont 77:869cf507173a 3952 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
emilmont 77:869cf507173a 3953 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
emilmont 77:869cf507173a 3954 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
emilmont 77:869cf507173a 3955 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
emilmont 77:869cf507173a 3956 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
emilmont 77:869cf507173a 3957 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
emilmont 77:869cf507173a 3958
emilmont 77:869cf507173a 3959 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
emilmont 77:869cf507173a 3960 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
emilmont 77:869cf507173a 3961 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
emilmont 77:869cf507173a 3962 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
emilmont 77:869cf507173a 3963 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
emilmont 77:869cf507173a 3964 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
emilmont 77:869cf507173a 3965 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
emilmont 77:869cf507173a 3966 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
emilmont 77:869cf507173a 3967 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
emilmont 77:869cf507173a 3968
emilmont 77:869cf507173a 3969 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
emilmont 77:869cf507173a 3970 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
emilmont 77:869cf507173a 3971
emilmont 77:869cf507173a 3972 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
emilmont 77:869cf507173a 3973 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
emilmont 77:869cf507173a 3974 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
emilmont 77:869cf507173a 3975 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
emilmont 77:869cf507173a 3976 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
emilmont 77:869cf507173a 3977 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
emilmont 77:869cf507173a 3978 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
emilmont 77:869cf507173a 3979 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
emilmont 77:869cf507173a 3980 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
emilmont 77:869cf507173a 3981
emilmont 77:869cf507173a 3982 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
emilmont 77:869cf507173a 3983 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
emilmont 77:869cf507173a 3984 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
emilmont 77:869cf507173a 3985 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
emilmont 77:869cf507173a 3986 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
emilmont 77:869cf507173a 3987 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
emilmont 77:869cf507173a 3988 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
emilmont 77:869cf507173a 3989 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
emilmont 77:869cf507173a 3990 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
emilmont 77:869cf507173a 3991
emilmont 77:869cf507173a 3992 /******************** Bit definition forUSB_OTG_HAINT register ********************/
emilmont 77:869cf507173a 3993 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
emilmont 77:869cf507173a 3994
emilmont 77:869cf507173a 3995 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
emilmont 77:869cf507173a 3996 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
emilmont 77:869cf507173a 3997 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
emilmont 77:869cf507173a 3998 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
emilmont 77:869cf507173a 3999 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
emilmont 77:869cf507173a 4000 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
emilmont 77:869cf507173a 4001 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
emilmont 77:869cf507173a 4002 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
emilmont 77:869cf507173a 4003
emilmont 77:869cf507173a 4004 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
emilmont 77:869cf507173a 4005 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
emilmont 77:869cf507173a 4006 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
emilmont 77:869cf507173a 4007 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
emilmont 77:869cf507173a 4008 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
emilmont 77:869cf507173a 4009 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
emilmont 77:869cf507173a 4010 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
emilmont 77:869cf507173a 4011 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
emilmont 77:869cf507173a 4012 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
emilmont 77:869cf507173a 4013 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
emilmont 77:869cf507173a 4014 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
emilmont 77:869cf507173a 4015 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
emilmont 77:869cf507173a 4016 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
emilmont 77:869cf507173a 4017 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
emilmont 77:869cf507173a 4018 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
emilmont 77:869cf507173a 4019 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
emilmont 77:869cf507173a 4020 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
emilmont 77:869cf507173a 4021 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
emilmont 77:869cf507173a 4022 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
emilmont 77:869cf507173a 4023 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
emilmont 77:869cf507173a 4024 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
emilmont 77:869cf507173a 4025 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
emilmont 77:869cf507173a 4026 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
emilmont 77:869cf507173a 4027 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
emilmont 77:869cf507173a 4028 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
emilmont 77:869cf507173a 4029 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
emilmont 77:869cf507173a 4030 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
emilmont 77:869cf507173a 4031
emilmont 77:869cf507173a 4032 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
emilmont 77:869cf507173a 4033 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
emilmont 77:869cf507173a 4034 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
emilmont 77:869cf507173a 4035 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
emilmont 77:869cf507173a 4036 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
emilmont 77:869cf507173a 4037 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
emilmont 77:869cf507173a 4038 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
emilmont 77:869cf507173a 4039 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
emilmont 77:869cf507173a 4040 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
emilmont 77:869cf507173a 4041 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
emilmont 77:869cf507173a 4042 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
emilmont 77:869cf507173a 4043 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
emilmont 77:869cf507173a 4044 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
emilmont 77:869cf507173a 4045 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
emilmont 77:869cf507173a 4046 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
emilmont 77:869cf507173a 4047 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
emilmont 77:869cf507173a 4048 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
emilmont 77:869cf507173a 4049 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
emilmont 77:869cf507173a 4050 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
emilmont 77:869cf507173a 4051 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
emilmont 77:869cf507173a 4052 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
emilmont 77:869cf507173a 4053 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
emilmont 77:869cf507173a 4054 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
emilmont 77:869cf507173a 4055 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
emilmont 77:869cf507173a 4056 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
emilmont 77:869cf507173a 4057 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
emilmont 77:869cf507173a 4058 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
emilmont 77:869cf507173a 4059
emilmont 77:869cf507173a 4060 /******************** Bit definition forUSB_OTG_DAINT register ********************/
emilmont 77:869cf507173a 4061 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
emilmont 77:869cf507173a 4062 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
emilmont 77:869cf507173a 4063
emilmont 77:869cf507173a 4064 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
emilmont 77:869cf507173a 4065 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
emilmont 77:869cf507173a 4066
emilmont 77:869cf507173a 4067 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
emilmont 77:869cf507173a 4068 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
emilmont 77:869cf507173a 4069 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
emilmont 77:869cf507173a 4070 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
emilmont 77:869cf507173a 4071 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
emilmont 77:869cf507173a 4072
emilmont 77:869cf507173a 4073 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
emilmont 77:869cf507173a 4074 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
emilmont 77:869cf507173a 4075 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
emilmont 77:869cf507173a 4076
emilmont 77:869cf507173a 4077 /******************** Bit definition for OTG register ********************/
emilmont 77:869cf507173a 4078
emilmont 77:869cf507173a 4079 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
emilmont 77:869cf507173a 4080 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 4081 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 4082 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 4083 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 4084 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
emilmont 77:869cf507173a 4085
emilmont 77:869cf507173a 4086 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
emilmont 77:869cf507173a 4087 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
emilmont 77:869cf507173a 4088 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
emilmont 77:869cf507173a 4089
emilmont 77:869cf507173a 4090 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
emilmont 77:869cf507173a 4091 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
emilmont 77:869cf507173a 4092 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
emilmont 77:869cf507173a 4093 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
emilmont 77:869cf507173a 4094 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
emilmont 77:869cf507173a 4095
emilmont 77:869cf507173a 4096 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
emilmont 77:869cf507173a 4097 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 4098 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 4099 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 4100 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 4101
emilmont 77:869cf507173a 4102 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
emilmont 77:869cf507173a 4103 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
emilmont 77:869cf507173a 4104 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
emilmont 77:869cf507173a 4105 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
emilmont 77:869cf507173a 4106 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
emilmont 77:869cf507173a 4107
emilmont 77:869cf507173a 4108 /******************** Bit definition for OTG register ********************/
emilmont 77:869cf507173a 4109
emilmont 77:869cf507173a 4110 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
emilmont 77:869cf507173a 4111 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 4112 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 4113 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 4114 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 4115 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
emilmont 77:869cf507173a 4116
emilmont 77:869cf507173a 4117 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
emilmont 77:869cf507173a 4118 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
emilmont 77:869cf507173a 4119 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
emilmont 77:869cf507173a 4120
emilmont 77:869cf507173a 4121 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
emilmont 77:869cf507173a 4122 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
emilmont 77:869cf507173a 4123 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
emilmont 77:869cf507173a 4124 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
emilmont 77:869cf507173a 4125 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
emilmont 77:869cf507173a 4126
emilmont 77:869cf507173a 4127 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
emilmont 77:869cf507173a 4128 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 4129 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 4130 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 4131 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 4132
emilmont 77:869cf507173a 4133 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
emilmont 77:869cf507173a 4134 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
emilmont 77:869cf507173a 4135 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
emilmont 77:869cf507173a 4136 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
emilmont 77:869cf507173a 4137 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
emilmont 77:869cf507173a 4138
emilmont 77:869cf507173a 4139 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
emilmont 77:869cf507173a 4140 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
emilmont 77:869cf507173a 4141
emilmont 77:869cf507173a 4142 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
emilmont 77:869cf507173a 4143 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
emilmont 77:869cf507173a 4144
emilmont 77:869cf507173a 4145 /******************** Bit definition for OTG register ********************/
emilmont 77:869cf507173a 4146 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
emilmont 77:869cf507173a 4147 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
emilmont 77:869cf507173a 4148 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
emilmont 77:869cf507173a 4149 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
emilmont 77:869cf507173a 4150
emilmont 77:869cf507173a 4151 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
emilmont 77:869cf507173a 4152 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
emilmont 77:869cf507173a 4153
emilmont 77:869cf507173a 4154 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
emilmont 77:869cf507173a 4155 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
emilmont 77:869cf507173a 4156
emilmont 77:869cf507173a 4157 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
emilmont 77:869cf507173a 4158 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
emilmont 77:869cf507173a 4159 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
emilmont 77:869cf507173a 4160 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
emilmont 77:869cf507173a 4161 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
emilmont 77:869cf507173a 4162 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
emilmont 77:869cf507173a 4163 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
emilmont 77:869cf507173a 4164 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
emilmont 77:869cf507173a 4165 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
emilmont 77:869cf507173a 4166
emilmont 77:869cf507173a 4167 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
emilmont 77:869cf507173a 4168 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
emilmont 77:869cf507173a 4169 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
emilmont 77:869cf507173a 4170 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
emilmont 77:869cf507173a 4171 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
emilmont 77:869cf507173a 4172 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
emilmont 77:869cf507173a 4173 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
emilmont 77:869cf507173a 4174 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
emilmont 77:869cf507173a 4175
emilmont 77:869cf507173a 4176 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
emilmont 77:869cf507173a 4177 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
emilmont 77:869cf507173a 4178 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
emilmont 77:869cf507173a 4179
emilmont 77:869cf507173a 4180 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
emilmont 77:869cf507173a 4181 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
emilmont 77:869cf507173a 4182 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
emilmont 77:869cf507173a 4183 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
emilmont 77:869cf507173a 4184 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
emilmont 77:869cf507173a 4185 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
emilmont 77:869cf507173a 4186 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
emilmont 77:869cf507173a 4187 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
emilmont 77:869cf507173a 4188 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
emilmont 77:869cf507173a 4189 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
emilmont 77:869cf507173a 4190 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
emilmont 77:869cf507173a 4191
emilmont 77:869cf507173a 4192 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
emilmont 77:869cf507173a 4193 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
emilmont 77:869cf507173a 4194 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
emilmont 77:869cf507173a 4195 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
emilmont 77:869cf507173a 4196 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
emilmont 77:869cf507173a 4197 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
emilmont 77:869cf507173a 4198 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
emilmont 77:869cf507173a 4199 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
emilmont 77:869cf507173a 4200 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
emilmont 77:869cf507173a 4201 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
emilmont 77:869cf507173a 4202 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
emilmont 77:869cf507173a 4203
emilmont 77:869cf507173a 4204 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
emilmont 77:869cf507173a 4205 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
emilmont 77:869cf507173a 4206
emilmont 77:869cf507173a 4207 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
emilmont 77:869cf507173a 4208 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
emilmont 77:869cf507173a 4209 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
emilmont 77:869cf507173a 4210
emilmont 77:869cf507173a 4211 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
emilmont 77:869cf507173a 4212 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
emilmont 77:869cf507173a 4213 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
emilmont 77:869cf507173a 4214 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
emilmont 77:869cf507173a 4215 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
emilmont 77:869cf507173a 4216 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
emilmont 77:869cf507173a 4217 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
emilmont 77:869cf507173a 4218
emilmont 77:869cf507173a 4219 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
emilmont 77:869cf507173a 4220 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
emilmont 77:869cf507173a 4221 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
emilmont 77:869cf507173a 4222
emilmont 77:869cf507173a 4223 /******************** Bit definition forUSB_OTG_CID register ********************/
emilmont 77:869cf507173a 4224 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
emilmont 77:869cf507173a 4225
emilmont 77:869cf507173a 4226 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
emilmont 77:869cf507173a 4227 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
emilmont 77:869cf507173a 4228 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
emilmont 77:869cf507173a 4229 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
emilmont 77:869cf507173a 4230 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
emilmont 77:869cf507173a 4231 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
emilmont 77:869cf507173a 4232 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
emilmont 77:869cf507173a 4233 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
emilmont 77:869cf507173a 4234 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
emilmont 77:869cf507173a 4235 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
emilmont 77:869cf507173a 4236
emilmont 77:869cf507173a 4237 /******************** Bit definition forUSB_OTG_HPRT register ********************/
emilmont 77:869cf507173a 4238 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
emilmont 77:869cf507173a 4239 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
emilmont 77:869cf507173a 4240 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
emilmont 77:869cf507173a 4241 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
emilmont 77:869cf507173a 4242 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
emilmont 77:869cf507173a 4243 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
emilmont 77:869cf507173a 4244 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
emilmont 77:869cf507173a 4245 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
emilmont 77:869cf507173a 4246 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
emilmont 77:869cf507173a 4247
emilmont 77:869cf507173a 4248 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
emilmont 77:869cf507173a 4249 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
emilmont 77:869cf507173a 4250 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
emilmont 77:869cf507173a 4251 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
emilmont 77:869cf507173a 4252
emilmont 77:869cf507173a 4253 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
emilmont 77:869cf507173a 4254 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
emilmont 77:869cf507173a 4255 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
emilmont 77:869cf507173a 4256 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
emilmont 77:869cf507173a 4257 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
emilmont 77:869cf507173a 4258
emilmont 77:869cf507173a 4259 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
emilmont 77:869cf507173a 4260 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
emilmont 77:869cf507173a 4261 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
emilmont 77:869cf507173a 4262
emilmont 77:869cf507173a 4263 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
emilmont 77:869cf507173a 4264 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
emilmont 77:869cf507173a 4265 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
emilmont 77:869cf507173a 4266 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
emilmont 77:869cf507173a 4267 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
emilmont 77:869cf507173a 4268 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
emilmont 77:869cf507173a 4269 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
emilmont 77:869cf507173a 4270 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
emilmont 77:869cf507173a 4271 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
emilmont 77:869cf507173a 4272 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
emilmont 77:869cf507173a 4273 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
emilmont 77:869cf507173a 4274 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
emilmont 77:869cf507173a 4275
emilmont 77:869cf507173a 4276 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
emilmont 77:869cf507173a 4277 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
emilmont 77:869cf507173a 4278 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
emilmont 77:869cf507173a 4279
emilmont 77:869cf507173a 4280 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
emilmont 77:869cf507173a 4281 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
emilmont 77:869cf507173a 4282 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
emilmont 77:869cf507173a 4283 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
emilmont 77:869cf507173a 4284 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
emilmont 77:869cf507173a 4285
emilmont 77:869cf507173a 4286 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
emilmont 77:869cf507173a 4287 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
emilmont 77:869cf507173a 4288 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
emilmont 77:869cf507173a 4289 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
emilmont 77:869cf507173a 4290
emilmont 77:869cf507173a 4291 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
emilmont 77:869cf507173a 4292 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
emilmont 77:869cf507173a 4293 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
emilmont 77:869cf507173a 4294 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
emilmont 77:869cf507173a 4295 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
emilmont 77:869cf507173a 4296 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
emilmont 77:869cf507173a 4297 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
emilmont 77:869cf507173a 4298 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
emilmont 77:869cf507173a 4299 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
emilmont 77:869cf507173a 4300 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
emilmont 77:869cf507173a 4301 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
emilmont 77:869cf507173a 4302
emilmont 77:869cf507173a 4303 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
emilmont 77:869cf507173a 4304 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
emilmont 77:869cf507173a 4305
emilmont 77:869cf507173a 4306 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
emilmont 77:869cf507173a 4307 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
emilmont 77:869cf507173a 4308 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
emilmont 77:869cf507173a 4309 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
emilmont 77:869cf507173a 4310 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
emilmont 77:869cf507173a 4311 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
emilmont 77:869cf507173a 4312 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
emilmont 77:869cf507173a 4313
emilmont 77:869cf507173a 4314 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
emilmont 77:869cf507173a 4315 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
emilmont 77:869cf507173a 4316 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
emilmont 77:869cf507173a 4317
emilmont 77:869cf507173a 4318 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
emilmont 77:869cf507173a 4319 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
emilmont 77:869cf507173a 4320 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
emilmont 77:869cf507173a 4321
emilmont 77:869cf507173a 4322 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
emilmont 77:869cf507173a 4323 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
emilmont 77:869cf507173a 4324 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
emilmont 77:869cf507173a 4325 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
emilmont 77:869cf507173a 4326 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
emilmont 77:869cf507173a 4327 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
emilmont 77:869cf507173a 4328 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
emilmont 77:869cf507173a 4329 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
emilmont 77:869cf507173a 4330 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
emilmont 77:869cf507173a 4331 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
emilmont 77:869cf507173a 4332 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
emilmont 77:869cf507173a 4333
emilmont 77:869cf507173a 4334 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
emilmont 77:869cf507173a 4335
emilmont 77:869cf507173a 4336 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
emilmont 77:869cf507173a 4337 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
emilmont 77:869cf507173a 4338 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
emilmont 77:869cf507173a 4339 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
emilmont 77:869cf507173a 4340 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
emilmont 77:869cf507173a 4341 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
emilmont 77:869cf507173a 4342 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
emilmont 77:869cf507173a 4343 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
emilmont 77:869cf507173a 4344
emilmont 77:869cf507173a 4345 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
emilmont 77:869cf507173a 4346 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
emilmont 77:869cf507173a 4347 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
emilmont 77:869cf507173a 4348 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
emilmont 77:869cf507173a 4349 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
emilmont 77:869cf507173a 4350 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
emilmont 77:869cf507173a 4351 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
emilmont 77:869cf507173a 4352 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
emilmont 77:869cf507173a 4353
emilmont 77:869cf507173a 4354 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
emilmont 77:869cf507173a 4355 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
emilmont 77:869cf507173a 4356 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
emilmont 77:869cf507173a 4357 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
emilmont 77:869cf507173a 4358 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
emilmont 77:869cf507173a 4359
emilmont 77:869cf507173a 4360 /******************** Bit definition forUSB_OTG_HCINT register ********************/
emilmont 77:869cf507173a 4361 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
emilmont 77:869cf507173a 4362 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
emilmont 77:869cf507173a 4363 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
emilmont 77:869cf507173a 4364 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
emilmont 77:869cf507173a 4365 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
emilmont 77:869cf507173a 4366 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
emilmont 77:869cf507173a 4367 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
emilmont 77:869cf507173a 4368 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
emilmont 77:869cf507173a 4369 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
emilmont 77:869cf507173a 4370 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
emilmont 77:869cf507173a 4371 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
emilmont 77:869cf507173a 4372
emilmont 77:869cf507173a 4373 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
emilmont 77:869cf507173a 4374 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
emilmont 77:869cf507173a 4375 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
emilmont 77:869cf507173a 4376 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
emilmont 77:869cf507173a 4377 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
emilmont 77:869cf507173a 4378 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
emilmont 77:869cf507173a 4379 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
emilmont 77:869cf507173a 4380 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
emilmont 77:869cf507173a 4381 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
emilmont 77:869cf507173a 4382 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
emilmont 77:869cf507173a 4383 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
emilmont 77:869cf507173a 4384 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
emilmont 77:869cf507173a 4385
emilmont 77:869cf507173a 4386 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
emilmont 77:869cf507173a 4387 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
emilmont 77:869cf507173a 4388 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
emilmont 77:869cf507173a 4389 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
emilmont 77:869cf507173a 4390 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
emilmont 77:869cf507173a 4391 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
emilmont 77:869cf507173a 4392 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
emilmont 77:869cf507173a 4393 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
emilmont 77:869cf507173a 4394 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
emilmont 77:869cf507173a 4395 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
emilmont 77:869cf507173a 4396 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
emilmont 77:869cf507173a 4397 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
emilmont 77:869cf507173a 4398
emilmont 77:869cf507173a 4399 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
emilmont 77:869cf507173a 4400
emilmont 77:869cf507173a 4401 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
emilmont 77:869cf507173a 4402 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
emilmont 77:869cf507173a 4403 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
emilmont 77:869cf507173a 4404 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
emilmont 77:869cf507173a 4405 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
emilmont 77:869cf507173a 4406 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
emilmont 77:869cf507173a 4407 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
emilmont 77:869cf507173a 4408 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
emilmont 77:869cf507173a 4409 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
emilmont 77:869cf507173a 4410 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
emilmont 77:869cf507173a 4411
emilmont 77:869cf507173a 4412 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
emilmont 77:869cf507173a 4413 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
emilmont 77:869cf507173a 4414
emilmont 77:869cf507173a 4415 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
emilmont 77:869cf507173a 4416 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
emilmont 77:869cf507173a 4417
emilmont 77:869cf507173a 4418 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
emilmont 77:869cf507173a 4419 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
emilmont 77:869cf507173a 4420
emilmont 77:869cf507173a 4421 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
emilmont 77:869cf507173a 4422 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
emilmont 77:869cf507173a 4423 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
emilmont 77:869cf507173a 4424
emilmont 77:869cf507173a 4425 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
emilmont 77:869cf507173a 4426
emilmont 77:869cf507173a 4427 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
emilmont 77:869cf507173a 4428 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
emilmont 77:869cf507173a 4429 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
emilmont 77:869cf507173a 4430 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
emilmont 77:869cf507173a 4431 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
emilmont 77:869cf507173a 4432 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
emilmont 77:869cf507173a 4433 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
emilmont 77:869cf507173a 4434 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
emilmont 77:869cf507173a 4435 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
emilmont 77:869cf507173a 4436 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
emilmont 77:869cf507173a 4437 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
emilmont 77:869cf507173a 4438 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
emilmont 77:869cf507173a 4439 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
emilmont 77:869cf507173a 4440 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
emilmont 77:869cf507173a 4441
emilmont 77:869cf507173a 4442 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
emilmont 77:869cf507173a 4443 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
emilmont 77:869cf507173a 4444 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
emilmont 77:869cf507173a 4445 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
emilmont 77:869cf507173a 4446 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
emilmont 77:869cf507173a 4447 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
emilmont 77:869cf507173a 4448 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
emilmont 77:869cf507173a 4449
emilmont 77:869cf507173a 4450 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
emilmont 77:869cf507173a 4451
emilmont 77:869cf507173a 4452 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
emilmont 77:869cf507173a 4453 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
emilmont 77:869cf507173a 4454
emilmont 77:869cf507173a 4455 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
emilmont 77:869cf507173a 4456 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
emilmont 77:869cf507173a 4457 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
emilmont 77:869cf507173a 4458
emilmont 77:869cf507173a 4459 /******************** Bit definition for PCGCCTL register ********************/
emilmont 77:869cf507173a 4460 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
emilmont 77:869cf507173a 4461 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
emilmont 77:869cf507173a 4462 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
emilmont 77:869cf507173a 4463
emilmont 77:869cf507173a 4464 /**
emilmont 77:869cf507173a 4465 * @}
emilmont 77:869cf507173a 4466 */
emilmont 77:869cf507173a 4467
emilmont 77:869cf507173a 4468 /**
emilmont 77:869cf507173a 4469 * @}
emilmont 77:869cf507173a 4470 */
emilmont 77:869cf507173a 4471
emilmont 77:869cf507173a 4472 /** @addtogroup Exported_macros
emilmont 77:869cf507173a 4473 * @{
emilmont 77:869cf507173a 4474 */
emilmont 77:869cf507173a 4475
emilmont 77:869cf507173a 4476 /******************************* ADC Instances ********************************/
emilmont 77:869cf507173a 4477 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
emilmont 77:869cf507173a 4478
emilmont 77:869cf507173a 4479 /******************************* CRC Instances ********************************/
emilmont 77:869cf507173a 4480 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
emilmont 77:869cf507173a 4481
emilmont 77:869cf507173a 4482 /******************************** DMA Instances *******************************/
emilmont 77:869cf507173a 4483 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
emilmont 77:869cf507173a 4484 ((INSTANCE) == DMA1_Stream1) || \
emilmont 77:869cf507173a 4485 ((INSTANCE) == DMA1_Stream2) || \
emilmont 77:869cf507173a 4486 ((INSTANCE) == DMA1_Stream3) || \
emilmont 77:869cf507173a 4487 ((INSTANCE) == DMA1_Stream4) || \
emilmont 77:869cf507173a 4488 ((INSTANCE) == DMA1_Stream5) || \
emilmont 77:869cf507173a 4489 ((INSTANCE) == DMA1_Stream6) || \
emilmont 77:869cf507173a 4490 ((INSTANCE) == DMA1_Stream7) || \
emilmont 77:869cf507173a 4491 ((INSTANCE) == DMA2_Stream0) || \
emilmont 77:869cf507173a 4492 ((INSTANCE) == DMA2_Stream1) || \
emilmont 77:869cf507173a 4493 ((INSTANCE) == DMA2_Stream2) || \
emilmont 77:869cf507173a 4494 ((INSTANCE) == DMA2_Stream3) || \
emilmont 77:869cf507173a 4495 ((INSTANCE) == DMA2_Stream4) || \
emilmont 77:869cf507173a 4496 ((INSTANCE) == DMA2_Stream5) || \
emilmont 77:869cf507173a 4497 ((INSTANCE) == DMA2_Stream6) || \
emilmont 77:869cf507173a 4498 ((INSTANCE) == DMA2_Stream7))
emilmont 77:869cf507173a 4499
emilmont 77:869cf507173a 4500 /******************************* GPIO Instances *******************************/
emilmont 77:869cf507173a 4501 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
emilmont 77:869cf507173a 4502 ((INSTANCE) == GPIOB) || \
emilmont 77:869cf507173a 4503 ((INSTANCE) == GPIOC) || \
emilmont 77:869cf507173a 4504 ((INSTANCE) == GPIOD) || \
emilmont 77:869cf507173a 4505 ((INSTANCE) == GPIOE) || \
emilmont 77:869cf507173a 4506 ((INSTANCE) == GPIOH))
emilmont 77:869cf507173a 4507
emilmont 77:869cf507173a 4508 /******************************** I2C Instances *******************************/
emilmont 77:869cf507173a 4509 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
emilmont 77:869cf507173a 4510 ((INSTANCE) == I2C2) || \
emilmont 77:869cf507173a 4511 ((INSTANCE) == I2C3))
emilmont 77:869cf507173a 4512
emilmont 77:869cf507173a 4513 /******************************** I2S Instances *******************************/
emilmont 77:869cf507173a 4514 #define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
emilmont 77:869cf507173a 4515 ((INSTANCE) == SPI3))
emilmont 77:869cf507173a 4516
emilmont 77:869cf507173a 4517 /*************************** I2S Extended Instances ***************************/
emilmont 77:869cf507173a 4518 #define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
emilmont 77:869cf507173a 4519 ((INSTANCE) == SPI3) || \
emilmont 77:869cf507173a 4520 ((INSTANCE) == I2S2ext) || \
emilmont 77:869cf507173a 4521 ((INSTANCE) == I2S3ext))
emilmont 77:869cf507173a 4522
emilmont 77:869cf507173a 4523 /****************************** RTC Instances *********************************/
emilmont 77:869cf507173a 4524 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
emilmont 77:869cf507173a 4525
emilmont 77:869cf507173a 4526 /******************************** SPI Instances *******************************/
emilmont 77:869cf507173a 4527 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
emilmont 77:869cf507173a 4528 ((INSTANCE) == SPI2) || \
emilmont 77:869cf507173a 4529 ((INSTANCE) == SPI3) || \
emilmont 77:869cf507173a 4530 ((INSTANCE) == SPI4))
emilmont 77:869cf507173a 4531
emilmont 77:869cf507173a 4532 /*************************** SPI Extended Instances ***************************/
emilmont 77:869cf507173a 4533 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
emilmont 77:869cf507173a 4534 ((INSTANCE) == SPI2) || \
emilmont 77:869cf507173a 4535 ((INSTANCE) == SPI3) || \
emilmont 77:869cf507173a 4536 ((INSTANCE) == I2S2ext) || \
emilmont 77:869cf507173a 4537 ((INSTANCE) == I2S3ext))
emilmont 77:869cf507173a 4538
emilmont 77:869cf507173a 4539 /****************** TIM Instances : All supported instances *******************/
emilmont 77:869cf507173a 4540 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4541 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4542 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4543 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4544 ((INSTANCE) == TIM5) || \
emilmont 77:869cf507173a 4545 ((INSTANCE) == TIM9) || \
emilmont 77:869cf507173a 4546 ((INSTANCE) == TIM10) || \
emilmont 77:869cf507173a 4547 ((INSTANCE) == TIM11))
emilmont 77:869cf507173a 4548
emilmont 77:869cf507173a 4549 /************* TIM Instances : at least 1 capture/compare channel *************/
emilmont 77:869cf507173a 4550 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4551 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4552 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4553 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4554 ((INSTANCE) == TIM5) || \
emilmont 77:869cf507173a 4555 ((INSTANCE) == TIM9) || \
emilmont 77:869cf507173a 4556 ((INSTANCE) == TIM10) || \
emilmont 77:869cf507173a 4557 ((INSTANCE) == TIM11))
emilmont 77:869cf507173a 4558
emilmont 77:869cf507173a 4559 /************ TIM Instances : at least 2 capture/compare channels *************/
emilmont 77:869cf507173a 4560 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4561 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4562 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4563 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4564 ((INSTANCE) == TIM5) || \
emilmont 77:869cf507173a 4565 ((INSTANCE) == TIM9))
emilmont 77:869cf507173a 4566
emilmont 77:869cf507173a 4567 /************ TIM Instances : at least 3 capture/compare channels *************/
emilmont 77:869cf507173a 4568 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4569 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4570 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4571 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4572 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4573
emilmont 77:869cf507173a 4574 /************ TIM Instances : at least 4 capture/compare channels *************/
emilmont 77:869cf507173a 4575 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4576 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4577 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4578 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4579 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4580
emilmont 77:869cf507173a 4581 /******************** TIM Instances : Advanced-control timers *****************/
emilmont 77:869cf507173a 4582 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
emilmont 77:869cf507173a 4583
emilmont 77:869cf507173a 4584 /******************* TIM Instances : Timer input XOR function *****************/
emilmont 77:869cf507173a 4585 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4586 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4587 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4588 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4589 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4590
emilmont 77:869cf507173a 4591 /****************** TIM Instances : DMA requests generation (UDE) *************/
emilmont 77:869cf507173a 4592 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4593 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4594 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4595 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4596 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4597
emilmont 77:869cf507173a 4598 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
emilmont 77:869cf507173a 4599 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4600 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4601 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4602 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4603 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4604
emilmont 77:869cf507173a 4605 /************ TIM Instances : DMA requests generation (COMDE) *****************/
emilmont 77:869cf507173a 4606 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4607 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4608 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4609 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4610 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4611
emilmont 77:869cf507173a 4612 /******************** TIM Instances : DMA burst feature ***********************/
emilmont 77:869cf507173a 4613 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4614 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4615 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4616 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4617 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4618
emilmont 77:869cf507173a 4619 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
emilmont 77:869cf507173a 4620 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4621 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4622 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4623 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4624 ((INSTANCE) == TIM5) || \
emilmont 77:869cf507173a 4625 ((INSTANCE) == TIM9))
emilmont 77:869cf507173a 4626
emilmont 77:869cf507173a 4627 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
emilmont 77:869cf507173a 4628 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4629 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4630 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4631 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4632 ((INSTANCE) == TIM5) || \
emilmont 77:869cf507173a 4633 ((INSTANCE) == TIM9))
emilmont 77:869cf507173a 4634
emilmont 77:869cf507173a 4635 /********************** TIM Instances : 32 bit Counter ************************/
emilmont 77:869cf507173a 4636 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4637 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4638
emilmont 77:869cf507173a 4639 /***************** TIM Instances : external trigger input availabe ************/
emilmont 77:869cf507173a 4640 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
emilmont 77:869cf507173a 4641 ((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4642 ((INSTANCE) == TIM3) || \
emilmont 77:869cf507173a 4643 ((INSTANCE) == TIM4) || \
emilmont 77:869cf507173a 4644 ((INSTANCE) == TIM5))
emilmont 77:869cf507173a 4645
emilmont 77:869cf507173a 4646 /****************** TIM Instances : remapping capability **********************/
emilmont 77:869cf507173a 4647 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
emilmont 77:869cf507173a 4648 ((INSTANCE) == TIM5) || \
emilmont 77:869cf507173a 4649 ((INSTANCE) == TIM11))
emilmont 77:869cf507173a 4650
emilmont 77:869cf507173a 4651 /******************* TIM Instances : output(s) available **********************/
emilmont 77:869cf507173a 4652 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
emilmont 77:869cf507173a 4653 ((((INSTANCE) == TIM1) && \
emilmont 77:869cf507173a 4654 (((CHANNEL) == TIM_CHANNEL_1) || \
emilmont 77:869cf507173a 4655 ((CHANNEL) == TIM_CHANNEL_2) || \
emilmont 77:869cf507173a 4656 ((CHANNEL) == TIM_CHANNEL_3) || \
emilmont 77:869cf507173a 4657 ((CHANNEL) == TIM_CHANNEL_4))) \
emilmont 77:869cf507173a 4658 || \
emilmont 77:869cf507173a 4659 (((INSTANCE) == TIM2) && \
emilmont 77:869cf507173a 4660 (((CHANNEL) == TIM_CHANNEL_1) || \
emilmont 77:869cf507173a 4661 ((CHANNEL) == TIM_CHANNEL_2) || \
emilmont 77:869cf507173a 4662 ((CHANNEL) == TIM_CHANNEL_3) || \
emilmont 77:869cf507173a 4663 ((CHANNEL) == TIM_CHANNEL_4))) \
emilmont 77:869cf507173a 4664 || \
emilmont 77:869cf507173a 4665 (((INSTANCE) == TIM3) && \
emilmont 77:869cf507173a 4666 (((CHANNEL) == TIM_CHANNEL_1) || \
emilmont 77:869cf507173a 4667 ((CHANNEL) == TIM_CHANNEL_2) || \
emilmont 77:869cf507173a 4668 ((CHANNEL) == TIM_CHANNEL_3) || \
emilmont 77:869cf507173a 4669 ((CHANNEL) == TIM_CHANNEL_4))) \
emilmont 77:869cf507173a 4670 || \
emilmont 77:869cf507173a 4671 (((INSTANCE) == TIM4) && \
emilmont 77:869cf507173a 4672 (((CHANNEL) == TIM_CHANNEL_1) || \
emilmont 77:869cf507173a 4673 ((CHANNEL) == TIM_CHANNEL_2) || \
emilmont 77:869cf507173a 4674 ((CHANNEL) == TIM_CHANNEL_3) || \
emilmont 77:869cf507173a 4675 ((CHANNEL) == TIM_CHANNEL_4))) \
emilmont 77:869cf507173a 4676 || \
emilmont 77:869cf507173a 4677 (((INSTANCE) == TIM5) && \
emilmont 77:869cf507173a 4678 (((CHANNEL) == TIM_CHANNEL_1) || \
emilmont 77:869cf507173a 4679 ((CHANNEL) == TIM_CHANNEL_2) || \
emilmont 77:869cf507173a 4680 ((CHANNEL) == TIM_CHANNEL_3) || \
emilmont 77:869cf507173a 4681 ((CHANNEL) == TIM_CHANNEL_4))) \
emilmont 77:869cf507173a 4682 || \
emilmont 77:869cf507173a 4683 (((INSTANCE) == TIM9) && \
emilmont 77:869cf507173a 4684 (((CHANNEL) == TIM_CHANNEL_1) || \
emilmont 77:869cf507173a 4685 ((CHANNEL) == TIM_CHANNEL_2))) \
emilmont 77:869cf507173a 4686 || \
emilmont 77:869cf507173a 4687 (((INSTANCE) == TIM10) && \
emilmont 77:869cf507173a 4688 (((CHANNEL) == TIM_CHANNEL_1))) \
emilmont 77:869cf507173a 4689 || \
emilmont 77:869cf507173a 4690 (((INSTANCE) == TIM11) && \
emilmont 77:869cf507173a 4691 (((CHANNEL) == TIM_CHANNEL_1))))
emilmont 77:869cf507173a 4692
emilmont 77:869cf507173a 4693 /************ TIM Instances : complementary output(s) available ***************/
emilmont 77:869cf507173a 4694 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
emilmont 77:869cf507173a 4695 ((((INSTANCE) == TIM1) && \
emilmont 77:869cf507173a 4696 (((CHANNEL) == TIM_CHANNEL_1) || \
emilmont 77:869cf507173a 4697 ((CHANNEL) == TIM_CHANNEL_2) || \
emilmont 77:869cf507173a 4698 ((CHANNEL) == TIM_CHANNEL_3))))
emilmont 77:869cf507173a 4699
emilmont 77:869cf507173a 4700 /******************** USART Instances : Synchronous mode **********************/
emilmont 77:869cf507173a 4701 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
emilmont 77:869cf507173a 4702 ((INSTANCE) == USART2) || \
emilmont 77:869cf507173a 4703 ((INSTANCE) == USART6))
emilmont 77:869cf507173a 4704
emilmont 77:869cf507173a 4705 /******************** UART Instances : Asynchronous mode **********************/
emilmont 77:869cf507173a 4706 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
emilmont 77:869cf507173a 4707 ((INSTANCE) == USART2) || \
emilmont 77:869cf507173a 4708 ((INSTANCE) == USART6))
emilmont 77:869cf507173a 4709
emilmont 77:869cf507173a 4710 /****************** UART Instances : Hardware Flow control ********************/
emilmont 77:869cf507173a 4711 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
emilmont 77:869cf507173a 4712 ((INSTANCE) == USART2) || \
emilmont 77:869cf507173a 4713 ((INSTANCE) == USART6))
emilmont 77:869cf507173a 4714
emilmont 77:869cf507173a 4715 /********************* UART Instances : Smard card mode ***********************/
emilmont 77:869cf507173a 4716 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
emilmont 77:869cf507173a 4717 ((INSTANCE) == USART2) || \
emilmont 77:869cf507173a 4718 ((INSTANCE) == USART6))
emilmont 77:869cf507173a 4719
emilmont 77:869cf507173a 4720 /*********************** UART Instances : IRDA mode ***************************/
emilmont 77:869cf507173a 4721 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
emilmont 77:869cf507173a 4722 ((INSTANCE) == USART2) || \
emilmont 77:869cf507173a 4723 ((INSTANCE) == USART6))
emilmont 77:869cf507173a 4724
emilmont 77:869cf507173a 4725 /****************************** IWDG Instances ********************************/
emilmont 77:869cf507173a 4726 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
emilmont 77:869cf507173a 4727
emilmont 77:869cf507173a 4728 /****************************** WWDG Instances ********************************/
emilmont 77:869cf507173a 4729 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
emilmont 77:869cf507173a 4730
emilmont 77:869cf507173a 4731
emilmont 77:869cf507173a 4732 /**
emilmont 77:869cf507173a 4733 * @}
emilmont 77:869cf507173a 4734 */
emilmont 77:869cf507173a 4735
emilmont 77:869cf507173a 4736 /**
emilmont 77:869cf507173a 4737 * @}
emilmont 77:869cf507173a 4738 */
emilmont 77:869cf507173a 4739
emilmont 77:869cf507173a 4740 /**
emilmont 77:869cf507173a 4741 * @}
emilmont 77:869cf507173a 4742 */
emilmont 77:869cf507173a 4743
emilmont 77:869cf507173a 4744 #ifdef __cplusplus
emilmont 77:869cf507173a 4745 }
emilmont 77:869cf507173a 4746 #endif /* __cplusplus */
emilmont 77:869cf507173a 4747
emilmont 77:869cf507173a 4748 #endif /* __STM32F401xE_H */
emilmont 77:869cf507173a 4749
emilmont 77:869cf507173a 4750
emilmont 77:869cf507173a 4751
emilmont 77:869cf507173a 4752 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/