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TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:: emilmont
Date:: Fri Feb 14 14:36:43 2014 +0000
Revision:: 77:869cf507173a
Child:: 81:7d30d6019079

Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_hal_eth.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
emilmont	77:869cf507173a	5	* @version V1.0.0RC2
emilmont	77:869cf507173a	6	* @date 04-February-2014
emilmont	77:869cf507173a	7	* @brief Header file of ETH HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_HAL_ETH_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_HAL_ETH_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
emilmont	77:869cf507173a	47	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	48	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	49
emilmont	77:869cf507173a	50	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	51	* @{
emilmont	77:869cf507173a	52	*/
emilmont	77:869cf507173a	53
emilmont	77:869cf507173a	54	/** @addtogroup ETH
emilmont	77:869cf507173a	55	* @{
emilmont	77:869cf507173a	56	*/
emilmont	77:869cf507173a	57
emilmont	77:869cf507173a	58	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	59
emilmont	77:869cf507173a	60	/**
emilmont	77:869cf507173a	61	* @brief HAL State structures definition
emilmont	77:869cf507173a	62	*/
emilmont	77:869cf507173a	63	typedef enum
emilmont	77:869cf507173a	64	{
emilmont	77:869cf507173a	65	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
emilmont	77:869cf507173a	66	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
emilmont	77:869cf507173a	67	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
emilmont	77:869cf507173a	68	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
emilmont	77:869cf507173a	69	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
emilmont	77:869cf507173a	70	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
emilmont	77:869cf507173a	71	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
emilmont	77:869cf507173a	72	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
emilmont	77:869cf507173a	73	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
emilmont	77:869cf507173a	74	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
emilmont	77:869cf507173a	75	}HAL_ETH_StateTypeDef;
emilmont	77:869cf507173a	76
emilmont	77:869cf507173a	77	/**
emilmont	77:869cf507173a	78	* @brief ETH Init Structure definition
emilmont	77:869cf507173a	79	*/
emilmont	77:869cf507173a	80
emilmont	77:869cf507173a	81	typedef struct
emilmont	77:869cf507173a	82	{
emilmont	77:869cf507173a	83	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
emilmont	77:869cf507173a	84	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
emilmont	77:869cf507173a	85	and the mode (half/full-duplex).
emilmont	77:869cf507173a	86	This parameter can be a value of @ref ETH_AutoNegotiation */
emilmont	77:869cf507173a	87
emilmont	77:869cf507173a	88	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps
emilmont	77:869cf507173a	89	This parameter can be a value of @ref ETH_Speed */
emilmont	77:869cf507173a	90
emilmont	77:869cf507173a	91	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
emilmont	77:869cf507173a	92	This parameter can be a value of @ref ETH_Duplex_Mode */
emilmont	77:869cf507173a	93
emilmont	77:869cf507173a	94	uint16_t PhyAddress; /*!< Ethernet PHY address
emilmont	77:869cf507173a	95	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
emilmont	77:869cf507173a	96
emilmont	77:869cf507173a	97	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
emilmont	77:869cf507173a	98
emilmont	77:869cf507173a	99	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode
emilmont	77:869cf507173a	100	This parameter can be a value of @ref ETH_Rx_Mode */
emilmont	77:869cf507173a	101
emilmont	77:869cf507173a	102	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software
emilmont	77:869cf507173a	103	This parameter can be a value of @ref ETH_Checksum_Mode */
emilmont	77:869cf507173a	104
emilmont	77:869cf507173a	105	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface
emilmont	77:869cf507173a	106	This parameter can be a value of @ref ETH_Media_Interface */
emilmont	77:869cf507173a	107
emilmont	77:869cf507173a	108	} ETH_InitTypeDef;
emilmont	77:869cf507173a	109
emilmont	77:869cf507173a	110
emilmont	77:869cf507173a	111	/**
emilmont	77:869cf507173a	112	* @brief ETH MAC Configuration Structure definition
emilmont	77:869cf507173a	113	*/
emilmont	77:869cf507173a	114
emilmont	77:869cf507173a	115	typedef struct
emilmont	77:869cf507173a	116	{
emilmont	77:869cf507173a	117	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
emilmont	77:869cf507173a	118	When enabled, the MAC allows no more then 2048 bytes to be received.
emilmont	77:869cf507173a	119	When disabled, the MAC can receive up to 16384 bytes.
emilmont	77:869cf507173a	120	This parameter can be a value of @ref ETH_watchdog */
emilmont	77:869cf507173a	121
emilmont	77:869cf507173a	122	uint32_t Jabber; /*!< Selects or not Jabber timer
emilmont	77:869cf507173a	123	When enabled, the MAC allows no more then 2048 bytes to be sent.
emilmont	77:869cf507173a	124	When disabled, the MAC can send up to 16384 bytes.
emilmont	77:869cf507173a	125	This parameter can be a value of @ref ETH_Jabber */
emilmont	77:869cf507173a	126
emilmont	77:869cf507173a	127	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission
emilmont	77:869cf507173a	128	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
emilmont	77:869cf507173a	129
emilmont	77:869cf507173a	130	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense
emilmont	77:869cf507173a	131	This parameter can be a value of @ref ETH_Carrier_Sense */
emilmont	77:869cf507173a	132
emilmont	77:869cf507173a	133	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn
emilmont	77:869cf507173a	134	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
emilmont	77:869cf507173a	135	in Half-Duplex mode
emilmont	77:869cf507173a	136	This parameter can be a value of @ref ETH_Receive_Own */
emilmont	77:869cf507173a	137
emilmont	77:869cf507173a	138	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode
emilmont	77:869cf507173a	139	This parameter can be a value of @ref ETH_Loop_Back_Mode */
emilmont	77:869cf507173a	140
emilmont	77:869cf507173a	141	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
emilmont	77:869cf507173a	142	This parameter can be a value of @ref ETH_Checksum_Offload */
emilmont	77:869cf507173a	143
emilmont	77:869cf507173a	144	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
emilmont	77:869cf507173a	145	when a collision occurs (Half-Duplex mode)
emilmont	77:869cf507173a	146	This parameter can be a value of @ref ETH_Retry_Transmission */
emilmont	77:869cf507173a	147
emilmont	77:869cf507173a	148	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping
emilmont	77:869cf507173a	149	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
emilmont	77:869cf507173a	150
emilmont	77:869cf507173a	151	uint32_t BackOffLimit; /*!< Selects the BackOff limit value
emilmont	77:869cf507173a	152	This parameter can be a value of @ref ETH_Back_Off_Limit */
emilmont	77:869cf507173a	153
emilmont	77:869cf507173a	154	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)
emilmont	77:869cf507173a	155	This parameter can be a value of @ref ETH_Deferral_Check */
emilmont	77:869cf507173a	156
emilmont	77:869cf507173a	157	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering)
emilmont	77:869cf507173a	158	This parameter can be a value of @ref ETH_Receive_All */
emilmont	77:869cf507173a	159
emilmont	77:869cf507173a	160	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode
emilmont	77:869cf507173a	161	This parameter can be a value of @ref ETH_Source_Addr_Filter */
emilmont	77:869cf507173a	162
emilmont	77:869cf507173a	163	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
emilmont	77:869cf507173a	164	This parameter can be a value of @ref ETH_Pass_Control_Frames */
emilmont	77:869cf507173a	165
emilmont	77:869cf507173a	166	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames
emilmont	77:869cf507173a	167	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
emilmont	77:869cf507173a	168
emilmont	77:869cf507173a	169	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames
emilmont	77:869cf507173a	170	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
emilmont	77:869cf507173a	171
emilmont	77:869cf507173a	172	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
emilmont	77:869cf507173a	173	This parameter can be a value of @ref ETH_Promiscuous_Mode */
emilmont	77:869cf507173a	174
emilmont	77:869cf507173a	175	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter
emilmont	77:869cf507173a	176	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
emilmont	77:869cf507173a	177
emilmont	77:869cf507173a	178	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter
emilmont	77:869cf507173a	179	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
emilmont	77:869cf507173a	180
emilmont	77:869cf507173a	181	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table
emilmont	77:869cf507173a	182	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
emilmont	77:869cf507173a	183
emilmont	77:869cf507173a	184	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table
emilmont	77:869cf507173a	185	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
emilmont	77:869cf507173a	186
emilmont	77:869cf507173a	187	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame
emilmont	77:869cf507173a	188	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
emilmont	77:869cf507173a	189
emilmont	77:869cf507173a	190	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames
emilmont	77:869cf507173a	191	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
emilmont	77:869cf507173a	192
emilmont	77:869cf507173a	193	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
emilmont	77:869cf507173a	194	automatic retransmission of PAUSE Frame
emilmont	77:869cf507173a	195	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
emilmont	77:869cf507173a	196
emilmont	77:869cf507173a	197	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
emilmont	77:869cf507173a	198	unicast address and unique multicast address)
emilmont	77:869cf507173a	199	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
emilmont	77:869cf507173a	200
emilmont	77:869cf507173a	201	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
emilmont	77:869cf507173a	202	disable its transmitter for a specified time (Pause Time)
emilmont	77:869cf507173a	203	This parameter can be a value of @ref ETH_Receive_Flow_Control */
emilmont	77:869cf507173a	204
emilmont	77:869cf507173a	205	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
emilmont	77:869cf507173a	206	or the MAC back-pressure operation (Half-Duplex mode)
emilmont	77:869cf507173a	207	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
emilmont	77:869cf507173a	208
emilmont	77:869cf507173a	209	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
emilmont	77:869cf507173a	210	comparison and filtering
emilmont	77:869cf507173a	211	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
emilmont	77:869cf507173a	212
emilmont	77:869cf507173a	213	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
emilmont	77:869cf507173a	214
emilmont	77:869cf507173a	215	} ETH_MACInitTypeDef;
emilmont	77:869cf507173a	216
emilmont	77:869cf507173a	217
emilmont	77:869cf507173a	218	/**
emilmont	77:869cf507173a	219	* @brief ETH DMA Configuration Structure definition
emilmont	77:869cf507173a	220	*/
emilmont	77:869cf507173a	221
emilmont	77:869cf507173a	222	typedef struct
emilmont	77:869cf507173a	223	{
emilmont	77:869cf507173a	224	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames
emilmont	77:869cf507173a	225	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
emilmont	77:869cf507173a	226
emilmont	77:869cf507173a	227	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode
emilmont	77:869cf507173a	228	This parameter can be a value of @ref ETH_Receive_Store_Forward */
emilmont	77:869cf507173a	229
emilmont	77:869cf507173a	230	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames
emilmont	77:869cf507173a	231	This parameter can be a value of @ref ETH_Flush_Received_Frame */
emilmont	77:869cf507173a	232
emilmont	77:869cf507173a	233	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode
emilmont	77:869cf507173a	234	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
emilmont	77:869cf507173a	235
emilmont	77:869cf507173a	236	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control
emilmont	77:869cf507173a	237	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
emilmont	77:869cf507173a	238
emilmont	77:869cf507173a	239	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames
emilmont	77:869cf507173a	240	This parameter can be a value of @ref ETH_Forward_Error_Frames */
emilmont	77:869cf507173a	241
emilmont	77:869cf507173a	242	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
emilmont	77:869cf507173a	243	and length less than 64 bytes) including pad-bytes and CRC)
emilmont	77:869cf507173a	244	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
emilmont	77:869cf507173a	245
emilmont	77:869cf507173a	246	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO
emilmont	77:869cf507173a	247	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
emilmont	77:869cf507173a	248
emilmont	77:869cf507173a	249	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
emilmont	77:869cf507173a	250	frame of Transmit data even before obtaining the status for the first frame.
emilmont	77:869cf507173a	251	This parameter can be a value of @ref ETH_Second_Frame_Operate */
emilmont	77:869cf507173a	252
emilmont	77:869cf507173a	253	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats
emilmont	77:869cf507173a	254	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
emilmont	77:869cf507173a	255
emilmont	77:869cf507173a	256	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers
emilmont	77:869cf507173a	257	This parameter can be a value of @ref ETH_Fixed_Burst */
emilmont	77:869cf507173a	258
emilmont	77:869cf507173a	259	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction
emilmont	77:869cf507173a	260	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
emilmont	77:869cf507173a	261
emilmont	77:869cf507173a	262	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction
emilmont	77:869cf507173a	263	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
emilmont	77:869cf507173a	264
emilmont	77:869cf507173a	265	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format
emilmont	77:869cf507173a	266	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
emilmont	77:869cf507173a	267
emilmont	77:869cf507173a	268	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
emilmont	77:869cf507173a	269	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
emilmont	77:869cf507173a	270
emilmont	77:869cf507173a	271	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration
emilmont	77:869cf507173a	272	This parameter can be a value of @ref ETH_DMA_Arbitration */
emilmont	77:869cf507173a	273	} ETH_DMAInitTypeDef;
emilmont	77:869cf507173a	274
emilmont	77:869cf507173a	275
emilmont	77:869cf507173a	276	/**
emilmont	77:869cf507173a	277	* @brief ETH DMA Descriptors data structure definition
emilmont	77:869cf507173a	278	*/
emilmont	77:869cf507173a	279
emilmont	77:869cf507173a	280	typedef struct
emilmont	77:869cf507173a	281	{
emilmont	77:869cf507173a	282	__IO uint32_t Status; /!< Status /
emilmont	77:869cf507173a	283
emilmont	77:869cf507173a	284	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
emilmont	77:869cf507173a	285
emilmont	77:869cf507173a	286	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
emilmont	77:869cf507173a	287
emilmont	77:869cf507173a	288	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
emilmont	77:869cf507173a	289
emilmont	77:869cf507173a	290	/!< Enhanced ETHERNET DMA PTP Descriptors /
emilmont	77:869cf507173a	291	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
emilmont	77:869cf507173a	292
emilmont	77:869cf507173a	293	uint32_t Reserved1; /!< Reserved /
emilmont	77:869cf507173a	294
emilmont	77:869cf507173a	295	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
emilmont	77:869cf507173a	296
emilmont	77:869cf507173a	297	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
emilmont	77:869cf507173a	298
emilmont	77:869cf507173a	299	} ETH_DMADescTypeDef;
emilmont	77:869cf507173a	300
emilmont	77:869cf507173a	301
emilmont	77:869cf507173a	302	/**
emilmont	77:869cf507173a	303	* @brief Received Frame Informations structure definition
emilmont	77:869cf507173a	304	*/
emilmont	77:869cf507173a	305	typedef struct
emilmont	77:869cf507173a	306	{
emilmont	77:869cf507173a	307	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
emilmont	77:869cf507173a	308
emilmont	77:869cf507173a	309	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
emilmont	77:869cf507173a	310
emilmont	77:869cf507173a	311	uint32_t SegCount; /!< Segment count /
emilmont	77:869cf507173a	312
emilmont	77:869cf507173a	313	uint32_t length; /!< Frame length /
emilmont	77:869cf507173a	314
emilmont	77:869cf507173a	315	uint32_t buffer; /!< Frame buffer /
emilmont	77:869cf507173a	316
emilmont	77:869cf507173a	317	} ETH_DMARxFrameInfos;
emilmont	77:869cf507173a	318
emilmont	77:869cf507173a	319
emilmont	77:869cf507173a	320	/**
emilmont	77:869cf507173a	321	* @brief ETH Handle Structure definition
emilmont	77:869cf507173a	322	*/
emilmont	77:869cf507173a	323
emilmont	77:869cf507173a	324	typedef struct
emilmont	77:869cf507173a	325	{
emilmont	77:869cf507173a	326	ETH_TypeDef Instance; /!< Register base address */
emilmont	77:869cf507173a	327
emilmont	77:869cf507173a	328	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
emilmont	77:869cf507173a	329
emilmont	77:869cf507173a	330	uint32_t LinkStatus; /!< Ethernet link status /
emilmont	77:869cf507173a	331
emilmont	77:869cf507173a	332	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
emilmont	77:869cf507173a	333
emilmont	77:869cf507173a	334	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
emilmont	77:869cf507173a	335
emilmont	77:869cf507173a	336	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
emilmont	77:869cf507173a	337
emilmont	77:869cf507173a	338	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
emilmont	77:869cf507173a	339
emilmont	77:869cf507173a	340	HAL_LockTypeDef Lock; /!< ETH Lock /
emilmont	77:869cf507173a	341
emilmont	77:869cf507173a	342	} ETH_HandleTypeDef;
emilmont	77:869cf507173a	343
emilmont	77:869cf507173a	344	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	345
emilmont	77:869cf507173a	346	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
emilmont	77:869cf507173a	347
emilmont	77:869cf507173a	348	/* Delay to wait when writing to some Ethernet registers */
emilmont	77:869cf507173a	349	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
emilmont	77:869cf507173a	350
emilmont	77:869cf507173a	351
emilmont	77:869cf507173a	352	/* ETHERNET Errors */
emilmont	77:869cf507173a	353	#define ETH_SUCCESS ((uint32_t)0)
emilmont	77:869cf507173a	354	#define ETH_ERROR ((uint32_t)1)
emilmont	77:869cf507173a	355
emilmont	77:869cf507173a	356	/** @defgroup ETH_Buffers_setting
emilmont	77:869cf507173a	357	* @{
emilmont	77:869cf507173a	358	*/
emilmont	77:869cf507173a	359	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC /
emilmont	77:869cf507173a	360	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
emilmont	77:869cf507173a	361	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
emilmont	77:869cf507173a	362	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
emilmont	77:869cf507173a	363	#define VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
emilmont	77:869cf507173a	364	#define MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
emilmont	77:869cf507173a	365	#define MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
emilmont	77:869cf507173a	366	#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
emilmont	77:869cf507173a	367
emilmont	77:869cf507173a	368	/* Ethernet driver receive buffers are organized in a chained linked-list, when
emilmont	77:869cf507173a	369	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
emilmont	77:869cf507173a	370	to the driver receive buffers memory.
emilmont	77:869cf507173a	371
emilmont	77:869cf507173a	372	Depending on the size of the received ethernet packet and the size of
emilmont	77:869cf507173a	373	each ethernet driver receive buffer, the received packet can take one or more
emilmont	77:869cf507173a	374	ethernet driver receive buffer.
emilmont	77:869cf507173a	375
emilmont	77:869cf507173a	376	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
emilmont	77:869cf507173a	377	and the total count of the driver receive buffers ETH_RXBUFNB.
emilmont	77:869cf507173a	378
emilmont	77:869cf507173a	379	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
emilmont	77:869cf507173a	380	example, they can be reconfigured in the application layer to fit the application
emilmont	77:869cf507173a	381	needs */
emilmont	77:869cf507173a	382
emilmont	77:869cf507173a	383	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
emilmont	77:869cf507173a	384	packet */
emilmont	77:869cf507173a	385	#ifndef ETH_RX_BUF_SIZE
emilmont	77:869cf507173a	386	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
emilmont	77:869cf507173a	387	#endif
emilmont	77:869cf507173a	388
emilmont	77:869cf507173a	389	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
emilmont	77:869cf507173a	390	#ifndef ETH_RXBUFNB
emilmont	77:869cf507173a	391	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
emilmont	77:869cf507173a	392	#endif
emilmont	77:869cf507173a	393
emilmont	77:869cf507173a	394
emilmont	77:869cf507173a	395	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
emilmont	77:869cf507173a	396	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
emilmont	77:869cf507173a	397	driver transmit buffers memory to the TxFIFO.
emilmont	77:869cf507173a	398
emilmont	77:869cf507173a	399	Depending on the size of the Ethernet packet to be transmitted and the size of
emilmont	77:869cf507173a	400	each ethernet driver transmit buffer, the packet to be transmitted can take
emilmont	77:869cf507173a	401	one or more ethernet driver transmit buffer.
emilmont	77:869cf507173a	402
emilmont	77:869cf507173a	403	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
emilmont	77:869cf507173a	404	and the total count of the driver transmit buffers ETH_TXBUFNB.
emilmont	77:869cf507173a	405
emilmont	77:869cf507173a	406	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
emilmont	77:869cf507173a	407	example, they can be reconfigured in the application layer to fit the application
emilmont	77:869cf507173a	408	needs */
emilmont	77:869cf507173a	409
emilmont	77:869cf507173a	410	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
emilmont	77:869cf507173a	411	packet */
emilmont	77:869cf507173a	412	#ifndef ETH_TX_BUF_SIZE
emilmont	77:869cf507173a	413	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
emilmont	77:869cf507173a	414	#endif
emilmont	77:869cf507173a	415
emilmont	77:869cf507173a	416	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
emilmont	77:869cf507173a	417	#ifndef ETH_TXBUFNB
emilmont	77:869cf507173a	418	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
emilmont	77:869cf507173a	419	#endif
emilmont	77:869cf507173a	420
emilmont	77:869cf507173a	421
emilmont	77:869cf507173a	422	/*
emilmont	77:869cf507173a	423	DMA Tx Desciptor
emilmont	77:869cf507173a	424	-----------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	425	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
emilmont	77:869cf507173a	426	-----------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	427	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
emilmont	77:869cf507173a	428	-----------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	429	TDES2 \| Buffer1 Address [31:0] \|
emilmont	77:869cf507173a	430	-----------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	431	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
emilmont	77:869cf507173a	432	-----------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	433	*/
emilmont	77:869cf507173a	434
emilmont	77:869cf507173a	435	/**
emilmont	77:869cf507173a	436	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
emilmont	77:869cf507173a	437	*/
emilmont	77:869cf507173a	438	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
emilmont	77:869cf507173a	439	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
emilmont	77:869cf507173a	440	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
emilmont	77:869cf507173a	441	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
emilmont	77:869cf507173a	442	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
emilmont	77:869cf507173a	443	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
emilmont	77:869cf507173a	444	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
emilmont	77:869cf507173a	445	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
emilmont	77:869cf507173a	446	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
emilmont	77:869cf507173a	447	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
emilmont	77:869cf507173a	448	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
emilmont	77:869cf507173a	449	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
emilmont	77:869cf507173a	450	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
emilmont	77:869cf507173a	451	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
emilmont	77:869cf507173a	452	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
emilmont	77:869cf507173a	453	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
emilmont	77:869cf507173a	454	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
emilmont	77:869cf507173a	455	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
emilmont	77:869cf507173a	456	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
emilmont	77:869cf507173a	457	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
emilmont	77:869cf507173a	458	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
emilmont	77:869cf507173a	459	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
emilmont	77:869cf507173a	460	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
emilmont	77:869cf507173a	461	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
emilmont	77:869cf507173a	462	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
emilmont	77:869cf507173a	463	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
emilmont	77:869cf507173a	464	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
emilmont	77:869cf507173a	465	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
emilmont	77:869cf507173a	466	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
emilmont	77:869cf507173a	467
emilmont	77:869cf507173a	468	/**
emilmont	77:869cf507173a	469	* @brief Bit definition of TDES1 register
emilmont	77:869cf507173a	470	*/
emilmont	77:869cf507173a	471	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
emilmont	77:869cf507173a	472	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
emilmont	77:869cf507173a	473
emilmont	77:869cf507173a	474	/**
emilmont	77:869cf507173a	475	* @brief Bit definition of TDES2 register
emilmont	77:869cf507173a	476	*/
emilmont	77:869cf507173a	477	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
emilmont	77:869cf507173a	478
emilmont	77:869cf507173a	479	/**
emilmont	77:869cf507173a	480	* @brief Bit definition of TDES3 register
emilmont	77:869cf507173a	481	*/
emilmont	77:869cf507173a	482	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
emilmont	77:869cf507173a	483
emilmont	77:869cf507173a	484	/*---------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	485	TDES6 \| Transmit Time Stamp Low [31:0] \|
emilmont	77:869cf507173a	486	-----------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	487	TDES7 \| Transmit Time Stamp High [31:0] \|
emilmont	77:869cf507173a	488	----------------------------------------------------------------------------------------------*/
emilmont	77:869cf507173a	489
emilmont	77:869cf507173a	490	/* Bit definition of TDES6 register */
emilmont	77:869cf507173a	491	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
emilmont	77:869cf507173a	492
emilmont	77:869cf507173a	493	/* Bit definition of TDES7 register */
emilmont	77:869cf507173a	494	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
emilmont	77:869cf507173a	495
emilmont	77:869cf507173a	496	/**
emilmont	77:869cf507173a	497	* @}
emilmont	77:869cf507173a	498	*/
emilmont	77:869cf507173a	499
emilmont	77:869cf507173a	500
emilmont	77:869cf507173a	501	/** @defgroup ETH_DMA_Rx_descriptor
emilmont	77:869cf507173a	502	* @{
emilmont	77:869cf507173a	503	*/
emilmont	77:869cf507173a	504
emilmont	77:869cf507173a	505	/*
emilmont	77:869cf507173a	506	DMA Rx Descriptor
emilmont	77:869cf507173a	507	--------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	508	RDES0 \| OWN(31) \| Status [30:0] \|
emilmont	77:869cf507173a	509	---------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	510	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
emilmont	77:869cf507173a	511	---------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	512	RDES2 \| Buffer1 Address [31:0] \|
emilmont	77:869cf507173a	513	---------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	514	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
emilmont	77:869cf507173a	515	---------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	516	*/
emilmont	77:869cf507173a	517
emilmont	77:869cf507173a	518	/**
emilmont	77:869cf507173a	519	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
emilmont	77:869cf507173a	520	*/
emilmont	77:869cf507173a	521	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
emilmont	77:869cf507173a	522	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
emilmont	77:869cf507173a	523	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
emilmont	77:869cf507173a	524	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
emilmont	77:869cf507173a	525	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
emilmont	77:869cf507173a	526	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
emilmont	77:869cf507173a	527	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
emilmont	77:869cf507173a	528	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
emilmont	77:869cf507173a	529	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
emilmont	77:869cf507173a	530	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
emilmont	77:869cf507173a	531	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
emilmont	77:869cf507173a	532	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
emilmont	77:869cf507173a	533	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
emilmont	77:869cf507173a	534	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
emilmont	77:869cf507173a	535	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
emilmont	77:869cf507173a	536	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
emilmont	77:869cf507173a	537	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
emilmont	77:869cf507173a	538	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
emilmont	77:869cf507173a	539	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
emilmont	77:869cf507173a	540
emilmont	77:869cf507173a	541	/**
emilmont	77:869cf507173a	542	* @brief Bit definition of RDES1 register
emilmont	77:869cf507173a	543	*/
emilmont	77:869cf507173a	544	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
emilmont	77:869cf507173a	545	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
emilmont	77:869cf507173a	546	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
emilmont	77:869cf507173a	547	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
emilmont	77:869cf507173a	548	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
emilmont	77:869cf507173a	549
emilmont	77:869cf507173a	550	/**
emilmont	77:869cf507173a	551	* @brief Bit definition of RDES2 register
emilmont	77:869cf507173a	552	*/
emilmont	77:869cf507173a	553	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
emilmont	77:869cf507173a	554
emilmont	77:869cf507173a	555	/**
emilmont	77:869cf507173a	556	* @brief Bit definition of RDES3 register
emilmont	77:869cf507173a	557	*/
emilmont	77:869cf507173a	558	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
emilmont	77:869cf507173a	559
emilmont	77:869cf507173a	560	/*---------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	561	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
emilmont	77:869cf507173a	562	---------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	563	RDES5 \| Reserved[31:0] \|
emilmont	77:869cf507173a	564	---------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	565	RDES6 \| Receive Time Stamp Low [31:0] \|
emilmont	77:869cf507173a	566	---------------------------------------------------------------------------------------------------------------------
emilmont	77:869cf507173a	567	RDES7 \| Receive Time Stamp High [31:0] \|
emilmont	77:869cf507173a	568	--------------------------------------------------------------------------------------------------------------------*/
emilmont	77:869cf507173a	569
emilmont	77:869cf507173a	570	/* Bit definition of RDES4 register */
emilmont	77:869cf507173a	571	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
emilmont	77:869cf507173a	572	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
emilmont	77:869cf507173a	573	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
emilmont	77:869cf507173a	574	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
emilmont	77:869cf507173a	575	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
emilmont	77:869cf507173a	576	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
emilmont	77:869cf507173a	577	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
emilmont	77:869cf507173a	578	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
emilmont	77:869cf507173a	579	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
emilmont	77:869cf507173a	580	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
emilmont	77:869cf507173a	581	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
emilmont	77:869cf507173a	582	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
emilmont	77:869cf507173a	583	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
emilmont	77:869cf507173a	584	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
emilmont	77:869cf507173a	585	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
emilmont	77:869cf507173a	586	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
emilmont	77:869cf507173a	587	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
emilmont	77:869cf507173a	588	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
emilmont	77:869cf507173a	589	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
emilmont	77:869cf507173a	590
emilmont	77:869cf507173a	591	/* Bit definition of RDES6 register */
emilmont	77:869cf507173a	592	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
emilmont	77:869cf507173a	593
emilmont	77:869cf507173a	594	/* Bit definition of RDES7 register */
emilmont	77:869cf507173a	595	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
emilmont	77:869cf507173a	596
emilmont	77:869cf507173a	597
emilmont	77:869cf507173a	598	/** @defgroup ETH_AutoNegotiation
emilmont	77:869cf507173a	599	* @{
emilmont	77:869cf507173a	600	*/
emilmont	77:869cf507173a	601	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	602	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	603	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
emilmont	77:869cf507173a	604	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
emilmont	77:869cf507173a	605	/**
emilmont	77:869cf507173a	606	* @}
emilmont	77:869cf507173a	607	*/
emilmont	77:869cf507173a	608	/** @defgroup ETH_Speed
emilmont	77:869cf507173a	609	* @{
emilmont	77:869cf507173a	610	*/
emilmont	77:869cf507173a	611	#define ETH_SPEED_10M ((uint32_t)0x00000000)
emilmont	77:869cf507173a	612	#define ETH_SPEED_100M ((uint32_t)0x00004000)
emilmont	77:869cf507173a	613	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
emilmont	77:869cf507173a	614	((SPEED) == ETH_SPEED_100M))
emilmont	77:869cf507173a	615	/**
emilmont	77:869cf507173a	616	* @}
emilmont	77:869cf507173a	617	*/
emilmont	77:869cf507173a	618	/** @defgroup ETH_Duplex_Mode
emilmont	77:869cf507173a	619	* @{
emilmont	77:869cf507173a	620	*/
emilmont	77:869cf507173a	621	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
emilmont	77:869cf507173a	622	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
emilmont	77:869cf507173a	623	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
emilmont	77:869cf507173a	624	((MODE) == ETH_MODE_HALFDUPLEX))
emilmont	77:869cf507173a	625	/**
emilmont	77:869cf507173a	626	* @}
emilmont	77:869cf507173a	627	*/
emilmont	77:869cf507173a	628	/** @defgroup ETH_Rx_Mode
emilmont	77:869cf507173a	629	* @{
emilmont	77:869cf507173a	630	*/
emilmont	77:869cf507173a	631	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	632	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	633	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
emilmont	77:869cf507173a	634	((MODE) == ETH_RXINTERRUPT_MODE))
emilmont	77:869cf507173a	635	/**
emilmont	77:869cf507173a	636	* @}
emilmont	77:869cf507173a	637	*/
emilmont	77:869cf507173a	638
emilmont	77:869cf507173a	639	/** @defgroup ETH_Checksum_Mode
emilmont	77:869cf507173a	640	* @{
emilmont	77:869cf507173a	641	*/
emilmont	77:869cf507173a	642	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	643	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	644	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
emilmont	77:869cf507173a	645	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
emilmont	77:869cf507173a	646	/**
emilmont	77:869cf507173a	647	* @}
emilmont	77:869cf507173a	648	*/
emilmont	77:869cf507173a	649
emilmont	77:869cf507173a	650	/** @defgroup ETH_Media_Interface
emilmont	77:869cf507173a	651	* @{
emilmont	77:869cf507173a	652	*/
emilmont	77:869cf507173a	653	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
emilmont	77:869cf507173a	654	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
emilmont	77:869cf507173a	655	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
emilmont	77:869cf507173a	656	((MODE) == ETH_MEDIA_INTERFACE_RMII))
emilmont	77:869cf507173a	657
emilmont	77:869cf507173a	658	/**
emilmont	77:869cf507173a	659	* @}
emilmont	77:869cf507173a	660	*/
emilmont	77:869cf507173a	661
emilmont	77:869cf507173a	662	/** @defgroup ETH_watchdog
emilmont	77:869cf507173a	663	* @{
emilmont	77:869cf507173a	664	*/
emilmont	77:869cf507173a	665	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	666	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
emilmont	77:869cf507173a	667	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
emilmont	77:869cf507173a	668	((CMD) == ETH_WATCHDOG_DISABLE))
emilmont	77:869cf507173a	669
emilmont	77:869cf507173a	670	/**
emilmont	77:869cf507173a	671	* @}
emilmont	77:869cf507173a	672	*/
emilmont	77:869cf507173a	673
emilmont	77:869cf507173a	674	/** @defgroup ETH_Jabber
emilmont	77:869cf507173a	675	* @{
emilmont	77:869cf507173a	676	*/
emilmont	77:869cf507173a	677	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	678	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
emilmont	77:869cf507173a	679	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
emilmont	77:869cf507173a	680	((CMD) == ETH_JABBER_DISABLE))
emilmont	77:869cf507173a	681
emilmont	77:869cf507173a	682	/**
emilmont	77:869cf507173a	683	* @}
emilmont	77:869cf507173a	684	*/
emilmont	77:869cf507173a	685
emilmont	77:869cf507173a	686	/** @defgroup ETH_Inter_Frame_Gap
emilmont	77:869cf507173a	687	* @{
emilmont	77:869cf507173a	688	*/
emilmont	77:869cf507173a	689	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
emilmont	77:869cf507173a	690	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
emilmont	77:869cf507173a	691	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
emilmont	77:869cf507173a	692	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
emilmont	77:869cf507173a	693	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
emilmont	77:869cf507173a	694	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
emilmont	77:869cf507173a	695	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
emilmont	77:869cf507173a	696	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
emilmont	77:869cf507173a	697	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
emilmont	77:869cf507173a	698	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
emilmont	77:869cf507173a	699	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
emilmont	77:869cf507173a	700	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
emilmont	77:869cf507173a	701	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
emilmont	77:869cf507173a	702	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
emilmont	77:869cf507173a	703	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
emilmont	77:869cf507173a	704	((GAP) == ETH_INTERFRAMEGAP_40BIT))
emilmont	77:869cf507173a	705
emilmont	77:869cf507173a	706	/**
emilmont	77:869cf507173a	707	* @}
emilmont	77:869cf507173a	708	*/
emilmont	77:869cf507173a	709
emilmont	77:869cf507173a	710	/** @defgroup ETH_Carrier_Sense
emilmont	77:869cf507173a	711	* @{
emilmont	77:869cf507173a	712	*/
emilmont	77:869cf507173a	713	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	714	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
emilmont	77:869cf507173a	715	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
emilmont	77:869cf507173a	716	((CMD) == ETH_CARRIERSENCE_DISABLE))
emilmont	77:869cf507173a	717
emilmont	77:869cf507173a	718	/**
emilmont	77:869cf507173a	719	* @}
emilmont	77:869cf507173a	720	*/
emilmont	77:869cf507173a	721
emilmont	77:869cf507173a	722	/** @defgroup ETH_Receive_Own
emilmont	77:869cf507173a	723	* @{
emilmont	77:869cf507173a	724	*/
emilmont	77:869cf507173a	725	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	726	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
emilmont	77:869cf507173a	727	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
emilmont	77:869cf507173a	728	((CMD) == ETH_RECEIVEOWN_DISABLE))
emilmont	77:869cf507173a	729
emilmont	77:869cf507173a	730	/**
emilmont	77:869cf507173a	731	* @}
emilmont	77:869cf507173a	732	*/
emilmont	77:869cf507173a	733
emilmont	77:869cf507173a	734	/** @defgroup ETH_Loop_Back_Mode
emilmont	77:869cf507173a	735	* @{
emilmont	77:869cf507173a	736	*/
emilmont	77:869cf507173a	737	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
emilmont	77:869cf507173a	738	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	739	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
emilmont	77:869cf507173a	740	((CMD) == ETH_LOOPBACKMODE_DISABLE))
emilmont	77:869cf507173a	741
emilmont	77:869cf507173a	742	/**
emilmont	77:869cf507173a	743	* @}
emilmont	77:869cf507173a	744	*/
emilmont	77:869cf507173a	745
emilmont	77:869cf507173a	746	/** @defgroup ETH_Checksum_Offload
emilmont	77:869cf507173a	747	* @{
emilmont	77:869cf507173a	748	*/
emilmont	77:869cf507173a	749	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
emilmont	77:869cf507173a	750	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	751	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
emilmont	77:869cf507173a	752	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
emilmont	77:869cf507173a	753
emilmont	77:869cf507173a	754	/**
emilmont	77:869cf507173a	755	* @}
emilmont	77:869cf507173a	756	*/
emilmont	77:869cf507173a	757
emilmont	77:869cf507173a	758	/** @defgroup ETH_Retry_Transmission
emilmont	77:869cf507173a	759	* @{
emilmont	77:869cf507173a	760	*/
emilmont	77:869cf507173a	761	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	762	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
emilmont	77:869cf507173a	763	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
emilmont	77:869cf507173a	764	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
emilmont	77:869cf507173a	765
emilmont	77:869cf507173a	766	/**
emilmont	77:869cf507173a	767	* @}
emilmont	77:869cf507173a	768	*/
emilmont	77:869cf507173a	769
emilmont	77:869cf507173a	770	/** @defgroup ETH_Automatic_Pad_CRC_Strip
emilmont	77:869cf507173a	771	* @{
emilmont	77:869cf507173a	772	*/
emilmont	77:869cf507173a	773	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
emilmont	77:869cf507173a	774	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	775	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
emilmont	77:869cf507173a	776	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
emilmont	77:869cf507173a	777
emilmont	77:869cf507173a	778	/**
emilmont	77:869cf507173a	779	* @}
emilmont	77:869cf507173a	780	*/
emilmont	77:869cf507173a	781
emilmont	77:869cf507173a	782	/** @defgroup ETH_Back_Off_Limit
emilmont	77:869cf507173a	783	* @{
emilmont	77:869cf507173a	784	*/
emilmont	77:869cf507173a	785	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	786	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	787	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	788	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
emilmont	77:869cf507173a	789	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
emilmont	77:869cf507173a	790	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
emilmont	77:869cf507173a	791	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
emilmont	77:869cf507173a	792	((LIMIT) == ETH_BACKOFFLIMIT_1))
emilmont	77:869cf507173a	793
emilmont	77:869cf507173a	794	/**
emilmont	77:869cf507173a	795	* @}
emilmont	77:869cf507173a	796	*/
emilmont	77:869cf507173a	797
emilmont	77:869cf507173a	798	/** @defgroup ETH_Deferral_Check
emilmont	77:869cf507173a	799	* @{
emilmont	77:869cf507173a	800	*/
emilmont	77:869cf507173a	801	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
emilmont	77:869cf507173a	802	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	803	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
emilmont	77:869cf507173a	804	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
emilmont	77:869cf507173a	805
emilmont	77:869cf507173a	806	/**
emilmont	77:869cf507173a	807	* @}
emilmont	77:869cf507173a	808	*/
emilmont	77:869cf507173a	809
emilmont	77:869cf507173a	810	/** @defgroup ETH_Receive_All
emilmont	77:869cf507173a	811	* @{
emilmont	77:869cf507173a	812	*/
emilmont	77:869cf507173a	813	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
emilmont	77:869cf507173a	814	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	815	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
emilmont	77:869cf507173a	816	((CMD) == ETH_RECEIVEAll_DISABLE))
emilmont	77:869cf507173a	817
emilmont	77:869cf507173a	818	/**
emilmont	77:869cf507173a	819	* @}
emilmont	77:869cf507173a	820	*/
emilmont	77:869cf507173a	821
emilmont	77:869cf507173a	822	/** @defgroup ETH_Source_Addr_Filter
emilmont	77:869cf507173a	823	* @{
emilmont	77:869cf507173a	824	*/
emilmont	77:869cf507173a	825	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
emilmont	77:869cf507173a	826	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
emilmont	77:869cf507173a	827	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	828	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
emilmont	77:869cf507173a	829	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
emilmont	77:869cf507173a	830	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
emilmont	77:869cf507173a	831
emilmont	77:869cf507173a	832	/**
emilmont	77:869cf507173a	833	* @}
emilmont	77:869cf507173a	834	*/
emilmont	77:869cf507173a	835
emilmont	77:869cf507173a	836	/** @defgroup ETH_Pass_Control_Frames
emilmont	77:869cf507173a	837	* @{
emilmont	77:869cf507173a	838	*/
emilmont	77:869cf507173a	839	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
emilmont	77:869cf507173a	840	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
emilmont	77:869cf507173a	841	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
emilmont	77:869cf507173a	842	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
emilmont	77:869cf507173a	843	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
emilmont	77:869cf507173a	844	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
emilmont	77:869cf507173a	845
emilmont	77:869cf507173a	846	/**
emilmont	77:869cf507173a	847	* @}
emilmont	77:869cf507173a	848	*/
emilmont	77:869cf507173a	849
emilmont	77:869cf507173a	850	/** @defgroup ETH_Broadcast_Frames_Reception
emilmont	77:869cf507173a	851	* @{
emilmont	77:869cf507173a	852	*/
emilmont	77:869cf507173a	853	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	854	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
emilmont	77:869cf507173a	855	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
emilmont	77:869cf507173a	856	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
emilmont	77:869cf507173a	857
emilmont	77:869cf507173a	858	/**
emilmont	77:869cf507173a	859	* @}
emilmont	77:869cf507173a	860	*/
emilmont	77:869cf507173a	861
emilmont	77:869cf507173a	862	/** @defgroup ETH_Destination_Addr_Filter
emilmont	77:869cf507173a	863	* @{
emilmont	77:869cf507173a	864	*/
emilmont	77:869cf507173a	865	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
emilmont	77:869cf507173a	866	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
emilmont	77:869cf507173a	867	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
emilmont	77:869cf507173a	868	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
emilmont	77:869cf507173a	869
emilmont	77:869cf507173a	870	/**
emilmont	77:869cf507173a	871	* @}
emilmont	77:869cf507173a	872	*/
emilmont	77:869cf507173a	873
emilmont	77:869cf507173a	874	/** @defgroup ETH_Promiscuous_Mode
emilmont	77:869cf507173a	875	* @{
emilmont	77:869cf507173a	876	*/
emilmont	77:869cf507173a	877	#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	878	#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	879	#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) \|\| \
emilmont	77:869cf507173a	880	((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
emilmont	77:869cf507173a	881
emilmont	77:869cf507173a	882	/**
emilmont	77:869cf507173a	883	* @}
emilmont	77:869cf507173a	884	*/
emilmont	77:869cf507173a	885
emilmont	77:869cf507173a	886	/** @defgroup ETH_Multicast_Frames_Filter
emilmont	77:869cf507173a	887	* @{
emilmont	77:869cf507173a	888	*/
emilmont	77:869cf507173a	889	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
emilmont	77:869cf507173a	890	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	891	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
emilmont	77:869cf507173a	892	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
emilmont	77:869cf507173a	893	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
emilmont	77:869cf507173a	894	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
emilmont	77:869cf507173a	895	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
emilmont	77:869cf507173a	896	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
emilmont	77:869cf507173a	897	/**
emilmont	77:869cf507173a	898	* @}
emilmont	77:869cf507173a	899	*/
emilmont	77:869cf507173a	900
emilmont	77:869cf507173a	901	/** @defgroup ETH_Unicast_Frames_Filter
emilmont	77:869cf507173a	902	* @{
emilmont	77:869cf507173a	903	*/
emilmont	77:869cf507173a	904	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
emilmont	77:869cf507173a	905	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
emilmont	77:869cf507173a	906	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
emilmont	77:869cf507173a	907	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
emilmont	77:869cf507173a	908	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
emilmont	77:869cf507173a	909	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
emilmont	77:869cf507173a	910	/**
emilmont	77:869cf507173a	911	* @}
emilmont	77:869cf507173a	912	*/
emilmont	77:869cf507173a	913
emilmont	77:869cf507173a	914	/** @defgroup ETH_Pause_Time
emilmont	77:869cf507173a	915	* @{
emilmont	77:869cf507173a	916	*/
emilmont	77:869cf507173a	917	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
emilmont	77:869cf507173a	918
emilmont	77:869cf507173a	919	/**
emilmont	77:869cf507173a	920	* @}
emilmont	77:869cf507173a	921	*/
emilmont	77:869cf507173a	922
emilmont	77:869cf507173a	923	/** @defgroup ETH_Zero_Quanta_Pause
emilmont	77:869cf507173a	924	* @{
emilmont	77:869cf507173a	925	*/
emilmont	77:869cf507173a	926	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	927	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
emilmont	77:869cf507173a	928	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
emilmont	77:869cf507173a	929	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
emilmont	77:869cf507173a	930	/**
emilmont	77:869cf507173a	931	* @}
emilmont	77:869cf507173a	932	*/
emilmont	77:869cf507173a	933
emilmont	77:869cf507173a	934	/** @defgroup ETH_Pause_Low_Threshold
emilmont	77:869cf507173a	935	* @{
emilmont	77:869cf507173a	936	*/
emilmont	77:869cf507173a	937	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
emilmont	77:869cf507173a	938	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
emilmont	77:869cf507173a	939	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
emilmont	77:869cf507173a	940	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
emilmont	77:869cf507173a	941	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
emilmont	77:869cf507173a	942	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
emilmont	77:869cf507173a	943	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
emilmont	77:869cf507173a	944	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
emilmont	77:869cf507173a	945	/**
emilmont	77:869cf507173a	946	* @}
emilmont	77:869cf507173a	947	*/
emilmont	77:869cf507173a	948
emilmont	77:869cf507173a	949	/** @defgroup ETH_Unicast_Pause_Frame_Detect
emilmont	77:869cf507173a	950	* @{
emilmont	77:869cf507173a	951	*/
emilmont	77:869cf507173a	952	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
emilmont	77:869cf507173a	953	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	954	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
emilmont	77:869cf507173a	955	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
emilmont	77:869cf507173a	956	/**
emilmont	77:869cf507173a	957	* @}
emilmont	77:869cf507173a	958	*/
emilmont	77:869cf507173a	959
emilmont	77:869cf507173a	960	/** @defgroup ETH_Receive_Flow_Control
emilmont	77:869cf507173a	961	* @{
emilmont	77:869cf507173a	962	*/
emilmont	77:869cf507173a	963	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	964	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	965	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
emilmont	77:869cf507173a	966	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
emilmont	77:869cf507173a	967	/**
emilmont	77:869cf507173a	968	* @}
emilmont	77:869cf507173a	969	*/
emilmont	77:869cf507173a	970
emilmont	77:869cf507173a	971	/** @defgroup ETH_Transmit_Flow_Control
emilmont	77:869cf507173a	972	* @{
emilmont	77:869cf507173a	973	*/
emilmont	77:869cf507173a	974	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
emilmont	77:869cf507173a	975	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	976	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
emilmont	77:869cf507173a	977	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
emilmont	77:869cf507173a	978	/**
emilmont	77:869cf507173a	979	* @}
emilmont	77:869cf507173a	980	*/
emilmont	77:869cf507173a	981
emilmont	77:869cf507173a	982	/** @defgroup ETH_VLAN_Tag_Comparison
emilmont	77:869cf507173a	983	* @{
emilmont	77:869cf507173a	984	*/
emilmont	77:869cf507173a	985	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
emilmont	77:869cf507173a	986	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
emilmont	77:869cf507173a	987	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
emilmont	77:869cf507173a	988	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
emilmont	77:869cf507173a	989	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
emilmont	77:869cf507173a	990
emilmont	77:869cf507173a	991	/**
emilmont	77:869cf507173a	992	* @}
emilmont	77:869cf507173a	993	*/
emilmont	77:869cf507173a	994
emilmont	77:869cf507173a	995	/** @defgroup ETH_MAC_addresses
emilmont	77:869cf507173a	996	* @{
emilmont	77:869cf507173a	997	*/
emilmont	77:869cf507173a	998	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	999	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	1000	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	1001	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
emilmont	77:869cf507173a	1002	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
emilmont	77:869cf507173a	1003	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
emilmont	77:869cf507173a	1004	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
emilmont	77:869cf507173a	1005	((ADDRESS) == ETH_MAC_ADDRESS3))
emilmont	77:869cf507173a	1006	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
emilmont	77:869cf507173a	1007	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
emilmont	77:869cf507173a	1008	((ADDRESS) == ETH_MAC_ADDRESS3))
emilmont	77:869cf507173a	1009	/**
emilmont	77:869cf507173a	1010	* @}
emilmont	77:869cf507173a	1011	*/
emilmont	77:869cf507173a	1012
emilmont	77:869cf507173a	1013	/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
emilmont	77:869cf507173a	1014	* @{
emilmont	77:869cf507173a	1015	*/
emilmont	77:869cf507173a	1016	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1017	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
emilmont	77:869cf507173a	1018	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
emilmont	77:869cf507173a	1019	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
emilmont	77:869cf507173a	1020	/**
emilmont	77:869cf507173a	1021	* @}
emilmont	77:869cf507173a	1022	*/
emilmont	77:869cf507173a	1023
emilmont	77:869cf507173a	1024	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
emilmont	77:869cf507173a	1025	* @{
emilmont	77:869cf507173a	1026	*/
emilmont	77:869cf507173a	1027	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
emilmont	77:869cf507173a	1028	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
emilmont	77:869cf507173a	1029	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
emilmont	77:869cf507173a	1030	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
emilmont	77:869cf507173a	1031	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
emilmont	77:869cf507173a	1032	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
emilmont	77:869cf507173a	1033	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
emilmont	77:869cf507173a	1034	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
emilmont	77:869cf507173a	1035	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
emilmont	77:869cf507173a	1036	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
emilmont	77:869cf507173a	1037	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
emilmont	77:869cf507173a	1038	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
emilmont	77:869cf507173a	1039
emilmont	77:869cf507173a	1040	/**
emilmont	77:869cf507173a	1041	* @}
emilmont	77:869cf507173a	1042	*/
emilmont	77:869cf507173a	1043
emilmont	77:869cf507173a	1044	/** @defgroup ETH_MAC_Debug_flags
emilmont	77:869cf507173a	1045	* @{
emilmont	77:869cf507173a	1046	*/
emilmont	77:869cf507173a	1047	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
emilmont	77:869cf507173a	1048
emilmont	77:869cf507173a	1049	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
emilmont	77:869cf507173a	1050
emilmont	77:869cf507173a	1051	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
emilmont	77:869cf507173a	1052
emilmont	77:869cf507173a	1053	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
emilmont	77:869cf507173a	1054	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
emilmont	77:869cf507173a	1055	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
emilmont	77:869cf507173a	1056	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
emilmont	77:869cf507173a	1057
emilmont	77:869cf507173a	1058	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
emilmont	77:869cf507173a	1059
emilmont	77:869cf507173a	1060	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
emilmont	77:869cf507173a	1061	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
emilmont	77:869cf507173a	1062	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
emilmont	77:869cf507173a	1063	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
emilmont	77:869cf507173a	1064
emilmont	77:869cf507173a	1065	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
emilmont	77:869cf507173a	1066
emilmont	77:869cf507173a	1067	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
emilmont	77:869cf507173a	1068	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
emilmont	77:869cf507173a	1069	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
emilmont	77:869cf507173a	1070	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
emilmont	77:869cf507173a	1071
emilmont	77:869cf507173a	1072	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
emilmont	77:869cf507173a	1073	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
emilmont	77:869cf507173a	1074	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
emilmont	77:869cf507173a	1075	#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
emilmont	77:869cf507173a	1076
emilmont	77:869cf507173a	1077	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
emilmont	77:869cf507173a	1078
emilmont	77:869cf507173a	1079	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
emilmont	77:869cf507173a	1080	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
emilmont	77:869cf507173a	1081	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
emilmont	77:869cf507173a	1082	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
emilmont	77:869cf507173a	1083
emilmont	77:869cf507173a	1084	#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
emilmont	77:869cf507173a	1085
emilmont	77:869cf507173a	1086	/**
emilmont	77:869cf507173a	1087	* @}
emilmont	77:869cf507173a	1088	*/
emilmont	77:869cf507173a	1089
emilmont	77:869cf507173a	1090	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
emilmont	77:869cf507173a	1091	* @{
emilmont	77:869cf507173a	1092	*/
emilmont	77:869cf507173a	1093	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1094	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
emilmont	77:869cf507173a	1095	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
emilmont	77:869cf507173a	1096	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
emilmont	77:869cf507173a	1097	/**
emilmont	77:869cf507173a	1098	* @}
emilmont	77:869cf507173a	1099	*/
emilmont	77:869cf507173a	1100
emilmont	77:869cf507173a	1101	/** @defgroup ETH_Receive_Store_Forward
emilmont	77:869cf507173a	1102	* @{
emilmont	77:869cf507173a	1103	*/
emilmont	77:869cf507173a	1104	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
emilmont	77:869cf507173a	1105	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1106	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
emilmont	77:869cf507173a	1107	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
emilmont	77:869cf507173a	1108	/**
emilmont	77:869cf507173a	1109	* @}
emilmont	77:869cf507173a	1110	*/
emilmont	77:869cf507173a	1111
emilmont	77:869cf507173a	1112	/** @defgroup ETH_Flush_Received_Frame
emilmont	77:869cf507173a	1113	* @{
emilmont	77:869cf507173a	1114	*/
emilmont	77:869cf507173a	1115	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1116	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
emilmont	77:869cf507173a	1117	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
emilmont	77:869cf507173a	1118	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
emilmont	77:869cf507173a	1119	/**
emilmont	77:869cf507173a	1120	* @}
emilmont	77:869cf507173a	1121	*/
emilmont	77:869cf507173a	1122
emilmont	77:869cf507173a	1123	/** @defgroup ETH_Transmit_Store_Forward
emilmont	77:869cf507173a	1124	* @{
emilmont	77:869cf507173a	1125	*/
emilmont	77:869cf507173a	1126	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
emilmont	77:869cf507173a	1127	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1128	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
emilmont	77:869cf507173a	1129	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
emilmont	77:869cf507173a	1130	/**
emilmont	77:869cf507173a	1131	* @}
emilmont	77:869cf507173a	1132	*/
emilmont	77:869cf507173a	1133
emilmont	77:869cf507173a	1134	/** @defgroup ETH_Transmit_Threshold_Control
emilmont	77:869cf507173a	1135	* @{
emilmont	77:869cf507173a	1136	*/
emilmont	77:869cf507173a	1137	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
emilmont	77:869cf507173a	1138	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
emilmont	77:869cf507173a	1139	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
emilmont	77:869cf507173a	1140	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
emilmont	77:869cf507173a	1141	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
emilmont	77:869cf507173a	1142	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
emilmont	77:869cf507173a	1143	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
emilmont	77:869cf507173a	1144	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
emilmont	77:869cf507173a	1145	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
emilmont	77:869cf507173a	1146	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
emilmont	77:869cf507173a	1147	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
emilmont	77:869cf507173a	1148	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
emilmont	77:869cf507173a	1149	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
emilmont	77:869cf507173a	1150	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
emilmont	77:869cf507173a	1151	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
emilmont	77:869cf507173a	1152	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
emilmont	77:869cf507173a	1153	/**
emilmont	77:869cf507173a	1154	* @}
emilmont	77:869cf507173a	1155	*/
emilmont	77:869cf507173a	1156
emilmont	77:869cf507173a	1157	/** @defgroup ETH_Forward_Error_Frames
emilmont	77:869cf507173a	1158	* @{
emilmont	77:869cf507173a	1159	*/
emilmont	77:869cf507173a	1160	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
emilmont	77:869cf507173a	1161	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1162	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
emilmont	77:869cf507173a	1163	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
emilmont	77:869cf507173a	1164	/**
emilmont	77:869cf507173a	1165	* @}
emilmont	77:869cf507173a	1166	*/
emilmont	77:869cf507173a	1167
emilmont	77:869cf507173a	1168	/** @defgroup ETH_Forward_Undersized_Good_Frames
emilmont	77:869cf507173a	1169	* @{
emilmont	77:869cf507173a	1170	*/
emilmont	77:869cf507173a	1171	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
emilmont	77:869cf507173a	1172	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1173	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
emilmont	77:869cf507173a	1174	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
emilmont	77:869cf507173a	1175
emilmont	77:869cf507173a	1176	/**
emilmont	77:869cf507173a	1177	* @}
emilmont	77:869cf507173a	1178	*/
emilmont	77:869cf507173a	1179
emilmont	77:869cf507173a	1180	/** @defgroup ETH_Receive_Threshold_Control
emilmont	77:869cf507173a	1181	* @{
emilmont	77:869cf507173a	1182	*/
emilmont	77:869cf507173a	1183	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
emilmont	77:869cf507173a	1184	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
emilmont	77:869cf507173a	1185	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
emilmont	77:869cf507173a	1186	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
emilmont	77:869cf507173a	1187	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
emilmont	77:869cf507173a	1188	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
emilmont	77:869cf507173a	1189	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
emilmont	77:869cf507173a	1190	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
emilmont	77:869cf507173a	1191	/**
emilmont	77:869cf507173a	1192	* @}
emilmont	77:869cf507173a	1193	*/
emilmont	77:869cf507173a	1194
emilmont	77:869cf507173a	1195	/** @defgroup ETH_Second_Frame_Operate
emilmont	77:869cf507173a	1196	* @{
emilmont	77:869cf507173a	1197	*/
emilmont	77:869cf507173a	1198	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	1199	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1200	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
emilmont	77:869cf507173a	1201	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
emilmont	77:869cf507173a	1202
emilmont	77:869cf507173a	1203	/**
emilmont	77:869cf507173a	1204	* @}
emilmont	77:869cf507173a	1205	*/
emilmont	77:869cf507173a	1206
emilmont	77:869cf507173a	1207	/** @defgroup ETH_Address_Aligned_Beats
emilmont	77:869cf507173a	1208	* @{
emilmont	77:869cf507173a	1209	*/
emilmont	77:869cf507173a	1210	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
emilmont	77:869cf507173a	1211	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1212	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
emilmont	77:869cf507173a	1213	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
emilmont	77:869cf507173a	1214
emilmont	77:869cf507173a	1215	/**
emilmont	77:869cf507173a	1216	* @}
emilmont	77:869cf507173a	1217	*/
emilmont	77:869cf507173a	1218
emilmont	77:869cf507173a	1219	/** @defgroup ETH_Fixed_Burst
emilmont	77:869cf507173a	1220	* @{
emilmont	77:869cf507173a	1221	*/
emilmont	77:869cf507173a	1222	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
emilmont	77:869cf507173a	1223	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1224	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
emilmont	77:869cf507173a	1225	((CMD) == ETH_FIXEDBURST_DISABLE))
emilmont	77:869cf507173a	1226
emilmont	77:869cf507173a	1227	/**
emilmont	77:869cf507173a	1228	* @}
emilmont	77:869cf507173a	1229	*/
emilmont	77:869cf507173a	1230
emilmont	77:869cf507173a	1231	/** @defgroup ETH_Rx_DMA_Burst_Length
emilmont	77:869cf507173a	1232	* @{
emilmont	77:869cf507173a	1233	*/
emilmont	77:869cf507173a	1234	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
emilmont	77:869cf507173a	1235	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
emilmont	77:869cf507173a	1236	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
emilmont	77:869cf507173a	1237	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
emilmont	77:869cf507173a	1238	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
emilmont	77:869cf507173a	1239	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
emilmont	77:869cf507173a	1240	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
emilmont	77:869cf507173a	1241	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
emilmont	77:869cf507173a	1242	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
emilmont	77:869cf507173a	1243	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
emilmont	77:869cf507173a	1244	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
emilmont	77:869cf507173a	1245	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
emilmont	77:869cf507173a	1246
emilmont	77:869cf507173a	1247	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
emilmont	77:869cf507173a	1248	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
emilmont	77:869cf507173a	1249	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
emilmont	77:869cf507173a	1250	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
emilmont	77:869cf507173a	1251	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
emilmont	77:869cf507173a	1252	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
emilmont	77:869cf507173a	1253	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
emilmont	77:869cf507173a	1254	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
emilmont	77:869cf507173a	1255	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
emilmont	77:869cf507173a	1256	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
emilmont	77:869cf507173a	1257	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
emilmont	77:869cf507173a	1258	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
emilmont	77:869cf507173a	1259
emilmont	77:869cf507173a	1260	/**
emilmont	77:869cf507173a	1261	* @}
emilmont	77:869cf507173a	1262	*/
emilmont	77:869cf507173a	1263
emilmont	77:869cf507173a	1264	/** @defgroup ETH_Tx_DMA_Burst_Length
emilmont	77:869cf507173a	1265	* @{
emilmont	77:869cf507173a	1266	*/
emilmont	77:869cf507173a	1267	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
emilmont	77:869cf507173a	1268	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
emilmont	77:869cf507173a	1269	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
emilmont	77:869cf507173a	1270	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
emilmont	77:869cf507173a	1271	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
emilmont	77:869cf507173a	1272	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
emilmont	77:869cf507173a	1273	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
emilmont	77:869cf507173a	1274	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
emilmont	77:869cf507173a	1275	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
emilmont	77:869cf507173a	1276	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
emilmont	77:869cf507173a	1277	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
emilmont	77:869cf507173a	1278	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
emilmont	77:869cf507173a	1279
emilmont	77:869cf507173a	1280	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
emilmont	77:869cf507173a	1281	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
emilmont	77:869cf507173a	1282	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
emilmont	77:869cf507173a	1283	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
emilmont	77:869cf507173a	1284	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
emilmont	77:869cf507173a	1285	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
emilmont	77:869cf507173a	1286	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
emilmont	77:869cf507173a	1287	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
emilmont	77:869cf507173a	1288	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
emilmont	77:869cf507173a	1289	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
emilmont	77:869cf507173a	1290	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
emilmont	77:869cf507173a	1291	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
emilmont	77:869cf507173a	1292
emilmont	77:869cf507173a	1293	/**
emilmont	77:869cf507173a	1294	* @brief ETH_DMA_Enhanced_descriptor_format
emilmont	77:869cf507173a	1295	*/
emilmont	77:869cf507173a	1296	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
emilmont	77:869cf507173a	1297	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1298
emilmont	77:869cf507173a	1299	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
emilmont	77:869cf507173a	1300	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
emilmont	77:869cf507173a	1301
emilmont	77:869cf507173a	1302	/**
emilmont	77:869cf507173a	1303	* @}
emilmont	77:869cf507173a	1304	*/
emilmont	77:869cf507173a	1305
emilmont	77:869cf507173a	1306	/**
emilmont	77:869cf507173a	1307	* @brief ETH DMA Descriptor SkipLength
emilmont	77:869cf507173a	1308	*/
emilmont	77:869cf507173a	1309	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
emilmont	77:869cf507173a	1310
emilmont	77:869cf507173a	1311
emilmont	77:869cf507173a	1312	/** @defgroup ETH_DMA_Arbitration
emilmont	77:869cf507173a	1313	* @{
emilmont	77:869cf507173a	1314	*/
emilmont	77:869cf507173a	1315	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	1316	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	1317	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	1318	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
emilmont	77:869cf507173a	1319	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
emilmont	77:869cf507173a	1320	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
emilmont	77:869cf507173a	1321	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
emilmont	77:869cf507173a	1322	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
emilmont	77:869cf507173a	1323	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
emilmont	77:869cf507173a	1324	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
emilmont	77:869cf507173a	1325	/**
emilmont	77:869cf507173a	1326	* @}
emilmont	77:869cf507173a	1327	*/
emilmont	77:869cf507173a	1328
emilmont	77:869cf507173a	1329	/** @defgroup ETH_DMA_Tx_descriptor_flags
emilmont	77:869cf507173a	1330	* @{
emilmont	77:869cf507173a	1331	*/
emilmont	77:869cf507173a	1332	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
emilmont	77:869cf507173a	1333	((FLAG) == ETH_DMATXDESC_IC) \|\| \
emilmont	77:869cf507173a	1334	((FLAG) == ETH_DMATXDESC_LS) \|\| \
emilmont	77:869cf507173a	1335	((FLAG) == ETH_DMATXDESC_FS) \|\| \
emilmont	77:869cf507173a	1336	((FLAG) == ETH_DMATXDESC_DC) \|\| \
emilmont	77:869cf507173a	1337	((FLAG) == ETH_DMATXDESC_DP) \|\| \
emilmont	77:869cf507173a	1338	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
emilmont	77:869cf507173a	1339	((FLAG) == ETH_DMATXDESC_TER) \|\| \
emilmont	77:869cf507173a	1340	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
emilmont	77:869cf507173a	1341	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
emilmont	77:869cf507173a	1342	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
emilmont	77:869cf507173a	1343	((FLAG) == ETH_DMATXDESC_ES) \|\| \
emilmont	77:869cf507173a	1344	((FLAG) == ETH_DMATXDESC_JT) \|\| \
emilmont	77:869cf507173a	1345	((FLAG) == ETH_DMATXDESC_FF) \|\| \
emilmont	77:869cf507173a	1346	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
emilmont	77:869cf507173a	1347	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
emilmont	77:869cf507173a	1348	((FLAG) == ETH_DMATXDESC_NC) \|\| \
emilmont	77:869cf507173a	1349	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
emilmont	77:869cf507173a	1350	((FLAG) == ETH_DMATXDESC_EC) \|\| \
emilmont	77:869cf507173a	1351	((FLAG) == ETH_DMATXDESC_VF) \|\| \
emilmont	77:869cf507173a	1352	((FLAG) == ETH_DMATXDESC_CC) \|\| \
emilmont	77:869cf507173a	1353	((FLAG) == ETH_DMATXDESC_ED) \|\| \
emilmont	77:869cf507173a	1354	((FLAG) == ETH_DMATXDESC_UF) \|\| \
emilmont	77:869cf507173a	1355	((FLAG) == ETH_DMATXDESC_DB))
emilmont	77:869cf507173a	1356
emilmont	77:869cf507173a	1357	/**
emilmont	77:869cf507173a	1358	* @}
emilmont	77:869cf507173a	1359	*/
emilmont	77:869cf507173a	1360
emilmont	77:869cf507173a	1361	/** @defgroup ETH_DMA_Tx_descriptor_segment
emilmont	77:869cf507173a	1362	* @{
emilmont	77:869cf507173a	1363	*/
emilmont	77:869cf507173a	1364	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
emilmont	77:869cf507173a	1365	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
emilmont	77:869cf507173a	1366	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
emilmont	77:869cf507173a	1367	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
emilmont	77:869cf507173a	1368
emilmont	77:869cf507173a	1369	/**
emilmont	77:869cf507173a	1370	* @}
emilmont	77:869cf507173a	1371	*/
emilmont	77:869cf507173a	1372
emilmont	77:869cf507173a	1373	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
emilmont	77:869cf507173a	1374	* @{
emilmont	77:869cf507173a	1375	*/
emilmont	77:869cf507173a	1376	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
emilmont	77:869cf507173a	1377	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
emilmont	77:869cf507173a	1378	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
emilmont	77:869cf507173a	1379	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
emilmont	77:869cf507173a	1380	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
emilmont	77:869cf507173a	1381	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
emilmont	77:869cf507173a	1382	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
emilmont	77:869cf507173a	1383	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
emilmont	77:869cf507173a	1384	/**
emilmont	77:869cf507173a	1385	* @brief ETH DMA Tx Desciptor buffer size
emilmont	77:869cf507173a	1386	*/
emilmont	77:869cf507173a	1387	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
emilmont	77:869cf507173a	1388
emilmont	77:869cf507173a	1389	/**
emilmont	77:869cf507173a	1390	* @}
emilmont	77:869cf507173a	1391	*/
emilmont	77:869cf507173a	1392
emilmont	77:869cf507173a	1393	/** @defgroup ETH_DMA_Rx_descriptor_flags
emilmont	77:869cf507173a	1394	* @{
emilmont	77:869cf507173a	1395	*/
emilmont	77:869cf507173a	1396	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
emilmont	77:869cf507173a	1397	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
emilmont	77:869cf507173a	1398	((FLAG) == ETH_DMARXDESC_ES) \|\| \
emilmont	77:869cf507173a	1399	((FLAG) == ETH_DMARXDESC_DE) \|\| \
emilmont	77:869cf507173a	1400	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
emilmont	77:869cf507173a	1401	((FLAG) == ETH_DMARXDESC_LE) \|\| \
emilmont	77:869cf507173a	1402	((FLAG) == ETH_DMARXDESC_OE) \|\| \
emilmont	77:869cf507173a	1403	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
emilmont	77:869cf507173a	1404	((FLAG) == ETH_DMARXDESC_FS) \|\| \
emilmont	77:869cf507173a	1405	((FLAG) == ETH_DMARXDESC_LS) \|\| \
emilmont	77:869cf507173a	1406	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
emilmont	77:869cf507173a	1407	((FLAG) == ETH_DMARXDESC_LC) \|\| \
emilmont	77:869cf507173a	1408	((FLAG) == ETH_DMARXDESC_FT) \|\| \
emilmont	77:869cf507173a	1409	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
emilmont	77:869cf507173a	1410	((FLAG) == ETH_DMARXDESC_RE) \|\| \
emilmont	77:869cf507173a	1411	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
emilmont	77:869cf507173a	1412	((FLAG) == ETH_DMARXDESC_CE) \|\| \
emilmont	77:869cf507173a	1413	((FLAG) == ETH_DMARXDESC_MAMPCE))
emilmont	77:869cf507173a	1414
emilmont	77:869cf507173a	1415	/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
emilmont	77:869cf507173a	1416	#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) \|\| \
emilmont	77:869cf507173a	1417	((FLAG) == ETH_DMAPTPRXDESC_PTPFT) \|\| \
emilmont	77:869cf507173a	1418	((FLAG) == ETH_DMAPTPRXDESC_PTPMT) \|\| \
emilmont	77:869cf507173a	1419	((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) \|\| \
emilmont	77:869cf507173a	1420	((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) \|\| \
emilmont	77:869cf507173a	1421	((FLAG) == ETH_DMAPTPRXDESC_IPCB) \|\| \
emilmont	77:869cf507173a	1422	((FLAG) == ETH_DMAPTPRXDESC_IPPE) \|\| \
emilmont	77:869cf507173a	1423	((FLAG) == ETH_DMAPTPRXDESC_IPHE) \|\| \
emilmont	77:869cf507173a	1424	((FLAG) == ETH_DMAPTPRXDESC_IPPT))
emilmont	77:869cf507173a	1425
emilmont	77:869cf507173a	1426	/**
emilmont	77:869cf507173a	1427	* @}
emilmont	77:869cf507173a	1428	*/
emilmont	77:869cf507173a	1429
emilmont	77:869cf507173a	1430	/** @defgroup ETH_DMA_Rx_descriptor_buffers_
emilmont	77:869cf507173a	1431	* @{
emilmont	77:869cf507173a	1432	*/
emilmont	77:869cf507173a	1433	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
emilmont	77:869cf507173a	1434	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
emilmont	77:869cf507173a	1435	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
emilmont	77:869cf507173a	1436	((BUFFER) == ETH_DMARXDESC_BUFFER2))
emilmont	77:869cf507173a	1437
emilmont	77:869cf507173a	1438
emilmont	77:869cf507173a	1439	/* ETHERNET DMA Tx descriptors Collision Count Shift */
emilmont	77:869cf507173a	1440	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
emilmont	77:869cf507173a	1441
emilmont	77:869cf507173a	1442	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
emilmont	77:869cf507173a	1443	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
emilmont	77:869cf507173a	1444
emilmont	77:869cf507173a	1445	/* ETHERNET DMA Rx descriptors Frame Length Shift */
emilmont	77:869cf507173a	1446	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
emilmont	77:869cf507173a	1447
emilmont	77:869cf507173a	1448	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
emilmont	77:869cf507173a	1449	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
emilmont	77:869cf507173a	1450
emilmont	77:869cf507173a	1451	/* ETHERNET DMA Rx descriptors Frame length Shift */
emilmont	77:869cf507173a	1452	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
emilmont	77:869cf507173a	1453
emilmont	77:869cf507173a	1454	/**
emilmont	77:869cf507173a	1455	* @}
emilmont	77:869cf507173a	1456	*/
emilmont	77:869cf507173a	1457
emilmont	77:869cf507173a	1458	/** @defgroup ETH_PMT_Flags
emilmont	77:869cf507173a	1459	* @{
emilmont	77:869cf507173a	1460	*/
emilmont	77:869cf507173a	1461	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
emilmont	77:869cf507173a	1462	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
emilmont	77:869cf507173a	1463	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
emilmont	77:869cf507173a	1464	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
emilmont	77:869cf507173a	1465	((FLAG) == ETH_PMT_FLAG_MPR))
emilmont	77:869cf507173a	1466	/**
emilmont	77:869cf507173a	1467	* @}
emilmont	77:869cf507173a	1468	*/
emilmont	77:869cf507173a	1469
emilmont	77:869cf507173a	1470	/** @defgroup ETH_MMC_Tx_Interrupts
emilmont	77:869cf507173a	1471	* @{
emilmont	77:869cf507173a	1472	*/
emilmont	77:869cf507173a	1473	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
emilmont	77:869cf507173a	1474	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
emilmont	77:869cf507173a	1475	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
emilmont	77:869cf507173a	1476
emilmont	77:869cf507173a	1477	/**
emilmont	77:869cf507173a	1478	* @}
emilmont	77:869cf507173a	1479	*/
emilmont	77:869cf507173a	1480
emilmont	77:869cf507173a	1481	/** @defgroup ETH_MMC_Rx_Interrupts
emilmont	77:869cf507173a	1482	* @{
emilmont	77:869cf507173a	1483	*/
emilmont	77:869cf507173a	1484	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
emilmont	77:869cf507173a	1485	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
emilmont	77:869cf507173a	1486	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
emilmont	77:869cf507173a	1487	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
emilmont	77:869cf507173a	1488	((IT) != 0x00))
emilmont	77:869cf507173a	1489	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
emilmont	77:869cf507173a	1490	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
emilmont	77:869cf507173a	1491	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
emilmont	77:869cf507173a	1492	/**
emilmont	77:869cf507173a	1493	* @}
emilmont	77:869cf507173a	1494	*/
emilmont	77:869cf507173a	1495
emilmont	77:869cf507173a	1496	/** @defgroup ETH_MMC_Registers
emilmont	77:869cf507173a	1497	* @{
emilmont	77:869cf507173a	1498	*/
emilmont	77:869cf507173a	1499	#define ETH_MMCCR ((uint32_t)0x00000100) /!< MMC CR register /
emilmont	77:869cf507173a	1500	#define ETH_MMCRIR ((uint32_t)0x00000104) /!< MMC RIR register /
emilmont	77:869cf507173a	1501	#define ETH_MMCTIR ((uint32_t)0x00000108) /!< MMC TIR register /
emilmont	77:869cf507173a	1502	#define ETH_MMCRIMR ((uint32_t)0x0000010C) /!< MMC RIMR register /
emilmont	77:869cf507173a	1503	#define ETH_MMCTIMR ((uint32_t)0x00000110) /!< MMC TIMR register /
emilmont	77:869cf507173a	1504	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /!< MMC TGFSCCR register /
emilmont	77:869cf507173a	1505	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /!< MMC TGFMSCCR register /
emilmont	77:869cf507173a	1506	#define ETH_MMCTGFCR ((uint32_t)0x00000168) /!< MMC TGFCR register /
emilmont	77:869cf507173a	1507	#define ETH_MMCRFCECR ((uint32_t)0x00000194) /!< MMC RFCECR register /
emilmont	77:869cf507173a	1508	#define ETH_MMCRFAECR ((uint32_t)0x00000198) /!< MMC RFAECR register /
emilmont	77:869cf507173a	1509	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /!< MMC RGUFCR register /
emilmont	77:869cf507173a	1510
emilmont	77:869cf507173a	1511	/**
emilmont	77:869cf507173a	1512	* @brief ETH MMC registers
emilmont	77:869cf507173a	1513	*/
emilmont	77:869cf507173a	1514	#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) \|\| ((REG) == ETH_MMCRIR) \|\| \
emilmont	77:869cf507173a	1515	((REG) == ETH_MMCTIR) \|\| ((REG) == ETH_MMCRIMR) \|\| \
emilmont	77:869cf507173a	1516	((REG) == ETH_MMCTIMR) \|\| ((REG) == ETH_MMCTGFSCCR) \|\| \
emilmont	77:869cf507173a	1517	((REG) == ETH_MMCTGFMSCCR) \|\| ((REG) == ETH_MMCTGFCR) \|\| \
emilmont	77:869cf507173a	1518	((REG) == ETH_MMCRFCECR) \|\| ((REG) == ETH_MMCRFAECR) \|\| \
emilmont	77:869cf507173a	1519	((REG) == ETH_MMCRGUFCR))
emilmont	77:869cf507173a	1520	/**
emilmont	77:869cf507173a	1521	* @}
emilmont	77:869cf507173a	1522	*/
emilmont	77:869cf507173a	1523
emilmont	77:869cf507173a	1524	/** @defgroup ETH_MAC_Flags
emilmont	77:869cf507173a	1525	* @{
emilmont	77:869cf507173a	1526	*/
emilmont	77:869cf507173a	1527	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
emilmont	77:869cf507173a	1528	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
emilmont	77:869cf507173a	1529	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
emilmont	77:869cf507173a	1530	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
emilmont	77:869cf507173a	1531	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
emilmont	77:869cf507173a	1532	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
emilmont	77:869cf507173a	1533	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
emilmont	77:869cf507173a	1534	((FLAG) == ETH_MAC_FLAG_PMT))
emilmont	77:869cf507173a	1535	/**
emilmont	77:869cf507173a	1536	* @}
emilmont	77:869cf507173a	1537	*/
emilmont	77:869cf507173a	1538
emilmont	77:869cf507173a	1539	/** @defgroup ETH_DMA_Flags
emilmont	77:869cf507173a	1540	* @{
emilmont	77:869cf507173a	1541	*/
emilmont	77:869cf507173a	1542	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
emilmont	77:869cf507173a	1543	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
emilmont	77:869cf507173a	1544	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
emilmont	77:869cf507173a	1545	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
emilmont	77:869cf507173a	1546	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write trnsf, 1-read transfr /
emilmont	77:869cf507173a	1547	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
emilmont	77:869cf507173a	1548	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
emilmont	77:869cf507173a	1549	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
emilmont	77:869cf507173a	1550	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
emilmont	77:869cf507173a	1551	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
emilmont	77:869cf507173a	1552	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
emilmont	77:869cf507173a	1553	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
emilmont	77:869cf507173a	1554	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
emilmont	77:869cf507173a	1555	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
emilmont	77:869cf507173a	1556	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
emilmont	77:869cf507173a	1557	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
emilmont	77:869cf507173a	1558	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
emilmont	77:869cf507173a	1559	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
emilmont	77:869cf507173a	1560	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
emilmont	77:869cf507173a	1561	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
emilmont	77:869cf507173a	1562	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
emilmont	77:869cf507173a	1563
emilmont	77:869cf507173a	1564	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
emilmont	77:869cf507173a	1565	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
emilmont	77:869cf507173a	1566	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
emilmont	77:869cf507173a	1567	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
emilmont	77:869cf507173a	1568	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
emilmont	77:869cf507173a	1569	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
emilmont	77:869cf507173a	1570	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
emilmont	77:869cf507173a	1571	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
emilmont	77:869cf507173a	1572	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
emilmont	77:869cf507173a	1573	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
emilmont	77:869cf507173a	1574	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
emilmont	77:869cf507173a	1575	((FLAG) == ETH_DMA_FLAG_T))
emilmont	77:869cf507173a	1576	/**
emilmont	77:869cf507173a	1577	* @}
emilmont	77:869cf507173a	1578	*/
emilmont	77:869cf507173a	1579
emilmont	77:869cf507173a	1580	/** @defgroup ETH_MAC_Interrupts
emilmont	77:869cf507173a	1581	* @{
emilmont	77:869cf507173a	1582	*/
emilmont	77:869cf507173a	1583	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
emilmont	77:869cf507173a	1584	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
emilmont	77:869cf507173a	1585	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
emilmont	77:869cf507173a	1586	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
emilmont	77:869cf507173a	1587	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
emilmont	77:869cf507173a	1588	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
emilmont	77:869cf507173a	1589	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
emilmont	77:869cf507173a	1590	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
emilmont	77:869cf507173a	1591	((IT) == ETH_MAC_IT_PMT))
emilmont	77:869cf507173a	1592	/**
emilmont	77:869cf507173a	1593	* @}
emilmont	77:869cf507173a	1594	*/
emilmont	77:869cf507173a	1595
emilmont	77:869cf507173a	1596	/** @defgroup ETH_DMA_Interrupts
emilmont	77:869cf507173a	1597	* @{
emilmont	77:869cf507173a	1598	*/
emilmont	77:869cf507173a	1599	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
emilmont	77:869cf507173a	1600	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
emilmont	77:869cf507173a	1601	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
emilmont	77:869cf507173a	1602	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
emilmont	77:869cf507173a	1603	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
emilmont	77:869cf507173a	1604	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
emilmont	77:869cf507173a	1605	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
emilmont	77:869cf507173a	1606	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
emilmont	77:869cf507173a	1607	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
emilmont	77:869cf507173a	1608	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
emilmont	77:869cf507173a	1609	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
emilmont	77:869cf507173a	1610	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
emilmont	77:869cf507173a	1611	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
emilmont	77:869cf507173a	1612	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
emilmont	77:869cf507173a	1613	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
emilmont	77:869cf507173a	1614	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
emilmont	77:869cf507173a	1615	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
emilmont	77:869cf507173a	1616	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
emilmont	77:869cf507173a	1617
emilmont	77:869cf507173a	1618	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
emilmont	77:869cf507173a	1619	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
emilmont	77:869cf507173a	1620	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
emilmont	77:869cf507173a	1621	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
emilmont	77:869cf507173a	1622	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
emilmont	77:869cf507173a	1623	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
emilmont	77:869cf507173a	1624	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
emilmont	77:869cf507173a	1625	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
emilmont	77:869cf507173a	1626	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
emilmont	77:869cf507173a	1627	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
emilmont	77:869cf507173a	1628
emilmont	77:869cf507173a	1629	/**
emilmont	77:869cf507173a	1630	* @}
emilmont	77:869cf507173a	1631	*/
emilmont	77:869cf507173a	1632
emilmont	77:869cf507173a	1633	/** @defgroup ETH_DMA_transmit_process_state_
emilmont	77:869cf507173a	1634	* @{
emilmont	77:869cf507173a	1635	*/
emilmont	77:869cf507173a	1636	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
emilmont	77:869cf507173a	1637	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
emilmont	77:869cf507173a	1638	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
emilmont	77:869cf507173a	1639	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
emilmont	77:869cf507173a	1640	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
emilmont	77:869cf507173a	1641	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
emilmont	77:869cf507173a	1642
emilmont	77:869cf507173a	1643	/**
emilmont	77:869cf507173a	1644	* @}
emilmont	77:869cf507173a	1645	*/
emilmont	77:869cf507173a	1646
emilmont	77:869cf507173a	1647
emilmont	77:869cf507173a	1648	/** @defgroup ETH_DMA_receive_process_state_
emilmont	77:869cf507173a	1649	* @{
emilmont	77:869cf507173a	1650	*/
emilmont	77:869cf507173a	1651	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
emilmont	77:869cf507173a	1652	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
emilmont	77:869cf507173a	1653	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
emilmont	77:869cf507173a	1654	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
emilmont	77:869cf507173a	1655	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
emilmont	77:869cf507173a	1656	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
emilmont	77:869cf507173a	1657
emilmont	77:869cf507173a	1658	/**
emilmont	77:869cf507173a	1659	* @}
emilmont	77:869cf507173a	1660	*/
emilmont	77:869cf507173a	1661
emilmont	77:869cf507173a	1662	/** @defgroup ETH_DMA_overflow_
emilmont	77:869cf507173a	1663	* @{
emilmont	77:869cf507173a	1664	*/
emilmont	77:869cf507173a	1665	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
emilmont	77:869cf507173a	1666	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
emilmont	77:869cf507173a	1667	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
emilmont	77:869cf507173a	1668	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
emilmont	77:869cf507173a	1669	/**
emilmont	77:869cf507173a	1670	* @}
emilmont	77:869cf507173a	1671	*/
emilmont	77:869cf507173a	1672
emilmont	77:869cf507173a	1673	/* ETHERNET MAC address offsets */
emilmont	77:869cf507173a	1674	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
emilmont	77:869cf507173a	1675	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
emilmont	77:869cf507173a	1676
emilmont	77:869cf507173a	1677	/* ETHERNET MACMIIAR register Mask */
emilmont	77:869cf507173a	1678	#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
emilmont	77:869cf507173a	1679
emilmont	77:869cf507173a	1680	/* ETHERNET MACCR register Mask */
emilmont	77:869cf507173a	1681	#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
emilmont	77:869cf507173a	1682
emilmont	77:869cf507173a	1683	/* ETHERNET MACFCR register Mask */
emilmont	77:869cf507173a	1684	#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
emilmont	77:869cf507173a	1685
emilmont	77:869cf507173a	1686
emilmont	77:869cf507173a	1687	/* ETHERNET DMAOMR register Mask */
emilmont	77:869cf507173a	1688	#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
emilmont	77:869cf507173a	1689
emilmont	77:869cf507173a	1690
emilmont	77:869cf507173a	1691	/* ETHERNET Remote Wake-up frame register length */
emilmont	77:869cf507173a	1692	#define ETH_WAKEUP_REGISTER_LENGTH 8
emilmont	77:869cf507173a	1693
emilmont	77:869cf507173a	1694	/* ETHERNET Missed frames counter Shift */
emilmont	77:869cf507173a	1695	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
emilmont	77:869cf507173a	1696
emilmont	77:869cf507173a	1697	/**
emilmont	77:869cf507173a	1698	* @}
emilmont	77:869cf507173a	1699	*/
emilmont	77:869cf507173a	1700
emilmont	77:869cf507173a	1701	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	1702
emilmont	77:869cf507173a	1703	/**
emilmont	77:869cf507173a	1704	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
emilmont	77:869cf507173a	1705	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1706	* @param __FLAG__: specifies the flag to check.
emilmont	77:869cf507173a	1707	* @retval the ETH_DMATxDescFlag (SET or RESET).
emilmont	77:869cf507173a	1708	*/
emilmont	77:869cf507173a	1709	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
emilmont	77:869cf507173a	1710
emilmont	77:869cf507173a	1711	/**
emilmont	77:869cf507173a	1712	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
emilmont	77:869cf507173a	1713	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1714	* @param __FLAG__: specifies the flag to check.
emilmont	77:869cf507173a	1715	* @retval the ETH_DMATxDescFlag (SET or RESET).
emilmont	77:869cf507173a	1716	*/
emilmont	77:869cf507173a	1717	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
emilmont	77:869cf507173a	1718
emilmont	77:869cf507173a	1719	/**
emilmont	77:869cf507173a	1720	* @brief Enables the specified DMA Rx Desc receive interrupt.
emilmont	77:869cf507173a	1721	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1722	* @retval None
emilmont	77:869cf507173a	1723	*/
emilmont	77:869cf507173a	1724	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
emilmont	77:869cf507173a	1725
emilmont	77:869cf507173a	1726	/**
emilmont	77:869cf507173a	1727	* @brief Disables the specified DMA Rx Desc receive interrupt.
emilmont	77:869cf507173a	1728	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1729	* @retval None
emilmont	77:869cf507173a	1730	*/
emilmont	77:869cf507173a	1731	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
emilmont	77:869cf507173a	1732
emilmont	77:869cf507173a	1733	/**
emilmont	77:869cf507173a	1734	* @brief Set the specified DMA Rx Desc Own bit.
emilmont	77:869cf507173a	1735	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1736	* @retval None
emilmont	77:869cf507173a	1737	*/
emilmont	77:869cf507173a	1738	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
emilmont	77:869cf507173a	1739
emilmont	77:869cf507173a	1740	/**
emilmont	77:869cf507173a	1741	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
emilmont	77:869cf507173a	1742	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1743	* @retval The Transmit descriptor collision counter value.
emilmont	77:869cf507173a	1744	*/
emilmont	77:869cf507173a	1745	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
emilmont	77:869cf507173a	1746
emilmont	77:869cf507173a	1747	/**
emilmont	77:869cf507173a	1748	* @brief Set the specified DMA Tx Desc Own bit.
emilmont	77:869cf507173a	1749	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1750	* @retval None
emilmont	77:869cf507173a	1751	*/
emilmont	77:869cf507173a	1752	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
emilmont	77:869cf507173a	1753
emilmont	77:869cf507173a	1754	/**
emilmont	77:869cf507173a	1755	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
emilmont	77:869cf507173a	1756	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1757	* @retval None
emilmont	77:869cf507173a	1758	*/
emilmont	77:869cf507173a	1759	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
emilmont	77:869cf507173a	1760
emilmont	77:869cf507173a	1761	/**
emilmont	77:869cf507173a	1762	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
emilmont	77:869cf507173a	1763	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1764	* @retval None
emilmont	77:869cf507173a	1765	*/
emilmont	77:869cf507173a	1766	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
emilmont	77:869cf507173a	1767
emilmont	77:869cf507173a	1768	/**
emilmont	77:869cf507173a	1769	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
emilmont	77:869cf507173a	1770	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1771	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
emilmont	77:869cf507173a	1772	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1773	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
emilmont	77:869cf507173a	1774	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
emilmont	77:869cf507173a	1775	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
emilmont	77:869cf507173a	1776	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
emilmont	77:869cf507173a	1777	* @retval None
emilmont	77:869cf507173a	1778	*/
emilmont	77:869cf507173a	1779	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
emilmont	77:869cf507173a	1780
emilmont	77:869cf507173a	1781	/**
emilmont	77:869cf507173a	1782	* @brief Enables the DMA Tx Desc CRC.
emilmont	77:869cf507173a	1783	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1784	* @retval None
emilmont	77:869cf507173a	1785	*/
emilmont	77:869cf507173a	1786	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
emilmont	77:869cf507173a	1787
emilmont	77:869cf507173a	1788	/**
emilmont	77:869cf507173a	1789	* @brief Disables the DMA Tx Desc CRC.
emilmont	77:869cf507173a	1790	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1791	* @retval None
emilmont	77:869cf507173a	1792	*/
emilmont	77:869cf507173a	1793	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
emilmont	77:869cf507173a	1794
emilmont	77:869cf507173a	1795	/**
emilmont	77:869cf507173a	1796	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
emilmont	77:869cf507173a	1797	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1798	* @retval None
emilmont	77:869cf507173a	1799	*/
emilmont	77:869cf507173a	1800	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
emilmont	77:869cf507173a	1801
emilmont	77:869cf507173a	1802	/**
emilmont	77:869cf507173a	1803	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
emilmont	77:869cf507173a	1804	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1805	* @retval None
emilmont	77:869cf507173a	1806	*/
emilmont	77:869cf507173a	1807	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
emilmont	77:869cf507173a	1808
emilmont	77:869cf507173a	1809	/**
emilmont	77:869cf507173a	1810	* @brief Enables the specified ETHERNET MAC interrupts.
emilmont	77:869cf507173a	1811	* @param __HANDLE__ : ETH Handle
emilmont	77:869cf507173a	1812	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
emilmont	77:869cf507173a	1813	* enabled or disabled.
emilmont	77:869cf507173a	1814	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1815	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
emilmont	77:869cf507173a	1816	* @arg ETH_MAC_IT_PMT : PMT interrupt
emilmont	77:869cf507173a	1817	* @retval None
emilmont	77:869cf507173a	1818	*/
emilmont	77:869cf507173a	1819	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1820
emilmont	77:869cf507173a	1821	/**
emilmont	77:869cf507173a	1822	* @brief Disables the specified ETHERNET MAC interrupts.
emilmont	77:869cf507173a	1823	* @param __HANDLE__ : ETH Handle
emilmont	77:869cf507173a	1824	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
emilmont	77:869cf507173a	1825	* enabled or disabled.
emilmont	77:869cf507173a	1826	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1827	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
emilmont	77:869cf507173a	1828	* @arg ETH_MAC_IT_PMT : PMT interrupt
emilmont	77:869cf507173a	1829	* @retval None
emilmont	77:869cf507173a	1830	*/
emilmont	77:869cf507173a	1831	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1832
emilmont	77:869cf507173a	1833	/**
emilmont	77:869cf507173a	1834	* @brief Initiate a Pause Control Frame (Full-duplex only).
emilmont	77:869cf507173a	1835	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1836	* @retval None
emilmont	77:869cf507173a	1837	*/
emilmont	77:869cf507173a	1838	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
emilmont	77:869cf507173a	1839
emilmont	77:869cf507173a	1840	/**
emilmont	77:869cf507173a	1841	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
emilmont	77:869cf507173a	1842	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1843	* @retval The new state of flow control busy status bit (SET or RESET).
emilmont	77:869cf507173a	1844	*/
emilmont	77:869cf507173a	1845	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
emilmont	77:869cf507173a	1846
emilmont	77:869cf507173a	1847	/**
emilmont	77:869cf507173a	1848	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
emilmont	77:869cf507173a	1849	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1850	* @retval None
emilmont	77:869cf507173a	1851	*/
emilmont	77:869cf507173a	1852	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
emilmont	77:869cf507173a	1853
emilmont	77:869cf507173a	1854	/**
emilmont	77:869cf507173a	1855	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
emilmont	77:869cf507173a	1856	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1857	* @retval None
emilmont	77:869cf507173a	1858	*/
emilmont	77:869cf507173a	1859	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
emilmont	77:869cf507173a	1860
emilmont	77:869cf507173a	1861	/**
emilmont	77:869cf507173a	1862	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
emilmont	77:869cf507173a	1863	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1864	* @param __FLAG__: specifies the flag to check.
emilmont	77:869cf507173a	1865	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1866	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
emilmont	77:869cf507173a	1867	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
emilmont	77:869cf507173a	1868	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
emilmont	77:869cf507173a	1869	* @arg ETH_MAC_FLAG_MMC : MMC flag
emilmont	77:869cf507173a	1870	* @arg ETH_MAC_FLAG_PMT : PMT flag
emilmont	77:869cf507173a	1871	* @retval The state of ETHERNET MAC flag.
emilmont	77:869cf507173a	1872	*/
emilmont	77:869cf507173a	1873	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
emilmont	77:869cf507173a	1874
emilmont	77:869cf507173a	1875	/**
emilmont	77:869cf507173a	1876	* @brief Clears the specified ETHERNET MAC flag.
emilmont	77:869cf507173a	1877	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1878	* @param __FLAG__: specifies the flag to clear.
emilmont	77:869cf507173a	1879	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1880	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
emilmont	77:869cf507173a	1881	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
emilmont	77:869cf507173a	1882	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
emilmont	77:869cf507173a	1883	* @arg ETH_MAC_FLAG_MMC : MMC flag
emilmont	77:869cf507173a	1884	* @arg ETH_MAC_FLAG_PMT : PMT flag
emilmont	77:869cf507173a	1885	* @retval None.
emilmont	77:869cf507173a	1886	*/
emilmont	77:869cf507173a	1887	#define __HAL_ETH_MAC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->MACSR &= ~(__FLAG__))
emilmont	77:869cf507173a	1888
emilmont	77:869cf507173a	1889	/**
emilmont	77:869cf507173a	1890	* @brief Enables the specified ETHERNET DMA interrupts.
emilmont	77:869cf507173a	1891	* @param __HANDLE__ : ETH Handle
emilmont	77:869cf507173a	1892	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
emilmont	77:869cf507173a	1893	* enabled @defgroup ETH_DMA_Interrupts
emilmont	77:869cf507173a	1894	* @retval None
emilmont	77:869cf507173a	1895	*/
emilmont	77:869cf507173a	1896	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1897
emilmont	77:869cf507173a	1898	/**
emilmont	77:869cf507173a	1899	* @brief Disables the specified ETHERNET DMA interrupts.
emilmont	77:869cf507173a	1900	* @param __HANDLE__ : ETH Handle
emilmont	77:869cf507173a	1901	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
emilmont	77:869cf507173a	1902	* disabled. @defgroup ETH_DMA_Interrupts
emilmont	77:869cf507173a	1903	* @retval None
emilmont	77:869cf507173a	1904	*/
emilmont	77:869cf507173a	1905	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1906
emilmont	77:869cf507173a	1907	/**
emilmont	77:869cf507173a	1908	* @brief Clears the ETHERNET DMA IT pending bit.
emilmont	77:869cf507173a	1909	* @param __HANDLE__ : ETH Handle
emilmont	77:869cf507173a	1910	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
emilmont	77:869cf507173a	1911	* @retval None
emilmont	77:869cf507173a	1912	*/
emilmont	77:869cf507173a	1913	#define __HAL_ETH_DMA_CLEAR_IT_PENDING_BIT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
emilmont	77:869cf507173a	1914
emilmont	77:869cf507173a	1915	/**
emilmont	77:869cf507173a	1916	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
emilmont	77:869cf507173a	1917	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1918	* @param __FLAG__: specifies the flag to check.
emilmont	77:869cf507173a	1919	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
emilmont	77:869cf507173a	1920	*/
emilmont	77:869cf507173a	1921	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
emilmont	77:869cf507173a	1922
emilmont	77:869cf507173a	1923	/**
emilmont	77:869cf507173a	1924	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
emilmont	77:869cf507173a	1925	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1926	* @param __FLAG__: specifies the flag to clear.
emilmont	77:869cf507173a	1927	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
emilmont	77:869cf507173a	1928	*/
emilmont	77:869cf507173a	1929	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR &= ~(__FLAG__))
emilmont	77:869cf507173a	1930
emilmont	77:869cf507173a	1931	/**
emilmont	77:869cf507173a	1932	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
emilmont	77:869cf507173a	1933	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1934	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
emilmont	77:869cf507173a	1935	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1936	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
emilmont	77:869cf507173a	1937	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
emilmont	77:869cf507173a	1938	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
emilmont	77:869cf507173a	1939	*/
emilmont	77:869cf507173a	1940	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
emilmont	77:869cf507173a	1941
emilmont	77:869cf507173a	1942	/**
emilmont	77:869cf507173a	1943	* @brief Set the DMA Receive status watchdog timer register value
emilmont	77:869cf507173a	1944	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1945	* @param __VALUE__: DMA Receive status watchdog timer register value
emilmont	77:869cf507173a	1946	* @retval None
emilmont	77:869cf507173a	1947	*/
emilmont	77:869cf507173a	1948	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
emilmont	77:869cf507173a	1949
emilmont	77:869cf507173a	1950	/**
emilmont	77:869cf507173a	1951	* @brief Enables any unicast packet filtered by the MAC address
emilmont	77:869cf507173a	1952	* recognition to be a wake-up frame.
emilmont	77:869cf507173a	1953	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	1954	* @retval None
emilmont	77:869cf507173a	1955	*/
emilmont	77:869cf507173a	1956	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
emilmont	77:869cf507173a	1957
emilmont	77:869cf507173a	1958	/**
emilmont	77:869cf507173a	1959	* @brief Disables any unicast packet filtered by the MAC address
emilmont	77:869cf507173a	1960	* recognition to be a wake-up frame.
emilmont	77:869cf507173a	1961	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	1962	* @retval None
emilmont	77:869cf507173a	1963	*/
emilmont	77:869cf507173a	1964	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
emilmont	77:869cf507173a	1965
emilmont	77:869cf507173a	1966	/**
emilmont	77:869cf507173a	1967	* @brief Enables the MAC Wake-Up Frame Detection.
emilmont	77:869cf507173a	1968	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	1969	* @retval None
emilmont	77:869cf507173a	1970	*/
emilmont	77:869cf507173a	1971	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
emilmont	77:869cf507173a	1972
emilmont	77:869cf507173a	1973	/**
emilmont	77:869cf507173a	1974	* @brief Disables the MAC Wake-Up Frame Detection.
emilmont	77:869cf507173a	1975	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	1976	* @retval None
emilmont	77:869cf507173a	1977	*/
emilmont	77:869cf507173a	1978	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
emilmont	77:869cf507173a	1979
emilmont	77:869cf507173a	1980	/**
emilmont	77:869cf507173a	1981	* @brief Enables the MAC Magic Packet Detection.
emilmont	77:869cf507173a	1982	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	1983	* @retval None
emilmont	77:869cf507173a	1984	*/
emilmont	77:869cf507173a	1985	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
emilmont	77:869cf507173a	1986
emilmont	77:869cf507173a	1987	/**
emilmont	77:869cf507173a	1988	* @brief Disables the MAC Magic Packet Detection.
emilmont	77:869cf507173a	1989	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	1990	* @retval None
emilmont	77:869cf507173a	1991	*/
emilmont	77:869cf507173a	1992	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
emilmont	77:869cf507173a	1993
emilmont	77:869cf507173a	1994	/**
emilmont	77:869cf507173a	1995	* @brief Enables the MAC Power Down.
emilmont	77:869cf507173a	1996	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	1997	* @retval None
emilmont	77:869cf507173a	1998	*/
emilmont	77:869cf507173a	1999	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
emilmont	77:869cf507173a	2000
emilmont	77:869cf507173a	2001	/**
emilmont	77:869cf507173a	2002	* @brief Disables the MAC Power Down.
emilmont	77:869cf507173a	2003	* @param __HANDLE__: ETH Handle
emilmont	77:869cf507173a	2004	* @retval None
emilmont	77:869cf507173a	2005	*/
emilmont	77:869cf507173a	2006	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
emilmont	77:869cf507173a	2007
emilmont	77:869cf507173a	2008	/**
emilmont	77:869cf507173a	2009	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
emilmont	77:869cf507173a	2010	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2011	* @param __FLAG__: specifies the flag to check.
emilmont	77:869cf507173a	2012	* This parameter can be one of the following values:
emilmont	77:869cf507173a	2013	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
emilmont	77:869cf507173a	2014	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
emilmont	77:869cf507173a	2015	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
emilmont	77:869cf507173a	2016	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
emilmont	77:869cf507173a	2017	*/
emilmont	77:869cf507173a	2018	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
emilmont	77:869cf507173a	2019
emilmont	77:869cf507173a	2020	/**
emilmont	77:869cf507173a	2021	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
emilmont	77:869cf507173a	2022	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2023	* @retval None
emilmont	77:869cf507173a	2024	*/
emilmont	77:869cf507173a	2025	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
emilmont	77:869cf507173a	2026
emilmont	77:869cf507173a	2027	/**
emilmont	77:869cf507173a	2028	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
emilmont	77:869cf507173a	2029	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2030	* @retval None
emilmont	77:869cf507173a	2031	*/
emilmont	77:869cf507173a	2032	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
emilmont	77:869cf507173a	2033	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
emilmont	77:869cf507173a	2034
emilmont	77:869cf507173a	2035	/**
emilmont	77:869cf507173a	2036	* @brief Enables the MMC Counter Freeze.
emilmont	77:869cf507173a	2037	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2038	* @retval None
emilmont	77:869cf507173a	2039	*/
emilmont	77:869cf507173a	2040	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
emilmont	77:869cf507173a	2041
emilmont	77:869cf507173a	2042	/**
emilmont	77:869cf507173a	2043	* @brief Disables the MMC Counter Freeze.
emilmont	77:869cf507173a	2044	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2045	* @retval None
emilmont	77:869cf507173a	2046	*/
emilmont	77:869cf507173a	2047	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
emilmont	77:869cf507173a	2048
emilmont	77:869cf507173a	2049	/**
emilmont	77:869cf507173a	2050	* @brief Enables the MMC Reset On Read.
emilmont	77:869cf507173a	2051	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2052	* @retval None
emilmont	77:869cf507173a	2053	*/
emilmont	77:869cf507173a	2054	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
emilmont	77:869cf507173a	2055
emilmont	77:869cf507173a	2056	/**
emilmont	77:869cf507173a	2057	* @brief Disables the MMC Reset On Read.
emilmont	77:869cf507173a	2058	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2059	* @retval None
emilmont	77:869cf507173a	2060	*/
emilmont	77:869cf507173a	2061	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
emilmont	77:869cf507173a	2062
emilmont	77:869cf507173a	2063	/**
emilmont	77:869cf507173a	2064	* @brief Enables the MMC Counter Stop Rollover.
emilmont	77:869cf507173a	2065	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2066	* @retval None
emilmont	77:869cf507173a	2067	*/
emilmont	77:869cf507173a	2068	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
emilmont	77:869cf507173a	2069
emilmont	77:869cf507173a	2070	/**
emilmont	77:869cf507173a	2071	* @brief Disables the MMC Counter Stop Rollover.
emilmont	77:869cf507173a	2072	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2073	* @retval None
emilmont	77:869cf507173a	2074	*/
emilmont	77:869cf507173a	2075	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
emilmont	77:869cf507173a	2076
emilmont	77:869cf507173a	2077	/**
emilmont	77:869cf507173a	2078	* @brief Resets the MMC Counters.
emilmont	77:869cf507173a	2079	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2080	* @retval None
emilmont	77:869cf507173a	2081	*/
emilmont	77:869cf507173a	2082	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
emilmont	77:869cf507173a	2083
emilmont	77:869cf507173a	2084	/**
emilmont	77:869cf507173a	2085	* @brief Enables the specified ETHERNET MMC Rx interrupts.
emilmont	77:869cf507173a	2086	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2087	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
emilmont	77:869cf507173a	2088	* This parameter can be one of the following values:
emilmont	77:869cf507173a	2089	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
emilmont	77:869cf507173a	2090	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
emilmont	77:869cf507173a	2091	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
emilmont	77:869cf507173a	2092	* @retval None
emilmont	77:869cf507173a	2093	*/
emilmont	77:869cf507173a	2094	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
emilmont	77:869cf507173a	2095	/**
emilmont	77:869cf507173a	2096	* @brief Disables the specified ETHERNET MMC Rx interrupts.
emilmont	77:869cf507173a	2097	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2098	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
emilmont	77:869cf507173a	2099	* This parameter can be one of the following values:
emilmont	77:869cf507173a	2100	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
emilmont	77:869cf507173a	2101	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
emilmont	77:869cf507173a	2102	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
emilmont	77:869cf507173a	2103	* @retval None
emilmont	77:869cf507173a	2104	*/
emilmont	77:869cf507173a	2105	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
emilmont	77:869cf507173a	2106	/**
emilmont	77:869cf507173a	2107	* @brief Enables the specified ETHERNET MMC Tx interrupts.
emilmont	77:869cf507173a	2108	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2109	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
emilmont	77:869cf507173a	2110	* This parameter can be one of the following values:
emilmont	77:869cf507173a	2111	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
emilmont	77:869cf507173a	2112	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
emilmont	77:869cf507173a	2113	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
emilmont	77:869cf507173a	2114	* @retval None
emilmont	77:869cf507173a	2115	*/
emilmont	77:869cf507173a	2116	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
emilmont	77:869cf507173a	2117
emilmont	77:869cf507173a	2118	/**
emilmont	77:869cf507173a	2119	* @brief Disables the specified ETHERNET MMC Tx interrupts.
emilmont	77:869cf507173a	2120	* @param __HANDLE__: ETH Handle.
emilmont	77:869cf507173a	2121	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
emilmont	77:869cf507173a	2122	* This parameter can be one of the following values:
emilmont	77:869cf507173a	2123	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
emilmont	77:869cf507173a	2124	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
emilmont	77:869cf507173a	2125	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
emilmont	77:869cf507173a	2126	* @retval None
emilmont	77:869cf507173a	2127	*/
emilmont	77:869cf507173a	2128	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
emilmont	77:869cf507173a	2129
emilmont	77:869cf507173a	2130
emilmont	77:869cf507173a	2131
emilmont	77:869cf507173a	2132	/* Exported functions --------------------------------------------------------*/
emilmont	77:869cf507173a	2133
emilmont	77:869cf507173a	2134	/* Initialization and de-initialization functions ****************************/
emilmont	77:869cf507173a	2135	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2136	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2137	__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2138	__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2139	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
emilmont	77:869cf507173a	2140	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
emilmont	77:869cf507173a	2141
emilmont	77:869cf507173a	2142	/* IO operation functions ****************************************************/
emilmont	77:869cf507173a	2143	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
emilmont	77:869cf507173a	2144	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2145
emilmont	77:869cf507173a	2146	/* Non-Blocking mode: Interrupt */
emilmont	77:869cf507173a	2147	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2148	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2149
emilmont	77:869cf507173a	2150	/* Callback in non blocking modes (Interrupt) */
emilmont	77:869cf507173a	2151	__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2152	__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2153	__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2154
emilmont	77:869cf507173a	2155	/* Cmmunication with PHY functions*/
emilmont	77:869cf507173a	2156	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
emilmont	77:869cf507173a	2157	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
emilmont	77:869cf507173a	2158
emilmont	77:869cf507173a	2159	/* Peripheral Control functions **********************************************/
emilmont	77:869cf507173a	2160	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2161	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2162
emilmont	77:869cf507173a	2163	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
emilmont	77:869cf507173a	2164	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
emilmont	77:869cf507173a	2165
emilmont	77:869cf507173a	2166	/* Peripheral State functions ************************************************/
emilmont	77:869cf507173a	2167	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
emilmont	77:869cf507173a	2168
emilmont	77:869cf507173a	2169	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
emilmont	77:869cf507173a	2170	/**
emilmont	77:869cf507173a	2171	* @}
emilmont	77:869cf507173a	2172	*/
emilmont	77:869cf507173a	2173
emilmont	77:869cf507173a	2174	/**
emilmont	77:869cf507173a	2175	* @}
emilmont	77:869cf507173a	2176	*/
emilmont	77:869cf507173a	2177
emilmont	77:869cf507173a	2178	#ifdef __cplusplus
emilmont	77:869cf507173a	2179	}
emilmont	77:869cf507173a	2180	#endif
emilmont	77:869cf507173a	2181
emilmont	77:869cf507173a	2182	#endif /* __STM32F4xx_HAL_ETH_H */
emilmont	77:869cf507173a	2183
emilmont	77:869cf507173a	2184
emilmont	77:869cf507173a	2185
emilmont	77:869cf507173a	2186	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	03 May 2015
Imports:	4
Forks:	0
Commits:	100
Dependents:	0
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Followers:	2

TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.h@77:869cf507173a, 2014-02-14 (annotated)

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