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TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
90:cb3d968589d8 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_rcc_ex.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.1.0
Kojto 90:cb3d968589d8 6 * @date 19-June-2014
emilmont 77:869cf507173a 7 * @brief Header file of RCC HAL Extension module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_RCC_EX_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_RCC_EX_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup RCCEx
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 59 /**
emilmont 77:869cf507173a 60 * @brief PLLI2S Clock structure definition
emilmont 77:869cf507173a 61 */
emilmont 77:869cf507173a 62 typedef struct
emilmont 77:869cf507173a 63 {
bogdanm 85:024bf7f99721 64 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 85:024bf7f99721 65 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont 77:869cf507173a 66 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 67
bogdanm 85:024bf7f99721 68 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm 85:024bf7f99721 69 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont 77:869cf507173a 70 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 71
emilmont 77:869cf507173a 72 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm 85:024bf7f99721 73 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont 77:869cf507173a 74 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
emilmont 77:869cf507173a 75 }RCC_PLLI2SInitTypeDef;
emilmont 77:869cf507173a 76
emilmont 77:869cf507173a 77 /**
emilmont 77:869cf507173a 78 * @brief PLLSAI Clock structure definition
emilmont 77:869cf507173a 79 */
emilmont 77:869cf507173a 80 typedef struct
emilmont 77:869cf507173a 81 {
emilmont 77:869cf507173a 82 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
bogdanm 85:024bf7f99721 83 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont 77:869cf507173a 84 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
bogdanm 85:024bf7f99721 87 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont 77:869cf507173a 88 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
emilmont 77:869cf507173a 89
emilmont 77:869cf507173a 90 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
bogdanm 85:024bf7f99721 91 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont 77:869cf507173a 92 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
emilmont 77:869cf507173a 93
emilmont 77:869cf507173a 94 }RCC_PLLSAIInitTypeDef;
emilmont 77:869cf507173a 95 /**
emilmont 77:869cf507173a 96 * @brief RCC extended clocks structure definition
emilmont 77:869cf507173a 97 */
emilmont 77:869cf507173a 98 typedef struct
emilmont 77:869cf507173a 99 {
emilmont 77:869cf507173a 100 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
emilmont 77:869cf507173a 101 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
emilmont 77:869cf507173a 102
bogdanm 85:024bf7f99721 103 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
emilmont 77:869cf507173a 104 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 105
bogdanm 85:024bf7f99721 106 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
emilmont 77:869cf507173a 107 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
emilmont 77:869cf507173a 108
bogdanm 85:024bf7f99721 109 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
emilmont 77:869cf507173a 110 This parameter must be a number between Min_Data = 1 and Max_Data = 32
emilmont 77:869cf507173a 111 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
emilmont 77:869cf507173a 112
emilmont 77:869cf507173a 113 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
emilmont 77:869cf507173a 114 This parameter must be a number between Min_Data = 1 and Max_Data = 32
emilmont 77:869cf507173a 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
emilmont 77:869cf507173a 116
emilmont 77:869cf507173a 117 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
emilmont 77:869cf507173a 118 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
emilmont 77:869cf507173a 119
bogdanm 85:024bf7f99721 120 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
emilmont 77:869cf507173a 121 This parameter can be a value of @ref RCC_RTC_Clock_Source */
emilmont 77:869cf507173a 122
bogdanm 85:024bf7f99721 123 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
emilmont 77:869cf507173a 124 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
emilmont 77:869cf507173a 125
emilmont 77:869cf507173a 126 }RCC_PeriphCLKInitTypeDef;
emilmont 77:869cf507173a 127 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 128
Kojto 90:cb3d968589d8 129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
Kojto 90:cb3d968589d8 130 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
emilmont 77:869cf507173a 131 /**
emilmont 77:869cf507173a 132 * @brief PLLI2S Clock structure definition
emilmont 77:869cf507173a 133 */
emilmont 77:869cf507173a 134 typedef struct
emilmont 77:869cf507173a 135 {
Kojto 90:cb3d968589d8 136 #if defined(STM32F411xE)
Kojto 90:cb3d968589d8 137 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
Kojto 90:cb3d968589d8 138 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
Kojto 90:cb3d968589d8 139 #endif /* STM32F411xE */
Kojto 90:cb3d968589d8 140
bogdanm 85:024bf7f99721 141 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
emilmont 77:869cf507173a 142 This parameter must be a number between Min_Data = 192 and Max_Data = 432
emilmont 77:869cf507173a 143 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 144
bogdanm 85:024bf7f99721 145 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
bogdanm 85:024bf7f99721 146 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont 77:869cf507173a 147 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 148
emilmont 77:869cf507173a 149 }RCC_PLLI2SInitTypeDef;
emilmont 77:869cf507173a 150
emilmont 77:869cf507173a 151
emilmont 77:869cf507173a 152 /**
emilmont 77:869cf507173a 153 * @brief RCC extended clocks structure definition
emilmont 77:869cf507173a 154 */
emilmont 77:869cf507173a 155 typedef struct
emilmont 77:869cf507173a 156 {
emilmont 77:869cf507173a 157 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
emilmont 77:869cf507173a 158 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
emilmont 77:869cf507173a 159
bogdanm 85:024bf7f99721 160 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
emilmont 77:869cf507173a 161 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
emilmont 77:869cf507173a 162
bogdanm 85:024bf7f99721 163 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto 90:cb3d968589d8 164 This parameter can be a value of @ref RCC_RTC_Clock_Source */
emilmont 77:869cf507173a 165
emilmont 77:869cf507173a 166 }RCC_PeriphCLKInitTypeDef;
Kojto 90:cb3d968589d8 167 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
emilmont 77:869cf507173a 168 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 169 /** @defgroup RCCEx_Exported_Constants
emilmont 77:869cf507173a 170 * @{
emilmont 77:869cf507173a 171 */
emilmont 77:869cf507173a 172
emilmont 77:869cf507173a 173 /** @defgroup RCCEx_Periph_Clock_Selection
emilmont 77:869cf507173a 174 * @{
emilmont 77:869cf507173a 175 */
emilmont 77:869cf507173a 176 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 177 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
emilmont 77:869cf507173a 178 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
emilmont 77:869cf507173a 179 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
emilmont 77:869cf507173a 180 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
emilmont 77:869cf507173a 181 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
emilmont 77:869cf507173a 182 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
emilmont 77:869cf507173a 183 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
emilmont 77:869cf507173a 184 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 185
Kojto 90:cb3d968589d8 186 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
Kojto 90:cb3d968589d8 187 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
emilmont 77:869cf507173a 188 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
emilmont 77:869cf507173a 189 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
emilmont 77:869cf507173a 190 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
Kojto 90:cb3d968589d8 191 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
emilmont 77:869cf507173a 192
emilmont 77:869cf507173a 193 /**
emilmont 77:869cf507173a 194 * @}
emilmont 77:869cf507173a 195 */
emilmont 77:869cf507173a 196
emilmont 77:869cf507173a 197 /** @defgroup RCCEx_BitAddress_AliasRegion
emilmont 77:869cf507173a 198 * @brief RCC registers bit address in the alias region
emilmont 77:869cf507173a 199 * @{
emilmont 77:869cf507173a 200 */
emilmont 77:869cf507173a 201 /* --- CR Register ---*/
emilmont 77:869cf507173a 202 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 203 /* Alias word address of PLLSAION bit */
emilmont 77:869cf507173a 204 #define PLLSAION_BitNumber 0x1C
emilmont 77:869cf507173a 205 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
emilmont 77:869cf507173a 206
emilmont 77:869cf507173a 207 /* --- DCKCFGR Register ---*/
emilmont 77:869cf507173a 208 /* Alias word address of TIMPRE bit */
emilmont 77:869cf507173a 209 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
emilmont 77:869cf507173a 210 #define TIMPRE_BitNumber 0x18
emilmont 77:869cf507173a 211 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
emilmont 77:869cf507173a 212 /**
emilmont 77:869cf507173a 213 * @}
emilmont 77:869cf507173a 214 */
emilmont 77:869cf507173a 215
emilmont 77:869cf507173a 216 /** @defgroup RCCEx_PLLI2S_Clock_Source
emilmont 77:869cf507173a 217 * @{
emilmont 77:869cf507173a 218 */
emilmont 77:869cf507173a 219 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
emilmont 77:869cf507173a 220 /**
emilmont 77:869cf507173a 221 * @}
emilmont 77:869cf507173a 222 */
emilmont 77:869cf507173a 223
emilmont 77:869cf507173a 224 /** @defgroup RCCEx_PLLSAI_Clock_Source
emilmont 77:869cf507173a 225 * @{
emilmont 77:869cf507173a 226 */
emilmont 77:869cf507173a 227 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
emilmont 77:869cf507173a 228 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
emilmont 77:869cf507173a 229 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
emilmont 77:869cf507173a 230 /**
emilmont 77:869cf507173a 231 * @}
emilmont 77:869cf507173a 232 */
emilmont 77:869cf507173a 233
emilmont 77:869cf507173a 234 /** @defgroup RCCEx_PLLSAI_DIVQ
emilmont 77:869cf507173a 235 * @{
emilmont 77:869cf507173a 236 */
emilmont 77:869cf507173a 237 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
emilmont 77:869cf507173a 238 /**
emilmont 77:869cf507173a 239 * @}
emilmont 77:869cf507173a 240 */
emilmont 77:869cf507173a 241
emilmont 77:869cf507173a 242 /** @defgroup RCCEx_PLLI2S_DIVQ
emilmont 77:869cf507173a 243 * @{
emilmont 77:869cf507173a 244 */
emilmont 77:869cf507173a 245 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
emilmont 77:869cf507173a 246
emilmont 77:869cf507173a 247 /**
emilmont 77:869cf507173a 248 * @}
emilmont 77:869cf507173a 249 */
emilmont 77:869cf507173a 250
emilmont 77:869cf507173a 251 /** @defgroup RCCEx_PLLSAI_DIVR
emilmont 77:869cf507173a 252 * @{
emilmont 77:869cf507173a 253 */
emilmont 77:869cf507173a 254 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
emilmont 77:869cf507173a 255 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 256 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 257 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
emilmont 77:869cf507173a 258 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
emilmont 77:869cf507173a 259 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
emilmont 77:869cf507173a 260 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
emilmont 77:869cf507173a 261 ((VALUE) == RCC_PLLSAIDIVR_16))
emilmont 77:869cf507173a 262
emilmont 77:869cf507173a 263 /**
emilmont 77:869cf507173a 264 * @}
emilmont 77:869cf507173a 265 */
emilmont 77:869cf507173a 266
emilmont 77:869cf507173a 267 /** @defgroup RCCEx_SAI_BlockA_Clock_Source
emilmont 77:869cf507173a 268 * @{
emilmont 77:869cf507173a 269 */
emilmont 77:869cf507173a 270 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
emilmont 77:869cf507173a 271 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
emilmont 77:869cf507173a 272 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
emilmont 77:869cf507173a 273 /**
emilmont 77:869cf507173a 274 * @}
emilmont 77:869cf507173a 275 */
emilmont 77:869cf507173a 276
emilmont 77:869cf507173a 277 /** @defgroup RCCEx_SAI_BlockB_Clock_Source
emilmont 77:869cf507173a 278 * @{
emilmont 77:869cf507173a 279 */
emilmont 77:869cf507173a 280 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
emilmont 77:869cf507173a 281 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
emilmont 77:869cf507173a 282 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
emilmont 77:869cf507173a 283 /**
emilmont 77:869cf507173a 284 * @}
emilmont 77:869cf507173a 285 */
emilmont 77:869cf507173a 286
emilmont 77:869cf507173a 287 /** @defgroup RCCEx_TIM_PRescaler_Selection
emilmont 77:869cf507173a 288 * @{
emilmont 77:869cf507173a 289 */
emilmont 77:869cf507173a 290 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
emilmont 77:869cf507173a 291 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
emilmont 77:869cf507173a 292 /**
emilmont 77:869cf507173a 293 * @}
emilmont 77:869cf507173a 294 */
emilmont 77:869cf507173a 295 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 90:cb3d968589d8 296
Kojto 90:cb3d968589d8 297 #if defined(STM32F411xE)
Kojto 90:cb3d968589d8 298 /** @defgroup RCCEx_PLLI2S_PLLI2SM
Kojto 90:cb3d968589d8 299 * @{
Kojto 90:cb3d968589d8 300 */
Kojto 90:cb3d968589d8 301 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
emilmont 77:869cf507173a 302 /**
emilmont 77:869cf507173a 303 * @}
emilmont 77:869cf507173a 304 */
emilmont 77:869cf507173a 305
Kojto 90:cb3d968589d8 306 /** @defgroup RCCEx_LSE_Dual_Mode_Selection
Kojto 90:cb3d968589d8 307 * @{
Kojto 90:cb3d968589d8 308 */
Kojto 90:cb3d968589d8 309 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
Kojto 90:cb3d968589d8 310 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
Kojto 90:cb3d968589d8 311 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
Kojto 90:cb3d968589d8 312 ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto 90:cb3d968589d8 313 /**
Kojto 90:cb3d968589d8 314 * @}
Kojto 90:cb3d968589d8 315 */
Kojto 90:cb3d968589d8 316
Kojto 90:cb3d968589d8 317 #endif /* STM32F411xE */
emilmont 77:869cf507173a 318 /**
emilmont 77:869cf507173a 319 * @}
emilmont 77:869cf507173a 320 */
emilmont 77:869cf507173a 321
emilmont 77:869cf507173a 322 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 323
Kojto 90:cb3d968589d8 324 /*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/
Kojto 90:cb3d968589d8 325 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 326 /** @brief Enables or disables the AHB1 peripheral clock.
emilmont 77:869cf507173a 327 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 328 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 329 * using it.
emilmont 77:869cf507173a 330 */
Kojto 90:cb3d968589d8 331 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
Kojto 90:cb3d968589d8 332 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
Kojto 90:cb3d968589d8 333 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
Kojto 90:cb3d968589d8 334 #define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
Kojto 90:cb3d968589d8 335 #define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
Kojto 90:cb3d968589d8 336 #define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
Kojto 90:cb3d968589d8 337 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
Kojto 90:cb3d968589d8 338 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
Kojto 90:cb3d968589d8 339 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
Kojto 90:cb3d968589d8 340 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
Kojto 90:cb3d968589d8 341 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
Kojto 90:cb3d968589d8 342 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
emilmont 77:869cf507173a 343
Kojto 90:cb3d968589d8 344 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 90:cb3d968589d8 345 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 90:cb3d968589d8 346 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto 90:cb3d968589d8 347 #define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto 90:cb3d968589d8 348 #define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto 90:cb3d968589d8 349 #define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto 90:cb3d968589d8 350 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto 90:cb3d968589d8 351 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto 90:cb3d968589d8 352 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto 90:cb3d968589d8 353 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto 90:cb3d968589d8 354 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 90:cb3d968589d8 355 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 90:cb3d968589d8 356
Kojto 90:cb3d968589d8 357 /**
Kojto 90:cb3d968589d8 358 * @brief Enable ETHERNET clock.
Kojto 90:cb3d968589d8 359 */
Kojto 90:cb3d968589d8 360 #define __ETH_CLK_ENABLE() do { \
Kojto 90:cb3d968589d8 361 __ETHMAC_CLK_ENABLE(); \
Kojto 90:cb3d968589d8 362 __ETHMACTX_CLK_ENABLE(); \
Kojto 90:cb3d968589d8 363 __ETHMACRX_CLK_ENABLE(); \
Kojto 90:cb3d968589d8 364 } while(0)
Kojto 90:cb3d968589d8 365 /**
Kojto 90:cb3d968589d8 366 * @brief Disable ETHERNET clock.
Kojto 90:cb3d968589d8 367 */
Kojto 90:cb3d968589d8 368 #define __ETH_CLK_DISABLE() do { \
Kojto 90:cb3d968589d8 369 __ETHMACTX_CLK_DISABLE(); \
Kojto 90:cb3d968589d8 370 __ETHMACRX_CLK_DISABLE(); \
Kojto 90:cb3d968589d8 371 __ETHMAC_CLK_DISABLE(); \
Kojto 90:cb3d968589d8 372 } while(0)
Kojto 90:cb3d968589d8 373
Kojto 90:cb3d968589d8 374 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 90:cb3d968589d8 375 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 376 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 377 * using it.
Kojto 90:cb3d968589d8 378 */
Kojto 90:cb3d968589d8 379
Kojto 90:cb3d968589d8 380 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
Kojto 90:cb3d968589d8 381 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 90:cb3d968589d8 382
Kojto 90:cb3d968589d8 383 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 90:cb3d968589d8 384 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
Kojto 90:cb3d968589d8 385 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
Kojto 90:cb3d968589d8 386
Kojto 90:cb3d968589d8 387 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto 90:cb3d968589d8 388 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto 90:cb3d968589d8 389 #endif /* STM32F437xx || STM32F439xx */
Kojto 90:cb3d968589d8 390
Kojto 90:cb3d968589d8 391 /** @brief Enables or disables the AHB3 peripheral clock.
Kojto 90:cb3d968589d8 392 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 393 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 394 * using it.
Kojto 90:cb3d968589d8 395 */
Kojto 90:cb3d968589d8 396 #define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
Kojto 90:cb3d968589d8 397 #define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto 90:cb3d968589d8 398
Kojto 90:cb3d968589d8 399 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 90:cb3d968589d8 400 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 401 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 402 * using it.
Kojto 90:cb3d968589d8 403 */
Kojto 90:cb3d968589d8 404 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
Kojto 90:cb3d968589d8 405 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
Kojto 90:cb3d968589d8 406 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
Kojto 90:cb3d968589d8 407 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
Kojto 90:cb3d968589d8 408 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
Kojto 90:cb3d968589d8 409 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
Kojto 90:cb3d968589d8 410 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
Kojto 90:cb3d968589d8 411 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
Kojto 90:cb3d968589d8 412 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
Kojto 90:cb3d968589d8 413 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
Kojto 90:cb3d968589d8 414 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
Kojto 90:cb3d968589d8 415 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
Kojto 90:cb3d968589d8 416 #define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
Kojto 90:cb3d968589d8 417 #define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
Kojto 90:cb3d968589d8 418
Kojto 90:cb3d968589d8 419 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 90:cb3d968589d8 420 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 90:cb3d968589d8 421 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 90:cb3d968589d8 422 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 90:cb3d968589d8 423 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 90:cb3d968589d8 424 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 90:cb3d968589d8 425 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 90:cb3d968589d8 426 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 90:cb3d968589d8 427 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 90:cb3d968589d8 428 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 90:cb3d968589d8 429 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 90:cb3d968589d8 430 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 90:cb3d968589d8 431 #define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto 90:cb3d968589d8 432 #define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto 90:cb3d968589d8 433
Kojto 90:cb3d968589d8 434 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 90:cb3d968589d8 435 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 436 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 437 * using it.
Kojto 90:cb3d968589d8 438 */
Kojto 90:cb3d968589d8 439 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
Kojto 90:cb3d968589d8 440 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
Kojto 90:cb3d968589d8 441 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
Kojto 90:cb3d968589d8 442 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
Kojto 90:cb3d968589d8 443 #define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
Kojto 90:cb3d968589d8 444 #define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
Kojto 90:cb3d968589d8 445
Kojto 90:cb3d968589d8 446 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 90:cb3d968589d8 447 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 90:cb3d968589d8 448 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 90:cb3d968589d8 449 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto 90:cb3d968589d8 450 #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto 90:cb3d968589d8 451 #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto 90:cb3d968589d8 452
Kojto 90:cb3d968589d8 453 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 90:cb3d968589d8 454 #define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
Kojto 90:cb3d968589d8 455
Kojto 90:cb3d968589d8 456 #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto 90:cb3d968589d8 457 #endif /* STM32F429xx || STM32F439xx */
Kojto 90:cb3d968589d8 458
Kojto 90:cb3d968589d8 459 /** @brief Force or release AHB1 peripheral reset.
Kojto 90:cb3d968589d8 460 */
Kojto 90:cb3d968589d8 461 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
Kojto 90:cb3d968589d8 462 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
Kojto 90:cb3d968589d8 463 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
Kojto 90:cb3d968589d8 464 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
Kojto 90:cb3d968589d8 465 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
Kojto 90:cb3d968589d8 466 #define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
Kojto 90:cb3d968589d8 467 #define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
Kojto 90:cb3d968589d8 468 #define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
Kojto 90:cb3d968589d8 469
Kojto 90:cb3d968589d8 470 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 90:cb3d968589d8 471 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 90:cb3d968589d8 472 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 90:cb3d968589d8 473 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto 90:cb3d968589d8 474 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto 90:cb3d968589d8 475 #define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto 90:cb3d968589d8 476 #define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto 90:cb3d968589d8 477 #define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto 90:cb3d968589d8 478
Kojto 90:cb3d968589d8 479 /** @brief Force or release AHB2 peripheral reset.
Kojto 90:cb3d968589d8 480 */
Kojto 90:cb3d968589d8 481 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
Kojto 90:cb3d968589d8 482 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 90:cb3d968589d8 483
Kojto 90:cb3d968589d8 484 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 90:cb3d968589d8 485 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
Kojto 90:cb3d968589d8 486 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
Kojto 90:cb3d968589d8 487
Kojto 90:cb3d968589d8 488 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto 90:cb3d968589d8 489 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto 90:cb3d968589d8 490 #endif /* STM32F437xx || STM32F439xx */
Kojto 90:cb3d968589d8 491
Kojto 90:cb3d968589d8 492 /** @brief Force or release AHB3 peripheral reset
Kojto 90:cb3d968589d8 493 */
Kojto 90:cb3d968589d8 494 #define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
Kojto 90:cb3d968589d8 495 #define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto 90:cb3d968589d8 496
Kojto 90:cb3d968589d8 497 /** @brief Force or release APB1 peripheral reset.
Kojto 90:cb3d968589d8 498 */
Kojto 90:cb3d968589d8 499 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 90:cb3d968589d8 500 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 90:cb3d968589d8 501 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 90:cb3d968589d8 502 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 90:cb3d968589d8 503 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 90:cb3d968589d8 504 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 90:cb3d968589d8 505 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 90:cb3d968589d8 506 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 90:cb3d968589d8 507 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 90:cb3d968589d8 508 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 90:cb3d968589d8 509 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 90:cb3d968589d8 510 #define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
Kojto 90:cb3d968589d8 511 #define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
Kojto 90:cb3d968589d8 512
Kojto 90:cb3d968589d8 513 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 90:cb3d968589d8 514 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 90:cb3d968589d8 515 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 90:cb3d968589d8 516 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 90:cb3d968589d8 517 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 90:cb3d968589d8 518 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 90:cb3d968589d8 519 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 90:cb3d968589d8 520 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 90:cb3d968589d8 521 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 90:cb3d968589d8 522 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 90:cb3d968589d8 523 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 90:cb3d968589d8 524 #define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto 90:cb3d968589d8 525 #define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto 90:cb3d968589d8 526
Kojto 90:cb3d968589d8 527 /** @brief Force or release APB2 peripheral reset.
Kojto 90:cb3d968589d8 528 */
Kojto 90:cb3d968589d8 529 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 90:cb3d968589d8 530 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
Kojto 90:cb3d968589d8 531 #define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
Kojto 90:cb3d968589d8 532 #define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
Kojto 90:cb3d968589d8 533
Kojto 90:cb3d968589d8 534 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 90:cb3d968589d8 535 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto 90:cb3d968589d8 536 #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto 90:cb3d968589d8 537 #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto 90:cb3d968589d8 538
Kojto 90:cb3d968589d8 539 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 90:cb3d968589d8 540 #define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
Kojto 90:cb3d968589d8 541 #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto 90:cb3d968589d8 542 #endif /* STM32F429xx|| STM32F439xx */
Kojto 90:cb3d968589d8 543
Kojto 90:cb3d968589d8 544 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 545 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 90:cb3d968589d8 546 * power consumption.
Kojto 90:cb3d968589d8 547 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 90:cb3d968589d8 548 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 549 */
Kojto 90:cb3d968589d8 550 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto 90:cb3d968589d8 551 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto 90:cb3d968589d8 552 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
Kojto 90:cb3d968589d8 553 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto 90:cb3d968589d8 554 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto 90:cb3d968589d8 555 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 90:cb3d968589d8 556 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 90:cb3d968589d8 557 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 90:cb3d968589d8 558 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto 90:cb3d968589d8 559 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 90:cb3d968589d8 560 #define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto 90:cb3d968589d8 561 #define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto 90:cb3d968589d8 562 #define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto 90:cb3d968589d8 563 #define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto 90:cb3d968589d8 564
Kojto 90:cb3d968589d8 565 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto 90:cb3d968589d8 566 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto 90:cb3d968589d8 567 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto 90:cb3d968589d8 568 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto 90:cb3d968589d8 569 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto 90:cb3d968589d8 570 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 90:cb3d968589d8 571 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 90:cb3d968589d8 572 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 90:cb3d968589d8 573 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto 90:cb3d968589d8 574 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 90:cb3d968589d8 575 #define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto 90:cb3d968589d8 576 #define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto 90:cb3d968589d8 577 #define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto 90:cb3d968589d8 578
Kojto 90:cb3d968589d8 579 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 580 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 90:cb3d968589d8 581 * power consumption.
Kojto 90:cb3d968589d8 582 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 90:cb3d968589d8 583 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 584 */
Kojto 90:cb3d968589d8 585 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Kojto 90:cb3d968589d8 586 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 90:cb3d968589d8 587
Kojto 90:cb3d968589d8 588 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 90:cb3d968589d8 589 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
Kojto 90:cb3d968589d8 590 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
Kojto 90:cb3d968589d8 591
Kojto 90:cb3d968589d8 592 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto 90:cb3d968589d8 593 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto 90:cb3d968589d8 594 #endif /* STM32F437xx || STM32F439xx */
Kojto 90:cb3d968589d8 595
Kojto 90:cb3d968589d8 596 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 597 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 90:cb3d968589d8 598 * power consumption.
Kojto 90:cb3d968589d8 599 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 90:cb3d968589d8 600 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 601 */
Kojto 90:cb3d968589d8 602 #define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
Kojto 90:cb3d968589d8 603 #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto 90:cb3d968589d8 604
Kojto 90:cb3d968589d8 605 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 606 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 90:cb3d968589d8 607 * power consumption.
Kojto 90:cb3d968589d8 608 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 90:cb3d968589d8 609 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 610 */
Kojto 90:cb3d968589d8 611 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
Kojto 90:cb3d968589d8 612 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
Kojto 90:cb3d968589d8 613 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
Kojto 90:cb3d968589d8 614 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
Kojto 90:cb3d968589d8 615 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
Kojto 90:cb3d968589d8 616 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
Kojto 90:cb3d968589d8 617 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 90:cb3d968589d8 618 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 90:cb3d968589d8 619 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
Kojto 90:cb3d968589d8 620 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
Kojto 90:cb3d968589d8 621 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
Kojto 90:cb3d968589d8 622 #define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
Kojto 90:cb3d968589d8 623 #define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
Kojto 90:cb3d968589d8 624
Kojto 90:cb3d968589d8 625 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto 90:cb3d968589d8 626 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto 90:cb3d968589d8 627 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto 90:cb3d968589d8 628 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto 90:cb3d968589d8 629 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto 90:cb3d968589d8 630 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto 90:cb3d968589d8 631 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 90:cb3d968589d8 632 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 90:cb3d968589d8 633 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto 90:cb3d968589d8 634 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto 90:cb3d968589d8 635 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto 90:cb3d968589d8 636 #define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto 90:cb3d968589d8 637 #define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto 90:cb3d968589d8 638
Kojto 90:cb3d968589d8 639 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 640 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 90:cb3d968589d8 641 * power consumption.
Kojto 90:cb3d968589d8 642 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 90:cb3d968589d8 643 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 644 */
Kojto 90:cb3d968589d8 645 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
Kojto 90:cb3d968589d8 646 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
Kojto 90:cb3d968589d8 647 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
Kojto 90:cb3d968589d8 648 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
Kojto 90:cb3d968589d8 649 #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
Kojto 90:cb3d968589d8 650 #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
Kojto 90:cb3d968589d8 651
Kojto 90:cb3d968589d8 652 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto 90:cb3d968589d8 653 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto 90:cb3d968589d8 654 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 90:cb3d968589d8 655 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto 90:cb3d968589d8 656 #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto 90:cb3d968589d8 657 #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 90:cb3d968589d8 660 #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
Kojto 90:cb3d968589d8 661
Kojto 90:cb3d968589d8 662 #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto 90:cb3d968589d8 663 #endif /* STM32F429xx || STM32F439xx */
Kojto 90:cb3d968589d8 664 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
Kojto 90:cb3d968589d8 665 /*---------------------------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 666
Kojto 90:cb3d968589d8 667 /*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/
Kojto 90:cb3d968589d8 668 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 90:cb3d968589d8 669 /** @brief Enables or disables the AHB1 peripheral clock.
Kojto 90:cb3d968589d8 670 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 671 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 672 * using it.
Kojto 90:cb3d968589d8 673 */
Kojto 90:cb3d968589d8 674 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
Kojto 90:cb3d968589d8 675 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
Kojto 90:cb3d968589d8 676 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
Kojto 90:cb3d968589d8 677 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
Kojto 90:cb3d968589d8 678 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
Kojto 90:cb3d968589d8 679
Kojto 90:cb3d968589d8 680 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 90:cb3d968589d8 681 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 90:cb3d968589d8 682 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto 90:cb3d968589d8 683 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 90:cb3d968589d8 684 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 90:cb3d968589d8 685
Kojto 90:cb3d968589d8 686 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 90:cb3d968589d8 687 /**
Kojto 90:cb3d968589d8 688 * @brief Enable ETHERNET clock.
Kojto 90:cb3d968589d8 689 */
emilmont 77:869cf507173a 690 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
emilmont 77:869cf507173a 691 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
emilmont 77:869cf507173a 692 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
Kojto 90:cb3d968589d8 693 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
emilmont 77:869cf507173a 694 #define __ETH_CLK_ENABLE() do { \
emilmont 77:869cf507173a 695 __ETHMAC_CLK_ENABLE(); \
emilmont 77:869cf507173a 696 __ETHMACTX_CLK_ENABLE(); \
emilmont 77:869cf507173a 697 __ETHMACRX_CLK_ENABLE(); \
emilmont 77:869cf507173a 698 } while(0)
emilmont 77:869cf507173a 699
emilmont 77:869cf507173a 700 /**
emilmont 77:869cf507173a 701 * @brief Disable ETHERNET clock.
emilmont 77:869cf507173a 702 */
Kojto 90:cb3d968589d8 703 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto 90:cb3d968589d8 704 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto 90:cb3d968589d8 705 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto 90:cb3d968589d8 706 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
emilmont 77:869cf507173a 707 #define __ETH_CLK_DISABLE() do { \
emilmont 77:869cf507173a 708 __ETHMACTX_CLK_DISABLE(); \
emilmont 77:869cf507173a 709 __ETHMACRX_CLK_DISABLE(); \
emilmont 77:869cf507173a 710 __ETHMAC_CLK_DISABLE(); \
emilmont 77:869cf507173a 711 } while(0)
Kojto 90:cb3d968589d8 712 #endif /* STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 713
emilmont 77:869cf507173a 714 /** @brief Enable or disable the AHB2 peripheral clock.
emilmont 77:869cf507173a 715 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 716 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 717 * using it.
emilmont 77:869cf507173a 718 */
Kojto 90:cb3d968589d8 719 #if defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 720 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
emilmont 77:869cf507173a 721 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 90:cb3d968589d8 722 #endif /* STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 723
Kojto 90:cb3d968589d8 724 #if defined(STM32F415xx) || defined(STM32F417xx)
emilmont 77:869cf507173a 725 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
emilmont 77:869cf507173a 726 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
emilmont 77:869cf507173a 727
emilmont 77:869cf507173a 728 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
emilmont 77:869cf507173a 729 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto 90:cb3d968589d8 730 #endif /* STM32F415xx || STM32F417xx */
emilmont 77:869cf507173a 731
emilmont 77:869cf507173a 732 /** @brief Enables or disables the AHB3 peripheral clock.
emilmont 77:869cf507173a 733 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 734 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 735 * using it.
emilmont 77:869cf507173a 736 */
emilmont 77:869cf507173a 737 #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
emilmont 77:869cf507173a 738 #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
emilmont 77:869cf507173a 739
emilmont 77:869cf507173a 740 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
emilmont 77:869cf507173a 741 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 742 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 743 * using it.
emilmont 77:869cf507173a 744 */
emilmont 77:869cf507173a 745 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
emilmont 77:869cf507173a 746 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
emilmont 77:869cf507173a 747 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
emilmont 77:869cf507173a 748 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
emilmont 77:869cf507173a 749 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
emilmont 77:869cf507173a 750 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
emilmont 77:869cf507173a 751 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
emilmont 77:869cf507173a 752 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
emilmont 77:869cf507173a 753 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
emilmont 77:869cf507173a 754 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
emilmont 77:869cf507173a 755 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
emilmont 77:869cf507173a 756 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
emilmont 77:869cf507173a 757
emilmont 77:869cf507173a 758 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
emilmont 77:869cf507173a 759 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
emilmont 77:869cf507173a 760 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
emilmont 77:869cf507173a 761 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
emilmont 77:869cf507173a 762 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
emilmont 77:869cf507173a 763 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
emilmont 77:869cf507173a 764 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
emilmont 77:869cf507173a 765 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
emilmont 77:869cf507173a 766 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
emilmont 77:869cf507173a 767 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
emilmont 77:869cf507173a 768 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
emilmont 77:869cf507173a 769 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
emilmont 77:869cf507173a 770
emilmont 77:869cf507173a 771 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
emilmont 77:869cf507173a 772 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 773 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 774 * using it.
emilmont 77:869cf507173a 775 */
emilmont 77:869cf507173a 776 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
emilmont 77:869cf507173a 777 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
emilmont 77:869cf507173a 778 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
emilmont 77:869cf507173a 779
emilmont 77:869cf507173a 780 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
emilmont 77:869cf507173a 781 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
emilmont 77:869cf507173a 782 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
emilmont 77:869cf507173a 783
emilmont 77:869cf507173a 784 /** @brief Force or release AHB1 peripheral reset.
emilmont 77:869cf507173a 785 */
emilmont 77:869cf507173a 786 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
emilmont 77:869cf507173a 787 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
emilmont 77:869cf507173a 788 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
emilmont 77:869cf507173a 789 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
emilmont 77:869cf507173a 790 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
emilmont 77:869cf507173a 791
emilmont 77:869cf507173a 792 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
emilmont 77:869cf507173a 793 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
emilmont 77:869cf507173a 794 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
emilmont 77:869cf507173a 795 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
emilmont 77:869cf507173a 796 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
emilmont 77:869cf507173a 797
emilmont 77:869cf507173a 798 /** @brief Force or release AHB2 peripheral reset.
emilmont 77:869cf507173a 799 */
Kojto 90:cb3d968589d8 800 #if defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 801 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
emilmont 77:869cf507173a 802 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 90:cb3d968589d8 803 #endif /* STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 804
Kojto 90:cb3d968589d8 805 #if defined(STM32F415xx) || defined(STM32F417xx)
emilmont 77:869cf507173a 806 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
emilmont 77:869cf507173a 807 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
emilmont 77:869cf507173a 808
emilmont 77:869cf507173a 809 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
emilmont 77:869cf507173a 810 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
emilmont 77:869cf507173a 811
Kojto 90:cb3d968589d8 812 #endif /* STM32F415xx || STM32F417xx */
emilmont 77:869cf507173a 813
emilmont 77:869cf507173a 814 /** @brief Force or release AHB3 peripheral reset
emilmont 77:869cf507173a 815 */
emilmont 77:869cf507173a 816 #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
emilmont 77:869cf507173a 817 #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
emilmont 77:869cf507173a 818
emilmont 77:869cf507173a 819 /** @brief Force or release APB1 peripheral reset.
Kojto 90:cb3d968589d8 820 */
emilmont 77:869cf507173a 821 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
emilmont 77:869cf507173a 822 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
emilmont 77:869cf507173a 823 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
emilmont 77:869cf507173a 824 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
emilmont 77:869cf507173a 825 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
emilmont 77:869cf507173a 826 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
emilmont 77:869cf507173a 827 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
emilmont 77:869cf507173a 828 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
emilmont 77:869cf507173a 829 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
emilmont 77:869cf507173a 830 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
emilmont 77:869cf507173a 831 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
emilmont 77:869cf507173a 832
emilmont 77:869cf507173a 833 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
emilmont 77:869cf507173a 834 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
emilmont 77:869cf507173a 835 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
emilmont 77:869cf507173a 836 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
emilmont 77:869cf507173a 837 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
emilmont 77:869cf507173a 838 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
emilmont 77:869cf507173a 839 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
emilmont 77:869cf507173a 840 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
emilmont 77:869cf507173a 841 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
emilmont 77:869cf507173a 842 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
emilmont 77:869cf507173a 843 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
emilmont 77:869cf507173a 844
emilmont 77:869cf507173a 845 /** @brief Force or release APB2 peripheral reset.
emilmont 77:869cf507173a 846 */
emilmont 77:869cf507173a 847 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
emilmont 77:869cf507173a 848 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
emilmont 77:869cf507173a 849
emilmont 77:869cf507173a 850 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 851 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 852 * power consumption.
emilmont 77:869cf507173a 853 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 854 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 855 */
emilmont 77:869cf507173a 856 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
emilmont 77:869cf507173a 857 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
emilmont 77:869cf507173a 858 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
emilmont 77:869cf507173a 859 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
emilmont 77:869cf507173a 860 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
emilmont 77:869cf507173a 861 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
emilmont 77:869cf507173a 862 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
emilmont 77:869cf507173a 863 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
emilmont 77:869cf507173a 864 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
emilmont 77:869cf507173a 865 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
emilmont 77:869cf507173a 866
emilmont 77:869cf507173a 867 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
emilmont 77:869cf507173a 868 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
emilmont 77:869cf507173a 869 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
emilmont 77:869cf507173a 870 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
emilmont 77:869cf507173a 871 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
emilmont 77:869cf507173a 872 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
emilmont 77:869cf507173a 873 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
emilmont 77:869cf507173a 874 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
emilmont 77:869cf507173a 875 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
emilmont 77:869cf507173a 876 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
emilmont 77:869cf507173a 877
emilmont 77:869cf507173a 878 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 879 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 880 * power consumption.
emilmont 77:869cf507173a 881 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 882 * @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont 77:869cf507173a 883 */
Kojto 90:cb3d968589d8 884 #if defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 885 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
emilmont 77:869cf507173a 886 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 90:cb3d968589d8 887 #endif /* STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 888
Kojto 90:cb3d968589d8 889 #if defined(STM32F415xx) || defined(STM32F417xx)
emilmont 77:869cf507173a 890 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
emilmont 77:869cf507173a 891 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
emilmont 77:869cf507173a 892
emilmont 77:869cf507173a 893 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
emilmont 77:869cf507173a 894 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto 90:cb3d968589d8 895 #endif /* STM32F415xx || STM32F417xx */
emilmont 77:869cf507173a 896
emilmont 77:869cf507173a 897 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 898 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 899 * power consumption.
emilmont 77:869cf507173a 900 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 901 * @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont 77:869cf507173a 902 */
emilmont 77:869cf507173a 903 #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
emilmont 77:869cf507173a 904 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
emilmont 77:869cf507173a 905
emilmont 77:869cf507173a 906 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 907 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 908 * power consumption.
emilmont 77:869cf507173a 909 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 910 * @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont 77:869cf507173a 911 */
emilmont 77:869cf507173a 912 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
emilmont 77:869cf507173a 913 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
emilmont 77:869cf507173a 914 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
emilmont 77:869cf507173a 915 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
emilmont 77:869cf507173a 916 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
emilmont 77:869cf507173a 917 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
emilmont 77:869cf507173a 918 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
emilmont 77:869cf507173a 919 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
emilmont 77:869cf507173a 920 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
emilmont 77:869cf507173a 921 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
emilmont 77:869cf507173a 922 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
emilmont 77:869cf507173a 923
emilmont 77:869cf507173a 924 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
emilmont 77:869cf507173a 925 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
emilmont 77:869cf507173a 926 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
emilmont 77:869cf507173a 927 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
emilmont 77:869cf507173a 928 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
emilmont 77:869cf507173a 929 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
emilmont 77:869cf507173a 930 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
emilmont 77:869cf507173a 931 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
emilmont 77:869cf507173a 932 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
emilmont 77:869cf507173a 933 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
emilmont 77:869cf507173a 934 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
emilmont 77:869cf507173a 935
emilmont 77:869cf507173a 936 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 937 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 938 * power consumption.
emilmont 77:869cf507173a 939 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 940 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 90:cb3d968589d8 941 */
emilmont 77:869cf507173a 942 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
emilmont 77:869cf507173a 943 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
emilmont 77:869cf507173a 944 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
emilmont 77:869cf507173a 945
emilmont 77:869cf507173a 946 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
emilmont 77:869cf507173a 947 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
emilmont 77:869cf507173a 948 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 90:cb3d968589d8 949 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 90:cb3d968589d8 950 /*---------------------------------------------------------------------------------------------*/
emilmont 77:869cf507173a 951
Kojto 90:cb3d968589d8 952 /*------------------------------------------ STM32F411xx --------------------------------------*/
Kojto 90:cb3d968589d8 953 #if defined(STM32F411xE)
Kojto 90:cb3d968589d8 954 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 90:cb3d968589d8 955 */
Kojto 90:cb3d968589d8 956 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
Kojto 90:cb3d968589d8 957 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto 90:cb3d968589d8 958
Kojto 90:cb3d968589d8 959 /** @brief Force or release APB2 peripheral reset.
Kojto 90:cb3d968589d8 960 */
Kojto 90:cb3d968589d8 961 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
Kojto 90:cb3d968589d8 962 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto 90:cb3d968589d8 963
Kojto 90:cb3d968589d8 964 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 90:cb3d968589d8 965 */
Kojto 90:cb3d968589d8 966 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
emilmont 77:869cf507173a 967 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
emilmont 77:869cf507173a 968
Kojto 90:cb3d968589d8 969 #endif /* STM32F411xE */
Kojto 90:cb3d968589d8 970 /*---------------------------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 971
Kojto 90:cb3d968589d8 972 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
Kojto 90:cb3d968589d8 973 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
emilmont 77:869cf507173a 974
emilmont 77:869cf507173a 975 /** @brief Macro to configure the Timers clocks prescalers
emilmont 77:869cf507173a 976 * @note This feature is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 977 * @param __PRESC__ : specifies the Timers clocks prescalers selection
emilmont 77:869cf507173a 978 * This parameter can be one of the following values:
emilmont 77:869cf507173a 979 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
emilmont 77:869cf507173a 980 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
emilmont 77:869cf507173a 981 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
emilmont 77:869cf507173a 982 * division by 4 or more.
emilmont 77:869cf507173a 983 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
emilmont 77:869cf507173a 984 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
emilmont 77:869cf507173a 985 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
emilmont 77:869cf507173a 986 * to division by 8 or more.
emilmont 77:869cf507173a 987 */
emilmont 77:869cf507173a 988 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
emilmont 77:869cf507173a 989
Kojto 90:cb3d968589d8 990 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 90:cb3d968589d8 991
Kojto 90:cb3d968589d8 992 #if defined(STM32F411xE)
Kojto 90:cb3d968589d8 993
Kojto 90:cb3d968589d8 994 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto 90:cb3d968589d8 995 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 90:cb3d968589d8 996 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 90:cb3d968589d8 997 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 90:cb3d968589d8 998 * HAL_RCC_ClockConfig() API).
Kojto 90:cb3d968589d8 999 * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto 90:cb3d968589d8 1000 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 90:cb3d968589d8 1001 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto 90:cb3d968589d8 1002 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 90:cb3d968589d8 1003 * of 2 MHz to limit PLLI2S jitter.
Kojto 90:cb3d968589d8 1004 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto 90:cb3d968589d8 1005 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 90:cb3d968589d8 1006 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 90:cb3d968589d8 1007 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 90:cb3d968589d8 1008 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 90:cb3d968589d8 1009 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 90:cb3d968589d8 1010 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 90:cb3d968589d8 1011 * on the I2S clock frequency.
Kojto 90:cb3d968589d8 1012 */
Kojto 90:cb3d968589d8 1013 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
Kojto 90:cb3d968589d8 1014 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__))
Kojto 90:cb3d968589d8 1015 #endif /* STM32F411xE */
Kojto 90:cb3d968589d8 1016
Kojto 90:cb3d968589d8 1017
Kojto 90:cb3d968589d8 1018 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 90:cb3d968589d8 1019
emilmont 77:869cf507173a 1020 /** @brief Macros to Enable or Disable the PLLISAI.
emilmont 77:869cf507173a 1021 * @note The PLLSAI is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 1022 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 1023 */
emilmont 77:869cf507173a 1024 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
emilmont 77:869cf507173a 1025 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
emilmont 77:869cf507173a 1026
emilmont 77:869cf507173a 1027 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
emilmont 77:869cf507173a 1028 * @note The PLLSAI is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 1029 * @note This function must be used only when the PLLSAI is disabled.
emilmont 77:869cf507173a 1030 * @note PLLSAI clock source is common with the main PLL (configured in
emilmont 77:869cf507173a 1031 * RCC_PLLConfig function )
emilmont 77:869cf507173a 1032 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
emilmont 77:869cf507173a 1033 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont 77:869cf507173a 1034 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
emilmont 77:869cf507173a 1035 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
emilmont 77:869cf507173a 1036 * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
emilmont 77:869cf507173a 1037 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont 77:869cf507173a 1038 * @param __PLLSAIR__: specifies the division factor for LTDC clock
emilmont 77:869cf507173a 1039 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont 77:869cf507173a 1040 */
emilmont 77:869cf507173a 1041 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
emilmont 77:869cf507173a 1042
emilmont 77:869cf507173a 1043 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
emilmont 77:869cf507173a 1044 * @note This macro must be used only when the PLLI2S is disabled.
emilmont 77:869cf507173a 1045 * @note PLLI2S clock source is common with the main PLL (configured in
emilmont 77:869cf507173a 1046 * HAL_RCC_ClockConfig() API)
emilmont 77:869cf507173a 1047 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
emilmont 77:869cf507173a 1048 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont 77:869cf507173a 1049 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
emilmont 77:869cf507173a 1050 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
emilmont 77:869cf507173a 1051 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
emilmont 77:869cf507173a 1052 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont 77:869cf507173a 1053 * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
emilmont 77:869cf507173a 1054 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
emilmont 77:869cf507173a 1055 * @param __PLLI2SR__: specifies the division factor for I2S clock
emilmont 77:869cf507173a 1056 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont 77:869cf507173a 1057 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
emilmont 77:869cf507173a 1058 * on the I2S clock frequency.
emilmont 77:869cf507173a 1059 */
emilmont 77:869cf507173a 1060 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
emilmont 77:869cf507173a 1061
emilmont 77:869cf507173a 1062 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
emilmont 77:869cf507173a 1063 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 1064 * @note This function must be called before enabling the PLLI2S.
emilmont 77:869cf507173a 1065 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
emilmont 77:869cf507173a 1066 * This parameter must be a number between 1 and 32.
emilmont 77:869cf507173a 1067 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
emilmont 77:869cf507173a 1068 */
emilmont 77:869cf507173a 1069 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
emilmont 77:869cf507173a 1070
emilmont 77:869cf507173a 1071 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
emilmont 77:869cf507173a 1072 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 1073 * @note This function must be called before enabling the PLLSAI.
emilmont 77:869cf507173a 1074 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
emilmont 77:869cf507173a 1075 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
emilmont 77:869cf507173a 1076 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
emilmont 77:869cf507173a 1077 */
emilmont 77:869cf507173a 1078 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
emilmont 77:869cf507173a 1079
emilmont 77:869cf507173a 1080 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
emilmont 77:869cf507173a 1081 *
emilmont 77:869cf507173a 1082 * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 1083 * @note This function must be called before enabling the PLLSAI.
emilmont 77:869cf507173a 1084 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
emilmont 77:869cf507173a 1085 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
emilmont 77:869cf507173a 1086 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
emilmont 77:869cf507173a 1087 */
emilmont 77:869cf507173a 1088 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
emilmont 77:869cf507173a 1089
emilmont 77:869cf507173a 1090 /** @brief Macro to configure SAI1BlockA clock source selection.
emilmont 77:869cf507173a 1091 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 1092 * @note This function must be called before enabling PLLSAI, PLLI2S and
emilmont 77:869cf507173a 1093 * the SAI clock.
emilmont 77:869cf507173a 1094 * @param __SOURCE__: specifies the SAI Block A clock source.
emilmont 77:869cf507173a 1095 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1096 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
emilmont 77:869cf507173a 1097 * as SAI1 Block A clock.
emilmont 77:869cf507173a 1098 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
emilmont 77:869cf507173a 1099 * as SAI1 Block A clock.
emilmont 77:869cf507173a 1100 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
emilmont 77:869cf507173a 1101 * used as SAI1 Block A clock.
emilmont 77:869cf507173a 1102 */
emilmont 77:869cf507173a 1103 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
emilmont 77:869cf507173a 1104
emilmont 77:869cf507173a 1105 /** @brief Macro to configure SAI1BlockB clock source selection.
emilmont 77:869cf507173a 1106 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
emilmont 77:869cf507173a 1107 * @note This function must be called before enabling PLLSAI, PLLI2S and
emilmont 77:869cf507173a 1108 * the SAI clock.
emilmont 77:869cf507173a 1109 * @param __SOURCE__: specifies the SAI Block B clock source.
emilmont 77:869cf507173a 1110 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1111 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
emilmont 77:869cf507173a 1112 * as SAI1 Block B clock.
emilmont 77:869cf507173a 1113 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
emilmont 77:869cf507173a 1114 * as SAI1 Block B clock.
emilmont 77:869cf507173a 1115 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
emilmont 77:869cf507173a 1116 * used as SAI1 Block B clock.
emilmont 77:869cf507173a 1117 */
emilmont 77:869cf507173a 1118 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
emilmont 77:869cf507173a 1119
emilmont 77:869cf507173a 1120 /** @brief Enable PLLSAI_RDY interrupt.
emilmont 77:869cf507173a 1121 */
emilmont 77:869cf507173a 1122 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
emilmont 77:869cf507173a 1123
emilmont 77:869cf507173a 1124 /** @brief Disable PLLSAI_RDY interrupt.
emilmont 77:869cf507173a 1125 */
emilmont 77:869cf507173a 1126 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
emilmont 77:869cf507173a 1127
emilmont 77:869cf507173a 1128 /** @brief Clear the PLLSAI RDY interrupt pending bits.
emilmont 77:869cf507173a 1129 */
emilmont 77:869cf507173a 1130 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
emilmont 77:869cf507173a 1131
emilmont 77:869cf507173a 1132 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
emilmont 77:869cf507173a 1133 * @retval The new state (TRUE or FALSE).
emilmont 77:869cf507173a 1134 */
emilmont 77:869cf507173a 1135 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
emilmont 77:869cf507173a 1136
emilmont 77:869cf507173a 1137 /** @brief Check PLLSAI RDY flag is set or not.
emilmont 77:869cf507173a 1138 * @retval The new state (TRUE or FALSE).
emilmont 77:869cf507173a 1139 */
emilmont 77:869cf507173a 1140 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
emilmont 77:869cf507173a 1141
emilmont 77:869cf507173a 1142 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 1143
emilmont 77:869cf507173a 1144 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 1145 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
emilmont 77:869cf507173a 1146 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
emilmont 77:869cf507173a 1147
Kojto 90:cb3d968589d8 1148 #if defined(STM32F411xE)
Kojto 90:cb3d968589d8 1149 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
Kojto 90:cb3d968589d8 1150 #endif /* STM32F411xE */
emilmont 77:869cf507173a 1151 /**
emilmont 77:869cf507173a 1152 * @}
emilmont 77:869cf507173a 1153 */
emilmont 77:869cf507173a 1154
emilmont 77:869cf507173a 1155 /**
emilmont 77:869cf507173a 1156 * @}
emilmont 77:869cf507173a 1157 */
emilmont 77:869cf507173a 1158
emilmont 77:869cf507173a 1159 #ifdef __cplusplus
emilmont 77:869cf507173a 1160 }
emilmont 77:869cf507173a 1161 #endif
emilmont 77:869cf507173a 1162
emilmont 77:869cf507173a 1163 #endif /* __STM32F4xx_HAL_RCC_EX_H */
emilmont 77:869cf507173a 1164
emilmont 77:869cf507173a 1165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/