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TARGET_NUCLEO_F334R8/stm32f3xx_hal_dma.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
92:4fc01daae5a5 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_dma.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 12-Sept-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of DMA HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_DMA_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_DMA_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup DMA DMA HAL module driver
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /** @defgroup DMA_Exported_Types DMA Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 86:04dd9b1680ae 61
bogdanm 86:04dd9b1680ae 62 /**
bogdanm 86:04dd9b1680ae 63 * @brief DMA Configuration Structure definition
bogdanm 86:04dd9b1680ae 64 */
bogdanm 86:04dd9b1680ae 65 typedef struct
bogdanm 86:04dd9b1680ae 66 {
bogdanm 86:04dd9b1680ae 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 86:04dd9b1680ae 68 from memory to memory or from peripheral to memory.
bogdanm 86:04dd9b1680ae 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 86:04dd9b1680ae 70
bogdanm 86:04dd9b1680ae 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 86:04dd9b1680ae 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 86:04dd9b1680ae 73
bogdanm 86:04dd9b1680ae 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 86:04dd9b1680ae 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 86:04dd9b1680ae 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 86:04dd9b1680ae 79
bogdanm 86:04dd9b1680ae 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 86:04dd9b1680ae 81 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 86:04dd9b1680ae 82
bogdanm 86:04dd9b1680ae 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 86:04dd9b1680ae 84 This parameter can be a value of @ref DMA_mode
bogdanm 86:04dd9b1680ae 85 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 86:04dd9b1680ae 86 data transfer is configured on the selected Channel */
bogdanm 86:04dd9b1680ae 87
bogdanm 86:04dd9b1680ae 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 86:04dd9b1680ae 89 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 86:04dd9b1680ae 90
bogdanm 86:04dd9b1680ae 91 } DMA_InitTypeDef;
bogdanm 86:04dd9b1680ae 92
bogdanm 86:04dd9b1680ae 93 /**
bogdanm 86:04dd9b1680ae 94 * @brief DMA Configuration enumeration values definition
bogdanm 86:04dd9b1680ae 95 */
bogdanm 86:04dd9b1680ae 96 typedef enum
bogdanm 86:04dd9b1680ae 97 {
bogdanm 86:04dd9b1680ae 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 86:04dd9b1680ae 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 86:04dd9b1680ae 100
bogdanm 86:04dd9b1680ae 101 } DMA_ControlTypeDef;
bogdanm 86:04dd9b1680ae 102
bogdanm 86:04dd9b1680ae 103 /**
bogdanm 86:04dd9b1680ae 104 * @brief HAL DMA State structures definition
bogdanm 86:04dd9b1680ae 105 */
bogdanm 86:04dd9b1680ae 106 typedef enum
bogdanm 86:04dd9b1680ae 107 {
bogdanm 86:04dd9b1680ae 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 86:04dd9b1680ae 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
bogdanm 86:04dd9b1680ae 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
bogdanm 86:04dd9b1680ae 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 86:04dd9b1680ae 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 86:04dd9b1680ae 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 86:04dd9b1680ae 114
bogdanm 86:04dd9b1680ae 115 }HAL_DMA_StateTypeDef;
bogdanm 86:04dd9b1680ae 116
bogdanm 86:04dd9b1680ae 117 /**
bogdanm 86:04dd9b1680ae 118 * @brief HAL DMA Error Code structure definition
bogdanm 86:04dd9b1680ae 119 */
bogdanm 86:04dd9b1680ae 120 typedef enum
bogdanm 86:04dd9b1680ae 121 {
bogdanm 86:04dd9b1680ae 122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 86:04dd9b1680ae 123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 86:04dd9b1680ae 124
bogdanm 86:04dd9b1680ae 125 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 86:04dd9b1680ae 126
bogdanm 86:04dd9b1680ae 127
bogdanm 86:04dd9b1680ae 128 /**
bogdanm 86:04dd9b1680ae 129 * @brief DMA handle Structure definition
bogdanm 86:04dd9b1680ae 130 */
bogdanm 86:04dd9b1680ae 131 typedef struct __DMA_HandleTypeDef
bogdanm 86:04dd9b1680ae 132 {
bogdanm 86:04dd9b1680ae 133 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 86:04dd9b1680ae 134
bogdanm 86:04dd9b1680ae 135 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 86:04dd9b1680ae 136
bogdanm 86:04dd9b1680ae 137 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 86:04dd9b1680ae 138
bogdanm 86:04dd9b1680ae 139 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 86:04dd9b1680ae 140
bogdanm 86:04dd9b1680ae 141 void *Parent; /*!< Parent object state */
bogdanm 86:04dd9b1680ae 142
bogdanm 86:04dd9b1680ae 143 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 86:04dd9b1680ae 144
bogdanm 86:04dd9b1680ae 145 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 86:04dd9b1680ae 146
bogdanm 86:04dd9b1680ae 147 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 86:04dd9b1680ae 148
bogdanm 86:04dd9b1680ae 149 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 86:04dd9b1680ae 150
bogdanm 86:04dd9b1680ae 151 } DMA_HandleTypeDef;
bogdanm 92:4fc01daae5a5 152 /**
bogdanm 92:4fc01daae5a5 153 * @}
bogdanm 92:4fc01daae5a5 154 */
bogdanm 86:04dd9b1680ae 155
bogdanm 86:04dd9b1680ae 156 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
bogdanm 86:04dd9b1680ae 158 * @{
bogdanm 86:04dd9b1680ae 159 */
bogdanm 86:04dd9b1680ae 160
bogdanm 92:4fc01daae5a5 161 /** @defgroup DMA_Error_Code DMA Error Code
bogdanm 86:04dd9b1680ae 162 * @{
bogdanm 86:04dd9b1680ae 163 */
bogdanm 86:04dd9b1680ae 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 86:04dd9b1680ae 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 86:04dd9b1680ae 166 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 86:04dd9b1680ae 167 /**
bogdanm 86:04dd9b1680ae 168 * @}
bogdanm 86:04dd9b1680ae 169 */
bogdanm 86:04dd9b1680ae 170
bogdanm 86:04dd9b1680ae 171
bogdanm 92:4fc01daae5a5 172 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
bogdanm 86:04dd9b1680ae 173 * @{
bogdanm 86:04dd9b1680ae 174 */
bogdanm 86:04dd9b1680ae 175 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 86:04dd9b1680ae 176 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
bogdanm 86:04dd9b1680ae 177 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
bogdanm 86:04dd9b1680ae 178
bogdanm 86:04dd9b1680ae 179 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 86:04dd9b1680ae 180 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 86:04dd9b1680ae 181 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 86:04dd9b1680ae 182 /**
bogdanm 86:04dd9b1680ae 183 * @}
bogdanm 86:04dd9b1680ae 184 */
bogdanm 86:04dd9b1680ae 185
bogdanm 92:4fc01daae5a5 186 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
bogdanm 86:04dd9b1680ae 187 * @{
bogdanm 86:04dd9b1680ae 188 */
bogdanm 86:04dd9b1680ae 189 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 86:04dd9b1680ae 190 /**
bogdanm 86:04dd9b1680ae 191 * @}
bogdanm 86:04dd9b1680ae 192 */
bogdanm 86:04dd9b1680ae 193
bogdanm 92:4fc01daae5a5 194 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
bogdanm 86:04dd9b1680ae 195 * @{
bogdanm 86:04dd9b1680ae 196 */
bogdanm 86:04dd9b1680ae 197 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
bogdanm 86:04dd9b1680ae 198 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 86:04dd9b1680ae 199
bogdanm 86:04dd9b1680ae 200 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 86:04dd9b1680ae 201 ((STATE) == DMA_PINC_DISABLE))
bogdanm 86:04dd9b1680ae 202 /**
bogdanm 86:04dd9b1680ae 203 * @}
bogdanm 86:04dd9b1680ae 204 */
bogdanm 86:04dd9b1680ae 205
bogdanm 92:4fc01daae5a5 206 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
bogdanm 86:04dd9b1680ae 207 * @{
bogdanm 86:04dd9b1680ae 208 */
bogdanm 86:04dd9b1680ae 209 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
bogdanm 86:04dd9b1680ae 210 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 86:04dd9b1680ae 211
bogdanm 86:04dd9b1680ae 212 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 86:04dd9b1680ae 213 ((STATE) == DMA_MINC_DISABLE))
bogdanm 86:04dd9b1680ae 214 /**
bogdanm 86:04dd9b1680ae 215 * @}
bogdanm 86:04dd9b1680ae 216 */
bogdanm 86:04dd9b1680ae 217
bogdanm 92:4fc01daae5a5 218 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
bogdanm 86:04dd9b1680ae 219 * @{
bogdanm 86:04dd9b1680ae 220 */
bogdanm 86:04dd9b1680ae 221 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
bogdanm 86:04dd9b1680ae 222 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
bogdanm 86:04dd9b1680ae 223 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
bogdanm 86:04dd9b1680ae 224
bogdanm 86:04dd9b1680ae 225 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 86:04dd9b1680ae 226 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 86:04dd9b1680ae 227 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 86:04dd9b1680ae 228 /**
bogdanm 86:04dd9b1680ae 229 * @}
bogdanm 86:04dd9b1680ae 230 */
bogdanm 86:04dd9b1680ae 231
bogdanm 86:04dd9b1680ae 232
bogdanm 92:4fc01daae5a5 233 /** @defgroup DMA_Memory_data_size DMA Memory data size
bogdanm 86:04dd9b1680ae 234 * @{
bogdanm 86:04dd9b1680ae 235 */
bogdanm 86:04dd9b1680ae 236 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
bogdanm 86:04dd9b1680ae 237 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
bogdanm 86:04dd9b1680ae 238 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
bogdanm 86:04dd9b1680ae 239
bogdanm 86:04dd9b1680ae 240 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 86:04dd9b1680ae 241 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 86:04dd9b1680ae 242 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 86:04dd9b1680ae 243 /**
bogdanm 86:04dd9b1680ae 244 * @}
bogdanm 86:04dd9b1680ae 245 */
bogdanm 86:04dd9b1680ae 246
bogdanm 92:4fc01daae5a5 247 /** @defgroup DMA_mode DMA mode
bogdanm 86:04dd9b1680ae 248 * @{
bogdanm 86:04dd9b1680ae 249 */
bogdanm 86:04dd9b1680ae 250 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
bogdanm 86:04dd9b1680ae 251 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
bogdanm 86:04dd9b1680ae 252
bogdanm 86:04dd9b1680ae 253 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 86:04dd9b1680ae 254 ((MODE) == DMA_CIRCULAR))
bogdanm 86:04dd9b1680ae 255 /**
bogdanm 86:04dd9b1680ae 256 * @}
bogdanm 86:04dd9b1680ae 257 */
bogdanm 86:04dd9b1680ae 258
bogdanm 92:4fc01daae5a5 259 /** @defgroup DMA_Priority_level DMA Priority level
bogdanm 86:04dd9b1680ae 260 * @{
bogdanm 86:04dd9b1680ae 261 */
bogdanm 86:04dd9b1680ae 262 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
bogdanm 86:04dd9b1680ae 263 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
bogdanm 86:04dd9b1680ae 264 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
bogdanm 86:04dd9b1680ae 265 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 86:04dd9b1680ae 266
bogdanm 86:04dd9b1680ae 267 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 86:04dd9b1680ae 268 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 86:04dd9b1680ae 269 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 86:04dd9b1680ae 270 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 86:04dd9b1680ae 271 /**
bogdanm 86:04dd9b1680ae 272 * @}
bogdanm 86:04dd9b1680ae 273 */
bogdanm 86:04dd9b1680ae 274
bogdanm 86:04dd9b1680ae 275
bogdanm 92:4fc01daae5a5 276 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
bogdanm 86:04dd9b1680ae 277 * @{
bogdanm 86:04dd9b1680ae 278 */
bogdanm 86:04dd9b1680ae 279
bogdanm 86:04dd9b1680ae 280 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 86:04dd9b1680ae 281 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 86:04dd9b1680ae 282 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 86:04dd9b1680ae 283
bogdanm 86:04dd9b1680ae 284 /**
bogdanm 86:04dd9b1680ae 285 * @}
bogdanm 86:04dd9b1680ae 286 */
bogdanm 86:04dd9b1680ae 287
bogdanm 92:4fc01daae5a5 288 /** @defgroup DMA_flag_definitions DMA flag definitions
bogdanm 86:04dd9b1680ae 289 * @{
bogdanm 86:04dd9b1680ae 290 */
bogdanm 86:04dd9b1680ae 291
bogdanm 86:04dd9b1680ae 292 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 293 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 294 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 295 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 296 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 297 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 298 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 299 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 300 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 301 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 302 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 303 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 304 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 305 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 306 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 307 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 308 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 309 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 310 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 311 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 312 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 313 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 314 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 315 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 316 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 317 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 318 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 319 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 320
bogdanm 86:04dd9b1680ae 321
bogdanm 86:04dd9b1680ae 322 /**
bogdanm 86:04dd9b1680ae 323 * @}
bogdanm 86:04dd9b1680ae 324 */
bogdanm 86:04dd9b1680ae 325
bogdanm 86:04dd9b1680ae 326 /**
bogdanm 86:04dd9b1680ae 327 * @}
bogdanm 86:04dd9b1680ae 328 */
bogdanm 86:04dd9b1680ae 329
bogdanm 86:04dd9b1680ae 330 /* Exported macros -----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 331 /** @defgroup DMA_Exported_Macros DMA Exported Macros
bogdanm 92:4fc01daae5a5 332 * @{
bogdanm 92:4fc01daae5a5 333 */
bogdanm 86:04dd9b1680ae 334
bogdanm 86:04dd9b1680ae 335 /** @brief Reset DMA handle state
bogdanm 86:04dd9b1680ae 336 * @param __HANDLE__: DMA handle.
bogdanm 86:04dd9b1680ae 337 * @retval None
bogdanm 86:04dd9b1680ae 338 */
bogdanm 86:04dd9b1680ae 339 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 86:04dd9b1680ae 340
bogdanm 86:04dd9b1680ae 341 /**
bogdanm 86:04dd9b1680ae 342 * @brief Enable the specified DMA Channel.
bogdanm 86:04dd9b1680ae 343 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 344 * @retval None.
bogdanm 86:04dd9b1680ae 345 */
bogdanm 86:04dd9b1680ae 346 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
bogdanm 86:04dd9b1680ae 347
bogdanm 86:04dd9b1680ae 348 /**
bogdanm 86:04dd9b1680ae 349 * @brief Disable the specified DMA Channel.
bogdanm 86:04dd9b1680ae 350 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 351 * @retval None.
bogdanm 86:04dd9b1680ae 352 */
bogdanm 86:04dd9b1680ae 353 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
bogdanm 86:04dd9b1680ae 354
bogdanm 86:04dd9b1680ae 355
bogdanm 86:04dd9b1680ae 356 /* Interrupt & Flag management */
bogdanm 86:04dd9b1680ae 357
bogdanm 86:04dd9b1680ae 358 /**
bogdanm 86:04dd9b1680ae 359 * @brief Enables the specified DMA Channel interrupts.
bogdanm 86:04dd9b1680ae 360 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 361 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 86:04dd9b1680ae 362 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 363 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 364 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 365 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 366 * @retval None
bogdanm 86:04dd9b1680ae 367 */
bogdanm 86:04dd9b1680ae 368 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 369
bogdanm 86:04dd9b1680ae 370 /**
bogdanm 86:04dd9b1680ae 371 * @brief Disables the specified DMA Channel interrupts.
bogdanm 86:04dd9b1680ae 372 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 373 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 86:04dd9b1680ae 374 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 375 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 376 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 377 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 378 * @retval None
bogdanm 86:04dd9b1680ae 379 */
bogdanm 86:04dd9b1680ae 380 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 381
bogdanm 86:04dd9b1680ae 382 /**
bogdanm 86:04dd9b1680ae 383 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
bogdanm 86:04dd9b1680ae 384 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 385 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 86:04dd9b1680ae 386 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 387 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 388 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 389 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 390 * @retval The state of DMA_IT (SET or RESET).
bogdanm 86:04dd9b1680ae 391 */
bogdanm 86:04dd9b1680ae 392 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 86:04dd9b1680ae 393
bogdanm 92:4fc01daae5a5 394 /**
bogdanm 92:4fc01daae5a5 395 * @}
bogdanm 92:4fc01daae5a5 396 */
bogdanm 92:4fc01daae5a5 397
bogdanm 92:4fc01daae5a5 398 /* Include DMA HAL Extended module */
bogdanm 86:04dd9b1680ae 399 #include "stm32f3xx_hal_dma_ex.h"
bogdanm 86:04dd9b1680ae 400
bogdanm 86:04dd9b1680ae 401 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 402 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
bogdanm 92:4fc01daae5a5 403 * @{
bogdanm 92:4fc01daae5a5 404 */
bogdanm 92:4fc01daae5a5 405
bogdanm 92:4fc01daae5a5 406 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 92:4fc01daae5a5 407 * @{
bogdanm 92:4fc01daae5a5 408 */
bogdanm 86:04dd9b1680ae 409 /* Initialization and de-initialization functions *****************************/
bogdanm 86:04dd9b1680ae 410 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 411 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 412
bogdanm 92:4fc01daae5a5 413 /**
bogdanm 92:4fc01daae5a5 414 * @}
bogdanm 92:4fc01daae5a5 415 */
bogdanm 92:4fc01daae5a5 416
bogdanm 92:4fc01daae5a5 417 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
bogdanm 92:4fc01daae5a5 418 * @{
bogdanm 92:4fc01daae5a5 419 */
bogdanm 86:04dd9b1680ae 420 /* IO operation functions *****************************************************/
bogdanm 86:04dd9b1680ae 421 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 86:04dd9b1680ae 422 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 86:04dd9b1680ae 423 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 424 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 86:04dd9b1680ae 425 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 426
bogdanm 92:4fc01daae5a5 427 /**
bogdanm 92:4fc01daae5a5 428 * @}
bogdanm 92:4fc01daae5a5 429 */
bogdanm 92:4fc01daae5a5 430
bogdanm 92:4fc01daae5a5 431 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
bogdanm 92:4fc01daae5a5 432 * @{
bogdanm 92:4fc01daae5a5 433 */
bogdanm 86:04dd9b1680ae 434 /* Peripheral State and Error functions ***************************************/
bogdanm 86:04dd9b1680ae 435 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 436 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 437
bogdanm 86:04dd9b1680ae 438 /**
bogdanm 86:04dd9b1680ae 439 * @}
bogdanm 92:4fc01daae5a5 440 */
bogdanm 92:4fc01daae5a5 441
bogdanm 92:4fc01daae5a5 442 /**
bogdanm 92:4fc01daae5a5 443 * @}
bogdanm 92:4fc01daae5a5 444 */
bogdanm 92:4fc01daae5a5 445
bogdanm 92:4fc01daae5a5 446 /**
bogdanm 92:4fc01daae5a5 447 * @}
bogdanm 86:04dd9b1680ae 448 */
bogdanm 86:04dd9b1680ae 449
bogdanm 86:04dd9b1680ae 450 /**
bogdanm 86:04dd9b1680ae 451 * @}
bogdanm 86:04dd9b1680ae 452 */
bogdanm 86:04dd9b1680ae 453
bogdanm 86:04dd9b1680ae 454 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 455 }
bogdanm 86:04dd9b1680ae 456 #endif
bogdanm 86:04dd9b1680ae 457
bogdanm 86:04dd9b1680ae 458 #endif /* __STM32F3xx_HAL_DMA_H */
bogdanm 86:04dd9b1680ae 459
bogdanm 86:04dd9b1680ae 460 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/