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TARGET_ARCH_PRO/LPC17xx.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
85:024bf7f99721 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**************************************************************************//**
bogdanm 85:024bf7f99721 2 * @file LPC17xx.h
bogdanm 85:024bf7f99721 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
bogdanm 85:024bf7f99721 4 * NXP LPC17xx Device Series
bogdanm 85:024bf7f99721 5 * @version: V1.09
bogdanm 85:024bf7f99721 6 * @date: 17. March 2010
bogdanm 85:024bf7f99721 7
bogdanm 85:024bf7f99721 8 *
bogdanm 85:024bf7f99721 9 * @note
bogdanm 85:024bf7f99721 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
bogdanm 85:024bf7f99721 11 *
bogdanm 85:024bf7f99721 12 * @par
bogdanm 85:024bf7f99721 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 85:024bf7f99721 14 * processor based microcontrollers. This file can be freely distributed
bogdanm 85:024bf7f99721 15 * within development tools that are supporting such ARM based processors.
bogdanm 85:024bf7f99721 16 *
bogdanm 85:024bf7f99721 17 * @par
bogdanm 85:024bf7f99721 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 85:024bf7f99721 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 85:024bf7f99721 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 85:024bf7f99721 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 85:024bf7f99721 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 ******************************************************************************/
bogdanm 85:024bf7f99721 25
bogdanm 85:024bf7f99721 26
bogdanm 85:024bf7f99721 27 #ifndef __LPC17xx_H__
bogdanm 85:024bf7f99721 28 #define __LPC17xx_H__
bogdanm 85:024bf7f99721 29
bogdanm 85:024bf7f99721 30 /*
bogdanm 85:024bf7f99721 31 * ==========================================================================
bogdanm 85:024bf7f99721 32 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 85:024bf7f99721 33 * ==========================================================================
bogdanm 85:024bf7f99721 34 */
bogdanm 85:024bf7f99721 35
bogdanm 85:024bf7f99721 36 typedef enum IRQn
bogdanm 85:024bf7f99721 37 {
bogdanm 85:024bf7f99721 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
bogdanm 85:024bf7f99721 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 85:024bf7f99721 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
bogdanm 85:024bf7f99721 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
bogdanm 85:024bf7f99721 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
bogdanm 85:024bf7f99721 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
bogdanm 85:024bf7f99721 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
bogdanm 85:024bf7f99721 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
bogdanm 85:024bf7f99721 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
bogdanm 85:024bf7f99721 47
bogdanm 85:024bf7f99721 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
bogdanm 85:024bf7f99721 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
bogdanm 85:024bf7f99721 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
bogdanm 85:024bf7f99721 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
bogdanm 85:024bf7f99721 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
bogdanm 85:024bf7f99721 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
bogdanm 85:024bf7f99721 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
bogdanm 85:024bf7f99721 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
bogdanm 85:024bf7f99721 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
bogdanm 85:024bf7f99721 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
bogdanm 85:024bf7f99721 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
bogdanm 85:024bf7f99721 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
bogdanm 85:024bf7f99721 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
bogdanm 85:024bf7f99721 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
bogdanm 85:024bf7f99721 62 SPI_IRQn = 13, /*!< SPI Interrupt */
bogdanm 85:024bf7f99721 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
bogdanm 85:024bf7f99721 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
bogdanm 85:024bf7f99721 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
bogdanm 85:024bf7f99721 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
bogdanm 85:024bf7f99721 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
bogdanm 85:024bf7f99721 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
bogdanm 85:024bf7f99721 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
bogdanm 85:024bf7f99721 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
bogdanm 85:024bf7f99721 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
bogdanm 85:024bf7f99721 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
bogdanm 85:024bf7f99721 73 USB_IRQn = 24, /*!< USB Interrupt */
bogdanm 85:024bf7f99721 74 CAN_IRQn = 25, /*!< CAN Interrupt */
bogdanm 85:024bf7f99721 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
bogdanm 85:024bf7f99721 76 I2S_IRQn = 27, /*!< I2S Interrupt */
bogdanm 85:024bf7f99721 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
bogdanm 85:024bf7f99721 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
bogdanm 85:024bf7f99721 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
bogdanm 85:024bf7f99721 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
bogdanm 85:024bf7f99721 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
bogdanm 85:024bf7f99721 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
bogdanm 85:024bf7f99721 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
bogdanm 85:024bf7f99721 84 } IRQn_Type;
bogdanm 85:024bf7f99721 85
bogdanm 85:024bf7f99721 86
bogdanm 85:024bf7f99721 87 /*
bogdanm 85:024bf7f99721 88 * ==========================================================================
bogdanm 85:024bf7f99721 89 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 85:024bf7f99721 90 * ==========================================================================
bogdanm 85:024bf7f99721 91 */
bogdanm 85:024bf7f99721 92
bogdanm 85:024bf7f99721 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
bogdanm 85:024bf7f99721 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 85:024bf7f99721 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 85:024bf7f99721 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 85:024bf7f99721 97
bogdanm 85:024bf7f99721 98
bogdanm 85:024bf7f99721 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
bogdanm 85:024bf7f99721 100 #include "system_LPC17xx.h" /* System Header */
bogdanm 85:024bf7f99721 101
bogdanm 85:024bf7f99721 102
bogdanm 85:024bf7f99721 103 /******************************************************************************/
bogdanm 85:024bf7f99721 104 /* Device Specific Peripheral registers structures */
bogdanm 85:024bf7f99721 105 /******************************************************************************/
bogdanm 85:024bf7f99721 106
bogdanm 85:024bf7f99721 107 #if defined ( __CC_ARM )
bogdanm 85:024bf7f99721 108 #pragma anon_unions
bogdanm 85:024bf7f99721 109 #endif
bogdanm 85:024bf7f99721 110
bogdanm 85:024bf7f99721 111 /*------------- System Control (SC) ------------------------------------------*/
bogdanm 85:024bf7f99721 112 typedef struct
bogdanm 85:024bf7f99721 113 {
bogdanm 85:024bf7f99721 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
bogdanm 85:024bf7f99721 115 uint32_t RESERVED0[31];
bogdanm 85:024bf7f99721 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
bogdanm 85:024bf7f99721 117 __IO uint32_t PLL0CFG;
bogdanm 85:024bf7f99721 118 __I uint32_t PLL0STAT;
bogdanm 85:024bf7f99721 119 __O uint32_t PLL0FEED;
bogdanm 85:024bf7f99721 120 uint32_t RESERVED1[4];
bogdanm 85:024bf7f99721 121 __IO uint32_t PLL1CON;
bogdanm 85:024bf7f99721 122 __IO uint32_t PLL1CFG;
bogdanm 85:024bf7f99721 123 __I uint32_t PLL1STAT;
bogdanm 85:024bf7f99721 124 __O uint32_t PLL1FEED;
bogdanm 85:024bf7f99721 125 uint32_t RESERVED2[4];
bogdanm 85:024bf7f99721 126 __IO uint32_t PCON;
bogdanm 85:024bf7f99721 127 __IO uint32_t PCONP;
bogdanm 85:024bf7f99721 128 uint32_t RESERVED3[15];
bogdanm 85:024bf7f99721 129 __IO uint32_t CCLKCFG;
bogdanm 85:024bf7f99721 130 __IO uint32_t USBCLKCFG;
bogdanm 85:024bf7f99721 131 __IO uint32_t CLKSRCSEL;
bogdanm 85:024bf7f99721 132 __IO uint32_t CANSLEEPCLR;
bogdanm 85:024bf7f99721 133 __IO uint32_t CANWAKEFLAGS;
bogdanm 85:024bf7f99721 134 uint32_t RESERVED4[10];
bogdanm 85:024bf7f99721 135 __IO uint32_t EXTINT; /* External Interrupts */
bogdanm 85:024bf7f99721 136 uint32_t RESERVED5;
bogdanm 85:024bf7f99721 137 __IO uint32_t EXTMODE;
bogdanm 85:024bf7f99721 138 __IO uint32_t EXTPOLAR;
bogdanm 85:024bf7f99721 139 uint32_t RESERVED6[12];
bogdanm 85:024bf7f99721 140 __IO uint32_t RSID; /* Reset */
bogdanm 85:024bf7f99721 141 uint32_t RESERVED7[7];
bogdanm 85:024bf7f99721 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
bogdanm 85:024bf7f99721 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
bogdanm 85:024bf7f99721 144 __IO uint32_t PCLKSEL0;
bogdanm 85:024bf7f99721 145 __IO uint32_t PCLKSEL1;
bogdanm 85:024bf7f99721 146 uint32_t RESERVED8[4];
bogdanm 85:024bf7f99721 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
bogdanm 85:024bf7f99721 148 __IO uint32_t DMAREQSEL;
bogdanm 85:024bf7f99721 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
bogdanm 85:024bf7f99721 150 } LPC_SC_TypeDef;
bogdanm 85:024bf7f99721 151
bogdanm 85:024bf7f99721 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
bogdanm 85:024bf7f99721 153 typedef struct
bogdanm 85:024bf7f99721 154 {
bogdanm 85:024bf7f99721 155 __IO uint32_t PINSEL0;
bogdanm 85:024bf7f99721 156 __IO uint32_t PINSEL1;
bogdanm 85:024bf7f99721 157 __IO uint32_t PINSEL2;
bogdanm 85:024bf7f99721 158 __IO uint32_t PINSEL3;
bogdanm 85:024bf7f99721 159 __IO uint32_t PINSEL4;
bogdanm 85:024bf7f99721 160 __IO uint32_t PINSEL5;
bogdanm 85:024bf7f99721 161 __IO uint32_t PINSEL6;
bogdanm 85:024bf7f99721 162 __IO uint32_t PINSEL7;
bogdanm 85:024bf7f99721 163 __IO uint32_t PINSEL8;
bogdanm 85:024bf7f99721 164 __IO uint32_t PINSEL9;
bogdanm 85:024bf7f99721 165 __IO uint32_t PINSEL10;
bogdanm 85:024bf7f99721 166 uint32_t RESERVED0[5];
bogdanm 85:024bf7f99721 167 __IO uint32_t PINMODE0;
bogdanm 85:024bf7f99721 168 __IO uint32_t PINMODE1;
bogdanm 85:024bf7f99721 169 __IO uint32_t PINMODE2;
bogdanm 85:024bf7f99721 170 __IO uint32_t PINMODE3;
bogdanm 85:024bf7f99721 171 __IO uint32_t PINMODE4;
bogdanm 85:024bf7f99721 172 __IO uint32_t PINMODE5;
bogdanm 85:024bf7f99721 173 __IO uint32_t PINMODE6;
bogdanm 85:024bf7f99721 174 __IO uint32_t PINMODE7;
bogdanm 85:024bf7f99721 175 __IO uint32_t PINMODE8;
bogdanm 85:024bf7f99721 176 __IO uint32_t PINMODE9;
bogdanm 85:024bf7f99721 177 __IO uint32_t PINMODE_OD0;
bogdanm 85:024bf7f99721 178 __IO uint32_t PINMODE_OD1;
bogdanm 85:024bf7f99721 179 __IO uint32_t PINMODE_OD2;
bogdanm 85:024bf7f99721 180 __IO uint32_t PINMODE_OD3;
bogdanm 85:024bf7f99721 181 __IO uint32_t PINMODE_OD4;
bogdanm 85:024bf7f99721 182 __IO uint32_t I2CPADCFG;
bogdanm 85:024bf7f99721 183 } LPC_PINCON_TypeDef;
bogdanm 85:024bf7f99721 184
bogdanm 85:024bf7f99721 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 85:024bf7f99721 186 typedef struct
bogdanm 85:024bf7f99721 187 {
bogdanm 85:024bf7f99721 188 union {
bogdanm 85:024bf7f99721 189 __IO uint32_t FIODIR;
bogdanm 85:024bf7f99721 190 struct {
bogdanm 85:024bf7f99721 191 __IO uint16_t FIODIRL;
bogdanm 85:024bf7f99721 192 __IO uint16_t FIODIRH;
bogdanm 85:024bf7f99721 193 };
bogdanm 85:024bf7f99721 194 struct {
bogdanm 85:024bf7f99721 195 __IO uint8_t FIODIR0;
bogdanm 85:024bf7f99721 196 __IO uint8_t FIODIR1;
bogdanm 85:024bf7f99721 197 __IO uint8_t FIODIR2;
bogdanm 85:024bf7f99721 198 __IO uint8_t FIODIR3;
bogdanm 85:024bf7f99721 199 };
bogdanm 85:024bf7f99721 200 };
bogdanm 85:024bf7f99721 201 uint32_t RESERVED0[3];
bogdanm 85:024bf7f99721 202 union {
bogdanm 85:024bf7f99721 203 __IO uint32_t FIOMASK;
bogdanm 85:024bf7f99721 204 struct {
bogdanm 85:024bf7f99721 205 __IO uint16_t FIOMASKL;
bogdanm 85:024bf7f99721 206 __IO uint16_t FIOMASKH;
bogdanm 85:024bf7f99721 207 };
bogdanm 85:024bf7f99721 208 struct {
bogdanm 85:024bf7f99721 209 __IO uint8_t FIOMASK0;
bogdanm 85:024bf7f99721 210 __IO uint8_t FIOMASK1;
bogdanm 85:024bf7f99721 211 __IO uint8_t FIOMASK2;
bogdanm 85:024bf7f99721 212 __IO uint8_t FIOMASK3;
bogdanm 85:024bf7f99721 213 };
bogdanm 85:024bf7f99721 214 };
bogdanm 85:024bf7f99721 215 union {
bogdanm 85:024bf7f99721 216 __IO uint32_t FIOPIN;
bogdanm 85:024bf7f99721 217 struct {
bogdanm 85:024bf7f99721 218 __IO uint16_t FIOPINL;
bogdanm 85:024bf7f99721 219 __IO uint16_t FIOPINH;
bogdanm 85:024bf7f99721 220 };
bogdanm 85:024bf7f99721 221 struct {
bogdanm 85:024bf7f99721 222 __IO uint8_t FIOPIN0;
bogdanm 85:024bf7f99721 223 __IO uint8_t FIOPIN1;
bogdanm 85:024bf7f99721 224 __IO uint8_t FIOPIN2;
bogdanm 85:024bf7f99721 225 __IO uint8_t FIOPIN3;
bogdanm 85:024bf7f99721 226 };
bogdanm 85:024bf7f99721 227 };
bogdanm 85:024bf7f99721 228 union {
bogdanm 85:024bf7f99721 229 __IO uint32_t FIOSET;
bogdanm 85:024bf7f99721 230 struct {
bogdanm 85:024bf7f99721 231 __IO uint16_t FIOSETL;
bogdanm 85:024bf7f99721 232 __IO uint16_t FIOSETH;
bogdanm 85:024bf7f99721 233 };
bogdanm 85:024bf7f99721 234 struct {
bogdanm 85:024bf7f99721 235 __IO uint8_t FIOSET0;
bogdanm 85:024bf7f99721 236 __IO uint8_t FIOSET1;
bogdanm 85:024bf7f99721 237 __IO uint8_t FIOSET2;
bogdanm 85:024bf7f99721 238 __IO uint8_t FIOSET3;
bogdanm 85:024bf7f99721 239 };
bogdanm 85:024bf7f99721 240 };
bogdanm 85:024bf7f99721 241 union {
bogdanm 85:024bf7f99721 242 __O uint32_t FIOCLR;
bogdanm 85:024bf7f99721 243 struct {
bogdanm 85:024bf7f99721 244 __O uint16_t FIOCLRL;
bogdanm 85:024bf7f99721 245 __O uint16_t FIOCLRH;
bogdanm 85:024bf7f99721 246 };
bogdanm 85:024bf7f99721 247 struct {
bogdanm 85:024bf7f99721 248 __O uint8_t FIOCLR0;
bogdanm 85:024bf7f99721 249 __O uint8_t FIOCLR1;
bogdanm 85:024bf7f99721 250 __O uint8_t FIOCLR2;
bogdanm 85:024bf7f99721 251 __O uint8_t FIOCLR3;
bogdanm 85:024bf7f99721 252 };
bogdanm 85:024bf7f99721 253 };
bogdanm 85:024bf7f99721 254 } LPC_GPIO_TypeDef;
bogdanm 85:024bf7f99721 255
bogdanm 85:024bf7f99721 256 typedef struct
bogdanm 85:024bf7f99721 257 {
bogdanm 85:024bf7f99721 258 __I uint32_t IntStatus;
bogdanm 85:024bf7f99721 259 __I uint32_t IO0IntStatR;
bogdanm 85:024bf7f99721 260 __I uint32_t IO0IntStatF;
bogdanm 85:024bf7f99721 261 __O uint32_t IO0IntClr;
bogdanm 85:024bf7f99721 262 __IO uint32_t IO0IntEnR;
bogdanm 85:024bf7f99721 263 __IO uint32_t IO0IntEnF;
bogdanm 85:024bf7f99721 264 uint32_t RESERVED0[3];
bogdanm 85:024bf7f99721 265 __I uint32_t IO2IntStatR;
bogdanm 85:024bf7f99721 266 __I uint32_t IO2IntStatF;
bogdanm 85:024bf7f99721 267 __O uint32_t IO2IntClr;
bogdanm 85:024bf7f99721 268 __IO uint32_t IO2IntEnR;
bogdanm 85:024bf7f99721 269 __IO uint32_t IO2IntEnF;
bogdanm 85:024bf7f99721 270 } LPC_GPIOINT_TypeDef;
bogdanm 85:024bf7f99721 271
bogdanm 85:024bf7f99721 272 /*------------- Timer (TIM) --------------------------------------------------*/
bogdanm 85:024bf7f99721 273 typedef struct
bogdanm 85:024bf7f99721 274 {
bogdanm 85:024bf7f99721 275 __IO uint32_t IR;
bogdanm 85:024bf7f99721 276 __IO uint32_t TCR;
bogdanm 85:024bf7f99721 277 __IO uint32_t TC;
bogdanm 85:024bf7f99721 278 __IO uint32_t PR;
bogdanm 85:024bf7f99721 279 __IO uint32_t PC;
bogdanm 85:024bf7f99721 280 __IO uint32_t MCR;
bogdanm 85:024bf7f99721 281 __IO uint32_t MR0;
bogdanm 85:024bf7f99721 282 __IO uint32_t MR1;
bogdanm 85:024bf7f99721 283 __IO uint32_t MR2;
bogdanm 85:024bf7f99721 284 __IO uint32_t MR3;
bogdanm 85:024bf7f99721 285 __IO uint32_t CCR;
bogdanm 85:024bf7f99721 286 __I uint32_t CR0;
bogdanm 85:024bf7f99721 287 __I uint32_t CR1;
bogdanm 85:024bf7f99721 288 uint32_t RESERVED0[2];
bogdanm 85:024bf7f99721 289 __IO uint32_t EMR;
bogdanm 85:024bf7f99721 290 uint32_t RESERVED1[12];
bogdanm 85:024bf7f99721 291 __IO uint32_t CTCR;
bogdanm 85:024bf7f99721 292 } LPC_TIM_TypeDef;
bogdanm 85:024bf7f99721 293
bogdanm 85:024bf7f99721 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
bogdanm 85:024bf7f99721 295 typedef struct
bogdanm 85:024bf7f99721 296 {
bogdanm 85:024bf7f99721 297 __IO uint32_t IR;
bogdanm 85:024bf7f99721 298 __IO uint32_t TCR;
bogdanm 85:024bf7f99721 299 __IO uint32_t TC;
bogdanm 85:024bf7f99721 300 __IO uint32_t PR;
bogdanm 85:024bf7f99721 301 __IO uint32_t PC;
bogdanm 85:024bf7f99721 302 __IO uint32_t MCR;
bogdanm 85:024bf7f99721 303 __IO uint32_t MR0;
bogdanm 85:024bf7f99721 304 __IO uint32_t MR1;
bogdanm 85:024bf7f99721 305 __IO uint32_t MR2;
bogdanm 85:024bf7f99721 306 __IO uint32_t MR3;
bogdanm 85:024bf7f99721 307 __IO uint32_t CCR;
bogdanm 85:024bf7f99721 308 __I uint32_t CR0;
bogdanm 85:024bf7f99721 309 __I uint32_t CR1;
bogdanm 85:024bf7f99721 310 __I uint32_t CR2;
bogdanm 85:024bf7f99721 311 __I uint32_t CR3;
bogdanm 85:024bf7f99721 312 uint32_t RESERVED0;
bogdanm 85:024bf7f99721 313 __IO uint32_t MR4;
bogdanm 85:024bf7f99721 314 __IO uint32_t MR5;
bogdanm 85:024bf7f99721 315 __IO uint32_t MR6;
bogdanm 85:024bf7f99721 316 __IO uint32_t PCR;
bogdanm 85:024bf7f99721 317 __IO uint32_t LER;
bogdanm 85:024bf7f99721 318 uint32_t RESERVED1[7];
bogdanm 85:024bf7f99721 319 __IO uint32_t CTCR;
bogdanm 85:024bf7f99721 320 } LPC_PWM_TypeDef;
bogdanm 85:024bf7f99721 321
bogdanm 85:024bf7f99721 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
bogdanm 85:024bf7f99721 323 typedef struct
bogdanm 85:024bf7f99721 324 {
bogdanm 85:024bf7f99721 325 union {
bogdanm 85:024bf7f99721 326 __I uint8_t RBR;
bogdanm 85:024bf7f99721 327 __O uint8_t THR;
bogdanm 85:024bf7f99721 328 __IO uint8_t DLL;
bogdanm 85:024bf7f99721 329 uint32_t RESERVED0;
bogdanm 85:024bf7f99721 330 };
bogdanm 85:024bf7f99721 331 union {
bogdanm 85:024bf7f99721 332 __IO uint8_t DLM;
bogdanm 85:024bf7f99721 333 __IO uint32_t IER;
bogdanm 85:024bf7f99721 334 };
bogdanm 85:024bf7f99721 335 union {
bogdanm 85:024bf7f99721 336 __I uint32_t IIR;
bogdanm 85:024bf7f99721 337 __O uint8_t FCR;
bogdanm 85:024bf7f99721 338 };
bogdanm 85:024bf7f99721 339 __IO uint8_t LCR;
bogdanm 85:024bf7f99721 340 uint8_t RESERVED1[7];
bogdanm 85:024bf7f99721 341 __I uint8_t LSR;
bogdanm 85:024bf7f99721 342 uint8_t RESERVED2[7];
bogdanm 85:024bf7f99721 343 __IO uint8_t SCR;
bogdanm 85:024bf7f99721 344 uint8_t RESERVED3[3];
bogdanm 85:024bf7f99721 345 __IO uint32_t ACR;
bogdanm 85:024bf7f99721 346 __IO uint8_t ICR;
bogdanm 85:024bf7f99721 347 uint8_t RESERVED4[3];
bogdanm 85:024bf7f99721 348 __IO uint8_t FDR;
bogdanm 85:024bf7f99721 349 uint8_t RESERVED5[7];
bogdanm 85:024bf7f99721 350 __IO uint8_t TER;
bogdanm 85:024bf7f99721 351 uint8_t RESERVED6[39];
bogdanm 85:024bf7f99721 352 __IO uint32_t FIFOLVL;
bogdanm 85:024bf7f99721 353 } LPC_UART_TypeDef;
bogdanm 85:024bf7f99721 354
bogdanm 85:024bf7f99721 355 typedef struct
bogdanm 85:024bf7f99721 356 {
bogdanm 85:024bf7f99721 357 union {
bogdanm 85:024bf7f99721 358 __I uint8_t RBR;
bogdanm 85:024bf7f99721 359 __O uint8_t THR;
bogdanm 85:024bf7f99721 360 __IO uint8_t DLL;
bogdanm 85:024bf7f99721 361 uint32_t RESERVED0;
bogdanm 85:024bf7f99721 362 };
bogdanm 85:024bf7f99721 363 union {
bogdanm 85:024bf7f99721 364 __IO uint8_t DLM;
bogdanm 85:024bf7f99721 365 __IO uint32_t IER;
bogdanm 85:024bf7f99721 366 };
bogdanm 85:024bf7f99721 367 union {
bogdanm 85:024bf7f99721 368 __I uint32_t IIR;
bogdanm 85:024bf7f99721 369 __O uint8_t FCR;
bogdanm 85:024bf7f99721 370 };
bogdanm 85:024bf7f99721 371 __IO uint8_t LCR;
bogdanm 85:024bf7f99721 372 uint8_t RESERVED1[7];
bogdanm 85:024bf7f99721 373 __I uint8_t LSR;
bogdanm 85:024bf7f99721 374 uint8_t RESERVED2[7];
bogdanm 85:024bf7f99721 375 __IO uint8_t SCR;
bogdanm 85:024bf7f99721 376 uint8_t RESERVED3[3];
bogdanm 85:024bf7f99721 377 __IO uint32_t ACR;
bogdanm 85:024bf7f99721 378 __IO uint8_t ICR;
bogdanm 85:024bf7f99721 379 uint8_t RESERVED4[3];
bogdanm 85:024bf7f99721 380 __IO uint8_t FDR;
bogdanm 85:024bf7f99721 381 uint8_t RESERVED5[7];
bogdanm 85:024bf7f99721 382 __IO uint8_t TER;
bogdanm 85:024bf7f99721 383 uint8_t RESERVED6[39];
bogdanm 85:024bf7f99721 384 __IO uint32_t FIFOLVL;
bogdanm 85:024bf7f99721 385 } LPC_UART0_TypeDef;
bogdanm 85:024bf7f99721 386
bogdanm 85:024bf7f99721 387 typedef struct
bogdanm 85:024bf7f99721 388 {
bogdanm 85:024bf7f99721 389 union {
bogdanm 85:024bf7f99721 390 __I uint8_t RBR;
bogdanm 85:024bf7f99721 391 __O uint8_t THR;
bogdanm 85:024bf7f99721 392 __IO uint8_t DLL;
bogdanm 85:024bf7f99721 393 uint32_t RESERVED0;
bogdanm 85:024bf7f99721 394 };
bogdanm 85:024bf7f99721 395 union {
bogdanm 85:024bf7f99721 396 __IO uint8_t DLM;
bogdanm 85:024bf7f99721 397 __IO uint32_t IER;
bogdanm 85:024bf7f99721 398 };
bogdanm 85:024bf7f99721 399 union {
bogdanm 85:024bf7f99721 400 __I uint32_t IIR;
bogdanm 85:024bf7f99721 401 __O uint8_t FCR;
bogdanm 85:024bf7f99721 402 };
bogdanm 85:024bf7f99721 403 __IO uint8_t LCR;
bogdanm 85:024bf7f99721 404 uint8_t RESERVED1[3];
bogdanm 85:024bf7f99721 405 __IO uint8_t MCR;
bogdanm 85:024bf7f99721 406 uint8_t RESERVED2[3];
bogdanm 85:024bf7f99721 407 __I uint8_t LSR;
bogdanm 85:024bf7f99721 408 uint8_t RESERVED3[3];
bogdanm 85:024bf7f99721 409 __I uint8_t MSR;
bogdanm 85:024bf7f99721 410 uint8_t RESERVED4[3];
bogdanm 85:024bf7f99721 411 __IO uint8_t SCR;
bogdanm 85:024bf7f99721 412 uint8_t RESERVED5[3];
bogdanm 85:024bf7f99721 413 __IO uint32_t ACR;
bogdanm 85:024bf7f99721 414 uint32_t RESERVED6;
bogdanm 85:024bf7f99721 415 __IO uint32_t FDR;
bogdanm 85:024bf7f99721 416 uint32_t RESERVED7;
bogdanm 85:024bf7f99721 417 __IO uint8_t TER;
bogdanm 85:024bf7f99721 418 uint8_t RESERVED8[27];
bogdanm 85:024bf7f99721 419 __IO uint8_t RS485CTRL;
bogdanm 85:024bf7f99721 420 uint8_t RESERVED9[3];
bogdanm 85:024bf7f99721 421 __IO uint8_t ADRMATCH;
bogdanm 85:024bf7f99721 422 uint8_t RESERVED10[3];
bogdanm 85:024bf7f99721 423 __IO uint8_t RS485DLY;
bogdanm 85:024bf7f99721 424 uint8_t RESERVED11[3];
bogdanm 85:024bf7f99721 425 __IO uint32_t FIFOLVL;
bogdanm 85:024bf7f99721 426 } LPC_UART1_TypeDef;
bogdanm 85:024bf7f99721 427
bogdanm 85:024bf7f99721 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
bogdanm 85:024bf7f99721 429 typedef struct
bogdanm 85:024bf7f99721 430 {
bogdanm 85:024bf7f99721 431 __IO uint32_t SPCR;
bogdanm 85:024bf7f99721 432 __I uint32_t SPSR;
bogdanm 85:024bf7f99721 433 __IO uint32_t SPDR;
bogdanm 85:024bf7f99721 434 __IO uint32_t SPCCR;
bogdanm 85:024bf7f99721 435 uint32_t RESERVED0[3];
bogdanm 85:024bf7f99721 436 __IO uint32_t SPINT;
bogdanm 85:024bf7f99721 437 } LPC_SPI_TypeDef;
bogdanm 85:024bf7f99721 438
bogdanm 85:024bf7f99721 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 85:024bf7f99721 440 typedef struct
bogdanm 85:024bf7f99721 441 {
bogdanm 85:024bf7f99721 442 __IO uint32_t CR0;
bogdanm 85:024bf7f99721 443 __IO uint32_t CR1;
bogdanm 85:024bf7f99721 444 __IO uint32_t DR;
bogdanm 85:024bf7f99721 445 __I uint32_t SR;
bogdanm 85:024bf7f99721 446 __IO uint32_t CPSR;
bogdanm 85:024bf7f99721 447 __IO uint32_t IMSC;
bogdanm 85:024bf7f99721 448 __IO uint32_t RIS;
bogdanm 85:024bf7f99721 449 __IO uint32_t MIS;
bogdanm 85:024bf7f99721 450 __IO uint32_t ICR;
bogdanm 85:024bf7f99721 451 __IO uint32_t DMACR;
bogdanm 85:024bf7f99721 452 } LPC_SSP_TypeDef;
bogdanm 85:024bf7f99721 453
bogdanm 85:024bf7f99721 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 85:024bf7f99721 455 typedef struct
bogdanm 85:024bf7f99721 456 {
bogdanm 85:024bf7f99721 457 __IO uint32_t I2CONSET;
bogdanm 85:024bf7f99721 458 __I uint32_t I2STAT;
bogdanm 85:024bf7f99721 459 __IO uint32_t I2DAT;
bogdanm 85:024bf7f99721 460 __IO uint32_t I2ADR0;
bogdanm 85:024bf7f99721 461 __IO uint32_t I2SCLH;
bogdanm 85:024bf7f99721 462 __IO uint32_t I2SCLL;
bogdanm 85:024bf7f99721 463 __O uint32_t I2CONCLR;
bogdanm 85:024bf7f99721 464 __IO uint32_t MMCTRL;
bogdanm 85:024bf7f99721 465 __IO uint32_t I2ADR1;
bogdanm 85:024bf7f99721 466 __IO uint32_t I2ADR2;
bogdanm 85:024bf7f99721 467 __IO uint32_t I2ADR3;
bogdanm 85:024bf7f99721 468 __I uint32_t I2DATA_BUFFER;
bogdanm 85:024bf7f99721 469 __IO uint32_t I2MASK0;
bogdanm 85:024bf7f99721 470 __IO uint32_t I2MASK1;
bogdanm 85:024bf7f99721 471 __IO uint32_t I2MASK2;
bogdanm 85:024bf7f99721 472 __IO uint32_t I2MASK3;
bogdanm 85:024bf7f99721 473 } LPC_I2C_TypeDef;
bogdanm 85:024bf7f99721 474
bogdanm 85:024bf7f99721 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
bogdanm 85:024bf7f99721 476 typedef struct
bogdanm 85:024bf7f99721 477 {
bogdanm 85:024bf7f99721 478 __IO uint32_t I2SDAO;
bogdanm 85:024bf7f99721 479 __IO uint32_t I2SDAI;
bogdanm 85:024bf7f99721 480 __O uint32_t I2STXFIFO;
bogdanm 85:024bf7f99721 481 __I uint32_t I2SRXFIFO;
bogdanm 85:024bf7f99721 482 __I uint32_t I2SSTATE;
bogdanm 85:024bf7f99721 483 __IO uint32_t I2SDMA1;
bogdanm 85:024bf7f99721 484 __IO uint32_t I2SDMA2;
bogdanm 85:024bf7f99721 485 __IO uint32_t I2SIRQ;
bogdanm 85:024bf7f99721 486 __IO uint32_t I2STXRATE;
bogdanm 85:024bf7f99721 487 __IO uint32_t I2SRXRATE;
bogdanm 85:024bf7f99721 488 __IO uint32_t I2STXBITRATE;
bogdanm 85:024bf7f99721 489 __IO uint32_t I2SRXBITRATE;
bogdanm 85:024bf7f99721 490 __IO uint32_t I2STXMODE;
bogdanm 85:024bf7f99721 491 __IO uint32_t I2SRXMODE;
bogdanm 85:024bf7f99721 492 } LPC_I2S_TypeDef;
bogdanm 85:024bf7f99721 493
bogdanm 85:024bf7f99721 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
bogdanm 85:024bf7f99721 495 typedef struct
bogdanm 85:024bf7f99721 496 {
bogdanm 85:024bf7f99721 497 __IO uint32_t RICOMPVAL;
bogdanm 85:024bf7f99721 498 __IO uint32_t RIMASK;
bogdanm 85:024bf7f99721 499 __IO uint8_t RICTRL;
bogdanm 85:024bf7f99721 500 uint8_t RESERVED0[3];
bogdanm 85:024bf7f99721 501 __IO uint32_t RICOUNTER;
bogdanm 85:024bf7f99721 502 } LPC_RIT_TypeDef;
bogdanm 85:024bf7f99721 503
bogdanm 85:024bf7f99721 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
bogdanm 85:024bf7f99721 505 typedef struct
bogdanm 85:024bf7f99721 506 {
bogdanm 85:024bf7f99721 507 __IO uint8_t ILR;
bogdanm 85:024bf7f99721 508 uint8_t RESERVED0[7];
bogdanm 85:024bf7f99721 509 __IO uint8_t CCR;
bogdanm 85:024bf7f99721 510 uint8_t RESERVED1[3];
bogdanm 85:024bf7f99721 511 __IO uint8_t CIIR;
bogdanm 85:024bf7f99721 512 uint8_t RESERVED2[3];
bogdanm 85:024bf7f99721 513 __IO uint8_t AMR;
bogdanm 85:024bf7f99721 514 uint8_t RESERVED3[3];
bogdanm 85:024bf7f99721 515 __I uint32_t CTIME0;
bogdanm 85:024bf7f99721 516 __I uint32_t CTIME1;
bogdanm 85:024bf7f99721 517 __I uint32_t CTIME2;
bogdanm 85:024bf7f99721 518 __IO uint8_t SEC;
bogdanm 85:024bf7f99721 519 uint8_t RESERVED4[3];
bogdanm 85:024bf7f99721 520 __IO uint8_t MIN;
bogdanm 85:024bf7f99721 521 uint8_t RESERVED5[3];
bogdanm 85:024bf7f99721 522 __IO uint8_t HOUR;
bogdanm 85:024bf7f99721 523 uint8_t RESERVED6[3];
bogdanm 85:024bf7f99721 524 __IO uint8_t DOM;
bogdanm 85:024bf7f99721 525 uint8_t RESERVED7[3];
bogdanm 85:024bf7f99721 526 __IO uint8_t DOW;
bogdanm 85:024bf7f99721 527 uint8_t RESERVED8[3];
bogdanm 85:024bf7f99721 528 __IO uint16_t DOY;
bogdanm 85:024bf7f99721 529 uint16_t RESERVED9;
bogdanm 85:024bf7f99721 530 __IO uint8_t MONTH;
bogdanm 85:024bf7f99721 531 uint8_t RESERVED10[3];
bogdanm 85:024bf7f99721 532 __IO uint16_t YEAR;
bogdanm 85:024bf7f99721 533 uint16_t RESERVED11;
bogdanm 85:024bf7f99721 534 __IO uint32_t CALIBRATION;
bogdanm 85:024bf7f99721 535 __IO uint32_t GPREG0;
bogdanm 85:024bf7f99721 536 __IO uint32_t GPREG1;
bogdanm 85:024bf7f99721 537 __IO uint32_t GPREG2;
bogdanm 85:024bf7f99721 538 __IO uint32_t GPREG3;
bogdanm 85:024bf7f99721 539 __IO uint32_t GPREG4;
bogdanm 85:024bf7f99721 540 __IO uint8_t RTC_AUXEN;
bogdanm 85:024bf7f99721 541 uint8_t RESERVED12[3];
bogdanm 85:024bf7f99721 542 __IO uint8_t RTC_AUX;
bogdanm 85:024bf7f99721 543 uint8_t RESERVED13[3];
bogdanm 85:024bf7f99721 544 __IO uint8_t ALSEC;
bogdanm 85:024bf7f99721 545 uint8_t RESERVED14[3];
bogdanm 85:024bf7f99721 546 __IO uint8_t ALMIN;
bogdanm 85:024bf7f99721 547 uint8_t RESERVED15[3];
bogdanm 85:024bf7f99721 548 __IO uint8_t ALHOUR;
bogdanm 85:024bf7f99721 549 uint8_t RESERVED16[3];
bogdanm 85:024bf7f99721 550 __IO uint8_t ALDOM;
bogdanm 85:024bf7f99721 551 uint8_t RESERVED17[3];
bogdanm 85:024bf7f99721 552 __IO uint8_t ALDOW;
bogdanm 85:024bf7f99721 553 uint8_t RESERVED18[3];
bogdanm 85:024bf7f99721 554 __IO uint16_t ALDOY;
bogdanm 85:024bf7f99721 555 uint16_t RESERVED19;
bogdanm 85:024bf7f99721 556 __IO uint8_t ALMON;
bogdanm 85:024bf7f99721 557 uint8_t RESERVED20[3];
bogdanm 85:024bf7f99721 558 __IO uint16_t ALYEAR;
bogdanm 85:024bf7f99721 559 uint16_t RESERVED21;
bogdanm 85:024bf7f99721 560 } LPC_RTC_TypeDef;
bogdanm 85:024bf7f99721 561
bogdanm 85:024bf7f99721 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 85:024bf7f99721 563 typedef struct
bogdanm 85:024bf7f99721 564 {
bogdanm 85:024bf7f99721 565 __IO uint8_t WDMOD;
bogdanm 85:024bf7f99721 566 uint8_t RESERVED0[3];
bogdanm 85:024bf7f99721 567 __IO uint32_t WDTC;
bogdanm 85:024bf7f99721 568 __O uint8_t WDFEED;
bogdanm 85:024bf7f99721 569 uint8_t RESERVED1[3];
bogdanm 85:024bf7f99721 570 __I uint32_t WDTV;
bogdanm 85:024bf7f99721 571 __IO uint32_t WDCLKSEL;
bogdanm 85:024bf7f99721 572 } LPC_WDT_TypeDef;
bogdanm 85:024bf7f99721 573
bogdanm 85:024bf7f99721 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 85:024bf7f99721 575 typedef struct
bogdanm 85:024bf7f99721 576 {
bogdanm 85:024bf7f99721 577 __IO uint32_t ADCR;
bogdanm 85:024bf7f99721 578 __IO uint32_t ADGDR;
bogdanm 85:024bf7f99721 579 uint32_t RESERVED0;
bogdanm 85:024bf7f99721 580 __IO uint32_t ADINTEN;
bogdanm 85:024bf7f99721 581 __I uint32_t ADDR0;
bogdanm 85:024bf7f99721 582 __I uint32_t ADDR1;
bogdanm 85:024bf7f99721 583 __I uint32_t ADDR2;
bogdanm 85:024bf7f99721 584 __I uint32_t ADDR3;
bogdanm 85:024bf7f99721 585 __I uint32_t ADDR4;
bogdanm 85:024bf7f99721 586 __I uint32_t ADDR5;
bogdanm 85:024bf7f99721 587 __I uint32_t ADDR6;
bogdanm 85:024bf7f99721 588 __I uint32_t ADDR7;
bogdanm 85:024bf7f99721 589 __I uint32_t ADSTAT;
bogdanm 85:024bf7f99721 590 __IO uint32_t ADTRM;
bogdanm 85:024bf7f99721 591 } LPC_ADC_TypeDef;
bogdanm 85:024bf7f99721 592
bogdanm 85:024bf7f99721 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
bogdanm 85:024bf7f99721 594 typedef struct
bogdanm 85:024bf7f99721 595 {
bogdanm 85:024bf7f99721 596 __IO uint32_t DACR;
bogdanm 85:024bf7f99721 597 __IO uint32_t DACCTRL;
bogdanm 85:024bf7f99721 598 __IO uint16_t DACCNTVAL;
bogdanm 85:024bf7f99721 599 } LPC_DAC_TypeDef;
bogdanm 85:024bf7f99721 600
bogdanm 85:024bf7f99721 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
bogdanm 85:024bf7f99721 602 typedef struct
bogdanm 85:024bf7f99721 603 {
bogdanm 85:024bf7f99721 604 __I uint32_t MCCON;
bogdanm 85:024bf7f99721 605 __O uint32_t MCCON_SET;
bogdanm 85:024bf7f99721 606 __O uint32_t MCCON_CLR;
bogdanm 85:024bf7f99721 607 __I uint32_t MCCAPCON;
bogdanm 85:024bf7f99721 608 __O uint32_t MCCAPCON_SET;
bogdanm 85:024bf7f99721 609 __O uint32_t MCCAPCON_CLR;
bogdanm 85:024bf7f99721 610 __IO uint32_t MCTIM0;
bogdanm 85:024bf7f99721 611 __IO uint32_t MCTIM1;
bogdanm 85:024bf7f99721 612 __IO uint32_t MCTIM2;
bogdanm 85:024bf7f99721 613 __IO uint32_t MCPER0;
bogdanm 85:024bf7f99721 614 __IO uint32_t MCPER1;
bogdanm 85:024bf7f99721 615 __IO uint32_t MCPER2;
bogdanm 85:024bf7f99721 616 __IO uint32_t MCPW0;
bogdanm 85:024bf7f99721 617 __IO uint32_t MCPW1;
bogdanm 85:024bf7f99721 618 __IO uint32_t MCPW2;
bogdanm 85:024bf7f99721 619 __IO uint32_t MCDEADTIME;
bogdanm 85:024bf7f99721 620 __IO uint32_t MCCCP;
bogdanm 85:024bf7f99721 621 __IO uint32_t MCCR0;
bogdanm 85:024bf7f99721 622 __IO uint32_t MCCR1;
bogdanm 85:024bf7f99721 623 __IO uint32_t MCCR2;
bogdanm 85:024bf7f99721 624 __I uint32_t MCINTEN;
bogdanm 85:024bf7f99721 625 __O uint32_t MCINTEN_SET;
bogdanm 85:024bf7f99721 626 __O uint32_t MCINTEN_CLR;
bogdanm 85:024bf7f99721 627 __I uint32_t MCCNTCON;
bogdanm 85:024bf7f99721 628 __O uint32_t MCCNTCON_SET;
bogdanm 85:024bf7f99721 629 __O uint32_t MCCNTCON_CLR;
bogdanm 85:024bf7f99721 630 __I uint32_t MCINTFLAG;
bogdanm 85:024bf7f99721 631 __O uint32_t MCINTFLAG_SET;
bogdanm 85:024bf7f99721 632 __O uint32_t MCINTFLAG_CLR;
bogdanm 85:024bf7f99721 633 __O uint32_t MCCAP_CLR;
bogdanm 85:024bf7f99721 634 } LPC_MCPWM_TypeDef;
bogdanm 85:024bf7f99721 635
bogdanm 85:024bf7f99721 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
bogdanm 85:024bf7f99721 637 typedef struct
bogdanm 85:024bf7f99721 638 {
bogdanm 85:024bf7f99721 639 __O uint32_t QEICON;
bogdanm 85:024bf7f99721 640 __I uint32_t QEISTAT;
bogdanm 85:024bf7f99721 641 __IO uint32_t QEICONF;
bogdanm 85:024bf7f99721 642 __I uint32_t QEIPOS;
bogdanm 85:024bf7f99721 643 __IO uint32_t QEIMAXPOS;
bogdanm 85:024bf7f99721 644 __IO uint32_t CMPOS0;
bogdanm 85:024bf7f99721 645 __IO uint32_t CMPOS1;
bogdanm 85:024bf7f99721 646 __IO uint32_t CMPOS2;
bogdanm 85:024bf7f99721 647 __I uint32_t INXCNT;
bogdanm 85:024bf7f99721 648 __IO uint32_t INXCMP;
bogdanm 85:024bf7f99721 649 __IO uint32_t QEILOAD;
bogdanm 85:024bf7f99721 650 __I uint32_t QEITIME;
bogdanm 85:024bf7f99721 651 __I uint32_t QEIVEL;
bogdanm 85:024bf7f99721 652 __I uint32_t QEICAP;
bogdanm 85:024bf7f99721 653 __IO uint32_t VELCOMP;
bogdanm 85:024bf7f99721 654 __IO uint32_t FILTER;
bogdanm 85:024bf7f99721 655 uint32_t RESERVED0[998];
bogdanm 85:024bf7f99721 656 __O uint32_t QEIIEC;
bogdanm 85:024bf7f99721 657 __O uint32_t QEIIES;
bogdanm 85:024bf7f99721 658 __I uint32_t QEIINTSTAT;
bogdanm 85:024bf7f99721 659 __I uint32_t QEIIE;
bogdanm 85:024bf7f99721 660 __O uint32_t QEICLR;
bogdanm 85:024bf7f99721 661 __O uint32_t QEISET;
bogdanm 85:024bf7f99721 662 } LPC_QEI_TypeDef;
bogdanm 85:024bf7f99721 663
bogdanm 85:024bf7f99721 664 /*------------- Controller Area Network (CAN) --------------------------------*/
bogdanm 85:024bf7f99721 665 typedef struct
bogdanm 85:024bf7f99721 666 {
bogdanm 85:024bf7f99721 667 __IO uint32_t mask[512]; /* ID Masks */
bogdanm 85:024bf7f99721 668 } LPC_CANAF_RAM_TypeDef;
bogdanm 85:024bf7f99721 669
bogdanm 85:024bf7f99721 670 typedef struct /* Acceptance Filter Registers */
bogdanm 85:024bf7f99721 671 {
bogdanm 85:024bf7f99721 672 __IO uint32_t AFMR;
bogdanm 85:024bf7f99721 673 __IO uint32_t SFF_sa;
bogdanm 85:024bf7f99721 674 __IO uint32_t SFF_GRP_sa;
bogdanm 85:024bf7f99721 675 __IO uint32_t EFF_sa;
bogdanm 85:024bf7f99721 676 __IO uint32_t EFF_GRP_sa;
bogdanm 85:024bf7f99721 677 __IO uint32_t ENDofTable;
bogdanm 85:024bf7f99721 678 __I uint32_t LUTerrAd;
bogdanm 85:024bf7f99721 679 __I uint32_t LUTerr;
bogdanm 85:024bf7f99721 680 __IO uint32_t FCANIE;
bogdanm 85:024bf7f99721 681 __IO uint32_t FCANIC0;
bogdanm 85:024bf7f99721 682 __IO uint32_t FCANIC1;
bogdanm 85:024bf7f99721 683 } LPC_CANAF_TypeDef;
bogdanm 85:024bf7f99721 684
bogdanm 85:024bf7f99721 685 typedef struct /* Central Registers */
bogdanm 85:024bf7f99721 686 {
bogdanm 85:024bf7f99721 687 __I uint32_t CANTxSR;
bogdanm 85:024bf7f99721 688 __I uint32_t CANRxSR;
bogdanm 85:024bf7f99721 689 __I uint32_t CANMSR;
bogdanm 85:024bf7f99721 690 } LPC_CANCR_TypeDef;
bogdanm 85:024bf7f99721 691
bogdanm 85:024bf7f99721 692 typedef struct /* Controller Registers */
bogdanm 85:024bf7f99721 693 {
bogdanm 85:024bf7f99721 694 __IO uint32_t MOD;
bogdanm 85:024bf7f99721 695 __O uint32_t CMR;
bogdanm 85:024bf7f99721 696 __IO uint32_t GSR;
bogdanm 85:024bf7f99721 697 __I uint32_t ICR;
bogdanm 85:024bf7f99721 698 __IO uint32_t IER;
bogdanm 85:024bf7f99721 699 __IO uint32_t BTR;
bogdanm 85:024bf7f99721 700 __IO uint32_t EWL;
bogdanm 85:024bf7f99721 701 __I uint32_t SR;
bogdanm 85:024bf7f99721 702 __IO uint32_t RFS;
bogdanm 85:024bf7f99721 703 __IO uint32_t RID;
bogdanm 85:024bf7f99721 704 __IO uint32_t RDA;
bogdanm 85:024bf7f99721 705 __IO uint32_t RDB;
bogdanm 85:024bf7f99721 706 __IO uint32_t TFI1;
bogdanm 85:024bf7f99721 707 __IO uint32_t TID1;
bogdanm 85:024bf7f99721 708 __IO uint32_t TDA1;
bogdanm 85:024bf7f99721 709 __IO uint32_t TDB1;
bogdanm 85:024bf7f99721 710 __IO uint32_t TFI2;
bogdanm 85:024bf7f99721 711 __IO uint32_t TID2;
bogdanm 85:024bf7f99721 712 __IO uint32_t TDA2;
bogdanm 85:024bf7f99721 713 __IO uint32_t TDB2;
bogdanm 85:024bf7f99721 714 __IO uint32_t TFI3;
bogdanm 85:024bf7f99721 715 __IO uint32_t TID3;
bogdanm 85:024bf7f99721 716 __IO uint32_t TDA3;
bogdanm 85:024bf7f99721 717 __IO uint32_t TDB3;
bogdanm 85:024bf7f99721 718 } LPC_CAN_TypeDef;
bogdanm 85:024bf7f99721 719
bogdanm 85:024bf7f99721 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
bogdanm 85:024bf7f99721 721 typedef struct /* Common Registers */
bogdanm 85:024bf7f99721 722 {
bogdanm 85:024bf7f99721 723 __I uint32_t DMACIntStat;
bogdanm 85:024bf7f99721 724 __I uint32_t DMACIntTCStat;
bogdanm 85:024bf7f99721 725 __O uint32_t DMACIntTCClear;
bogdanm 85:024bf7f99721 726 __I uint32_t DMACIntErrStat;
bogdanm 85:024bf7f99721 727 __O uint32_t DMACIntErrClr;
bogdanm 85:024bf7f99721 728 __I uint32_t DMACRawIntTCStat;
bogdanm 85:024bf7f99721 729 __I uint32_t DMACRawIntErrStat;
bogdanm 85:024bf7f99721 730 __I uint32_t DMACEnbldChns;
bogdanm 85:024bf7f99721 731 __IO uint32_t DMACSoftBReq;
bogdanm 85:024bf7f99721 732 __IO uint32_t DMACSoftSReq;
bogdanm 85:024bf7f99721 733 __IO uint32_t DMACSoftLBReq;
bogdanm 85:024bf7f99721 734 __IO uint32_t DMACSoftLSReq;
bogdanm 85:024bf7f99721 735 __IO uint32_t DMACConfig;
bogdanm 85:024bf7f99721 736 __IO uint32_t DMACSync;
bogdanm 85:024bf7f99721 737 } LPC_GPDMA_TypeDef;
bogdanm 85:024bf7f99721 738
bogdanm 85:024bf7f99721 739 typedef struct /* Channel Registers */
bogdanm 85:024bf7f99721 740 {
bogdanm 85:024bf7f99721 741 __IO uint32_t DMACCSrcAddr;
bogdanm 85:024bf7f99721 742 __IO uint32_t DMACCDestAddr;
bogdanm 85:024bf7f99721 743 __IO uint32_t DMACCLLI;
bogdanm 85:024bf7f99721 744 __IO uint32_t DMACCControl;
bogdanm 85:024bf7f99721 745 __IO uint32_t DMACCConfig;
bogdanm 85:024bf7f99721 746 } LPC_GPDMACH_TypeDef;
bogdanm 85:024bf7f99721 747
bogdanm 85:024bf7f99721 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
bogdanm 85:024bf7f99721 749 typedef struct
bogdanm 85:024bf7f99721 750 {
bogdanm 85:024bf7f99721 751 __I uint32_t HcRevision; /* USB Host Registers */
bogdanm 85:024bf7f99721 752 __IO uint32_t HcControl;
bogdanm 85:024bf7f99721 753 __IO uint32_t HcCommandStatus;
bogdanm 85:024bf7f99721 754 __IO uint32_t HcInterruptStatus;
bogdanm 85:024bf7f99721 755 __IO uint32_t HcInterruptEnable;
bogdanm 85:024bf7f99721 756 __IO uint32_t HcInterruptDisable;
bogdanm 85:024bf7f99721 757 __IO uint32_t HcHCCA;
bogdanm 85:024bf7f99721 758 __I uint32_t HcPeriodCurrentED;
bogdanm 85:024bf7f99721 759 __IO uint32_t HcControlHeadED;
bogdanm 85:024bf7f99721 760 __IO uint32_t HcControlCurrentED;
bogdanm 85:024bf7f99721 761 __IO uint32_t HcBulkHeadED;
bogdanm 85:024bf7f99721 762 __IO uint32_t HcBulkCurrentED;
bogdanm 85:024bf7f99721 763 __I uint32_t HcDoneHead;
bogdanm 85:024bf7f99721 764 __IO uint32_t HcFmInterval;
bogdanm 85:024bf7f99721 765 __I uint32_t HcFmRemaining;
bogdanm 85:024bf7f99721 766 __I uint32_t HcFmNumber;
bogdanm 85:024bf7f99721 767 __IO uint32_t HcPeriodicStart;
bogdanm 85:024bf7f99721 768 __IO uint32_t HcLSTreshold;
bogdanm 85:024bf7f99721 769 __IO uint32_t HcRhDescriptorA;
bogdanm 85:024bf7f99721 770 __IO uint32_t HcRhDescriptorB;
bogdanm 85:024bf7f99721 771 __IO uint32_t HcRhStatus;
bogdanm 85:024bf7f99721 772 __IO uint32_t HcRhPortStatus1;
bogdanm 85:024bf7f99721 773 __IO uint32_t HcRhPortStatus2;
bogdanm 85:024bf7f99721 774 uint32_t RESERVED0[40];
bogdanm 85:024bf7f99721 775 __I uint32_t Module_ID;
bogdanm 85:024bf7f99721 776
bogdanm 85:024bf7f99721 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
bogdanm 85:024bf7f99721 778 __IO uint32_t OTGIntEn;
bogdanm 85:024bf7f99721 779 __O uint32_t OTGIntSet;
bogdanm 85:024bf7f99721 780 __O uint32_t OTGIntClr;
bogdanm 85:024bf7f99721 781 __IO uint32_t OTGStCtrl;
bogdanm 85:024bf7f99721 782 __IO uint32_t OTGTmr;
bogdanm 85:024bf7f99721 783 uint32_t RESERVED1[58];
bogdanm 85:024bf7f99721 784
bogdanm 85:024bf7f99721 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
bogdanm 85:024bf7f99721 786 __IO uint32_t USBDevIntEn;
bogdanm 85:024bf7f99721 787 __O uint32_t USBDevIntClr;
bogdanm 85:024bf7f99721 788 __O uint32_t USBDevIntSet;
bogdanm 85:024bf7f99721 789
bogdanm 85:024bf7f99721 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
bogdanm 85:024bf7f99721 791 __I uint32_t USBCmdData;
bogdanm 85:024bf7f99721 792
bogdanm 85:024bf7f99721 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
bogdanm 85:024bf7f99721 794 __O uint32_t USBTxData;
bogdanm 85:024bf7f99721 795 __I uint32_t USBRxPLen;
bogdanm 85:024bf7f99721 796 __O uint32_t USBTxPLen;
bogdanm 85:024bf7f99721 797 __IO uint32_t USBCtrl;
bogdanm 85:024bf7f99721 798 __O uint32_t USBDevIntPri;
bogdanm 85:024bf7f99721 799
bogdanm 85:024bf7f99721 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
bogdanm 85:024bf7f99721 801 __IO uint32_t USBEpIntEn;
bogdanm 85:024bf7f99721 802 __O uint32_t USBEpIntClr;
bogdanm 85:024bf7f99721 803 __O uint32_t USBEpIntSet;
bogdanm 85:024bf7f99721 804 __O uint32_t USBEpIntPri;
bogdanm 85:024bf7f99721 805
bogdanm 85:024bf7f99721 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
bogdanm 85:024bf7f99721 807 __O uint32_t USBEpInd;
bogdanm 85:024bf7f99721 808 __IO uint32_t USBMaxPSize;
bogdanm 85:024bf7f99721 809
bogdanm 85:024bf7f99721 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
bogdanm 85:024bf7f99721 811 __O uint32_t USBDMARClr;
bogdanm 85:024bf7f99721 812 __O uint32_t USBDMARSet;
bogdanm 85:024bf7f99721 813 uint32_t RESERVED2[9];
bogdanm 85:024bf7f99721 814 __IO uint32_t USBUDCAH;
bogdanm 85:024bf7f99721 815 __I uint32_t USBEpDMASt;
bogdanm 85:024bf7f99721 816 __O uint32_t USBEpDMAEn;
bogdanm 85:024bf7f99721 817 __O uint32_t USBEpDMADis;
bogdanm 85:024bf7f99721 818 __I uint32_t USBDMAIntSt;
bogdanm 85:024bf7f99721 819 __IO uint32_t USBDMAIntEn;
bogdanm 85:024bf7f99721 820 uint32_t RESERVED3[2];
bogdanm 85:024bf7f99721 821 __I uint32_t USBEoTIntSt;
bogdanm 85:024bf7f99721 822 __O uint32_t USBEoTIntClr;
bogdanm 85:024bf7f99721 823 __O uint32_t USBEoTIntSet;
bogdanm 85:024bf7f99721 824 __I uint32_t USBNDDRIntSt;
bogdanm 85:024bf7f99721 825 __O uint32_t USBNDDRIntClr;
bogdanm 85:024bf7f99721 826 __O uint32_t USBNDDRIntSet;
bogdanm 85:024bf7f99721 827 __I uint32_t USBSysErrIntSt;
bogdanm 85:024bf7f99721 828 __O uint32_t USBSysErrIntClr;
bogdanm 85:024bf7f99721 829 __O uint32_t USBSysErrIntSet;
bogdanm 85:024bf7f99721 830 uint32_t RESERVED4[15];
bogdanm 85:024bf7f99721 831
bogdanm 85:024bf7f99721 832 union {
bogdanm 85:024bf7f99721 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
bogdanm 85:024bf7f99721 834 __O uint32_t I2C_TX;
bogdanm 85:024bf7f99721 835 };
bogdanm 85:024bf7f99721 836 __I uint32_t I2C_STS;
bogdanm 85:024bf7f99721 837 __IO uint32_t I2C_CTL;
bogdanm 85:024bf7f99721 838 __IO uint32_t I2C_CLKHI;
bogdanm 85:024bf7f99721 839 __O uint32_t I2C_CLKLO;
bogdanm 85:024bf7f99721 840 uint32_t RESERVED5[824];
bogdanm 85:024bf7f99721 841
bogdanm 85:024bf7f99721 842 union {
bogdanm 85:024bf7f99721 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
bogdanm 85:024bf7f99721 844 __IO uint32_t OTGClkCtrl;
bogdanm 85:024bf7f99721 845 };
bogdanm 85:024bf7f99721 846 union {
bogdanm 85:024bf7f99721 847 __I uint32_t USBClkSt;
bogdanm 85:024bf7f99721 848 __I uint32_t OTGClkSt;
bogdanm 85:024bf7f99721 849 };
bogdanm 85:024bf7f99721 850 } LPC_USB_TypeDef;
bogdanm 85:024bf7f99721 851
bogdanm 85:024bf7f99721 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
bogdanm 85:024bf7f99721 853 typedef struct
bogdanm 85:024bf7f99721 854 {
bogdanm 85:024bf7f99721 855 __IO uint32_t MAC1; /* MAC Registers */
bogdanm 85:024bf7f99721 856 __IO uint32_t MAC2;
bogdanm 85:024bf7f99721 857 __IO uint32_t IPGT;
bogdanm 85:024bf7f99721 858 __IO uint32_t IPGR;
bogdanm 85:024bf7f99721 859 __IO uint32_t CLRT;
bogdanm 85:024bf7f99721 860 __IO uint32_t MAXF;
bogdanm 85:024bf7f99721 861 __IO uint32_t SUPP;
bogdanm 85:024bf7f99721 862 __IO uint32_t TEST;
bogdanm 85:024bf7f99721 863 __IO uint32_t MCFG;
bogdanm 85:024bf7f99721 864 __IO uint32_t MCMD;
bogdanm 85:024bf7f99721 865 __IO uint32_t MADR;
bogdanm 85:024bf7f99721 866 __O uint32_t MWTD;
bogdanm 85:024bf7f99721 867 __I uint32_t MRDD;
bogdanm 85:024bf7f99721 868 __I uint32_t MIND;
bogdanm 85:024bf7f99721 869 uint32_t RESERVED0[2];
bogdanm 85:024bf7f99721 870 __IO uint32_t SA0;
bogdanm 85:024bf7f99721 871 __IO uint32_t SA1;
bogdanm 85:024bf7f99721 872 __IO uint32_t SA2;
bogdanm 85:024bf7f99721 873 uint32_t RESERVED1[45];
bogdanm 85:024bf7f99721 874 __IO uint32_t Command; /* Control Registers */
bogdanm 85:024bf7f99721 875 __I uint32_t Status;
bogdanm 85:024bf7f99721 876 __IO uint32_t RxDescriptor;
bogdanm 85:024bf7f99721 877 __IO uint32_t RxStatus;
bogdanm 85:024bf7f99721 878 __IO uint32_t RxDescriptorNumber;
bogdanm 85:024bf7f99721 879 __I uint32_t RxProduceIndex;
bogdanm 85:024bf7f99721 880 __IO uint32_t RxConsumeIndex;
bogdanm 85:024bf7f99721 881 __IO uint32_t TxDescriptor;
bogdanm 85:024bf7f99721 882 __IO uint32_t TxStatus;
bogdanm 85:024bf7f99721 883 __IO uint32_t TxDescriptorNumber;
bogdanm 85:024bf7f99721 884 __IO uint32_t TxProduceIndex;
bogdanm 85:024bf7f99721 885 __I uint32_t TxConsumeIndex;
bogdanm 85:024bf7f99721 886 uint32_t RESERVED2[10];
bogdanm 85:024bf7f99721 887 __I uint32_t TSV0;
bogdanm 85:024bf7f99721 888 __I uint32_t TSV1;
bogdanm 85:024bf7f99721 889 __I uint32_t RSV;
bogdanm 85:024bf7f99721 890 uint32_t RESERVED3[3];
bogdanm 85:024bf7f99721 891 __IO uint32_t FlowControlCounter;
bogdanm 85:024bf7f99721 892 __I uint32_t FlowControlStatus;
bogdanm 85:024bf7f99721 893 uint32_t RESERVED4[34];
bogdanm 85:024bf7f99721 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
bogdanm 85:024bf7f99721 895 __IO uint32_t RxFilterWoLStatus;
bogdanm 85:024bf7f99721 896 __IO uint32_t RxFilterWoLClear;
bogdanm 85:024bf7f99721 897 uint32_t RESERVED5;
bogdanm 85:024bf7f99721 898 __IO uint32_t HashFilterL;
bogdanm 85:024bf7f99721 899 __IO uint32_t HashFilterH;
bogdanm 85:024bf7f99721 900 uint32_t RESERVED6[882];
bogdanm 85:024bf7f99721 901 __I uint32_t IntStatus; /* Module Control Registers */
bogdanm 85:024bf7f99721 902 __IO uint32_t IntEnable;
bogdanm 85:024bf7f99721 903 __O uint32_t IntClear;
bogdanm 85:024bf7f99721 904 __O uint32_t IntSet;
bogdanm 85:024bf7f99721 905 uint32_t RESERVED7;
bogdanm 85:024bf7f99721 906 __IO uint32_t PowerDown;
bogdanm 85:024bf7f99721 907 uint32_t RESERVED8;
bogdanm 85:024bf7f99721 908 __IO uint32_t Module_ID;
bogdanm 85:024bf7f99721 909 } LPC_EMAC_TypeDef;
bogdanm 85:024bf7f99721 910
bogdanm 85:024bf7f99721 911 #if defined ( __CC_ARM )
bogdanm 85:024bf7f99721 912 #pragma no_anon_unions
bogdanm 85:024bf7f99721 913 #endif
bogdanm 85:024bf7f99721 914
bogdanm 85:024bf7f99721 915
bogdanm 85:024bf7f99721 916 /******************************************************************************/
bogdanm 85:024bf7f99721 917 /* Peripheral memory map */
bogdanm 85:024bf7f99721 918 /******************************************************************************/
bogdanm 85:024bf7f99721 919 /* Base addresses */
bogdanm 85:024bf7f99721 920 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 85:024bf7f99721 921 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 85:024bf7f99721 922 #define LPC_GPIO_BASE (0x2009C000UL)
bogdanm 85:024bf7f99721 923 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 85:024bf7f99721 924 #define LPC_APB1_BASE (0x40080000UL)
bogdanm 85:024bf7f99721 925 #define LPC_AHB_BASE (0x50000000UL)
bogdanm 85:024bf7f99721 926 #define LPC_CM3_BASE (0xE0000000UL)
bogdanm 85:024bf7f99721 927
bogdanm 85:024bf7f99721 928 /* APB0 peripherals */
bogdanm 85:024bf7f99721 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 85:024bf7f99721 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 85:024bf7f99721 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 85:024bf7f99721 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 85:024bf7f99721 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
bogdanm 85:024bf7f99721 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
bogdanm 85:024bf7f99721 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
bogdanm 85:024bf7f99721 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
bogdanm 85:024bf7f99721 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
bogdanm 85:024bf7f99721 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
bogdanm 85:024bf7f99721 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
bogdanm 85:024bf7f99721 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
bogdanm 85:024bf7f99721 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
bogdanm 85:024bf7f99721 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
bogdanm 85:024bf7f99721 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
bogdanm 85:024bf7f99721 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 85:024bf7f99721 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 85:024bf7f99721 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 85:024bf7f99721 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
bogdanm 85:024bf7f99721 948
bogdanm 85:024bf7f99721 949 /* APB1 peripherals */
bogdanm 85:024bf7f99721 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
bogdanm 85:024bf7f99721 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
bogdanm 85:024bf7f99721 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
bogdanm 85:024bf7f99721 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
bogdanm 85:024bf7f99721 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
bogdanm 85:024bf7f99721 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
bogdanm 85:024bf7f99721 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
bogdanm 85:024bf7f99721 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
bogdanm 85:024bf7f99721 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
bogdanm 85:024bf7f99721 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
bogdanm 85:024bf7f99721 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
bogdanm 85:024bf7f99721 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
bogdanm 85:024bf7f99721 962
bogdanm 85:024bf7f99721 963 /* AHB peripherals */
bogdanm 85:024bf7f99721 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 85:024bf7f99721 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
bogdanm 85:024bf7f99721 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
bogdanm 85:024bf7f99721 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
bogdanm 85:024bf7f99721 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
bogdanm 85:024bf7f99721 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
bogdanm 85:024bf7f99721 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
bogdanm 85:024bf7f99721 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
bogdanm 85:024bf7f99721 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
bogdanm 85:024bf7f99721 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
bogdanm 85:024bf7f99721 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
bogdanm 85:024bf7f99721 975
bogdanm 85:024bf7f99721 976 /* GPIOs */
bogdanm 85:024bf7f99721 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
bogdanm 85:024bf7f99721 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
bogdanm 85:024bf7f99721 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
bogdanm 85:024bf7f99721 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
bogdanm 85:024bf7f99721 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
bogdanm 85:024bf7f99721 982
bogdanm 85:024bf7f99721 983
bogdanm 85:024bf7f99721 984 /******************************************************************************/
bogdanm 85:024bf7f99721 985 /* Peripheral declaration */
bogdanm 85:024bf7f99721 986 /******************************************************************************/
bogdanm 85:024bf7f99721 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
bogdanm 85:024bf7f99721 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
bogdanm 85:024bf7f99721 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
bogdanm 85:024bf7f99721 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
bogdanm 85:024bf7f99721 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
bogdanm 85:024bf7f99721 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
bogdanm 85:024bf7f99721 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
bogdanm 85:024bf7f99721 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
bogdanm 85:024bf7f99721 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
bogdanm 85:024bf7f99721 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
bogdanm 85:024bf7f99721 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
bogdanm 85:024bf7f99721 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
bogdanm 85:024bf7f99721 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
bogdanm 85:024bf7f99721 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
bogdanm 85:024bf7f99721 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
bogdanm 85:024bf7f99721 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
bogdanm 85:024bf7f99721 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
bogdanm 85:024bf7f99721 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
bogdanm 85:024bf7f99721 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
bogdanm 85:024bf7f99721 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
bogdanm 85:024bf7f99721 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
bogdanm 85:024bf7f99721 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
bogdanm 85:024bf7f99721 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
bogdanm 85:024bf7f99721 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
bogdanm 85:024bf7f99721 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
bogdanm 85:024bf7f99721 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
bogdanm 85:024bf7f99721 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
bogdanm 85:024bf7f99721 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
bogdanm 85:024bf7f99721 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
bogdanm 85:024bf7f99721 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
bogdanm 85:024bf7f99721 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
bogdanm 85:024bf7f99721 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
bogdanm 85:024bf7f99721 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
bogdanm 85:024bf7f99721 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
bogdanm 85:024bf7f99721 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
bogdanm 85:024bf7f99721 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
bogdanm 85:024bf7f99721 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
bogdanm 85:024bf7f99721 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
bogdanm 85:024bf7f99721 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
bogdanm 85:024bf7f99721 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
bogdanm 85:024bf7f99721 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
bogdanm 85:024bf7f99721 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
bogdanm 85:024bf7f99721 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
bogdanm 85:024bf7f99721 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
bogdanm 85:024bf7f99721 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
bogdanm 85:024bf7f99721 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
bogdanm 85:024bf7f99721 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
bogdanm 85:024bf7f99721 1034
bogdanm 85:024bf7f99721 1035 #endif // __LPC17xx_H__