Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

TARGET_RZ_A1H/pwm_iodefine.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer*
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : pwm_iodefine.h
bogdanm 92:4fc01daae5a5 25 * $Rev: $
bogdanm 92:4fc01daae5a5 26 * $Date:: $
bogdanm 92:4fc01daae5a5 27 * Description : Definition of I/O Register (V1.00a)
bogdanm 92:4fc01daae5a5 28 ******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef PWM_IODEFINE_H
bogdanm 92:4fc01daae5a5 30 #define PWM_IODEFINE_H
bogdanm 92:4fc01daae5a5 31 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
bogdanm 92:4fc01daae5a5 32 /* ->SEC M1.10.1 : Not magic number */
bogdanm 92:4fc01daae5a5 33
bogdanm 92:4fc01daae5a5 34 union reg16_8_t
bogdanm 92:4fc01daae5a5 35 {
bogdanm 92:4fc01daae5a5 36 volatile uint16_t UINT16; /* 16-bit Access */
bogdanm 92:4fc01daae5a5 37 volatile uint8_t UINT8[2]; /* 8-bit Access */
bogdanm 92:4fc01daae5a5 38 };
bogdanm 92:4fc01daae5a5 39
bogdanm 92:4fc01daae5a5 40 struct st_pwm
bogdanm 92:4fc01daae5a5 41 { /* PWM */
bogdanm 92:4fc01daae5a5 42 volatile uint8_t dummy559[2]; /* */
bogdanm 92:4fc01daae5a5 43 union reg16_8_t PWBTCR; /* PWBTCR */
bogdanm 92:4fc01daae5a5 44
bogdanm 92:4fc01daae5a5 45 volatile uint8_t dummy560[216]; /* */
bogdanm 92:4fc01daae5a5 46
bogdanm 92:4fc01daae5a5 47 /* start of struct st_pwm_common */
bogdanm 92:4fc01daae5a5 48 union reg16_8_t PWCR_1; /* PWCR_1 */
bogdanm 92:4fc01daae5a5 49
bogdanm 92:4fc01daae5a5 50 volatile uint8_t dummy561[2]; /* */
bogdanm 92:4fc01daae5a5 51 union reg16_8_t PWPR_1; /* PWPR_1 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 volatile uint16_t PWCYR_1; /* PWCYR_1 */
bogdanm 92:4fc01daae5a5 54 volatile uint16_t PWBFR_1A; /* PWBFR_1A */
bogdanm 92:4fc01daae5a5 55 volatile uint16_t PWBFR_1C; /* PWBFR_1C */
bogdanm 92:4fc01daae5a5 56 volatile uint16_t PWBFR_1E; /* PWBFR_1E */
bogdanm 92:4fc01daae5a5 57 volatile uint16_t PWBFR_1G; /* PWBFR_1G */
bogdanm 92:4fc01daae5a5 58 /* end of struct st_pwm_common */
bogdanm 92:4fc01daae5a5 59
bogdanm 92:4fc01daae5a5 60 /* start of struct st_pwm_common */
bogdanm 92:4fc01daae5a5 61 union reg16_8_t PWCR_2; /* PWCR_2 */
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63 volatile uint8_t dummy562[2]; /* */
bogdanm 92:4fc01daae5a5 64 union reg16_8_t PWPR_2; /* PWPR_2 */
bogdanm 92:4fc01daae5a5 65
bogdanm 92:4fc01daae5a5 66 volatile uint16_t PWCYR_2; /* PWCYR_2 */
bogdanm 92:4fc01daae5a5 67 volatile uint16_t PWBFR_2A; /* PWBFR_2A */
bogdanm 92:4fc01daae5a5 68 volatile uint16_t PWBFR_2C; /* PWBFR_2C */
bogdanm 92:4fc01daae5a5 69 volatile uint16_t PWBFR_2E; /* PWBFR_2E */
bogdanm 92:4fc01daae5a5 70 volatile uint16_t PWBFR_2G; /* PWBFR_2G */
bogdanm 92:4fc01daae5a5 71 /* end of struct st_pwm_common */
bogdanm 92:4fc01daae5a5 72 };
bogdanm 92:4fc01daae5a5 73
bogdanm 92:4fc01daae5a5 74
bogdanm 92:4fc01daae5a5 75 struct st_pwm_common
bogdanm 92:4fc01daae5a5 76 {
bogdanm 92:4fc01daae5a5 77 union reg16_8_t PWCR_1; /* PWCR_1 */
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 volatile uint8_t dummy572[2]; /* */
bogdanm 92:4fc01daae5a5 80 union reg16_8_t PWPR_1; /* PWPR_1 */
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 volatile uint16_t PWCYR_1; /* PWCYR_1 */
bogdanm 92:4fc01daae5a5 83 volatile uint16_t PWBFR_1A; /* PWBFR_1A */
bogdanm 92:4fc01daae5a5 84 volatile uint16_t PWBFR_1C; /* PWBFR_1C */
bogdanm 92:4fc01daae5a5 85 volatile uint16_t PWBFR_1E; /* PWBFR_1E */
bogdanm 92:4fc01daae5a5 86 volatile uint16_t PWBFR_1G; /* PWBFR_1G */
bogdanm 92:4fc01daae5a5 87 };
bogdanm 92:4fc01daae5a5 88
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 #define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93 /* Start of channnel array defines of PWM */
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95 /* Channnel array defines of PWMn */
bogdanm 92:4fc01daae5a5 96 /*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
bogdanm 92:4fc01daae5a5 97 #define PWMn_COUNT 2
bogdanm 92:4fc01daae5a5 98 #define PWMn_ADDRESS_LIST \
bogdanm 92:4fc01daae5a5 99 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
bogdanm 92:4fc01daae5a5 100 &PWM1, &PWM2 \
bogdanm 92:4fc01daae5a5 101 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
bogdanm 92:4fc01daae5a5 102 #define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
bogdanm 92:4fc01daae5a5 103 #define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 /* End of channnel array defines of PWM */
bogdanm 92:4fc01daae5a5 106
bogdanm 92:4fc01daae5a5 107
bogdanm 92:4fc01daae5a5 108 #define PWMPWBTCR PWM.PWBTCR.UINT16
bogdanm 92:4fc01daae5a5 109 #define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
bogdanm 92:4fc01daae5a5 110 #define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
bogdanm 92:4fc01daae5a5 111 #define PWMPWCR_1 PWM.PWCR_1.UINT16
bogdanm 92:4fc01daae5a5 112 #define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
bogdanm 92:4fc01daae5a5 113 #define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
bogdanm 92:4fc01daae5a5 114 #define PWMPWPR_1 PWM.PWPR_1.UINT16
bogdanm 92:4fc01daae5a5 115 #define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
bogdanm 92:4fc01daae5a5 116 #define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
bogdanm 92:4fc01daae5a5 117 #define PWMPWCYR_1 PWM.PWCYR_1
bogdanm 92:4fc01daae5a5 118 #define PWMPWBFR_1A PWM.PWBFR_1A
bogdanm 92:4fc01daae5a5 119 #define PWMPWBFR_1C PWM.PWBFR_1C
bogdanm 92:4fc01daae5a5 120 #define PWMPWBFR_1E PWM.PWBFR_1E
bogdanm 92:4fc01daae5a5 121 #define PWMPWBFR_1G PWM.PWBFR_1G
bogdanm 92:4fc01daae5a5 122 #define PWMPWCR_2 PWM.PWCR_2.UINT16
bogdanm 92:4fc01daae5a5 123 #define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
bogdanm 92:4fc01daae5a5 124 #define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
bogdanm 92:4fc01daae5a5 125 #define PWMPWPR_2 PWM.PWPR_2.UINT16
bogdanm 92:4fc01daae5a5 126 #define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
bogdanm 92:4fc01daae5a5 127 #define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
bogdanm 92:4fc01daae5a5 128 #define PWMPWCYR_2 PWM.PWCYR_2
bogdanm 92:4fc01daae5a5 129 #define PWMPWBFR_2A PWM.PWBFR_2A
bogdanm 92:4fc01daae5a5 130 #define PWMPWBFR_2C PWM.PWBFR_2C
bogdanm 92:4fc01daae5a5 131 #define PWMPWBFR_2E PWM.PWBFR_2E
bogdanm 92:4fc01daae5a5 132 #define PWMPWBFR_2G PWM.PWBFR_2G
bogdanm 92:4fc01daae5a5 133 /* <-SEC M1.10.1 */
bogdanm 92:4fc01daae5a5 134 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
bogdanm 92:4fc01daae5a5 135 #endif