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TARGET_LPC1768/LPC17xx.h@64:e3affc9e7238, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 12:28:09 2013 +0300
Revision:
64:e3affc9e7238
Parent:
LPC1768/LPC17xx.h@54:71b101360fb9
Child:
65:5798e58a58b1
New build system structure, new target (LPC1347), bug fixes (I2C read/write errors, LPC11U24 memory map and others)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 40:976df7c37ad5 1 /**************************************************************************//**
emilmont 40:976df7c37ad5 2 * @file LPC17xx.h
emilmont 40:976df7c37ad5 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
emilmont 40:976df7c37ad5 4 * NXP LPC17xx Device Series
emilmont 40:976df7c37ad5 5 * @version: V1.09
emilmont 40:976df7c37ad5 6 * @date: 17. March 2010
emilmont 40:976df7c37ad5 7
emilmont 40:976df7c37ad5 8 *
emilmont 40:976df7c37ad5 9 * @note
emilmont 40:976df7c37ad5 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 11 *
emilmont 40:976df7c37ad5 12 * @par
emilmont 40:976df7c37ad5 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 40:976df7c37ad5 14 * processor based microcontrollers. This file can be freely distributed
emilmont 40:976df7c37ad5 15 * within development tools that are supporting such ARM based processors.
emilmont 40:976df7c37ad5 16 *
emilmont 40:976df7c37ad5 17 * @par
emilmont 40:976df7c37ad5 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 40:976df7c37ad5 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 40:976df7c37ad5 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 40:976df7c37ad5 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 40:976df7c37ad5 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 40:976df7c37ad5 23 *
emilmont 40:976df7c37ad5 24 ******************************************************************************/
emilmont 40:976df7c37ad5 25
emilmont 40:976df7c37ad5 26
emilmont 40:976df7c37ad5 27 #ifndef __LPC17xx_H__
emilmont 40:976df7c37ad5 28 #define __LPC17xx_H__
emilmont 40:976df7c37ad5 29
emilmont 40:976df7c37ad5 30 /*
emilmont 40:976df7c37ad5 31 * ==========================================================================
emilmont 40:976df7c37ad5 32 * ---------- Interrupt Number Definition -----------------------------------
emilmont 40:976df7c37ad5 33 * ==========================================================================
emilmont 40:976df7c37ad5 34 */
emilmont 40:976df7c37ad5 35
emilmont 40:976df7c37ad5 36 typedef enum IRQn
emilmont 40:976df7c37ad5 37 {
emilmont 40:976df7c37ad5 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
emilmont 40:976df7c37ad5 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
emilmont 40:976df7c37ad5 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
emilmont 40:976df7c37ad5 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
emilmont 40:976df7c37ad5 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
emilmont 40:976df7c37ad5 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
emilmont 40:976df7c37ad5 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
emilmont 40:976df7c37ad5 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
emilmont 40:976df7c37ad5 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
emilmont 40:976df7c37ad5 47
emilmont 40:976df7c37ad5 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
emilmont 40:976df7c37ad5 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
emilmont 40:976df7c37ad5 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
emilmont 40:976df7c37ad5 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
emilmont 40:976df7c37ad5 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
emilmont 40:976df7c37ad5 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
emilmont 40:976df7c37ad5 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
emilmont 40:976df7c37ad5 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
emilmont 40:976df7c37ad5 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
emilmont 40:976df7c37ad5 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
emilmont 40:976df7c37ad5 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
emilmont 40:976df7c37ad5 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
emilmont 40:976df7c37ad5 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
emilmont 40:976df7c37ad5 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
emilmont 40:976df7c37ad5 62 SPI_IRQn = 13, /*!< SPI Interrupt */
emilmont 40:976df7c37ad5 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
emilmont 40:976df7c37ad5 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
emilmont 40:976df7c37ad5 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
emilmont 40:976df7c37ad5 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
emilmont 40:976df7c37ad5 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
emilmont 40:976df7c37ad5 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
emilmont 40:976df7c37ad5 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
emilmont 40:976df7c37ad5 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
emilmont 40:976df7c37ad5 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
emilmont 40:976df7c37ad5 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
emilmont 40:976df7c37ad5 73 USB_IRQn = 24, /*!< USB Interrupt */
emilmont 40:976df7c37ad5 74 CAN_IRQn = 25, /*!< CAN Interrupt */
emilmont 40:976df7c37ad5 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
emilmont 40:976df7c37ad5 76 I2S_IRQn = 27, /*!< I2S Interrupt */
emilmont 40:976df7c37ad5 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
emilmont 40:976df7c37ad5 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
emilmont 40:976df7c37ad5 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
emilmont 40:976df7c37ad5 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
emilmont 40:976df7c37ad5 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
emilmont 40:976df7c37ad5 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
emilmont 40:976df7c37ad5 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
emilmont 40:976df7c37ad5 84 } IRQn_Type;
emilmont 40:976df7c37ad5 85
emilmont 40:976df7c37ad5 86
emilmont 40:976df7c37ad5 87 /*
emilmont 40:976df7c37ad5 88 * ==========================================================================
emilmont 40:976df7c37ad5 89 * ----------- Processor and Core Peripheral Section ------------------------
emilmont 40:976df7c37ad5 90 * ==========================================================================
emilmont 40:976df7c37ad5 91 */
emilmont 40:976df7c37ad5 92
emilmont 40:976df7c37ad5 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
emilmont 40:976df7c37ad5 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
emilmont 40:976df7c37ad5 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
emilmont 40:976df7c37ad5 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 40:976df7c37ad5 97
emilmont 40:976df7c37ad5 98
emilmont 40:976df7c37ad5 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
emilmont 40:976df7c37ad5 100 #include "system_LPC17xx.h" /* System Header */
emilmont 40:976df7c37ad5 101
emilmont 40:976df7c37ad5 102
emilmont 40:976df7c37ad5 103 /******************************************************************************/
emilmont 40:976df7c37ad5 104 /* Device Specific Peripheral registers structures */
emilmont 40:976df7c37ad5 105 /******************************************************************************/
emilmont 40:976df7c37ad5 106
emilmont 40:976df7c37ad5 107 #if defined ( __CC_ARM )
emilmont 40:976df7c37ad5 108 #pragma anon_unions
emilmont 40:976df7c37ad5 109 #endif
emilmont 40:976df7c37ad5 110
emilmont 40:976df7c37ad5 111 /*------------- System Control (SC) ------------------------------------------*/
emilmont 40:976df7c37ad5 112 typedef struct
emilmont 40:976df7c37ad5 113 {
emilmont 40:976df7c37ad5 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
emilmont 40:976df7c37ad5 115 uint32_t RESERVED0[31];
emilmont 40:976df7c37ad5 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
emilmont 40:976df7c37ad5 117 __IO uint32_t PLL0CFG;
emilmont 40:976df7c37ad5 118 __I uint32_t PLL0STAT;
emilmont 40:976df7c37ad5 119 __O uint32_t PLL0FEED;
emilmont 40:976df7c37ad5 120 uint32_t RESERVED1[4];
emilmont 40:976df7c37ad5 121 __IO uint32_t PLL1CON;
emilmont 40:976df7c37ad5 122 __IO uint32_t PLL1CFG;
emilmont 40:976df7c37ad5 123 __I uint32_t PLL1STAT;
emilmont 40:976df7c37ad5 124 __O uint32_t PLL1FEED;
emilmont 40:976df7c37ad5 125 uint32_t RESERVED2[4];
emilmont 40:976df7c37ad5 126 __IO uint32_t PCON;
emilmont 40:976df7c37ad5 127 __IO uint32_t PCONP;
emilmont 40:976df7c37ad5 128 uint32_t RESERVED3[15];
emilmont 40:976df7c37ad5 129 __IO uint32_t CCLKCFG;
emilmont 40:976df7c37ad5 130 __IO uint32_t USBCLKCFG;
emilmont 40:976df7c37ad5 131 __IO uint32_t CLKSRCSEL;
emilmont 54:71b101360fb9 132 __IO uint32_t CANSLEEPCLR;
emilmont 54:71b101360fb9 133 __IO uint32_t CANWAKEFLAGS;
emilmont 40:976df7c37ad5 134 uint32_t RESERVED4[10];
emilmont 40:976df7c37ad5 135 __IO uint32_t EXTINT; /* External Interrupts */
emilmont 40:976df7c37ad5 136 uint32_t RESERVED5;
emilmont 40:976df7c37ad5 137 __IO uint32_t EXTMODE;
emilmont 40:976df7c37ad5 138 __IO uint32_t EXTPOLAR;
emilmont 40:976df7c37ad5 139 uint32_t RESERVED6[12];
emilmont 40:976df7c37ad5 140 __IO uint32_t RSID; /* Reset */
emilmont 40:976df7c37ad5 141 uint32_t RESERVED7[7];
emilmont 40:976df7c37ad5 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
emilmont 40:976df7c37ad5 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
emilmont 40:976df7c37ad5 144 __IO uint32_t PCLKSEL0;
emilmont 40:976df7c37ad5 145 __IO uint32_t PCLKSEL1;
emilmont 40:976df7c37ad5 146 uint32_t RESERVED8[4];
emilmont 40:976df7c37ad5 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
emilmont 40:976df7c37ad5 148 __IO uint32_t DMAREQSEL;
emilmont 40:976df7c37ad5 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
emilmont 40:976df7c37ad5 150 } LPC_SC_TypeDef;
emilmont 40:976df7c37ad5 151
emilmont 40:976df7c37ad5 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
emilmont 40:976df7c37ad5 153 typedef struct
emilmont 40:976df7c37ad5 154 {
emilmont 40:976df7c37ad5 155 __IO uint32_t PINSEL0;
emilmont 40:976df7c37ad5 156 __IO uint32_t PINSEL1;
emilmont 40:976df7c37ad5 157 __IO uint32_t PINSEL2;
emilmont 40:976df7c37ad5 158 __IO uint32_t PINSEL3;
emilmont 40:976df7c37ad5 159 __IO uint32_t PINSEL4;
emilmont 40:976df7c37ad5 160 __IO uint32_t PINSEL5;
emilmont 40:976df7c37ad5 161 __IO uint32_t PINSEL6;
emilmont 40:976df7c37ad5 162 __IO uint32_t PINSEL7;
emilmont 40:976df7c37ad5 163 __IO uint32_t PINSEL8;
emilmont 40:976df7c37ad5 164 __IO uint32_t PINSEL9;
emilmont 40:976df7c37ad5 165 __IO uint32_t PINSEL10;
emilmont 40:976df7c37ad5 166 uint32_t RESERVED0[5];
emilmont 40:976df7c37ad5 167 __IO uint32_t PINMODE0;
emilmont 40:976df7c37ad5 168 __IO uint32_t PINMODE1;
emilmont 40:976df7c37ad5 169 __IO uint32_t PINMODE2;
emilmont 40:976df7c37ad5 170 __IO uint32_t PINMODE3;
emilmont 40:976df7c37ad5 171 __IO uint32_t PINMODE4;
emilmont 40:976df7c37ad5 172 __IO uint32_t PINMODE5;
emilmont 40:976df7c37ad5 173 __IO uint32_t PINMODE6;
emilmont 40:976df7c37ad5 174 __IO uint32_t PINMODE7;
emilmont 40:976df7c37ad5 175 __IO uint32_t PINMODE8;
emilmont 40:976df7c37ad5 176 __IO uint32_t PINMODE9;
emilmont 40:976df7c37ad5 177 __IO uint32_t PINMODE_OD0;
emilmont 40:976df7c37ad5 178 __IO uint32_t PINMODE_OD1;
emilmont 40:976df7c37ad5 179 __IO uint32_t PINMODE_OD2;
emilmont 40:976df7c37ad5 180 __IO uint32_t PINMODE_OD3;
emilmont 40:976df7c37ad5 181 __IO uint32_t PINMODE_OD4;
emilmont 40:976df7c37ad5 182 __IO uint32_t I2CPADCFG;
emilmont 40:976df7c37ad5 183 } LPC_PINCON_TypeDef;
emilmont 40:976df7c37ad5 184
emilmont 40:976df7c37ad5 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
emilmont 40:976df7c37ad5 186 typedef struct
emilmont 40:976df7c37ad5 187 {
emilmont 40:976df7c37ad5 188 union {
emilmont 40:976df7c37ad5 189 __IO uint32_t FIODIR;
emilmont 40:976df7c37ad5 190 struct {
emilmont 40:976df7c37ad5 191 __IO uint16_t FIODIRL;
emilmont 40:976df7c37ad5 192 __IO uint16_t FIODIRH;
emilmont 40:976df7c37ad5 193 };
emilmont 40:976df7c37ad5 194 struct {
emilmont 40:976df7c37ad5 195 __IO uint8_t FIODIR0;
emilmont 40:976df7c37ad5 196 __IO uint8_t FIODIR1;
emilmont 40:976df7c37ad5 197 __IO uint8_t FIODIR2;
emilmont 40:976df7c37ad5 198 __IO uint8_t FIODIR3;
emilmont 40:976df7c37ad5 199 };
emilmont 40:976df7c37ad5 200 };
emilmont 40:976df7c37ad5 201 uint32_t RESERVED0[3];
emilmont 40:976df7c37ad5 202 union {
emilmont 40:976df7c37ad5 203 __IO uint32_t FIOMASK;
emilmont 40:976df7c37ad5 204 struct {
emilmont 40:976df7c37ad5 205 __IO uint16_t FIOMASKL;
emilmont 40:976df7c37ad5 206 __IO uint16_t FIOMASKH;
emilmont 40:976df7c37ad5 207 };
emilmont 40:976df7c37ad5 208 struct {
emilmont 40:976df7c37ad5 209 __IO uint8_t FIOMASK0;
emilmont 40:976df7c37ad5 210 __IO uint8_t FIOMASK1;
emilmont 40:976df7c37ad5 211 __IO uint8_t FIOMASK2;
emilmont 40:976df7c37ad5 212 __IO uint8_t FIOMASK3;
emilmont 40:976df7c37ad5 213 };
emilmont 40:976df7c37ad5 214 };
emilmont 40:976df7c37ad5 215 union {
emilmont 40:976df7c37ad5 216 __IO uint32_t FIOPIN;
emilmont 40:976df7c37ad5 217 struct {
emilmont 40:976df7c37ad5 218 __IO uint16_t FIOPINL;
emilmont 40:976df7c37ad5 219 __IO uint16_t FIOPINH;
emilmont 40:976df7c37ad5 220 };
emilmont 40:976df7c37ad5 221 struct {
emilmont 40:976df7c37ad5 222 __IO uint8_t FIOPIN0;
emilmont 40:976df7c37ad5 223 __IO uint8_t FIOPIN1;
emilmont 40:976df7c37ad5 224 __IO uint8_t FIOPIN2;
emilmont 40:976df7c37ad5 225 __IO uint8_t FIOPIN3;
emilmont 40:976df7c37ad5 226 };
emilmont 40:976df7c37ad5 227 };
emilmont 40:976df7c37ad5 228 union {
emilmont 40:976df7c37ad5 229 __IO uint32_t FIOSET;
emilmont 40:976df7c37ad5 230 struct {
emilmont 40:976df7c37ad5 231 __IO uint16_t FIOSETL;
emilmont 40:976df7c37ad5 232 __IO uint16_t FIOSETH;
emilmont 40:976df7c37ad5 233 };
emilmont 40:976df7c37ad5 234 struct {
emilmont 40:976df7c37ad5 235 __IO uint8_t FIOSET0;
emilmont 40:976df7c37ad5 236 __IO uint8_t FIOSET1;
emilmont 40:976df7c37ad5 237 __IO uint8_t FIOSET2;
emilmont 40:976df7c37ad5 238 __IO uint8_t FIOSET3;
emilmont 40:976df7c37ad5 239 };
emilmont 40:976df7c37ad5 240 };
emilmont 40:976df7c37ad5 241 union {
emilmont 40:976df7c37ad5 242 __O uint32_t FIOCLR;
emilmont 40:976df7c37ad5 243 struct {
emilmont 40:976df7c37ad5 244 __O uint16_t FIOCLRL;
emilmont 40:976df7c37ad5 245 __O uint16_t FIOCLRH;
emilmont 40:976df7c37ad5 246 };
emilmont 40:976df7c37ad5 247 struct {
emilmont 40:976df7c37ad5 248 __O uint8_t FIOCLR0;
emilmont 40:976df7c37ad5 249 __O uint8_t FIOCLR1;
emilmont 40:976df7c37ad5 250 __O uint8_t FIOCLR2;
emilmont 40:976df7c37ad5 251 __O uint8_t FIOCLR3;
emilmont 40:976df7c37ad5 252 };
emilmont 40:976df7c37ad5 253 };
emilmont 40:976df7c37ad5 254 } LPC_GPIO_TypeDef;
emilmont 40:976df7c37ad5 255
emilmont 40:976df7c37ad5 256 typedef struct
emilmont 40:976df7c37ad5 257 {
emilmont 40:976df7c37ad5 258 __I uint32_t IntStatus;
emilmont 40:976df7c37ad5 259 __I uint32_t IO0IntStatR;
emilmont 40:976df7c37ad5 260 __I uint32_t IO0IntStatF;
emilmont 40:976df7c37ad5 261 __O uint32_t IO0IntClr;
emilmont 40:976df7c37ad5 262 __IO uint32_t IO0IntEnR;
emilmont 40:976df7c37ad5 263 __IO uint32_t IO0IntEnF;
emilmont 40:976df7c37ad5 264 uint32_t RESERVED0[3];
emilmont 40:976df7c37ad5 265 __I uint32_t IO2IntStatR;
emilmont 40:976df7c37ad5 266 __I uint32_t IO2IntStatF;
emilmont 40:976df7c37ad5 267 __O uint32_t IO2IntClr;
emilmont 40:976df7c37ad5 268 __IO uint32_t IO2IntEnR;
emilmont 40:976df7c37ad5 269 __IO uint32_t IO2IntEnF;
emilmont 40:976df7c37ad5 270 } LPC_GPIOINT_TypeDef;
emilmont 40:976df7c37ad5 271
emilmont 40:976df7c37ad5 272 /*------------- Timer (TIM) --------------------------------------------------*/
emilmont 40:976df7c37ad5 273 typedef struct
emilmont 40:976df7c37ad5 274 {
emilmont 40:976df7c37ad5 275 __IO uint32_t IR;
emilmont 40:976df7c37ad5 276 __IO uint32_t TCR;
emilmont 40:976df7c37ad5 277 __IO uint32_t TC;
emilmont 40:976df7c37ad5 278 __IO uint32_t PR;
emilmont 40:976df7c37ad5 279 __IO uint32_t PC;
emilmont 40:976df7c37ad5 280 __IO uint32_t MCR;
emilmont 40:976df7c37ad5 281 __IO uint32_t MR0;
emilmont 40:976df7c37ad5 282 __IO uint32_t MR1;
emilmont 40:976df7c37ad5 283 __IO uint32_t MR2;
emilmont 40:976df7c37ad5 284 __IO uint32_t MR3;
emilmont 40:976df7c37ad5 285 __IO uint32_t CCR;
emilmont 40:976df7c37ad5 286 __I uint32_t CR0;
emilmont 40:976df7c37ad5 287 __I uint32_t CR1;
emilmont 40:976df7c37ad5 288 uint32_t RESERVED0[2];
emilmont 40:976df7c37ad5 289 __IO uint32_t EMR;
emilmont 40:976df7c37ad5 290 uint32_t RESERVED1[12];
emilmont 40:976df7c37ad5 291 __IO uint32_t CTCR;
emilmont 40:976df7c37ad5 292 } LPC_TIM_TypeDef;
emilmont 40:976df7c37ad5 293
emilmont 40:976df7c37ad5 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
emilmont 40:976df7c37ad5 295 typedef struct
emilmont 40:976df7c37ad5 296 {
emilmont 40:976df7c37ad5 297 __IO uint32_t IR;
emilmont 40:976df7c37ad5 298 __IO uint32_t TCR;
emilmont 40:976df7c37ad5 299 __IO uint32_t TC;
emilmont 40:976df7c37ad5 300 __IO uint32_t PR;
emilmont 40:976df7c37ad5 301 __IO uint32_t PC;
emilmont 40:976df7c37ad5 302 __IO uint32_t MCR;
emilmont 40:976df7c37ad5 303 __IO uint32_t MR0;
emilmont 40:976df7c37ad5 304 __IO uint32_t MR1;
emilmont 40:976df7c37ad5 305 __IO uint32_t MR2;
emilmont 40:976df7c37ad5 306 __IO uint32_t MR3;
emilmont 40:976df7c37ad5 307 __IO uint32_t CCR;
emilmont 40:976df7c37ad5 308 __I uint32_t CR0;
emilmont 40:976df7c37ad5 309 __I uint32_t CR1;
emilmont 40:976df7c37ad5 310 __I uint32_t CR2;
emilmont 40:976df7c37ad5 311 __I uint32_t CR3;
emilmont 40:976df7c37ad5 312 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 313 __IO uint32_t MR4;
emilmont 40:976df7c37ad5 314 __IO uint32_t MR5;
emilmont 40:976df7c37ad5 315 __IO uint32_t MR6;
emilmont 40:976df7c37ad5 316 __IO uint32_t PCR;
emilmont 40:976df7c37ad5 317 __IO uint32_t LER;
emilmont 40:976df7c37ad5 318 uint32_t RESERVED1[7];
emilmont 40:976df7c37ad5 319 __IO uint32_t CTCR;
emilmont 40:976df7c37ad5 320 } LPC_PWM_TypeDef;
emilmont 40:976df7c37ad5 321
emilmont 40:976df7c37ad5 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
emilmont 40:976df7c37ad5 323 typedef struct
emilmont 40:976df7c37ad5 324 {
emilmont 40:976df7c37ad5 325 union {
emilmont 40:976df7c37ad5 326 __I uint8_t RBR;
emilmont 40:976df7c37ad5 327 __O uint8_t THR;
emilmont 40:976df7c37ad5 328 __IO uint8_t DLL;
emilmont 40:976df7c37ad5 329 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 330 };
emilmont 40:976df7c37ad5 331 union {
emilmont 40:976df7c37ad5 332 __IO uint8_t DLM;
emilmont 40:976df7c37ad5 333 __IO uint32_t IER;
emilmont 40:976df7c37ad5 334 };
emilmont 40:976df7c37ad5 335 union {
emilmont 40:976df7c37ad5 336 __I uint32_t IIR;
emilmont 40:976df7c37ad5 337 __O uint8_t FCR;
emilmont 40:976df7c37ad5 338 };
emilmont 40:976df7c37ad5 339 __IO uint8_t LCR;
emilmont 40:976df7c37ad5 340 uint8_t RESERVED1[7];
emilmont 40:976df7c37ad5 341 __I uint8_t LSR;
emilmont 40:976df7c37ad5 342 uint8_t RESERVED2[7];
emilmont 40:976df7c37ad5 343 __IO uint8_t SCR;
emilmont 40:976df7c37ad5 344 uint8_t RESERVED3[3];
emilmont 40:976df7c37ad5 345 __IO uint32_t ACR;
emilmont 40:976df7c37ad5 346 __IO uint8_t ICR;
emilmont 40:976df7c37ad5 347 uint8_t RESERVED4[3];
emilmont 40:976df7c37ad5 348 __IO uint8_t FDR;
emilmont 40:976df7c37ad5 349 uint8_t RESERVED5[7];
emilmont 40:976df7c37ad5 350 __IO uint8_t TER;
emilmont 40:976df7c37ad5 351 uint8_t RESERVED6[39];
emilmont 40:976df7c37ad5 352 __IO uint32_t FIFOLVL;
emilmont 40:976df7c37ad5 353 } LPC_UART_TypeDef;
emilmont 40:976df7c37ad5 354
emilmont 40:976df7c37ad5 355 typedef struct
emilmont 40:976df7c37ad5 356 {
emilmont 40:976df7c37ad5 357 union {
emilmont 40:976df7c37ad5 358 __I uint8_t RBR;
emilmont 40:976df7c37ad5 359 __O uint8_t THR;
emilmont 40:976df7c37ad5 360 __IO uint8_t DLL;
emilmont 40:976df7c37ad5 361 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 362 };
emilmont 40:976df7c37ad5 363 union {
emilmont 40:976df7c37ad5 364 __IO uint8_t DLM;
emilmont 40:976df7c37ad5 365 __IO uint32_t IER;
emilmont 40:976df7c37ad5 366 };
emilmont 40:976df7c37ad5 367 union {
emilmont 40:976df7c37ad5 368 __I uint32_t IIR;
emilmont 40:976df7c37ad5 369 __O uint8_t FCR;
emilmont 40:976df7c37ad5 370 };
emilmont 40:976df7c37ad5 371 __IO uint8_t LCR;
emilmont 40:976df7c37ad5 372 uint8_t RESERVED1[7];
emilmont 40:976df7c37ad5 373 __I uint8_t LSR;
emilmont 40:976df7c37ad5 374 uint8_t RESERVED2[7];
emilmont 40:976df7c37ad5 375 __IO uint8_t SCR;
emilmont 40:976df7c37ad5 376 uint8_t RESERVED3[3];
emilmont 40:976df7c37ad5 377 __IO uint32_t ACR;
emilmont 40:976df7c37ad5 378 __IO uint8_t ICR;
emilmont 40:976df7c37ad5 379 uint8_t RESERVED4[3];
emilmont 40:976df7c37ad5 380 __IO uint8_t FDR;
emilmont 40:976df7c37ad5 381 uint8_t RESERVED5[7];
emilmont 40:976df7c37ad5 382 __IO uint8_t TER;
emilmont 40:976df7c37ad5 383 uint8_t RESERVED6[39];
emilmont 40:976df7c37ad5 384 __IO uint32_t FIFOLVL;
emilmont 40:976df7c37ad5 385 } LPC_UART0_TypeDef;
emilmont 40:976df7c37ad5 386
emilmont 40:976df7c37ad5 387 typedef struct
emilmont 40:976df7c37ad5 388 {
emilmont 40:976df7c37ad5 389 union {
emilmont 40:976df7c37ad5 390 __I uint8_t RBR;
emilmont 40:976df7c37ad5 391 __O uint8_t THR;
emilmont 40:976df7c37ad5 392 __IO uint8_t DLL;
emilmont 40:976df7c37ad5 393 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 394 };
emilmont 40:976df7c37ad5 395 union {
emilmont 40:976df7c37ad5 396 __IO uint8_t DLM;
emilmont 40:976df7c37ad5 397 __IO uint32_t IER;
emilmont 40:976df7c37ad5 398 };
emilmont 40:976df7c37ad5 399 union {
emilmont 40:976df7c37ad5 400 __I uint32_t IIR;
emilmont 40:976df7c37ad5 401 __O uint8_t FCR;
emilmont 40:976df7c37ad5 402 };
emilmont 40:976df7c37ad5 403 __IO uint8_t LCR;
emilmont 40:976df7c37ad5 404 uint8_t RESERVED1[3];
emilmont 40:976df7c37ad5 405 __IO uint8_t MCR;
emilmont 40:976df7c37ad5 406 uint8_t RESERVED2[3];
emilmont 40:976df7c37ad5 407 __I uint8_t LSR;
emilmont 40:976df7c37ad5 408 uint8_t RESERVED3[3];
emilmont 40:976df7c37ad5 409 __I uint8_t MSR;
emilmont 40:976df7c37ad5 410 uint8_t RESERVED4[3];
emilmont 40:976df7c37ad5 411 __IO uint8_t SCR;
emilmont 40:976df7c37ad5 412 uint8_t RESERVED5[3];
emilmont 40:976df7c37ad5 413 __IO uint32_t ACR;
emilmont 40:976df7c37ad5 414 uint32_t RESERVED6;
emilmont 40:976df7c37ad5 415 __IO uint32_t FDR;
emilmont 40:976df7c37ad5 416 uint32_t RESERVED7;
emilmont 40:976df7c37ad5 417 __IO uint8_t TER;
emilmont 40:976df7c37ad5 418 uint8_t RESERVED8[27];
emilmont 40:976df7c37ad5 419 __IO uint8_t RS485CTRL;
emilmont 40:976df7c37ad5 420 uint8_t RESERVED9[3];
emilmont 40:976df7c37ad5 421 __IO uint8_t ADRMATCH;
emilmont 40:976df7c37ad5 422 uint8_t RESERVED10[3];
emilmont 40:976df7c37ad5 423 __IO uint8_t RS485DLY;
emilmont 40:976df7c37ad5 424 uint8_t RESERVED11[3];
emilmont 40:976df7c37ad5 425 __IO uint32_t FIFOLVL;
emilmont 40:976df7c37ad5 426 } LPC_UART1_TypeDef;
emilmont 40:976df7c37ad5 427
emilmont 40:976df7c37ad5 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
emilmont 40:976df7c37ad5 429 typedef struct
emilmont 40:976df7c37ad5 430 {
emilmont 40:976df7c37ad5 431 __IO uint32_t SPCR;
emilmont 40:976df7c37ad5 432 __I uint32_t SPSR;
emilmont 40:976df7c37ad5 433 __IO uint32_t SPDR;
emilmont 40:976df7c37ad5 434 __IO uint32_t SPCCR;
emilmont 40:976df7c37ad5 435 uint32_t RESERVED0[3];
emilmont 40:976df7c37ad5 436 __IO uint32_t SPINT;
emilmont 40:976df7c37ad5 437 } LPC_SPI_TypeDef;
emilmont 40:976df7c37ad5 438
emilmont 40:976df7c37ad5 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
emilmont 40:976df7c37ad5 440 typedef struct
emilmont 40:976df7c37ad5 441 {
emilmont 40:976df7c37ad5 442 __IO uint32_t CR0;
emilmont 40:976df7c37ad5 443 __IO uint32_t CR1;
emilmont 40:976df7c37ad5 444 __IO uint32_t DR;
emilmont 40:976df7c37ad5 445 __I uint32_t SR;
emilmont 40:976df7c37ad5 446 __IO uint32_t CPSR;
emilmont 40:976df7c37ad5 447 __IO uint32_t IMSC;
emilmont 40:976df7c37ad5 448 __IO uint32_t RIS;
emilmont 40:976df7c37ad5 449 __IO uint32_t MIS;
emilmont 40:976df7c37ad5 450 __IO uint32_t ICR;
emilmont 40:976df7c37ad5 451 __IO uint32_t DMACR;
emilmont 40:976df7c37ad5 452 } LPC_SSP_TypeDef;
emilmont 40:976df7c37ad5 453
emilmont 40:976df7c37ad5 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
emilmont 40:976df7c37ad5 455 typedef struct
emilmont 40:976df7c37ad5 456 {
emilmont 40:976df7c37ad5 457 __IO uint32_t I2CONSET;
emilmont 40:976df7c37ad5 458 __I uint32_t I2STAT;
emilmont 40:976df7c37ad5 459 __IO uint32_t I2DAT;
emilmont 40:976df7c37ad5 460 __IO uint32_t I2ADR0;
emilmont 40:976df7c37ad5 461 __IO uint32_t I2SCLH;
emilmont 40:976df7c37ad5 462 __IO uint32_t I2SCLL;
emilmont 40:976df7c37ad5 463 __O uint32_t I2CONCLR;
emilmont 40:976df7c37ad5 464 __IO uint32_t MMCTRL;
emilmont 40:976df7c37ad5 465 __IO uint32_t I2ADR1;
emilmont 40:976df7c37ad5 466 __IO uint32_t I2ADR2;
emilmont 40:976df7c37ad5 467 __IO uint32_t I2ADR3;
emilmont 40:976df7c37ad5 468 __I uint32_t I2DATA_BUFFER;
emilmont 40:976df7c37ad5 469 __IO uint32_t I2MASK0;
emilmont 40:976df7c37ad5 470 __IO uint32_t I2MASK1;
emilmont 40:976df7c37ad5 471 __IO uint32_t I2MASK2;
emilmont 40:976df7c37ad5 472 __IO uint32_t I2MASK3;
emilmont 40:976df7c37ad5 473 } LPC_I2C_TypeDef;
emilmont 40:976df7c37ad5 474
emilmont 40:976df7c37ad5 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
emilmont 40:976df7c37ad5 476 typedef struct
emilmont 40:976df7c37ad5 477 {
emilmont 40:976df7c37ad5 478 __IO uint32_t I2SDAO;
emilmont 40:976df7c37ad5 479 __IO uint32_t I2SDAI;
emilmont 40:976df7c37ad5 480 __O uint32_t I2STXFIFO;
emilmont 40:976df7c37ad5 481 __I uint32_t I2SRXFIFO;
emilmont 40:976df7c37ad5 482 __I uint32_t I2SSTATE;
emilmont 40:976df7c37ad5 483 __IO uint32_t I2SDMA1;
emilmont 40:976df7c37ad5 484 __IO uint32_t I2SDMA2;
emilmont 40:976df7c37ad5 485 __IO uint32_t I2SIRQ;
emilmont 40:976df7c37ad5 486 __IO uint32_t I2STXRATE;
emilmont 40:976df7c37ad5 487 __IO uint32_t I2SRXRATE;
emilmont 40:976df7c37ad5 488 __IO uint32_t I2STXBITRATE;
emilmont 40:976df7c37ad5 489 __IO uint32_t I2SRXBITRATE;
emilmont 40:976df7c37ad5 490 __IO uint32_t I2STXMODE;
emilmont 40:976df7c37ad5 491 __IO uint32_t I2SRXMODE;
emilmont 40:976df7c37ad5 492 } LPC_I2S_TypeDef;
emilmont 40:976df7c37ad5 493
emilmont 40:976df7c37ad5 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
emilmont 40:976df7c37ad5 495 typedef struct
emilmont 40:976df7c37ad5 496 {
emilmont 40:976df7c37ad5 497 __IO uint32_t RICOMPVAL;
emilmont 40:976df7c37ad5 498 __IO uint32_t RIMASK;
emilmont 40:976df7c37ad5 499 __IO uint8_t RICTRL;
emilmont 40:976df7c37ad5 500 uint8_t RESERVED0[3];
emilmont 40:976df7c37ad5 501 __IO uint32_t RICOUNTER;
emilmont 40:976df7c37ad5 502 } LPC_RIT_TypeDef;
emilmont 40:976df7c37ad5 503
emilmont 40:976df7c37ad5 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
emilmont 40:976df7c37ad5 505 typedef struct
emilmont 40:976df7c37ad5 506 {
emilmont 40:976df7c37ad5 507 __IO uint8_t ILR;
emilmont 40:976df7c37ad5 508 uint8_t RESERVED0[7];
emilmont 40:976df7c37ad5 509 __IO uint8_t CCR;
emilmont 40:976df7c37ad5 510 uint8_t RESERVED1[3];
emilmont 40:976df7c37ad5 511 __IO uint8_t CIIR;
emilmont 40:976df7c37ad5 512 uint8_t RESERVED2[3];
emilmont 40:976df7c37ad5 513 __IO uint8_t AMR;
emilmont 40:976df7c37ad5 514 uint8_t RESERVED3[3];
emilmont 40:976df7c37ad5 515 __I uint32_t CTIME0;
emilmont 40:976df7c37ad5 516 __I uint32_t CTIME1;
emilmont 40:976df7c37ad5 517 __I uint32_t CTIME2;
emilmont 40:976df7c37ad5 518 __IO uint8_t SEC;
emilmont 40:976df7c37ad5 519 uint8_t RESERVED4[3];
emilmont 40:976df7c37ad5 520 __IO uint8_t MIN;
emilmont 40:976df7c37ad5 521 uint8_t RESERVED5[3];
emilmont 40:976df7c37ad5 522 __IO uint8_t HOUR;
emilmont 40:976df7c37ad5 523 uint8_t RESERVED6[3];
emilmont 40:976df7c37ad5 524 __IO uint8_t DOM;
emilmont 40:976df7c37ad5 525 uint8_t RESERVED7[3];
emilmont 40:976df7c37ad5 526 __IO uint8_t DOW;
emilmont 40:976df7c37ad5 527 uint8_t RESERVED8[3];
emilmont 40:976df7c37ad5 528 __IO uint16_t DOY;
emilmont 40:976df7c37ad5 529 uint16_t RESERVED9;
emilmont 40:976df7c37ad5 530 __IO uint8_t MONTH;
emilmont 40:976df7c37ad5 531 uint8_t RESERVED10[3];
emilmont 40:976df7c37ad5 532 __IO uint16_t YEAR;
emilmont 40:976df7c37ad5 533 uint16_t RESERVED11;
emilmont 40:976df7c37ad5 534 __IO uint32_t CALIBRATION;
emilmont 40:976df7c37ad5 535 __IO uint32_t GPREG0;
emilmont 40:976df7c37ad5 536 __IO uint32_t GPREG1;
emilmont 40:976df7c37ad5 537 __IO uint32_t GPREG2;
emilmont 40:976df7c37ad5 538 __IO uint32_t GPREG3;
emilmont 40:976df7c37ad5 539 __IO uint32_t GPREG4;
emilmont 40:976df7c37ad5 540 __IO uint8_t RTC_AUXEN;
emilmont 40:976df7c37ad5 541 uint8_t RESERVED12[3];
emilmont 40:976df7c37ad5 542 __IO uint8_t RTC_AUX;
emilmont 40:976df7c37ad5 543 uint8_t RESERVED13[3];
emilmont 40:976df7c37ad5 544 __IO uint8_t ALSEC;
emilmont 40:976df7c37ad5 545 uint8_t RESERVED14[3];
emilmont 40:976df7c37ad5 546 __IO uint8_t ALMIN;
emilmont 40:976df7c37ad5 547 uint8_t RESERVED15[3];
emilmont 40:976df7c37ad5 548 __IO uint8_t ALHOUR;
emilmont 40:976df7c37ad5 549 uint8_t RESERVED16[3];
emilmont 40:976df7c37ad5 550 __IO uint8_t ALDOM;
emilmont 40:976df7c37ad5 551 uint8_t RESERVED17[3];
emilmont 40:976df7c37ad5 552 __IO uint8_t ALDOW;
emilmont 40:976df7c37ad5 553 uint8_t RESERVED18[3];
emilmont 40:976df7c37ad5 554 __IO uint16_t ALDOY;
emilmont 40:976df7c37ad5 555 uint16_t RESERVED19;
emilmont 40:976df7c37ad5 556 __IO uint8_t ALMON;
emilmont 40:976df7c37ad5 557 uint8_t RESERVED20[3];
emilmont 40:976df7c37ad5 558 __IO uint16_t ALYEAR;
emilmont 40:976df7c37ad5 559 uint16_t RESERVED21;
emilmont 40:976df7c37ad5 560 } LPC_RTC_TypeDef;
emilmont 40:976df7c37ad5 561
emilmont 40:976df7c37ad5 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
emilmont 40:976df7c37ad5 563 typedef struct
emilmont 40:976df7c37ad5 564 {
emilmont 40:976df7c37ad5 565 __IO uint8_t WDMOD;
emilmont 40:976df7c37ad5 566 uint8_t RESERVED0[3];
emilmont 40:976df7c37ad5 567 __IO uint32_t WDTC;
emilmont 40:976df7c37ad5 568 __O uint8_t WDFEED;
emilmont 40:976df7c37ad5 569 uint8_t RESERVED1[3];
emilmont 40:976df7c37ad5 570 __I uint32_t WDTV;
emilmont 40:976df7c37ad5 571 __IO uint32_t WDCLKSEL;
emilmont 40:976df7c37ad5 572 } LPC_WDT_TypeDef;
emilmont 40:976df7c37ad5 573
emilmont 40:976df7c37ad5 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
emilmont 40:976df7c37ad5 575 typedef struct
emilmont 40:976df7c37ad5 576 {
emilmont 40:976df7c37ad5 577 __IO uint32_t ADCR;
emilmont 40:976df7c37ad5 578 __IO uint32_t ADGDR;
emilmont 40:976df7c37ad5 579 uint32_t RESERVED0;
emilmont 40:976df7c37ad5 580 __IO uint32_t ADINTEN;
emilmont 40:976df7c37ad5 581 __I uint32_t ADDR0;
emilmont 40:976df7c37ad5 582 __I uint32_t ADDR1;
emilmont 40:976df7c37ad5 583 __I uint32_t ADDR2;
emilmont 40:976df7c37ad5 584 __I uint32_t ADDR3;
emilmont 40:976df7c37ad5 585 __I uint32_t ADDR4;
emilmont 40:976df7c37ad5 586 __I uint32_t ADDR5;
emilmont 40:976df7c37ad5 587 __I uint32_t ADDR6;
emilmont 40:976df7c37ad5 588 __I uint32_t ADDR7;
emilmont 40:976df7c37ad5 589 __I uint32_t ADSTAT;
emilmont 40:976df7c37ad5 590 __IO uint32_t ADTRM;
emilmont 40:976df7c37ad5 591 } LPC_ADC_TypeDef;
emilmont 40:976df7c37ad5 592
emilmont 40:976df7c37ad5 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
emilmont 40:976df7c37ad5 594 typedef struct
emilmont 40:976df7c37ad5 595 {
emilmont 40:976df7c37ad5 596 __IO uint32_t DACR;
emilmont 40:976df7c37ad5 597 __IO uint32_t DACCTRL;
emilmont 40:976df7c37ad5 598 __IO uint16_t DACCNTVAL;
emilmont 40:976df7c37ad5 599 } LPC_DAC_TypeDef;
emilmont 40:976df7c37ad5 600
emilmont 40:976df7c37ad5 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
emilmont 40:976df7c37ad5 602 typedef struct
emilmont 40:976df7c37ad5 603 {
emilmont 40:976df7c37ad5 604 __I uint32_t MCCON;
emilmont 40:976df7c37ad5 605 __O uint32_t MCCON_SET;
emilmont 40:976df7c37ad5 606 __O uint32_t MCCON_CLR;
emilmont 40:976df7c37ad5 607 __I uint32_t MCCAPCON;
emilmont 40:976df7c37ad5 608 __O uint32_t MCCAPCON_SET;
emilmont 40:976df7c37ad5 609 __O uint32_t MCCAPCON_CLR;
emilmont 40:976df7c37ad5 610 __IO uint32_t MCTIM0;
emilmont 40:976df7c37ad5 611 __IO uint32_t MCTIM1;
emilmont 40:976df7c37ad5 612 __IO uint32_t MCTIM2;
emilmont 40:976df7c37ad5 613 __IO uint32_t MCPER0;
emilmont 40:976df7c37ad5 614 __IO uint32_t MCPER1;
emilmont 40:976df7c37ad5 615 __IO uint32_t MCPER2;
emilmont 40:976df7c37ad5 616 __IO uint32_t MCPW0;
emilmont 40:976df7c37ad5 617 __IO uint32_t MCPW1;
emilmont 40:976df7c37ad5 618 __IO uint32_t MCPW2;
emilmont 40:976df7c37ad5 619 __IO uint32_t MCDEADTIME;
emilmont 40:976df7c37ad5 620 __IO uint32_t MCCCP;
emilmont 40:976df7c37ad5 621 __IO uint32_t MCCR0;
emilmont 40:976df7c37ad5 622 __IO uint32_t MCCR1;
emilmont 40:976df7c37ad5 623 __IO uint32_t MCCR2;
emilmont 40:976df7c37ad5 624 __I uint32_t MCINTEN;
emilmont 40:976df7c37ad5 625 __O uint32_t MCINTEN_SET;
emilmont 40:976df7c37ad5 626 __O uint32_t MCINTEN_CLR;
emilmont 40:976df7c37ad5 627 __I uint32_t MCCNTCON;
emilmont 40:976df7c37ad5 628 __O uint32_t MCCNTCON_SET;
emilmont 40:976df7c37ad5 629 __O uint32_t MCCNTCON_CLR;
emilmont 40:976df7c37ad5 630 __I uint32_t MCINTFLAG;
emilmont 40:976df7c37ad5 631 __O uint32_t MCINTFLAG_SET;
emilmont 40:976df7c37ad5 632 __O uint32_t MCINTFLAG_CLR;
emilmont 40:976df7c37ad5 633 __O uint32_t MCCAP_CLR;
emilmont 40:976df7c37ad5 634 } LPC_MCPWM_TypeDef;
emilmont 40:976df7c37ad5 635
emilmont 40:976df7c37ad5 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
emilmont 40:976df7c37ad5 637 typedef struct
emilmont 40:976df7c37ad5 638 {
emilmont 40:976df7c37ad5 639 __O uint32_t QEICON;
emilmont 40:976df7c37ad5 640 __I uint32_t QEISTAT;
emilmont 40:976df7c37ad5 641 __IO uint32_t QEICONF;
emilmont 40:976df7c37ad5 642 __I uint32_t QEIPOS;
emilmont 40:976df7c37ad5 643 __IO uint32_t QEIMAXPOS;
emilmont 40:976df7c37ad5 644 __IO uint32_t CMPOS0;
emilmont 40:976df7c37ad5 645 __IO uint32_t CMPOS1;
emilmont 40:976df7c37ad5 646 __IO uint32_t CMPOS2;
emilmont 40:976df7c37ad5 647 __I uint32_t INXCNT;
emilmont 40:976df7c37ad5 648 __IO uint32_t INXCMP;
emilmont 40:976df7c37ad5 649 __IO uint32_t QEILOAD;
emilmont 40:976df7c37ad5 650 __I uint32_t QEITIME;
emilmont 40:976df7c37ad5 651 __I uint32_t QEIVEL;
emilmont 40:976df7c37ad5 652 __I uint32_t QEICAP;
emilmont 40:976df7c37ad5 653 __IO uint32_t VELCOMP;
emilmont 40:976df7c37ad5 654 __IO uint32_t FILTER;
emilmont 40:976df7c37ad5 655 uint32_t RESERVED0[998];
emilmont 40:976df7c37ad5 656 __O uint32_t QEIIEC;
emilmont 40:976df7c37ad5 657 __O uint32_t QEIIES;
emilmont 40:976df7c37ad5 658 __I uint32_t QEIINTSTAT;
emilmont 40:976df7c37ad5 659 __I uint32_t QEIIE;
emilmont 40:976df7c37ad5 660 __O uint32_t QEICLR;
emilmont 40:976df7c37ad5 661 __O uint32_t QEISET;
emilmont 40:976df7c37ad5 662 } LPC_QEI_TypeDef;
emilmont 40:976df7c37ad5 663
emilmont 40:976df7c37ad5 664 /*------------- Controller Area Network (CAN) --------------------------------*/
emilmont 40:976df7c37ad5 665 typedef struct
emilmont 40:976df7c37ad5 666 {
emilmont 40:976df7c37ad5 667 __IO uint32_t mask[512]; /* ID Masks */
emilmont 40:976df7c37ad5 668 } LPC_CANAF_RAM_TypeDef;
emilmont 40:976df7c37ad5 669
emilmont 40:976df7c37ad5 670 typedef struct /* Acceptance Filter Registers */
emilmont 40:976df7c37ad5 671 {
emilmont 40:976df7c37ad5 672 __IO uint32_t AFMR;
emilmont 40:976df7c37ad5 673 __IO uint32_t SFF_sa;
emilmont 40:976df7c37ad5 674 __IO uint32_t SFF_GRP_sa;
emilmont 40:976df7c37ad5 675 __IO uint32_t EFF_sa;
emilmont 40:976df7c37ad5 676 __IO uint32_t EFF_GRP_sa;
emilmont 40:976df7c37ad5 677 __IO uint32_t ENDofTable;
emilmont 40:976df7c37ad5 678 __I uint32_t LUTerrAd;
emilmont 40:976df7c37ad5 679 __I uint32_t LUTerr;
emilmont 40:976df7c37ad5 680 __IO uint32_t FCANIE;
emilmont 40:976df7c37ad5 681 __IO uint32_t FCANIC0;
emilmont 40:976df7c37ad5 682 __IO uint32_t FCANIC1;
emilmont 40:976df7c37ad5 683 } LPC_CANAF_TypeDef;
emilmont 40:976df7c37ad5 684
emilmont 40:976df7c37ad5 685 typedef struct /* Central Registers */
emilmont 40:976df7c37ad5 686 {
emilmont 40:976df7c37ad5 687 __I uint32_t CANTxSR;
emilmont 40:976df7c37ad5 688 __I uint32_t CANRxSR;
emilmont 40:976df7c37ad5 689 __I uint32_t CANMSR;
emilmont 40:976df7c37ad5 690 } LPC_CANCR_TypeDef;
emilmont 40:976df7c37ad5 691
emilmont 40:976df7c37ad5 692 typedef struct /* Controller Registers */
emilmont 40:976df7c37ad5 693 {
emilmont 40:976df7c37ad5 694 __IO uint32_t MOD;
emilmont 40:976df7c37ad5 695 __O uint32_t CMR;
emilmont 40:976df7c37ad5 696 __IO uint32_t GSR;
emilmont 40:976df7c37ad5 697 __I uint32_t ICR;
emilmont 40:976df7c37ad5 698 __IO uint32_t IER;
emilmont 40:976df7c37ad5 699 __IO uint32_t BTR;
emilmont 40:976df7c37ad5 700 __IO uint32_t EWL;
emilmont 40:976df7c37ad5 701 __I uint32_t SR;
emilmont 40:976df7c37ad5 702 __IO uint32_t RFS;
emilmont 40:976df7c37ad5 703 __IO uint32_t RID;
emilmont 40:976df7c37ad5 704 __IO uint32_t RDA;
emilmont 40:976df7c37ad5 705 __IO uint32_t RDB;
emilmont 40:976df7c37ad5 706 __IO uint32_t TFI1;
emilmont 40:976df7c37ad5 707 __IO uint32_t TID1;
emilmont 40:976df7c37ad5 708 __IO uint32_t TDA1;
emilmont 40:976df7c37ad5 709 __IO uint32_t TDB1;
emilmont 40:976df7c37ad5 710 __IO uint32_t TFI2;
emilmont 40:976df7c37ad5 711 __IO uint32_t TID2;
emilmont 40:976df7c37ad5 712 __IO uint32_t TDA2;
emilmont 40:976df7c37ad5 713 __IO uint32_t TDB2;
emilmont 40:976df7c37ad5 714 __IO uint32_t TFI3;
emilmont 40:976df7c37ad5 715 __IO uint32_t TID3;
emilmont 40:976df7c37ad5 716 __IO uint32_t TDA3;
emilmont 40:976df7c37ad5 717 __IO uint32_t TDB3;
emilmont 40:976df7c37ad5 718 } LPC_CAN_TypeDef;
emilmont 40:976df7c37ad5 719
emilmont 40:976df7c37ad5 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
emilmont 40:976df7c37ad5 721 typedef struct /* Common Registers */
emilmont 40:976df7c37ad5 722 {
emilmont 40:976df7c37ad5 723 __I uint32_t DMACIntStat;
emilmont 40:976df7c37ad5 724 __I uint32_t DMACIntTCStat;
emilmont 40:976df7c37ad5 725 __O uint32_t DMACIntTCClear;
emilmont 40:976df7c37ad5 726 __I uint32_t DMACIntErrStat;
emilmont 40:976df7c37ad5 727 __O uint32_t DMACIntErrClr;
emilmont 40:976df7c37ad5 728 __I uint32_t DMACRawIntTCStat;
emilmont 40:976df7c37ad5 729 __I uint32_t DMACRawIntErrStat;
emilmont 40:976df7c37ad5 730 __I uint32_t DMACEnbldChns;
emilmont 40:976df7c37ad5 731 __IO uint32_t DMACSoftBReq;
emilmont 40:976df7c37ad5 732 __IO uint32_t DMACSoftSReq;
emilmont 40:976df7c37ad5 733 __IO uint32_t DMACSoftLBReq;
emilmont 40:976df7c37ad5 734 __IO uint32_t DMACSoftLSReq;
emilmont 40:976df7c37ad5 735 __IO uint32_t DMACConfig;
emilmont 40:976df7c37ad5 736 __IO uint32_t DMACSync;
emilmont 40:976df7c37ad5 737 } LPC_GPDMA_TypeDef;
emilmont 40:976df7c37ad5 738
emilmont 40:976df7c37ad5 739 typedef struct /* Channel Registers */
emilmont 40:976df7c37ad5 740 {
emilmont 40:976df7c37ad5 741 __IO uint32_t DMACCSrcAddr;
emilmont 40:976df7c37ad5 742 __IO uint32_t DMACCDestAddr;
emilmont 40:976df7c37ad5 743 __IO uint32_t DMACCLLI;
emilmont 40:976df7c37ad5 744 __IO uint32_t DMACCControl;
emilmont 40:976df7c37ad5 745 __IO uint32_t DMACCConfig;
emilmont 40:976df7c37ad5 746 } LPC_GPDMACH_TypeDef;
emilmont 40:976df7c37ad5 747
emilmont 40:976df7c37ad5 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
emilmont 40:976df7c37ad5 749 typedef struct
emilmont 40:976df7c37ad5 750 {
emilmont 40:976df7c37ad5 751 __I uint32_t HcRevision; /* USB Host Registers */
emilmont 40:976df7c37ad5 752 __IO uint32_t HcControl;
emilmont 40:976df7c37ad5 753 __IO uint32_t HcCommandStatus;
emilmont 40:976df7c37ad5 754 __IO uint32_t HcInterruptStatus;
emilmont 40:976df7c37ad5 755 __IO uint32_t HcInterruptEnable;
emilmont 40:976df7c37ad5 756 __IO uint32_t HcInterruptDisable;
emilmont 40:976df7c37ad5 757 __IO uint32_t HcHCCA;
emilmont 40:976df7c37ad5 758 __I uint32_t HcPeriodCurrentED;
emilmont 40:976df7c37ad5 759 __IO uint32_t HcControlHeadED;
emilmont 40:976df7c37ad5 760 __IO uint32_t HcControlCurrentED;
emilmont 40:976df7c37ad5 761 __IO uint32_t HcBulkHeadED;
emilmont 40:976df7c37ad5 762 __IO uint32_t HcBulkCurrentED;
emilmont 40:976df7c37ad5 763 __I uint32_t HcDoneHead;
emilmont 40:976df7c37ad5 764 __IO uint32_t HcFmInterval;
emilmont 40:976df7c37ad5 765 __I uint32_t HcFmRemaining;
emilmont 40:976df7c37ad5 766 __I uint32_t HcFmNumber;
emilmont 40:976df7c37ad5 767 __IO uint32_t HcPeriodicStart;
emilmont 40:976df7c37ad5 768 __IO uint32_t HcLSTreshold;
emilmont 40:976df7c37ad5 769 __IO uint32_t HcRhDescriptorA;
emilmont 40:976df7c37ad5 770 __IO uint32_t HcRhDescriptorB;
emilmont 40:976df7c37ad5 771 __IO uint32_t HcRhStatus;
emilmont 40:976df7c37ad5 772 __IO uint32_t HcRhPortStatus1;
emilmont 40:976df7c37ad5 773 __IO uint32_t HcRhPortStatus2;
emilmont 40:976df7c37ad5 774 uint32_t RESERVED0[40];
emilmont 40:976df7c37ad5 775 __I uint32_t Module_ID;
emilmont 40:976df7c37ad5 776
emilmont 40:976df7c37ad5 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
emilmont 40:976df7c37ad5 778 __IO uint32_t OTGIntEn;
emilmont 40:976df7c37ad5 779 __O uint32_t OTGIntSet;
emilmont 40:976df7c37ad5 780 __O uint32_t OTGIntClr;
emilmont 40:976df7c37ad5 781 __IO uint32_t OTGStCtrl;
emilmont 40:976df7c37ad5 782 __IO uint32_t OTGTmr;
emilmont 40:976df7c37ad5 783 uint32_t RESERVED1[58];
emilmont 40:976df7c37ad5 784
emilmont 40:976df7c37ad5 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
emilmont 40:976df7c37ad5 786 __IO uint32_t USBDevIntEn;
emilmont 40:976df7c37ad5 787 __O uint32_t USBDevIntClr;
emilmont 40:976df7c37ad5 788 __O uint32_t USBDevIntSet;
emilmont 40:976df7c37ad5 789
emilmont 40:976df7c37ad5 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
emilmont 40:976df7c37ad5 791 __I uint32_t USBCmdData;
emilmont 40:976df7c37ad5 792
emilmont 40:976df7c37ad5 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
emilmont 40:976df7c37ad5 794 __O uint32_t USBTxData;
emilmont 40:976df7c37ad5 795 __I uint32_t USBRxPLen;
emilmont 40:976df7c37ad5 796 __O uint32_t USBTxPLen;
emilmont 40:976df7c37ad5 797 __IO uint32_t USBCtrl;
emilmont 40:976df7c37ad5 798 __O uint32_t USBDevIntPri;
emilmont 40:976df7c37ad5 799
emilmont 40:976df7c37ad5 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
emilmont 40:976df7c37ad5 801 __IO uint32_t USBEpIntEn;
emilmont 40:976df7c37ad5 802 __O uint32_t USBEpIntClr;
emilmont 40:976df7c37ad5 803 __O uint32_t USBEpIntSet;
emilmont 40:976df7c37ad5 804 __O uint32_t USBEpIntPri;
emilmont 40:976df7c37ad5 805
emilmont 40:976df7c37ad5 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
emilmont 40:976df7c37ad5 807 __O uint32_t USBEpInd;
emilmont 40:976df7c37ad5 808 __IO uint32_t USBMaxPSize;
emilmont 40:976df7c37ad5 809
emilmont 40:976df7c37ad5 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
emilmont 40:976df7c37ad5 811 __O uint32_t USBDMARClr;
emilmont 40:976df7c37ad5 812 __O uint32_t USBDMARSet;
emilmont 40:976df7c37ad5 813 uint32_t RESERVED2[9];
emilmont 40:976df7c37ad5 814 __IO uint32_t USBUDCAH;
emilmont 40:976df7c37ad5 815 __I uint32_t USBEpDMASt;
emilmont 40:976df7c37ad5 816 __O uint32_t USBEpDMAEn;
emilmont 40:976df7c37ad5 817 __O uint32_t USBEpDMADis;
emilmont 40:976df7c37ad5 818 __I uint32_t USBDMAIntSt;
emilmont 40:976df7c37ad5 819 __IO uint32_t USBDMAIntEn;
emilmont 40:976df7c37ad5 820 uint32_t RESERVED3[2];
emilmont 40:976df7c37ad5 821 __I uint32_t USBEoTIntSt;
emilmont 40:976df7c37ad5 822 __O uint32_t USBEoTIntClr;
emilmont 40:976df7c37ad5 823 __O uint32_t USBEoTIntSet;
emilmont 40:976df7c37ad5 824 __I uint32_t USBNDDRIntSt;
emilmont 40:976df7c37ad5 825 __O uint32_t USBNDDRIntClr;
emilmont 40:976df7c37ad5 826 __O uint32_t USBNDDRIntSet;
emilmont 40:976df7c37ad5 827 __I uint32_t USBSysErrIntSt;
emilmont 40:976df7c37ad5 828 __O uint32_t USBSysErrIntClr;
emilmont 40:976df7c37ad5 829 __O uint32_t USBSysErrIntSet;
emilmont 40:976df7c37ad5 830 uint32_t RESERVED4[15];
emilmont 40:976df7c37ad5 831
emilmont 40:976df7c37ad5 832 union {
emilmont 40:976df7c37ad5 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
emilmont 40:976df7c37ad5 834 __O uint32_t I2C_TX;
emilmont 40:976df7c37ad5 835 };
emilmont 40:976df7c37ad5 836 __I uint32_t I2C_STS;
emilmont 40:976df7c37ad5 837 __IO uint32_t I2C_CTL;
emilmont 40:976df7c37ad5 838 __IO uint32_t I2C_CLKHI;
emilmont 40:976df7c37ad5 839 __O uint32_t I2C_CLKLO;
emilmont 40:976df7c37ad5 840 uint32_t RESERVED5[824];
emilmont 40:976df7c37ad5 841
emilmont 40:976df7c37ad5 842 union {
emilmont 40:976df7c37ad5 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
emilmont 40:976df7c37ad5 844 __IO uint32_t OTGClkCtrl;
emilmont 40:976df7c37ad5 845 };
emilmont 40:976df7c37ad5 846 union {
emilmont 40:976df7c37ad5 847 __I uint32_t USBClkSt;
emilmont 40:976df7c37ad5 848 __I uint32_t OTGClkSt;
emilmont 40:976df7c37ad5 849 };
emilmont 40:976df7c37ad5 850 } LPC_USB_TypeDef;
emilmont 40:976df7c37ad5 851
emilmont 40:976df7c37ad5 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
emilmont 40:976df7c37ad5 853 typedef struct
emilmont 40:976df7c37ad5 854 {
emilmont 40:976df7c37ad5 855 __IO uint32_t MAC1; /* MAC Registers */
emilmont 40:976df7c37ad5 856 __IO uint32_t MAC2;
emilmont 40:976df7c37ad5 857 __IO uint32_t IPGT;
emilmont 40:976df7c37ad5 858 __IO uint32_t IPGR;
emilmont 40:976df7c37ad5 859 __IO uint32_t CLRT;
emilmont 40:976df7c37ad5 860 __IO uint32_t MAXF;
emilmont 40:976df7c37ad5 861 __IO uint32_t SUPP;
emilmont 40:976df7c37ad5 862 __IO uint32_t TEST;
emilmont 40:976df7c37ad5 863 __IO uint32_t MCFG;
emilmont 40:976df7c37ad5 864 __IO uint32_t MCMD;
emilmont 40:976df7c37ad5 865 __IO uint32_t MADR;
emilmont 40:976df7c37ad5 866 __O uint32_t MWTD;
emilmont 40:976df7c37ad5 867 __I uint32_t MRDD;
emilmont 40:976df7c37ad5 868 __I uint32_t MIND;
emilmont 40:976df7c37ad5 869 uint32_t RESERVED0[2];
emilmont 40:976df7c37ad5 870 __IO uint32_t SA0;
emilmont 40:976df7c37ad5 871 __IO uint32_t SA1;
emilmont 40:976df7c37ad5 872 __IO uint32_t SA2;
emilmont 40:976df7c37ad5 873 uint32_t RESERVED1[45];
emilmont 40:976df7c37ad5 874 __IO uint32_t Command; /* Control Registers */
emilmont 40:976df7c37ad5 875 __I uint32_t Status;
emilmont 40:976df7c37ad5 876 __IO uint32_t RxDescriptor;
emilmont 40:976df7c37ad5 877 __IO uint32_t RxStatus;
emilmont 40:976df7c37ad5 878 __IO uint32_t RxDescriptorNumber;
emilmont 40:976df7c37ad5 879 __I uint32_t RxProduceIndex;
emilmont 40:976df7c37ad5 880 __IO uint32_t RxConsumeIndex;
emilmont 40:976df7c37ad5 881 __IO uint32_t TxDescriptor;
emilmont 40:976df7c37ad5 882 __IO uint32_t TxStatus;
emilmont 40:976df7c37ad5 883 __IO uint32_t TxDescriptorNumber;
emilmont 40:976df7c37ad5 884 __IO uint32_t TxProduceIndex;
emilmont 40:976df7c37ad5 885 __I uint32_t TxConsumeIndex;
emilmont 40:976df7c37ad5 886 uint32_t RESERVED2[10];
emilmont 40:976df7c37ad5 887 __I uint32_t TSV0;
emilmont 40:976df7c37ad5 888 __I uint32_t TSV1;
emilmont 40:976df7c37ad5 889 __I uint32_t RSV;
emilmont 40:976df7c37ad5 890 uint32_t RESERVED3[3];
emilmont 40:976df7c37ad5 891 __IO uint32_t FlowControlCounter;
emilmont 40:976df7c37ad5 892 __I uint32_t FlowControlStatus;
emilmont 40:976df7c37ad5 893 uint32_t RESERVED4[34];
emilmont 40:976df7c37ad5 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
emilmont 40:976df7c37ad5 895 __IO uint32_t RxFilterWoLStatus;
emilmont 40:976df7c37ad5 896 __IO uint32_t RxFilterWoLClear;
emilmont 40:976df7c37ad5 897 uint32_t RESERVED5;
emilmont 40:976df7c37ad5 898 __IO uint32_t HashFilterL;
emilmont 40:976df7c37ad5 899 __IO uint32_t HashFilterH;
emilmont 40:976df7c37ad5 900 uint32_t RESERVED6[882];
emilmont 40:976df7c37ad5 901 __I uint32_t IntStatus; /* Module Control Registers */
emilmont 40:976df7c37ad5 902 __IO uint32_t IntEnable;
emilmont 40:976df7c37ad5 903 __O uint32_t IntClear;
emilmont 40:976df7c37ad5 904 __O uint32_t IntSet;
emilmont 40:976df7c37ad5 905 uint32_t RESERVED7;
emilmont 40:976df7c37ad5 906 __IO uint32_t PowerDown;
emilmont 40:976df7c37ad5 907 uint32_t RESERVED8;
emilmont 40:976df7c37ad5 908 __IO uint32_t Module_ID;
emilmont 40:976df7c37ad5 909 } LPC_EMAC_TypeDef;
emilmont 40:976df7c37ad5 910
emilmont 40:976df7c37ad5 911 #if defined ( __CC_ARM )
emilmont 40:976df7c37ad5 912 #pragma no_anon_unions
emilmont 40:976df7c37ad5 913 #endif
emilmont 40:976df7c37ad5 914
emilmont 40:976df7c37ad5 915
emilmont 40:976df7c37ad5 916 /******************************************************************************/
emilmont 40:976df7c37ad5 917 /* Peripheral memory map */
emilmont 40:976df7c37ad5 918 /******************************************************************************/
emilmont 40:976df7c37ad5 919 /* Base addresses */
emilmont 40:976df7c37ad5 920 #define LPC_FLASH_BASE (0x00000000UL)
emilmont 40:976df7c37ad5 921 #define LPC_RAM_BASE (0x10000000UL)
emilmont 40:976df7c37ad5 922 #define LPC_GPIO_BASE (0x2009C000UL)
emilmont 40:976df7c37ad5 923 #define LPC_APB0_BASE (0x40000000UL)
emilmont 40:976df7c37ad5 924 #define LPC_APB1_BASE (0x40080000UL)
emilmont 40:976df7c37ad5 925 #define LPC_AHB_BASE (0x50000000UL)
emilmont 40:976df7c37ad5 926 #define LPC_CM3_BASE (0xE0000000UL)
emilmont 40:976df7c37ad5 927
emilmont 40:976df7c37ad5 928 /* APB0 peripherals */
emilmont 40:976df7c37ad5 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
emilmont 40:976df7c37ad5 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
emilmont 40:976df7c37ad5 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
emilmont 40:976df7c37ad5 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
emilmont 40:976df7c37ad5 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
emilmont 40:976df7c37ad5 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
emilmont 40:976df7c37ad5 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
emilmont 40:976df7c37ad5 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
emilmont 40:976df7c37ad5 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
emilmont 40:976df7c37ad5 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
emilmont 40:976df7c37ad5 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
emilmont 40:976df7c37ad5 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
emilmont 40:976df7c37ad5 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
emilmont 40:976df7c37ad5 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
emilmont 40:976df7c37ad5 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
emilmont 40:976df7c37ad5 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
emilmont 40:976df7c37ad5 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
emilmont 40:976df7c37ad5 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
emilmont 40:976df7c37ad5 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
emilmont 40:976df7c37ad5 948
emilmont 40:976df7c37ad5 949 /* APB1 peripherals */
emilmont 40:976df7c37ad5 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
emilmont 40:976df7c37ad5 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
emilmont 40:976df7c37ad5 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
emilmont 40:976df7c37ad5 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
emilmont 40:976df7c37ad5 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
emilmont 40:976df7c37ad5 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
emilmont 40:976df7c37ad5 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
emilmont 40:976df7c37ad5 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
emilmont 40:976df7c37ad5 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
emilmont 40:976df7c37ad5 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
emilmont 40:976df7c37ad5 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
emilmont 40:976df7c37ad5 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
emilmont 40:976df7c37ad5 962
emilmont 40:976df7c37ad5 963 /* AHB peripherals */
emilmont 40:976df7c37ad5 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
emilmont 40:976df7c37ad5 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
emilmont 40:976df7c37ad5 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
emilmont 40:976df7c37ad5 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
emilmont 40:976df7c37ad5 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
emilmont 40:976df7c37ad5 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
emilmont 40:976df7c37ad5 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
emilmont 40:976df7c37ad5 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
emilmont 40:976df7c37ad5 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
emilmont 40:976df7c37ad5 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
emilmont 40:976df7c37ad5 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
emilmont 40:976df7c37ad5 975
emilmont 40:976df7c37ad5 976 /* GPIOs */
emilmont 40:976df7c37ad5 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
emilmont 40:976df7c37ad5 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
emilmont 40:976df7c37ad5 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
emilmont 40:976df7c37ad5 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
emilmont 40:976df7c37ad5 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
emilmont 40:976df7c37ad5 982
emilmont 40:976df7c37ad5 983
emilmont 40:976df7c37ad5 984 /******************************************************************************/
emilmont 40:976df7c37ad5 985 /* Peripheral declaration */
emilmont 40:976df7c37ad5 986 /******************************************************************************/
emilmont 40:976df7c37ad5 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
emilmont 40:976df7c37ad5 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
emilmont 40:976df7c37ad5 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
emilmont 40:976df7c37ad5 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
emilmont 40:976df7c37ad5 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
emilmont 40:976df7c37ad5 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
emilmont 40:976df7c37ad5 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
emilmont 40:976df7c37ad5 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
emilmont 40:976df7c37ad5 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
emilmont 40:976df7c37ad5 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
emilmont 40:976df7c37ad5 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
emilmont 40:976df7c37ad5 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
emilmont 40:976df7c37ad5 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
emilmont 40:976df7c37ad5 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
emilmont 40:976df7c37ad5 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
emilmont 40:976df7c37ad5 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
emilmont 40:976df7c37ad5 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
emilmont 40:976df7c37ad5 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
emilmont 40:976df7c37ad5 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
emilmont 40:976df7c37ad5 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
emilmont 40:976df7c37ad5 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
emilmont 40:976df7c37ad5 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
emilmont 40:976df7c37ad5 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
emilmont 40:976df7c37ad5 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
emilmont 40:976df7c37ad5 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
emilmont 40:976df7c37ad5 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
emilmont 40:976df7c37ad5 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
emilmont 40:976df7c37ad5 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
emilmont 40:976df7c37ad5 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
emilmont 40:976df7c37ad5 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
emilmont 40:976df7c37ad5 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
emilmont 40:976df7c37ad5 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
emilmont 40:976df7c37ad5 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
emilmont 40:976df7c37ad5 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
emilmont 40:976df7c37ad5 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
emilmont 40:976df7c37ad5 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
emilmont 40:976df7c37ad5 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
emilmont 40:976df7c37ad5 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
emilmont 40:976df7c37ad5 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
emilmont 40:976df7c37ad5 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
emilmont 40:976df7c37ad5 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
emilmont 40:976df7c37ad5 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
emilmont 40:976df7c37ad5 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
emilmont 40:976df7c37ad5 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
emilmont 40:976df7c37ad5 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
emilmont 40:976df7c37ad5 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
emilmont 40:976df7c37ad5 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
emilmont 40:976df7c37ad5 1034
emilmont 40:976df7c37ad5 1035 #endif // __LPC17xx_H__