Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

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TARGET_SSCI824/core_cm0plus.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**************************************************************************//**
Kojto 90:cb3d968589d8 2 * @file core_cm0plus.h
Kojto 90:cb3d968589d8 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
Kojto 90:cb3d968589d8 4 * @version V3.20
Kojto 90:cb3d968589d8 5 * @date 25. February 2013
Kojto 90:cb3d968589d8 6 *
Kojto 90:cb3d968589d8 7 * @note
Kojto 90:cb3d968589d8 8 *
Kojto 90:cb3d968589d8 9 ******************************************************************************/
Kojto 90:cb3d968589d8 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto 90:cb3d968589d8 11
Kojto 90:cb3d968589d8 12 All rights reserved.
Kojto 90:cb3d968589d8 13 Redistribution and use in source and binary forms, with or without
Kojto 90:cb3d968589d8 14 modification, are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 15 - Redistributions of source code must retain the above copyright
Kojto 90:cb3d968589d8 16 notice, this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 17 - Redistributions in binary form must reproduce the above copyright
Kojto 90:cb3d968589d8 18 notice, this list of conditions and the following disclaimer in the
Kojto 90:cb3d968589d8 19 documentation and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 20 - Neither the name of ARM nor the names of its contributors may be used
Kojto 90:cb3d968589d8 21 to endorse or promote products derived from this software without
Kojto 90:cb3d968589d8 22 specific prior written permission.
Kojto 90:cb3d968589d8 23 *
Kojto 90:cb3d968589d8 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto 90:cb3d968589d8 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto 90:cb3d968589d8 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto 90:cb3d968589d8 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto 90:cb3d968589d8 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto 90:cb3d968589d8 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto 90:cb3d968589d8 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto 90:cb3d968589d8 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 90:cb3d968589d8 34 POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 35 ---------------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 36
Kojto 90:cb3d968589d8 37
Kojto 90:cb3d968589d8 38 #if defined ( __ICCARM__ )
Kojto 90:cb3d968589d8 39 #pragma system_include /* treat file as system include file for MISRA check */
Kojto 90:cb3d968589d8 40 #endif
Kojto 90:cb3d968589d8 41
Kojto 90:cb3d968589d8 42 #ifdef __cplusplus
Kojto 90:cb3d968589d8 43 extern "C" {
Kojto 90:cb3d968589d8 44 #endif
Kojto 90:cb3d968589d8 45
Kojto 90:cb3d968589d8 46 #ifndef __CORE_CM0PLUS_H_GENERIC
Kojto 90:cb3d968589d8 47 #define __CORE_CM0PLUS_H_GENERIC
Kojto 90:cb3d968589d8 48
Kojto 90:cb3d968589d8 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto 90:cb3d968589d8 50 CMSIS violates the following MISRA-C:2004 rules:
Kojto 90:cb3d968589d8 51
Kojto 90:cb3d968589d8 52 \li Required Rule 8.5, object/function definition in header file.<br>
Kojto 90:cb3d968589d8 53 Function definitions in header files are used to allow 'inlining'.
Kojto 90:cb3d968589d8 54
Kojto 90:cb3d968589d8 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto 90:cb3d968589d8 56 Unions are used for effective representation of core registers.
Kojto 90:cb3d968589d8 57
Kojto 90:cb3d968589d8 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto 90:cb3d968589d8 59 Function-like macros are used to allow more efficient code.
Kojto 90:cb3d968589d8 60 */
Kojto 90:cb3d968589d8 61
Kojto 90:cb3d968589d8 62
Kojto 90:cb3d968589d8 63 /*******************************************************************************
Kojto 90:cb3d968589d8 64 * CMSIS definitions
Kojto 90:cb3d968589d8 65 ******************************************************************************/
Kojto 90:cb3d968589d8 66 /** \ingroup Cortex-M0+
Kojto 90:cb3d968589d8 67 @{
Kojto 90:cb3d968589d8 68 */
Kojto 90:cb3d968589d8 69
Kojto 90:cb3d968589d8 70 /* CMSIS CM0P definitions */
Kojto 90:cb3d968589d8 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
Kojto 90:cb3d968589d8 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
Kojto 90:cb3d968589d8 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
Kojto 90:cb3d968589d8 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Kojto 90:cb3d968589d8 75
Kojto 90:cb3d968589d8 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
Kojto 90:cb3d968589d8 77
Kojto 90:cb3d968589d8 78
Kojto 90:cb3d968589d8 79 #if defined ( __CC_ARM )
Kojto 90:cb3d968589d8 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Kojto 90:cb3d968589d8 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Kojto 90:cb3d968589d8 82 #define __STATIC_INLINE static __inline
Kojto 90:cb3d968589d8 83
Kojto 90:cb3d968589d8 84 #elif defined ( __ICCARM__ )
Kojto 90:cb3d968589d8 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Kojto 90:cb3d968589d8 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
Kojto 90:cb3d968589d8 87 #define __STATIC_INLINE static inline
Kojto 90:cb3d968589d8 88
Kojto 90:cb3d968589d8 89 #elif defined ( __GNUC__ )
Kojto 90:cb3d968589d8 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 90:cb3d968589d8 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 90:cb3d968589d8 92 #define __STATIC_INLINE static inline
Kojto 90:cb3d968589d8 93
Kojto 90:cb3d968589d8 94 #elif defined ( __TASKING__ )
Kojto 90:cb3d968589d8 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Kojto 90:cb3d968589d8 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Kojto 90:cb3d968589d8 97 #define __STATIC_INLINE static inline
Kojto 90:cb3d968589d8 98
Kojto 90:cb3d968589d8 99 #endif
Kojto 90:cb3d968589d8 100
Kojto 90:cb3d968589d8 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto 90:cb3d968589d8 102 */
Kojto 90:cb3d968589d8 103 #define __FPU_USED 0
Kojto 90:cb3d968589d8 104
Kojto 90:cb3d968589d8 105 #if defined ( __CC_ARM )
Kojto 90:cb3d968589d8 106 #if defined __TARGET_FPU_VFP
Kojto 90:cb3d968589d8 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 90:cb3d968589d8 108 #endif
Kojto 90:cb3d968589d8 109
Kojto 90:cb3d968589d8 110 #elif defined ( __ICCARM__ )
Kojto 90:cb3d968589d8 111 #if defined __ARMVFP__
Kojto 90:cb3d968589d8 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 90:cb3d968589d8 113 #endif
Kojto 90:cb3d968589d8 114
Kojto 90:cb3d968589d8 115 #elif defined ( __GNUC__ )
Kojto 90:cb3d968589d8 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 90:cb3d968589d8 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 90:cb3d968589d8 118 #endif
Kojto 90:cb3d968589d8 119
Kojto 90:cb3d968589d8 120 #elif defined ( __TASKING__ )
Kojto 90:cb3d968589d8 121 #if defined __FPU_VFP__
Kojto 90:cb3d968589d8 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 90:cb3d968589d8 123 #endif
Kojto 90:cb3d968589d8 124 #endif
Kojto 90:cb3d968589d8 125
Kojto 90:cb3d968589d8 126 #include <stdint.h> /* standard types definitions */
Kojto 90:cb3d968589d8 127 #include <core_cmInstr.h> /* Core Instruction Access */
Kojto 90:cb3d968589d8 128 #include <core_cmFunc.h> /* Core Function Access */
Kojto 90:cb3d968589d8 129
Kojto 90:cb3d968589d8 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
Kojto 90:cb3d968589d8 131
Kojto 90:cb3d968589d8 132 #ifndef __CMSIS_GENERIC
Kojto 90:cb3d968589d8 133
Kojto 90:cb3d968589d8 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
Kojto 90:cb3d968589d8 135 #define __CORE_CM0PLUS_H_DEPENDANT
Kojto 90:cb3d968589d8 136
Kojto 90:cb3d968589d8 137 /* check device defines and use defaults */
Kojto 90:cb3d968589d8 138 #if defined __CHECK_DEVICE_DEFINES
Kojto 90:cb3d968589d8 139 #ifndef __CM0PLUS_REV
Kojto 90:cb3d968589d8 140 #define __CM0PLUS_REV 0x0000
Kojto 90:cb3d968589d8 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
Kojto 90:cb3d968589d8 142 #endif
Kojto 90:cb3d968589d8 143
Kojto 90:cb3d968589d8 144 #ifndef __MPU_PRESENT
Kojto 90:cb3d968589d8 145 #define __MPU_PRESENT 0
Kojto 90:cb3d968589d8 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto 90:cb3d968589d8 147 #endif
Kojto 90:cb3d968589d8 148
Kojto 90:cb3d968589d8 149 #ifndef __VTOR_PRESENT
Kojto 90:cb3d968589d8 150 #define __VTOR_PRESENT 0
Kojto 90:cb3d968589d8 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
Kojto 90:cb3d968589d8 152 #endif
Kojto 90:cb3d968589d8 153
Kojto 90:cb3d968589d8 154 #ifndef __NVIC_PRIO_BITS
Kojto 90:cb3d968589d8 155 #define __NVIC_PRIO_BITS 2
Kojto 90:cb3d968589d8 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto 90:cb3d968589d8 157 #endif
Kojto 90:cb3d968589d8 158
Kojto 90:cb3d968589d8 159 #ifndef __Vendor_SysTickConfig
Kojto 90:cb3d968589d8 160 #define __Vendor_SysTickConfig 0
Kojto 90:cb3d968589d8 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto 90:cb3d968589d8 162 #endif
Kojto 90:cb3d968589d8 163 #endif
Kojto 90:cb3d968589d8 164
Kojto 90:cb3d968589d8 165 /* IO definitions (access restrictions to peripheral registers) */
Kojto 90:cb3d968589d8 166 /**
Kojto 90:cb3d968589d8 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto 90:cb3d968589d8 168
Kojto 90:cb3d968589d8 169 <strong>IO Type Qualifiers</strong> are used
Kojto 90:cb3d968589d8 170 \li to specify the access to peripheral variables.
Kojto 90:cb3d968589d8 171 \li for automatic generation of peripheral register debug information.
Kojto 90:cb3d968589d8 172 */
Kojto 90:cb3d968589d8 173 #ifdef __cplusplus
Kojto 90:cb3d968589d8 174 #define __I volatile /*!< Defines 'read only' permissions */
Kojto 90:cb3d968589d8 175 #else
Kojto 90:cb3d968589d8 176 #define __I volatile const /*!< Defines 'read only' permissions */
Kojto 90:cb3d968589d8 177 #endif
Kojto 90:cb3d968589d8 178 #define __O volatile /*!< Defines 'write only' permissions */
Kojto 90:cb3d968589d8 179 #define __IO volatile /*!< Defines 'read / write' permissions */
Kojto 90:cb3d968589d8 180
Kojto 90:cb3d968589d8 181 /*@} end of group Cortex-M0+ */
Kojto 90:cb3d968589d8 182
Kojto 90:cb3d968589d8 183
Kojto 90:cb3d968589d8 184
Kojto 90:cb3d968589d8 185 /*******************************************************************************
Kojto 90:cb3d968589d8 186 * Register Abstraction
Kojto 90:cb3d968589d8 187 Core Register contain:
Kojto 90:cb3d968589d8 188 - Core Register
Kojto 90:cb3d968589d8 189 - Core NVIC Register
Kojto 90:cb3d968589d8 190 - Core SCB Register
Kojto 90:cb3d968589d8 191 - Core SysTick Register
Kojto 90:cb3d968589d8 192 - Core MPU Register
Kojto 90:cb3d968589d8 193 ******************************************************************************/
Kojto 90:cb3d968589d8 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto 90:cb3d968589d8 195 \brief Type definitions and defines for Cortex-M processor based devices.
Kojto 90:cb3d968589d8 196 */
Kojto 90:cb3d968589d8 197
Kojto 90:cb3d968589d8 198 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 199 \defgroup CMSIS_CORE Status and Control Registers
Kojto 90:cb3d968589d8 200 \brief Core Register type definitions.
Kojto 90:cb3d968589d8 201 @{
Kojto 90:cb3d968589d8 202 */
Kojto 90:cb3d968589d8 203
Kojto 90:cb3d968589d8 204 /** \brief Union type to access the Application Program Status Register (APSR).
Kojto 90:cb3d968589d8 205 */
Kojto 90:cb3d968589d8 206 typedef union
Kojto 90:cb3d968589d8 207 {
Kojto 90:cb3d968589d8 208 struct
Kojto 90:cb3d968589d8 209 {
Kojto 90:cb3d968589d8 210 #if (__CORTEX_M != 0x04)
Kojto 90:cb3d968589d8 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
Kojto 90:cb3d968589d8 212 #else
Kojto 90:cb3d968589d8 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
Kojto 90:cb3d968589d8 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 90:cb3d968589d8 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
Kojto 90:cb3d968589d8 216 #endif
Kojto 90:cb3d968589d8 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 90:cb3d968589d8 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 90:cb3d968589d8 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 90:cb3d968589d8 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 90:cb3d968589d8 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 90:cb3d968589d8 222 } b; /*!< Structure used for bit access */
Kojto 90:cb3d968589d8 223 uint32_t w; /*!< Type used for word access */
Kojto 90:cb3d968589d8 224 } APSR_Type;
Kojto 90:cb3d968589d8 225
Kojto 90:cb3d968589d8 226
Kojto 90:cb3d968589d8 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto 90:cb3d968589d8 228 */
Kojto 90:cb3d968589d8 229 typedef union
Kojto 90:cb3d968589d8 230 {
Kojto 90:cb3d968589d8 231 struct
Kojto 90:cb3d968589d8 232 {
Kojto 90:cb3d968589d8 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 90:cb3d968589d8 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
Kojto 90:cb3d968589d8 235 } b; /*!< Structure used for bit access */
Kojto 90:cb3d968589d8 236 uint32_t w; /*!< Type used for word access */
Kojto 90:cb3d968589d8 237 } IPSR_Type;
Kojto 90:cb3d968589d8 238
Kojto 90:cb3d968589d8 239
Kojto 90:cb3d968589d8 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto 90:cb3d968589d8 241 */
Kojto 90:cb3d968589d8 242 typedef union
Kojto 90:cb3d968589d8 243 {
Kojto 90:cb3d968589d8 244 struct
Kojto 90:cb3d968589d8 245 {
Kojto 90:cb3d968589d8 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
Kojto 90:cb3d968589d8 247 #if (__CORTEX_M != 0x04)
Kojto 90:cb3d968589d8 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
Kojto 90:cb3d968589d8 249 #else
Kojto 90:cb3d968589d8 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
Kojto 90:cb3d968589d8 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
Kojto 90:cb3d968589d8 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
Kojto 90:cb3d968589d8 253 #endif
Kojto 90:cb3d968589d8 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 90:cb3d968589d8 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
Kojto 90:cb3d968589d8 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
Kojto 90:cb3d968589d8 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
Kojto 90:cb3d968589d8 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
Kojto 90:cb3d968589d8 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
Kojto 90:cb3d968589d8 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
Kojto 90:cb3d968589d8 261 } b; /*!< Structure used for bit access */
Kojto 90:cb3d968589d8 262 uint32_t w; /*!< Type used for word access */
Kojto 90:cb3d968589d8 263 } xPSR_Type;
Kojto 90:cb3d968589d8 264
Kojto 90:cb3d968589d8 265
Kojto 90:cb3d968589d8 266 /** \brief Union type to access the Control Registers (CONTROL).
Kojto 90:cb3d968589d8 267 */
Kojto 90:cb3d968589d8 268 typedef union
Kojto 90:cb3d968589d8 269 {
Kojto 90:cb3d968589d8 270 struct
Kojto 90:cb3d968589d8 271 {
Kojto 90:cb3d968589d8 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
Kojto 90:cb3d968589d8 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 90:cb3d968589d8 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
Kojto 90:cb3d968589d8 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
Kojto 90:cb3d968589d8 276 } b; /*!< Structure used for bit access */
Kojto 90:cb3d968589d8 277 uint32_t w; /*!< Type used for word access */
Kojto 90:cb3d968589d8 278 } CONTROL_Type;
Kojto 90:cb3d968589d8 279
Kojto 90:cb3d968589d8 280 /*@} end of group CMSIS_CORE */
Kojto 90:cb3d968589d8 281
Kojto 90:cb3d968589d8 282
Kojto 90:cb3d968589d8 283 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto 90:cb3d968589d8 285 \brief Type definitions for the NVIC Registers
Kojto 90:cb3d968589d8 286 @{
Kojto 90:cb3d968589d8 287 */
Kojto 90:cb3d968589d8 288
Kojto 90:cb3d968589d8 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto 90:cb3d968589d8 290 */
Kojto 90:cb3d968589d8 291 typedef struct
Kojto 90:cb3d968589d8 292 {
Kojto 90:cb3d968589d8 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
Kojto 90:cb3d968589d8 294 uint32_t RESERVED0[31];
Kojto 90:cb3d968589d8 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
Kojto 90:cb3d968589d8 296 uint32_t RSERVED1[31];
Kojto 90:cb3d968589d8 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
Kojto 90:cb3d968589d8 298 uint32_t RESERVED2[31];
Kojto 90:cb3d968589d8 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
Kojto 90:cb3d968589d8 300 uint32_t RESERVED3[31];
Kojto 90:cb3d968589d8 301 uint32_t RESERVED4[64];
Kojto 90:cb3d968589d8 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
Kojto 90:cb3d968589d8 303 } NVIC_Type;
Kojto 90:cb3d968589d8 304
Kojto 90:cb3d968589d8 305 /*@} end of group CMSIS_NVIC */
Kojto 90:cb3d968589d8 306
Kojto 90:cb3d968589d8 307
Kojto 90:cb3d968589d8 308 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 309 \defgroup CMSIS_SCB System Control Block (SCB)
Kojto 90:cb3d968589d8 310 \brief Type definitions for the System Control Block Registers
Kojto 90:cb3d968589d8 311 @{
Kojto 90:cb3d968589d8 312 */
Kojto 90:cb3d968589d8 313
Kojto 90:cb3d968589d8 314 /** \brief Structure type to access the System Control Block (SCB).
Kojto 90:cb3d968589d8 315 */
Kojto 90:cb3d968589d8 316 typedef struct
Kojto 90:cb3d968589d8 317 {
Kojto 90:cb3d968589d8 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
Kojto 90:cb3d968589d8 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
Kojto 90:cb3d968589d8 320 #if (__VTOR_PRESENT == 1)
Kojto 90:cb3d968589d8 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
Kojto 90:cb3d968589d8 322 #else
Kojto 90:cb3d968589d8 323 uint32_t RESERVED0;
Kojto 90:cb3d968589d8 324 #endif
Kojto 90:cb3d968589d8 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
Kojto 90:cb3d968589d8 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
Kojto 90:cb3d968589d8 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
Kojto 90:cb3d968589d8 328 uint32_t RESERVED1;
Kojto 90:cb3d968589d8 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
Kojto 90:cb3d968589d8 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
Kojto 90:cb3d968589d8 331 } SCB_Type;
Kojto 90:cb3d968589d8 332
Kojto 90:cb3d968589d8 333 /* SCB CPUID Register Definitions */
Kojto 90:cb3d968589d8 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
Kojto 90:cb3d968589d8 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
Kojto 90:cb3d968589d8 336
Kojto 90:cb3d968589d8 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
Kojto 90:cb3d968589d8 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
Kojto 90:cb3d968589d8 339
Kojto 90:cb3d968589d8 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
Kojto 90:cb3d968589d8 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
Kojto 90:cb3d968589d8 342
Kojto 90:cb3d968589d8 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
Kojto 90:cb3d968589d8 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
Kojto 90:cb3d968589d8 345
Kojto 90:cb3d968589d8 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 90:cb3d968589d8 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
Kojto 90:cb3d968589d8 348
Kojto 90:cb3d968589d8 349 /* SCB Interrupt Control State Register Definitions */
Kojto 90:cb3d968589d8 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
Kojto 90:cb3d968589d8 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
Kojto 90:cb3d968589d8 352
Kojto 90:cb3d968589d8 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
Kojto 90:cb3d968589d8 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
Kojto 90:cb3d968589d8 355
Kojto 90:cb3d968589d8 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
Kojto 90:cb3d968589d8 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
Kojto 90:cb3d968589d8 358
Kojto 90:cb3d968589d8 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
Kojto 90:cb3d968589d8 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
Kojto 90:cb3d968589d8 361
Kojto 90:cb3d968589d8 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
Kojto 90:cb3d968589d8 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
Kojto 90:cb3d968589d8 364
Kojto 90:cb3d968589d8 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
Kojto 90:cb3d968589d8 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
Kojto 90:cb3d968589d8 367
Kojto 90:cb3d968589d8 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
Kojto 90:cb3d968589d8 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
Kojto 90:cb3d968589d8 370
Kojto 90:cb3d968589d8 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
Kojto 90:cb3d968589d8 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
Kojto 90:cb3d968589d8 373
Kojto 90:cb3d968589d8 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 90:cb3d968589d8 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
Kojto 90:cb3d968589d8 376
Kojto 90:cb3d968589d8 377 #if (__VTOR_PRESENT == 1)
Kojto 90:cb3d968589d8 378 /* SCB Interrupt Control State Register Definitions */
Kojto 90:cb3d968589d8 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
Kojto 90:cb3d968589d8 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
Kojto 90:cb3d968589d8 381 #endif
Kojto 90:cb3d968589d8 382
Kojto 90:cb3d968589d8 383 /* SCB Application Interrupt and Reset Control Register Definitions */
Kojto 90:cb3d968589d8 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
Kojto 90:cb3d968589d8 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
Kojto 90:cb3d968589d8 386
Kojto 90:cb3d968589d8 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
Kojto 90:cb3d968589d8 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
Kojto 90:cb3d968589d8 389
Kojto 90:cb3d968589d8 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
Kojto 90:cb3d968589d8 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
Kojto 90:cb3d968589d8 392
Kojto 90:cb3d968589d8 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
Kojto 90:cb3d968589d8 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
Kojto 90:cb3d968589d8 395
Kojto 90:cb3d968589d8 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
Kojto 90:cb3d968589d8 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
Kojto 90:cb3d968589d8 398
Kojto 90:cb3d968589d8 399 /* SCB System Control Register Definitions */
Kojto 90:cb3d968589d8 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
Kojto 90:cb3d968589d8 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
Kojto 90:cb3d968589d8 402
Kojto 90:cb3d968589d8 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
Kojto 90:cb3d968589d8 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
Kojto 90:cb3d968589d8 405
Kojto 90:cb3d968589d8 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
Kojto 90:cb3d968589d8 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
Kojto 90:cb3d968589d8 408
Kojto 90:cb3d968589d8 409 /* SCB Configuration Control Register Definitions */
Kojto 90:cb3d968589d8 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
Kojto 90:cb3d968589d8 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
Kojto 90:cb3d968589d8 412
Kojto 90:cb3d968589d8 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
Kojto 90:cb3d968589d8 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
Kojto 90:cb3d968589d8 415
Kojto 90:cb3d968589d8 416 /* SCB System Handler Control and State Register Definitions */
Kojto 90:cb3d968589d8 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
Kojto 90:cb3d968589d8 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
Kojto 90:cb3d968589d8 419
Kojto 90:cb3d968589d8 420 /*@} end of group CMSIS_SCB */
Kojto 90:cb3d968589d8 421
Kojto 90:cb3d968589d8 422
Kojto 90:cb3d968589d8 423 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto 90:cb3d968589d8 425 \brief Type definitions for the System Timer Registers.
Kojto 90:cb3d968589d8 426 @{
Kojto 90:cb3d968589d8 427 */
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 /** \brief Structure type to access the System Timer (SysTick).
Kojto 90:cb3d968589d8 430 */
Kojto 90:cb3d968589d8 431 typedef struct
Kojto 90:cb3d968589d8 432 {
Kojto 90:cb3d968589d8 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
Kojto 90:cb3d968589d8 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
Kojto 90:cb3d968589d8 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
Kojto 90:cb3d968589d8 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
Kojto 90:cb3d968589d8 437 } SysTick_Type;
Kojto 90:cb3d968589d8 438
Kojto 90:cb3d968589d8 439 /* SysTick Control / Status Register Definitions */
Kojto 90:cb3d968589d8 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
Kojto 90:cb3d968589d8 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
Kojto 90:cb3d968589d8 442
Kojto 90:cb3d968589d8 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
Kojto 90:cb3d968589d8 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
Kojto 90:cb3d968589d8 445
Kojto 90:cb3d968589d8 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
Kojto 90:cb3d968589d8 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
Kojto 90:cb3d968589d8 448
Kojto 90:cb3d968589d8 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 90:cb3d968589d8 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
Kojto 90:cb3d968589d8 451
Kojto 90:cb3d968589d8 452 /* SysTick Reload Register Definitions */
Kojto 90:cb3d968589d8 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 90:cb3d968589d8 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
Kojto 90:cb3d968589d8 455
Kojto 90:cb3d968589d8 456 /* SysTick Current Register Definitions */
Kojto 90:cb3d968589d8 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 90:cb3d968589d8 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
Kojto 90:cb3d968589d8 459
Kojto 90:cb3d968589d8 460 /* SysTick Calibration Register Definitions */
Kojto 90:cb3d968589d8 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
Kojto 90:cb3d968589d8 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
Kojto 90:cb3d968589d8 463
Kojto 90:cb3d968589d8 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
Kojto 90:cb3d968589d8 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
Kojto 90:cb3d968589d8 466
Kojto 90:cb3d968589d8 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 90:cb3d968589d8 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
Kojto 90:cb3d968589d8 469
Kojto 90:cb3d968589d8 470 /*@} end of group CMSIS_SysTick */
Kojto 90:cb3d968589d8 471
Kojto 90:cb3d968589d8 472 #if (__MPU_PRESENT == 1)
Kojto 90:cb3d968589d8 473 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto 90:cb3d968589d8 475 \brief Type definitions for the Memory Protection Unit (MPU)
Kojto 90:cb3d968589d8 476 @{
Kojto 90:cb3d968589d8 477 */
Kojto 90:cb3d968589d8 478
Kojto 90:cb3d968589d8 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto 90:cb3d968589d8 480 */
Kojto 90:cb3d968589d8 481 typedef struct
Kojto 90:cb3d968589d8 482 {
Kojto 90:cb3d968589d8 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
Kojto 90:cb3d968589d8 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
Kojto 90:cb3d968589d8 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
Kojto 90:cb3d968589d8 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
Kojto 90:cb3d968589d8 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
Kojto 90:cb3d968589d8 488 } MPU_Type;
Kojto 90:cb3d968589d8 489
Kojto 90:cb3d968589d8 490 /* MPU Type Register */
Kojto 90:cb3d968589d8 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
Kojto 90:cb3d968589d8 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
Kojto 90:cb3d968589d8 493
Kojto 90:cb3d968589d8 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
Kojto 90:cb3d968589d8 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
Kojto 90:cb3d968589d8 496
Kojto 90:cb3d968589d8 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
Kojto 90:cb3d968589d8 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
Kojto 90:cb3d968589d8 499
Kojto 90:cb3d968589d8 500 /* MPU Control Register */
Kojto 90:cb3d968589d8 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
Kojto 90:cb3d968589d8 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
Kojto 90:cb3d968589d8 503
Kojto 90:cb3d968589d8 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
Kojto 90:cb3d968589d8 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
Kojto 90:cb3d968589d8 506
Kojto 90:cb3d968589d8 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
Kojto 90:cb3d968589d8 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
Kojto 90:cb3d968589d8 509
Kojto 90:cb3d968589d8 510 /* MPU Region Number Register */
Kojto 90:cb3d968589d8 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
Kojto 90:cb3d968589d8 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
Kojto 90:cb3d968589d8 513
Kojto 90:cb3d968589d8 514 /* MPU Region Base Address Register */
Kojto 90:cb3d968589d8 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
Kojto 90:cb3d968589d8 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
Kojto 90:cb3d968589d8 517
Kojto 90:cb3d968589d8 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
Kojto 90:cb3d968589d8 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
Kojto 90:cb3d968589d8 520
Kojto 90:cb3d968589d8 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
Kojto 90:cb3d968589d8 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
Kojto 90:cb3d968589d8 523
Kojto 90:cb3d968589d8 524 /* MPU Region Attribute and Size Register */
Kojto 90:cb3d968589d8 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
Kojto 90:cb3d968589d8 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
Kojto 90:cb3d968589d8 527
Kojto 90:cb3d968589d8 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
Kojto 90:cb3d968589d8 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
Kojto 90:cb3d968589d8 530
Kojto 90:cb3d968589d8 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
Kojto 90:cb3d968589d8 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
Kojto 90:cb3d968589d8 533
Kojto 90:cb3d968589d8 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
Kojto 90:cb3d968589d8 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
Kojto 90:cb3d968589d8 536
Kojto 90:cb3d968589d8 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
Kojto 90:cb3d968589d8 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
Kojto 90:cb3d968589d8 539
Kojto 90:cb3d968589d8 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
Kojto 90:cb3d968589d8 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
Kojto 90:cb3d968589d8 542
Kojto 90:cb3d968589d8 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
Kojto 90:cb3d968589d8 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
Kojto 90:cb3d968589d8 545
Kojto 90:cb3d968589d8 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
Kojto 90:cb3d968589d8 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
Kojto 90:cb3d968589d8 548
Kojto 90:cb3d968589d8 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
Kojto 90:cb3d968589d8 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
Kojto 90:cb3d968589d8 551
Kojto 90:cb3d968589d8 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
Kojto 90:cb3d968589d8 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
Kojto 90:cb3d968589d8 554
Kojto 90:cb3d968589d8 555 /*@} end of group CMSIS_MPU */
Kojto 90:cb3d968589d8 556 #endif
Kojto 90:cb3d968589d8 557
Kojto 90:cb3d968589d8 558
Kojto 90:cb3d968589d8 559 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto 90:cb3d968589d8 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
Kojto 90:cb3d968589d8 562 are only accessible over DAP and not via processor. Therefore
Kojto 90:cb3d968589d8 563 they are not covered by the Cortex-M0 header file.
Kojto 90:cb3d968589d8 564 @{
Kojto 90:cb3d968589d8 565 */
Kojto 90:cb3d968589d8 566 /*@} end of group CMSIS_CoreDebug */
Kojto 90:cb3d968589d8 567
Kojto 90:cb3d968589d8 568
Kojto 90:cb3d968589d8 569 /** \ingroup CMSIS_core_register
Kojto 90:cb3d968589d8 570 \defgroup CMSIS_core_base Core Definitions
Kojto 90:cb3d968589d8 571 \brief Definitions for base addresses, unions, and structures.
Kojto 90:cb3d968589d8 572 @{
Kojto 90:cb3d968589d8 573 */
Kojto 90:cb3d968589d8 574
Kojto 90:cb3d968589d8 575 /* Memory mapping of Cortex-M0+ Hardware */
Kojto 90:cb3d968589d8 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
Kojto 90:cb3d968589d8 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
Kojto 90:cb3d968589d8 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
Kojto 90:cb3d968589d8 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
Kojto 90:cb3d968589d8 580
Kojto 90:cb3d968589d8 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
Kojto 90:cb3d968589d8 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
Kojto 90:cb3d968589d8 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
Kojto 90:cb3d968589d8 584
Kojto 90:cb3d968589d8 585 #if (__MPU_PRESENT == 1)
Kojto 90:cb3d968589d8 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
Kojto 90:cb3d968589d8 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
Kojto 90:cb3d968589d8 588 #endif
Kojto 90:cb3d968589d8 589
Kojto 90:cb3d968589d8 590 /*@} */
Kojto 90:cb3d968589d8 591
Kojto 90:cb3d968589d8 592
Kojto 90:cb3d968589d8 593
Kojto 90:cb3d968589d8 594 /*******************************************************************************
Kojto 90:cb3d968589d8 595 * Hardware Abstraction Layer
Kojto 90:cb3d968589d8 596 Core Function Interface contains:
Kojto 90:cb3d968589d8 597 - Core NVIC Functions
Kojto 90:cb3d968589d8 598 - Core SysTick Functions
Kojto 90:cb3d968589d8 599 - Core Register Access Functions
Kojto 90:cb3d968589d8 600 ******************************************************************************/
Kojto 90:cb3d968589d8 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto 90:cb3d968589d8 602 */
Kojto 90:cb3d968589d8 603
Kojto 90:cb3d968589d8 604
Kojto 90:cb3d968589d8 605
Kojto 90:cb3d968589d8 606 /* ########################## NVIC functions #################################### */
Kojto 90:cb3d968589d8 607 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 90:cb3d968589d8 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto 90:cb3d968589d8 609 \brief Functions that manage interrupts and exceptions via the NVIC.
Kojto 90:cb3d968589d8 610 @{
Kojto 90:cb3d968589d8 611 */
Kojto 90:cb3d968589d8 612
Kojto 90:cb3d968589d8 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
Kojto 90:cb3d968589d8 614 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 90:cb3d968589d8 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
Kojto 90:cb3d968589d8 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
Kojto 90:cb3d968589d8 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
Kojto 90:cb3d968589d8 618
Kojto 90:cb3d968589d8 619
Kojto 90:cb3d968589d8 620 /** \brief Enable External Interrupt
Kojto 90:cb3d968589d8 621
Kojto 90:cb3d968589d8 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto 90:cb3d968589d8 623
Kojto 90:cb3d968589d8 624 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 90:cb3d968589d8 625 */
Kojto 90:cb3d968589d8 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 627 {
Kojto 90:cb3d968589d8 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 90:cb3d968589d8 629 }
Kojto 90:cb3d968589d8 630
Kojto 90:cb3d968589d8 631
Kojto 90:cb3d968589d8 632 /** \brief Disable External Interrupt
Kojto 90:cb3d968589d8 633
Kojto 90:cb3d968589d8 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto 90:cb3d968589d8 635
Kojto 90:cb3d968589d8 636 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 90:cb3d968589d8 637 */
Kojto 90:cb3d968589d8 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 639 {
Kojto 90:cb3d968589d8 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 90:cb3d968589d8 641 }
Kojto 90:cb3d968589d8 642
Kojto 90:cb3d968589d8 643
Kojto 90:cb3d968589d8 644 /** \brief Get Pending Interrupt
Kojto 90:cb3d968589d8 645
Kojto 90:cb3d968589d8 646 The function reads the pending register in the NVIC and returns the pending bit
Kojto 90:cb3d968589d8 647 for the specified interrupt.
Kojto 90:cb3d968589d8 648
Kojto 90:cb3d968589d8 649 \param [in] IRQn Interrupt number.
Kojto 90:cb3d968589d8 650
Kojto 90:cb3d968589d8 651 \return 0 Interrupt status is not pending.
Kojto 90:cb3d968589d8 652 \return 1 Interrupt status is pending.
Kojto 90:cb3d968589d8 653 */
Kojto 90:cb3d968589d8 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 655 {
Kojto 90:cb3d968589d8 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
Kojto 90:cb3d968589d8 657 }
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659
Kojto 90:cb3d968589d8 660 /** \brief Set Pending Interrupt
Kojto 90:cb3d968589d8 661
Kojto 90:cb3d968589d8 662 The function sets the pending bit of an external interrupt.
Kojto 90:cb3d968589d8 663
Kojto 90:cb3d968589d8 664 \param [in] IRQn Interrupt number. Value cannot be negative.
Kojto 90:cb3d968589d8 665 */
Kojto 90:cb3d968589d8 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 667 {
Kojto 90:cb3d968589d8 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
Kojto 90:cb3d968589d8 669 }
Kojto 90:cb3d968589d8 670
Kojto 90:cb3d968589d8 671
Kojto 90:cb3d968589d8 672 /** \brief Clear Pending Interrupt
Kojto 90:cb3d968589d8 673
Kojto 90:cb3d968589d8 674 The function clears the pending bit of an external interrupt.
Kojto 90:cb3d968589d8 675
Kojto 90:cb3d968589d8 676 \param [in] IRQn External interrupt number. Value cannot be negative.
Kojto 90:cb3d968589d8 677 */
Kojto 90:cb3d968589d8 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 679 {
Kojto 90:cb3d968589d8 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto 90:cb3d968589d8 681 }
Kojto 90:cb3d968589d8 682
Kojto 90:cb3d968589d8 683
Kojto 90:cb3d968589d8 684 /** \brief Set Interrupt Priority
Kojto 90:cb3d968589d8 685
Kojto 90:cb3d968589d8 686 The function sets the priority of an interrupt.
Kojto 90:cb3d968589d8 687
Kojto 90:cb3d968589d8 688 \note The priority cannot be set for every core interrupt.
Kojto 90:cb3d968589d8 689
Kojto 90:cb3d968589d8 690 \param [in] IRQn Interrupt number.
Kojto 90:cb3d968589d8 691 \param [in] priority Priority to set.
Kojto 90:cb3d968589d8 692 */
Kojto 90:cb3d968589d8 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto 90:cb3d968589d8 694 {
Kojto 90:cb3d968589d8 695 if(IRQn < 0) {
Kojto 90:cb3d968589d8 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 90:cb3d968589d8 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 90:cb3d968589d8 698 else {
Kojto 90:cb3d968589d8 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
Kojto 90:cb3d968589d8 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
Kojto 90:cb3d968589d8 701 }
Kojto 90:cb3d968589d8 702
Kojto 90:cb3d968589d8 703
Kojto 90:cb3d968589d8 704 /** \brief Get Interrupt Priority
Kojto 90:cb3d968589d8 705
Kojto 90:cb3d968589d8 706 The function reads the priority of an interrupt. The interrupt
Kojto 90:cb3d968589d8 707 number can be positive to specify an external (device specific)
Kojto 90:cb3d968589d8 708 interrupt, or negative to specify an internal (core) interrupt.
Kojto 90:cb3d968589d8 709
Kojto 90:cb3d968589d8 710
Kojto 90:cb3d968589d8 711 \param [in] IRQn Interrupt number.
Kojto 90:cb3d968589d8 712 \return Interrupt Priority. Value is aligned automatically to the implemented
Kojto 90:cb3d968589d8 713 priority bits of the microcontroller.
Kojto 90:cb3d968589d8 714 */
Kojto 90:cb3d968589d8 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto 90:cb3d968589d8 716 {
Kojto 90:cb3d968589d8 717
Kojto 90:cb3d968589d8 718 if(IRQn < 0) {
Kojto 90:cb3d968589d8 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
Kojto 90:cb3d968589d8 720 else {
Kojto 90:cb3d968589d8 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto 90:cb3d968589d8 722 }
Kojto 90:cb3d968589d8 723
Kojto 90:cb3d968589d8 724
Kojto 90:cb3d968589d8 725 /** \brief System Reset
Kojto 90:cb3d968589d8 726
Kojto 90:cb3d968589d8 727 The function initiates a system reset request to reset the MCU.
Kojto 90:cb3d968589d8 728 */
Kojto 90:cb3d968589d8 729 __STATIC_INLINE void NVIC_SystemReset(void)
Kojto 90:cb3d968589d8 730 {
Kojto 90:cb3d968589d8 731 __DSB(); /* Ensure all outstanding memory accesses included
Kojto 90:cb3d968589d8 732 buffered write are completed before reset */
Kojto 90:cb3d968589d8 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
Kojto 90:cb3d968589d8 734 SCB_AIRCR_SYSRESETREQ_Msk);
Kojto 90:cb3d968589d8 735 __DSB(); /* Ensure completion of memory access */
Kojto 90:cb3d968589d8 736 while(1); /* wait until reset */
Kojto 90:cb3d968589d8 737 }
Kojto 90:cb3d968589d8 738
Kojto 90:cb3d968589d8 739 /*@} end of CMSIS_Core_NVICFunctions */
Kojto 90:cb3d968589d8 740
Kojto 90:cb3d968589d8 741
Kojto 90:cb3d968589d8 742
Kojto 90:cb3d968589d8 743 /* ################################## SysTick function ############################################ */
Kojto 90:cb3d968589d8 744 /** \ingroup CMSIS_Core_FunctionInterface
Kojto 90:cb3d968589d8 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto 90:cb3d968589d8 746 \brief Functions that configure the System.
Kojto 90:cb3d968589d8 747 @{
Kojto 90:cb3d968589d8 748 */
Kojto 90:cb3d968589d8 749
Kojto 90:cb3d968589d8 750 #if (__Vendor_SysTickConfig == 0)
Kojto 90:cb3d968589d8 751
Kojto 90:cb3d968589d8 752 /** \brief System Tick Configuration
Kojto 90:cb3d968589d8 753
Kojto 90:cb3d968589d8 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto 90:cb3d968589d8 755 Counter is in free running mode to generate periodic interrupts.
Kojto 90:cb3d968589d8 756
Kojto 90:cb3d968589d8 757 \param [in] ticks Number of ticks between two interrupts.
Kojto 90:cb3d968589d8 758
Kojto 90:cb3d968589d8 759 \return 0 Function succeeded.
Kojto 90:cb3d968589d8 760 \return 1 Function failed.
Kojto 90:cb3d968589d8 761
Kojto 90:cb3d968589d8 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto 90:cb3d968589d8 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto 90:cb3d968589d8 764 must contain a vendor-specific implementation of this function.
Kojto 90:cb3d968589d8 765
Kojto 90:cb3d968589d8 766 */
Kojto 90:cb3d968589d8 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto 90:cb3d968589d8 768 {
Kojto 90:cb3d968589d8 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto 90:cb3d968589d8 770
Kojto 90:cb3d968589d8 771 SysTick->LOAD = ticks - 1; /* set reload register */
Kojto 90:cb3d968589d8 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto 90:cb3d968589d8 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto 90:cb3d968589d8 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
Kojto 90:cb3d968589d8 775 SysTick_CTRL_TICKINT_Msk |
Kojto 90:cb3d968589d8 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 90:cb3d968589d8 777 return (0); /* Function successful */
Kojto 90:cb3d968589d8 778 }
Kojto 90:cb3d968589d8 779
Kojto 90:cb3d968589d8 780 #endif
Kojto 90:cb3d968589d8 781
Kojto 90:cb3d968589d8 782 /*@} end of CMSIS_Core_SysTickFunctions */
Kojto 90:cb3d968589d8 783
Kojto 90:cb3d968589d8 784
Kojto 90:cb3d968589d8 785
Kojto 90:cb3d968589d8 786
Kojto 90:cb3d968589d8 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
Kojto 90:cb3d968589d8 788
Kojto 90:cb3d968589d8 789 #endif /* __CMSIS_GENERIC */
Kojto 90:cb3d968589d8 790
Kojto 90:cb3d968589d8 791 #ifdef __cplusplus
Kojto 90:cb3d968589d8 792 }
Kojto 90:cb3d968589d8 793 #endif