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TARGET_LPC824/core_cm3.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:: Kojto
Date:: Tue Oct 28 16:40:41 2014 +0000
Revision:: 90:cb3d968589d8

Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/************************************************************************//
Kojto	90:cb3d968589d8	2	* @file core_cm3.h
Kojto	90:cb3d968589d8	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Kojto	90:cb3d968589d8	4	* @version V3.20
Kojto	90:cb3d968589d8	5	* @date 25. February 2013
Kojto	90:cb3d968589d8	6	*
Kojto	90:cb3d968589d8	7	* @note
Kojto	90:cb3d968589d8	8	*
Kojto	90:cb3d968589d8	9	******************************************************************************/
Kojto	90:cb3d968589d8	10	/* Copyright (c) 2009 - 2013 ARM LIMITED
Kojto	90:cb3d968589d8	11
Kojto	90:cb3d968589d8	12	All rights reserved.
Kojto	90:cb3d968589d8	13	Redistribution and use in source and binary forms, with or without
Kojto	90:cb3d968589d8	14	modification, are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	15	- Redistributions of source code must retain the above copyright
Kojto	90:cb3d968589d8	16	notice, this list of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	17	- Redistributions in binary form must reproduce the above copyright
Kojto	90:cb3d968589d8	18	notice, this list of conditions and the following disclaimer in the
Kojto	90:cb3d968589d8	19	documentation and/or other materials provided with the distribution.
Kojto	90:cb3d968589d8	20	- Neither the name of ARM nor the names of its contributors may be used
Kojto	90:cb3d968589d8	21	to endorse or promote products derived from this software without
Kojto	90:cb3d968589d8	22	specific prior written permission.
Kojto	90:cb3d968589d8	23	*
Kojto	90:cb3d968589d8	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	90:cb3d968589d8	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	90:cb3d968589d8	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
Kojto	90:cb3d968589d8	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
Kojto	90:cb3d968589d8	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
Kojto	90:cb3d968589d8	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
Kojto	90:cb3d968589d8	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
Kojto	90:cb3d968589d8	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
Kojto	90:cb3d968589d8	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
Kojto	90:cb3d968589d8	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto	90:cb3d968589d8	34	POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	35	---------------------------------------------------------------------------*/
Kojto	90:cb3d968589d8	36
Kojto	90:cb3d968589d8	37
Kojto	90:cb3d968589d8	38	#if defined ( __ICCARM__ )
Kojto	90:cb3d968589d8	39	#pragma system_include /* treat file as system include file for MISRA check */
Kojto	90:cb3d968589d8	40	#endif
Kojto	90:cb3d968589d8	41
Kojto	90:cb3d968589d8	42	#ifdef __cplusplus
Kojto	90:cb3d968589d8	43	extern "C" {
Kojto	90:cb3d968589d8	44	#endif
Kojto	90:cb3d968589d8	45
Kojto	90:cb3d968589d8	46	#ifndef __CORE_CM3_H_GENERIC
Kojto	90:cb3d968589d8	47	#define __CORE_CM3_H_GENERIC
Kojto	90:cb3d968589d8	48
Kojto	90:cb3d968589d8	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Kojto	90:cb3d968589d8	50	CMSIS violates the following MISRA-C:2004 rules:
Kojto	90:cb3d968589d8	51
Kojto	90:cb3d968589d8	52	\li Required Rule 8.5, object/function definition in header file.<br>
Kojto	90:cb3d968589d8	53	Function definitions in header files are used to allow 'inlining'.
Kojto	90:cb3d968589d8	54
Kojto	90:cb3d968589d8	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Kojto	90:cb3d968589d8	56	Unions are used for effective representation of core registers.
Kojto	90:cb3d968589d8	57
Kojto	90:cb3d968589d8	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
Kojto	90:cb3d968589d8	59	Function-like macros are used to allow more efficient code.
Kojto	90:cb3d968589d8	60	*/
Kojto	90:cb3d968589d8	61
Kojto	90:cb3d968589d8	62
Kojto	90:cb3d968589d8	63	/*******************************************************************************
Kojto	90:cb3d968589d8	64	* CMSIS definitions
Kojto	90:cb3d968589d8	65	******************************************************************************/
Kojto	90:cb3d968589d8	66	/** \ingroup Cortex_M3
Kojto	90:cb3d968589d8	67	@{
Kojto	90:cb3d968589d8	68	*/
Kojto	90:cb3d968589d8	69
Kojto	90:cb3d968589d8	70	/* CMSIS CM3 definitions */
Kojto	90:cb3d968589d8	71	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
Kojto	90:cb3d968589d8	72	#define __CM3_CMSIS_VERSION_SUB (0x20) /!< [15:0] CMSIS HAL sub version /
Kojto	90:cb3d968589d8	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
Kojto	90:cb3d968589d8	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Kojto	90:cb3d968589d8	75
Kojto	90:cb3d968589d8	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
Kojto	90:cb3d968589d8	77
Kojto	90:cb3d968589d8	78
Kojto	90:cb3d968589d8	79	#if defined ( __CC_ARM )
Kojto	90:cb3d968589d8	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
Kojto	90:cb3d968589d8	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Kojto	90:cb3d968589d8	82	#define __STATIC_INLINE static __inline
Kojto	90:cb3d968589d8	83
Kojto	90:cb3d968589d8	84	#elif defined ( __ICCARM__ )
Kojto	90:cb3d968589d8	85	#define __ASM __asm /!< asm keyword for IAR Compiler /
Kojto	90:cb3d968589d8	86	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Kojto	90:cb3d968589d8	87	#define __STATIC_INLINE static inline
Kojto	90:cb3d968589d8	88
Kojto	90:cb3d968589d8	89	#elif defined ( __TMS470__ )
Kojto	90:cb3d968589d8	90	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Kojto	90:cb3d968589d8	91	#define __STATIC_INLINE static inline
Kojto	90:cb3d968589d8	92
Kojto	90:cb3d968589d8	93	#elif defined ( __GNUC__ )
Kojto	90:cb3d968589d8	94	#define __ASM __asm /!< asm keyword for GNU Compiler /
Kojto	90:cb3d968589d8	95	#define __INLINE inline /!< inline keyword for GNU Compiler /
Kojto	90:cb3d968589d8	96	#define __STATIC_INLINE static inline
Kojto	90:cb3d968589d8	97
Kojto	90:cb3d968589d8	98	#elif defined ( __TASKING__ )
Kojto	90:cb3d968589d8	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Kojto	90:cb3d968589d8	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Kojto	90:cb3d968589d8	101	#define __STATIC_INLINE static inline
Kojto	90:cb3d968589d8	102
Kojto	90:cb3d968589d8	103	#endif
Kojto	90:cb3d968589d8	104
Kojto	90:cb3d968589d8	105	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Kojto	90:cb3d968589d8	106	*/
Kojto	90:cb3d968589d8	107	#define __FPU_USED 0
Kojto	90:cb3d968589d8	108
Kojto	90:cb3d968589d8	109	#if defined ( __CC_ARM )
Kojto	90:cb3d968589d8	110	#if defined __TARGET_FPU_VFP
Kojto	90:cb3d968589d8	111	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	90:cb3d968589d8	112	#endif
Kojto	90:cb3d968589d8	113
Kojto	90:cb3d968589d8	114	#elif defined ( __ICCARM__ )
Kojto	90:cb3d968589d8	115	#if defined __ARMVFP__
Kojto	90:cb3d968589d8	116	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	90:cb3d968589d8	117	#endif
Kojto	90:cb3d968589d8	118
Kojto	90:cb3d968589d8	119	#elif defined ( __TMS470__ )
Kojto	90:cb3d968589d8	120	#if defined __TI__VFP_SUPPORT____
Kojto	90:cb3d968589d8	121	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	90:cb3d968589d8	122	#endif
Kojto	90:cb3d968589d8	123
Kojto	90:cb3d968589d8	124	#elif defined ( __GNUC__ )
Kojto	90:cb3d968589d8	125	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto	90:cb3d968589d8	126	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	90:cb3d968589d8	127	#endif
Kojto	90:cb3d968589d8	128
Kojto	90:cb3d968589d8	129	#elif defined ( __TASKING__ )
Kojto	90:cb3d968589d8	130	#if defined __FPU_VFP__
Kojto	90:cb3d968589d8	131	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto	90:cb3d968589d8	132	#endif
Kojto	90:cb3d968589d8	133	#endif
Kojto	90:cb3d968589d8	134
Kojto	90:cb3d968589d8	135	#include <stdint.h> /* standard types definitions */
Kojto	90:cb3d968589d8	136	#include <core_cmInstr.h> /* Core Instruction Access */
Kojto	90:cb3d968589d8	137	#include <core_cmFunc.h> /* Core Function Access */
Kojto	90:cb3d968589d8	138
Kojto	90:cb3d968589d8	139	#endif /* __CORE_CM3_H_GENERIC */
Kojto	90:cb3d968589d8	140
Kojto	90:cb3d968589d8	141	#ifndef __CMSIS_GENERIC
Kojto	90:cb3d968589d8	142
Kojto	90:cb3d968589d8	143	#ifndef __CORE_CM3_H_DEPENDANT
Kojto	90:cb3d968589d8	144	#define __CORE_CM3_H_DEPENDANT
Kojto	90:cb3d968589d8	145
Kojto	90:cb3d968589d8	146	/* check device defines and use defaults */
Kojto	90:cb3d968589d8	147	#if defined __CHECK_DEVICE_DEFINES
Kojto	90:cb3d968589d8	148	#ifndef __CM3_REV
Kojto	90:cb3d968589d8	149	#define __CM3_REV 0x0200
Kojto	90:cb3d968589d8	150	#warning "__CM3_REV not defined in device header file; using default!"
Kojto	90:cb3d968589d8	151	#endif
Kojto	90:cb3d968589d8	152
Kojto	90:cb3d968589d8	153	#ifndef __MPU_PRESENT
Kojto	90:cb3d968589d8	154	#define __MPU_PRESENT 0
Kojto	90:cb3d968589d8	155	#warning "__MPU_PRESENT not defined in device header file; using default!"
Kojto	90:cb3d968589d8	156	#endif
Kojto	90:cb3d968589d8	157
Kojto	90:cb3d968589d8	158	#ifndef __NVIC_PRIO_BITS
Kojto	90:cb3d968589d8	159	#define __NVIC_PRIO_BITS 4
Kojto	90:cb3d968589d8	160	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Kojto	90:cb3d968589d8	161	#endif
Kojto	90:cb3d968589d8	162
Kojto	90:cb3d968589d8	163	#ifndef __Vendor_SysTickConfig
Kojto	90:cb3d968589d8	164	#define __Vendor_SysTickConfig 0
Kojto	90:cb3d968589d8	165	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Kojto	90:cb3d968589d8	166	#endif
Kojto	90:cb3d968589d8	167	#endif
Kojto	90:cb3d968589d8	168
Kojto	90:cb3d968589d8	169	/* IO definitions (access restrictions to peripheral registers) */
Kojto	90:cb3d968589d8	170	/**
Kojto	90:cb3d968589d8	171	\defgroup CMSIS_glob_defs CMSIS Global Defines
Kojto	90:cb3d968589d8	172
Kojto	90:cb3d968589d8	173	<strong>IO Type Qualifiers</strong> are used
Kojto	90:cb3d968589d8	174	\li to specify the access to peripheral variables.
Kojto	90:cb3d968589d8	175	\li for automatic generation of peripheral register debug information.
Kojto	90:cb3d968589d8	176	*/
Kojto	90:cb3d968589d8	177	#ifdef __cplusplus
Kojto	90:cb3d968589d8	178	#define __I volatile /!< Defines 'read only' permissions /
Kojto	90:cb3d968589d8	179	#else
Kojto	90:cb3d968589d8	180	#define __I volatile const /!< Defines 'read only' permissions /
Kojto	90:cb3d968589d8	181	#endif
Kojto	90:cb3d968589d8	182	#define __O volatile /!< Defines 'write only' permissions /
Kojto	90:cb3d968589d8	183	#define __IO volatile /!< Defines 'read / write' permissions /
Kojto	90:cb3d968589d8	184
Kojto	90:cb3d968589d8	185	/@} end of group Cortex_M3 /
Kojto	90:cb3d968589d8	186
Kojto	90:cb3d968589d8	187
Kojto	90:cb3d968589d8	188
Kojto	90:cb3d968589d8	189	/*******************************************************************************
Kojto	90:cb3d968589d8	190	* Register Abstraction
Kojto	90:cb3d968589d8	191	Core Register contain:
Kojto	90:cb3d968589d8	192	- Core Register
Kojto	90:cb3d968589d8	193	- Core NVIC Register
Kojto	90:cb3d968589d8	194	- Core SCB Register
Kojto	90:cb3d968589d8	195	- Core SysTick Register
Kojto	90:cb3d968589d8	196	- Core Debug Register
Kojto	90:cb3d968589d8	197	- Core MPU Register
Kojto	90:cb3d968589d8	198	******************************************************************************/
Kojto	90:cb3d968589d8	199	/** \defgroup CMSIS_core_register Defines and Type Definitions
Kojto	90:cb3d968589d8	200	\brief Type definitions and defines for Cortex-M processor based devices.
Kojto	90:cb3d968589d8	201	*/
Kojto	90:cb3d968589d8	202
Kojto	90:cb3d968589d8	203	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	204	\defgroup CMSIS_CORE Status and Control Registers
Kojto	90:cb3d968589d8	205	\brief Core Register type definitions.
Kojto	90:cb3d968589d8	206	@{
Kojto	90:cb3d968589d8	207	*/
Kojto	90:cb3d968589d8	208
Kojto	90:cb3d968589d8	209	/** \brief Union type to access the Application Program Status Register (APSR).
Kojto	90:cb3d968589d8	210	*/
Kojto	90:cb3d968589d8	211	typedef union
Kojto	90:cb3d968589d8	212	{
Kojto	90:cb3d968589d8	213	struct
Kojto	90:cb3d968589d8	214	{
Kojto	90:cb3d968589d8	215	#if (__CORTEX_M != 0x04)
Kojto	90:cb3d968589d8	216	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
Kojto	90:cb3d968589d8	217	#else
Kojto	90:cb3d968589d8	218	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Kojto	90:cb3d968589d8	219	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	90:cb3d968589d8	220	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Kojto	90:cb3d968589d8	221	#endif
Kojto	90:cb3d968589d8	222	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	90:cb3d968589d8	223	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	90:cb3d968589d8	224	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	90:cb3d968589d8	225	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	90:cb3d968589d8	226	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	90:cb3d968589d8	227	} b; /!< Structure used for bit access /
Kojto	90:cb3d968589d8	228	uint32_t w; /!< Type used for word access /
Kojto	90:cb3d968589d8	229	} APSR_Type;
Kojto	90:cb3d968589d8	230
Kojto	90:cb3d968589d8	231
Kojto	90:cb3d968589d8	232	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Kojto	90:cb3d968589d8	233	*/
Kojto	90:cb3d968589d8	234	typedef union
Kojto	90:cb3d968589d8	235	{
Kojto	90:cb3d968589d8	236	struct
Kojto	90:cb3d968589d8	237	{
Kojto	90:cb3d968589d8	238	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	90:cb3d968589d8	239	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Kojto	90:cb3d968589d8	240	} b; /!< Structure used for bit access /
Kojto	90:cb3d968589d8	241	uint32_t w; /!< Type used for word access /
Kojto	90:cb3d968589d8	242	} IPSR_Type;
Kojto	90:cb3d968589d8	243
Kojto	90:cb3d968589d8	244
Kojto	90:cb3d968589d8	245	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Kojto	90:cb3d968589d8	246	*/
Kojto	90:cb3d968589d8	247	typedef union
Kojto	90:cb3d968589d8	248	{
Kojto	90:cb3d968589d8	249	struct
Kojto	90:cb3d968589d8	250	{
Kojto	90:cb3d968589d8	251	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Kojto	90:cb3d968589d8	252	#if (__CORTEX_M != 0x04)
Kojto	90:cb3d968589d8	253	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
Kojto	90:cb3d968589d8	254	#else
Kojto	90:cb3d968589d8	255	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Kojto	90:cb3d968589d8	256	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Kojto	90:cb3d968589d8	257	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Kojto	90:cb3d968589d8	258	#endif
Kojto	90:cb3d968589d8	259	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Kojto	90:cb3d968589d8	260	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Kojto	90:cb3d968589d8	261	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Kojto	90:cb3d968589d8	262	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Kojto	90:cb3d968589d8	263	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Kojto	90:cb3d968589d8	264	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Kojto	90:cb3d968589d8	265	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Kojto	90:cb3d968589d8	266	} b; /!< Structure used for bit access /
Kojto	90:cb3d968589d8	267	uint32_t w; /!< Type used for word access /
Kojto	90:cb3d968589d8	268	} xPSR_Type;
Kojto	90:cb3d968589d8	269
Kojto	90:cb3d968589d8	270
Kojto	90:cb3d968589d8	271	/** \brief Union type to access the Control Registers (CONTROL).
Kojto	90:cb3d968589d8	272	*/
Kojto	90:cb3d968589d8	273	typedef union
Kojto	90:cb3d968589d8	274	{
Kojto	90:cb3d968589d8	275	struct
Kojto	90:cb3d968589d8	276	{
Kojto	90:cb3d968589d8	277	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Kojto	90:cb3d968589d8	278	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Kojto	90:cb3d968589d8	279	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Kojto	90:cb3d968589d8	280	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Kojto	90:cb3d968589d8	281	} b; /!< Structure used for bit access /
Kojto	90:cb3d968589d8	282	uint32_t w; /!< Type used for word access /
Kojto	90:cb3d968589d8	283	} CONTROL_Type;
Kojto	90:cb3d968589d8	284
Kojto	90:cb3d968589d8	285	/@} end of group CMSIS_CORE /
Kojto	90:cb3d968589d8	286
Kojto	90:cb3d968589d8	287
Kojto	90:cb3d968589d8	288	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	289	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Kojto	90:cb3d968589d8	290	\brief Type definitions for the NVIC Registers
Kojto	90:cb3d968589d8	291	@{
Kojto	90:cb3d968589d8	292	*/
Kojto	90:cb3d968589d8	293
Kojto	90:cb3d968589d8	294	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Kojto	90:cb3d968589d8	295	*/
Kojto	90:cb3d968589d8	296	typedef struct
Kojto	90:cb3d968589d8	297	{
Kojto	90:cb3d968589d8	298	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Kojto	90:cb3d968589d8	299	uint32_t RESERVED0[24];
Kojto	90:cb3d968589d8	300	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Kojto	90:cb3d968589d8	301	uint32_t RSERVED1[24];
Kojto	90:cb3d968589d8	302	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Kojto	90:cb3d968589d8	303	uint32_t RESERVED2[24];
Kojto	90:cb3d968589d8	304	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Kojto	90:cb3d968589d8	305	uint32_t RESERVED3[24];
Kojto	90:cb3d968589d8	306	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Kojto	90:cb3d968589d8	307	uint32_t RESERVED4[56];
Kojto	90:cb3d968589d8	308	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Kojto	90:cb3d968589d8	309	uint32_t RESERVED5[644];
Kojto	90:cb3d968589d8	310	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Kojto	90:cb3d968589d8	311	} NVIC_Type;
Kojto	90:cb3d968589d8	312
Kojto	90:cb3d968589d8	313	/* Software Triggered Interrupt Register Definitions */
Kojto	90:cb3d968589d8	314	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Kojto	90:cb3d968589d8	315	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
Kojto	90:cb3d968589d8	316
Kojto	90:cb3d968589d8	317	/@} end of group CMSIS_NVIC /
Kojto	90:cb3d968589d8	318
Kojto	90:cb3d968589d8	319
Kojto	90:cb3d968589d8	320	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	321	\defgroup CMSIS_SCB System Control Block (SCB)
Kojto	90:cb3d968589d8	322	\brief Type definitions for the System Control Block Registers
Kojto	90:cb3d968589d8	323	@{
Kojto	90:cb3d968589d8	324	*/
Kojto	90:cb3d968589d8	325
Kojto	90:cb3d968589d8	326	/** \brief Structure type to access the System Control Block (SCB).
Kojto	90:cb3d968589d8	327	*/
Kojto	90:cb3d968589d8	328	typedef struct
Kojto	90:cb3d968589d8	329	{
Kojto	90:cb3d968589d8	330	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Kojto	90:cb3d968589d8	331	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Kojto	90:cb3d968589d8	332	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Kojto	90:cb3d968589d8	333	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Kojto	90:cb3d968589d8	334	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Kojto	90:cb3d968589d8	335	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Kojto	90:cb3d968589d8	336	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Kojto	90:cb3d968589d8	337	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Kojto	90:cb3d968589d8	338	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Kojto	90:cb3d968589d8	339	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Kojto	90:cb3d968589d8	340	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Kojto	90:cb3d968589d8	341	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Kojto	90:cb3d968589d8	342	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Kojto	90:cb3d968589d8	343	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Kojto	90:cb3d968589d8	344	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Kojto	90:cb3d968589d8	345	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Kojto	90:cb3d968589d8	346	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Kojto	90:cb3d968589d8	347	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Kojto	90:cb3d968589d8	348	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Kojto	90:cb3d968589d8	349	uint32_t RESERVED0[5];
Kojto	90:cb3d968589d8	350	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Kojto	90:cb3d968589d8	351	} SCB_Type;
Kojto	90:cb3d968589d8	352
Kojto	90:cb3d968589d8	353	/* SCB CPUID Register Definitions */
Kojto	90:cb3d968589d8	354	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Kojto	90:cb3d968589d8	355	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Kojto	90:cb3d968589d8	356
Kojto	90:cb3d968589d8	357	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Kojto	90:cb3d968589d8	358	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Kojto	90:cb3d968589d8	359
Kojto	90:cb3d968589d8	360	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Kojto	90:cb3d968589d8	361	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Kojto	90:cb3d968589d8	362
Kojto	90:cb3d968589d8	363	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Kojto	90:cb3d968589d8	364	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Kojto	90:cb3d968589d8	365
Kojto	90:cb3d968589d8	366	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Kojto	90:cb3d968589d8	367	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
Kojto	90:cb3d968589d8	368
Kojto	90:cb3d968589d8	369	/* SCB Interrupt Control State Register Definitions */
Kojto	90:cb3d968589d8	370	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Kojto	90:cb3d968589d8	371	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Kojto	90:cb3d968589d8	372
Kojto	90:cb3d968589d8	373	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Kojto	90:cb3d968589d8	374	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Kojto	90:cb3d968589d8	375
Kojto	90:cb3d968589d8	376	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Kojto	90:cb3d968589d8	377	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Kojto	90:cb3d968589d8	378
Kojto	90:cb3d968589d8	379	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Kojto	90:cb3d968589d8	380	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Kojto	90:cb3d968589d8	381
Kojto	90:cb3d968589d8	382	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Kojto	90:cb3d968589d8	383	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Kojto	90:cb3d968589d8	384
Kojto	90:cb3d968589d8	385	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Kojto	90:cb3d968589d8	386	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Kojto	90:cb3d968589d8	387
Kojto	90:cb3d968589d8	388	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Kojto	90:cb3d968589d8	389	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Kojto	90:cb3d968589d8	390
Kojto	90:cb3d968589d8	391	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Kojto	90:cb3d968589d8	392	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Kojto	90:cb3d968589d8	393
Kojto	90:cb3d968589d8	394	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Kojto	90:cb3d968589d8	395	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Kojto	90:cb3d968589d8	396
Kojto	90:cb3d968589d8	397	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Kojto	90:cb3d968589d8	398	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
Kojto	90:cb3d968589d8	399
Kojto	90:cb3d968589d8	400	/* SCB Vector Table Offset Register Definitions */
Kojto	90:cb3d968589d8	401	#if (__CM3_REV < 0x0201) /* core r2p1 */
Kojto	90:cb3d968589d8	402	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
Kojto	90:cb3d968589d8	403	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
Kojto	90:cb3d968589d8	404
Kojto	90:cb3d968589d8	405	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Kojto	90:cb3d968589d8	406	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	90:cb3d968589d8	407	#else
Kojto	90:cb3d968589d8	408	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Kojto	90:cb3d968589d8	409	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Kojto	90:cb3d968589d8	410	#endif
Kojto	90:cb3d968589d8	411
Kojto	90:cb3d968589d8	412	/* SCB Application Interrupt and Reset Control Register Definitions */
Kojto	90:cb3d968589d8	413	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Kojto	90:cb3d968589d8	414	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Kojto	90:cb3d968589d8	415
Kojto	90:cb3d968589d8	416	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Kojto	90:cb3d968589d8	417	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Kojto	90:cb3d968589d8	418
Kojto	90:cb3d968589d8	419	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Kojto	90:cb3d968589d8	420	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Kojto	90:cb3d968589d8	421
Kojto	90:cb3d968589d8	422	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Kojto	90:cb3d968589d8	423	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Kojto	90:cb3d968589d8	424
Kojto	90:cb3d968589d8	425	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Kojto	90:cb3d968589d8	426	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Kojto	90:cb3d968589d8	427
Kojto	90:cb3d968589d8	428	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Kojto	90:cb3d968589d8	429	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Kojto	90:cb3d968589d8	430
Kojto	90:cb3d968589d8	431	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Kojto	90:cb3d968589d8	432	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
Kojto	90:cb3d968589d8	433
Kojto	90:cb3d968589d8	434	/* SCB System Control Register Definitions */
Kojto	90:cb3d968589d8	435	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Kojto	90:cb3d968589d8	436	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Kojto	90:cb3d968589d8	437
Kojto	90:cb3d968589d8	438	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Kojto	90:cb3d968589d8	439	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Kojto	90:cb3d968589d8	440
Kojto	90:cb3d968589d8	441	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Kojto	90:cb3d968589d8	442	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Kojto	90:cb3d968589d8	443
Kojto	90:cb3d968589d8	444	/* SCB Configuration Control Register Definitions */
Kojto	90:cb3d968589d8	445	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Kojto	90:cb3d968589d8	446	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Kojto	90:cb3d968589d8	447
Kojto	90:cb3d968589d8	448	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Kojto	90:cb3d968589d8	449	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Kojto	90:cb3d968589d8	450
Kojto	90:cb3d968589d8	451	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Kojto	90:cb3d968589d8	452	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Kojto	90:cb3d968589d8	453
Kojto	90:cb3d968589d8	454	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Kojto	90:cb3d968589d8	455	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Kojto	90:cb3d968589d8	456
Kojto	90:cb3d968589d8	457	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Kojto	90:cb3d968589d8	458	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Kojto	90:cb3d968589d8	459
Kojto	90:cb3d968589d8	460	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Kojto	90:cb3d968589d8	461	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
Kojto	90:cb3d968589d8	462
Kojto	90:cb3d968589d8	463	/* SCB System Handler Control and State Register Definitions */
Kojto	90:cb3d968589d8	464	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Kojto	90:cb3d968589d8	465	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Kojto	90:cb3d968589d8	466
Kojto	90:cb3d968589d8	467	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Kojto	90:cb3d968589d8	468	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Kojto	90:cb3d968589d8	469
Kojto	90:cb3d968589d8	470	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Kojto	90:cb3d968589d8	471	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Kojto	90:cb3d968589d8	472
Kojto	90:cb3d968589d8	473	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Kojto	90:cb3d968589d8	474	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Kojto	90:cb3d968589d8	475
Kojto	90:cb3d968589d8	476	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Kojto	90:cb3d968589d8	477	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Kojto	90:cb3d968589d8	478
Kojto	90:cb3d968589d8	479	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Kojto	90:cb3d968589d8	480	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Kojto	90:cb3d968589d8	481
Kojto	90:cb3d968589d8	482	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Kojto	90:cb3d968589d8	483	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Kojto	90:cb3d968589d8	484
Kojto	90:cb3d968589d8	485	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Kojto	90:cb3d968589d8	486	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Kojto	90:cb3d968589d8	487
Kojto	90:cb3d968589d8	488	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Kojto	90:cb3d968589d8	489	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Kojto	90:cb3d968589d8	490
Kojto	90:cb3d968589d8	491	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Kojto	90:cb3d968589d8	492	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Kojto	90:cb3d968589d8	493
Kojto	90:cb3d968589d8	494	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Kojto	90:cb3d968589d8	495	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Kojto	90:cb3d968589d8	496
Kojto	90:cb3d968589d8	497	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Kojto	90:cb3d968589d8	498	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Kojto	90:cb3d968589d8	499
Kojto	90:cb3d968589d8	500	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Kojto	90:cb3d968589d8	501	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Kojto	90:cb3d968589d8	502
Kojto	90:cb3d968589d8	503	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Kojto	90:cb3d968589d8	504	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
Kojto	90:cb3d968589d8	505
Kojto	90:cb3d968589d8	506	/* SCB Configurable Fault Status Registers Definitions */
Kojto	90:cb3d968589d8	507	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Kojto	90:cb3d968589d8	508	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Kojto	90:cb3d968589d8	509
Kojto	90:cb3d968589d8	510	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Kojto	90:cb3d968589d8	511	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Kojto	90:cb3d968589d8	512
Kojto	90:cb3d968589d8	513	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Kojto	90:cb3d968589d8	514	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Kojto	90:cb3d968589d8	515
Kojto	90:cb3d968589d8	516	/* SCB Hard Fault Status Registers Definitions */
Kojto	90:cb3d968589d8	517	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Kojto	90:cb3d968589d8	518	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Kojto	90:cb3d968589d8	519
Kojto	90:cb3d968589d8	520	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Kojto	90:cb3d968589d8	521	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Kojto	90:cb3d968589d8	522
Kojto	90:cb3d968589d8	523	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Kojto	90:cb3d968589d8	524	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Kojto	90:cb3d968589d8	525
Kojto	90:cb3d968589d8	526	/* SCB Debug Fault Status Register Definitions */
Kojto	90:cb3d968589d8	527	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Kojto	90:cb3d968589d8	528	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Kojto	90:cb3d968589d8	529
Kojto	90:cb3d968589d8	530	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Kojto	90:cb3d968589d8	531	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Kojto	90:cb3d968589d8	532
Kojto	90:cb3d968589d8	533	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Kojto	90:cb3d968589d8	534	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Kojto	90:cb3d968589d8	535
Kojto	90:cb3d968589d8	536	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Kojto	90:cb3d968589d8	537	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Kojto	90:cb3d968589d8	538
Kojto	90:cb3d968589d8	539	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Kojto	90:cb3d968589d8	540	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
Kojto	90:cb3d968589d8	541
Kojto	90:cb3d968589d8	542	/@} end of group CMSIS_SCB /
Kojto	90:cb3d968589d8	543
Kojto	90:cb3d968589d8	544
Kojto	90:cb3d968589d8	545	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	546	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Kojto	90:cb3d968589d8	547	\brief Type definitions for the System Control and ID Register not in the SCB
Kojto	90:cb3d968589d8	548	@{
Kojto	90:cb3d968589d8	549	*/
Kojto	90:cb3d968589d8	550
Kojto	90:cb3d968589d8	551	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Kojto	90:cb3d968589d8	552	*/
Kojto	90:cb3d968589d8	553	typedef struct
Kojto	90:cb3d968589d8	554	{
Kojto	90:cb3d968589d8	555	uint32_t RESERVED0[1];
Kojto	90:cb3d968589d8	556	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Kojto	90:cb3d968589d8	557	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Kojto	90:cb3d968589d8	558	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Kojto	90:cb3d968589d8	559	#else
Kojto	90:cb3d968589d8	560	uint32_t RESERVED1[1];
Kojto	90:cb3d968589d8	561	#endif
Kojto	90:cb3d968589d8	562	} SCnSCB_Type;
Kojto	90:cb3d968589d8	563
Kojto	90:cb3d968589d8	564	/* Interrupt Controller Type Register Definitions */
Kojto	90:cb3d968589d8	565	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Kojto	90:cb3d968589d8	566	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
Kojto	90:cb3d968589d8	567
Kojto	90:cb3d968589d8	568	/* Auxiliary Control Register Definitions */
Kojto	90:cb3d968589d8	569
Kojto	90:cb3d968589d8	570	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Kojto	90:cb3d968589d8	571	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Kojto	90:cb3d968589d8	572
Kojto	90:cb3d968589d8	573	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
Kojto	90:cb3d968589d8	574	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
Kojto	90:cb3d968589d8	575
Kojto	90:cb3d968589d8	576	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Kojto	90:cb3d968589d8	577	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
Kojto	90:cb3d968589d8	578
Kojto	90:cb3d968589d8	579	/@} end of group CMSIS_SCnotSCB /
Kojto	90:cb3d968589d8	580
Kojto	90:cb3d968589d8	581
Kojto	90:cb3d968589d8	582	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	583	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Kojto	90:cb3d968589d8	584	\brief Type definitions for the System Timer Registers.
Kojto	90:cb3d968589d8	585	@{
Kojto	90:cb3d968589d8	586	*/
Kojto	90:cb3d968589d8	587
Kojto	90:cb3d968589d8	588	/** \brief Structure type to access the System Timer (SysTick).
Kojto	90:cb3d968589d8	589	*/
Kojto	90:cb3d968589d8	590	typedef struct
Kojto	90:cb3d968589d8	591	{
Kojto	90:cb3d968589d8	592	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Kojto	90:cb3d968589d8	593	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Kojto	90:cb3d968589d8	594	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Kojto	90:cb3d968589d8	595	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Kojto	90:cb3d968589d8	596	} SysTick_Type;
Kojto	90:cb3d968589d8	597
Kojto	90:cb3d968589d8	598	/* SysTick Control / Status Register Definitions */
Kojto	90:cb3d968589d8	599	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Kojto	90:cb3d968589d8	600	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Kojto	90:cb3d968589d8	601
Kojto	90:cb3d968589d8	602	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Kojto	90:cb3d968589d8	603	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Kojto	90:cb3d968589d8	604
Kojto	90:cb3d968589d8	605	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Kojto	90:cb3d968589d8	606	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Kojto	90:cb3d968589d8	607
Kojto	90:cb3d968589d8	608	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Kojto	90:cb3d968589d8	609	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
Kojto	90:cb3d968589d8	610
Kojto	90:cb3d968589d8	611	/* SysTick Reload Register Definitions */
Kojto	90:cb3d968589d8	612	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Kojto	90:cb3d968589d8	613	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
Kojto	90:cb3d968589d8	614
Kojto	90:cb3d968589d8	615	/* SysTick Current Register Definitions */
Kojto	90:cb3d968589d8	616	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Kojto	90:cb3d968589d8	617	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
Kojto	90:cb3d968589d8	618
Kojto	90:cb3d968589d8	619	/* SysTick Calibration Register Definitions */
Kojto	90:cb3d968589d8	620	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Kojto	90:cb3d968589d8	621	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Kojto	90:cb3d968589d8	622
Kojto	90:cb3d968589d8	623	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Kojto	90:cb3d968589d8	624	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Kojto	90:cb3d968589d8	625
Kojto	90:cb3d968589d8	626	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Kojto	90:cb3d968589d8	627	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
Kojto	90:cb3d968589d8	628
Kojto	90:cb3d968589d8	629	/@} end of group CMSIS_SysTick /
Kojto	90:cb3d968589d8	630
Kojto	90:cb3d968589d8	631
Kojto	90:cb3d968589d8	632	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	633	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Kojto	90:cb3d968589d8	634	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Kojto	90:cb3d968589d8	635	@{
Kojto	90:cb3d968589d8	636	*/
Kojto	90:cb3d968589d8	637
Kojto	90:cb3d968589d8	638	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Kojto	90:cb3d968589d8	639	*/
Kojto	90:cb3d968589d8	640	typedef struct
Kojto	90:cb3d968589d8	641	{
Kojto	90:cb3d968589d8	642	__O union
Kojto	90:cb3d968589d8	643	{
Kojto	90:cb3d968589d8	644	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Kojto	90:cb3d968589d8	645	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Kojto	90:cb3d968589d8	646	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Kojto	90:cb3d968589d8	647	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Kojto	90:cb3d968589d8	648	uint32_t RESERVED0[864];
Kojto	90:cb3d968589d8	649	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Kojto	90:cb3d968589d8	650	uint32_t RESERVED1[15];
Kojto	90:cb3d968589d8	651	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Kojto	90:cb3d968589d8	652	uint32_t RESERVED2[15];
Kojto	90:cb3d968589d8	653	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Kojto	90:cb3d968589d8	654	uint32_t RESERVED3[29];
Kojto	90:cb3d968589d8	655	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Kojto	90:cb3d968589d8	656	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Kojto	90:cb3d968589d8	657	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Kojto	90:cb3d968589d8	658	uint32_t RESERVED4[43];
Kojto	90:cb3d968589d8	659	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Kojto	90:cb3d968589d8	660	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Kojto	90:cb3d968589d8	661	uint32_t RESERVED5[6];
Kojto	90:cb3d968589d8	662	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Kojto	90:cb3d968589d8	663	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Kojto	90:cb3d968589d8	664	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Kojto	90:cb3d968589d8	665	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Kojto	90:cb3d968589d8	666	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Kojto	90:cb3d968589d8	667	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Kojto	90:cb3d968589d8	668	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Kojto	90:cb3d968589d8	669	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Kojto	90:cb3d968589d8	670	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Kojto	90:cb3d968589d8	671	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Kojto	90:cb3d968589d8	672	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Kojto	90:cb3d968589d8	673	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Kojto	90:cb3d968589d8	674	} ITM_Type;
Kojto	90:cb3d968589d8	675
Kojto	90:cb3d968589d8	676	/* ITM Trace Privilege Register Definitions */
Kojto	90:cb3d968589d8	677	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Kojto	90:cb3d968589d8	678	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
Kojto	90:cb3d968589d8	679
Kojto	90:cb3d968589d8	680	/* ITM Trace Control Register Definitions */
Kojto	90:cb3d968589d8	681	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Kojto	90:cb3d968589d8	682	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Kojto	90:cb3d968589d8	683
Kojto	90:cb3d968589d8	684	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Kojto	90:cb3d968589d8	685	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Kojto	90:cb3d968589d8	686
Kojto	90:cb3d968589d8	687	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Kojto	90:cb3d968589d8	688	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Kojto	90:cb3d968589d8	689
Kojto	90:cb3d968589d8	690	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Kojto	90:cb3d968589d8	691	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Kojto	90:cb3d968589d8	692
Kojto	90:cb3d968589d8	693	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Kojto	90:cb3d968589d8	694	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Kojto	90:cb3d968589d8	695
Kojto	90:cb3d968589d8	696	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Kojto	90:cb3d968589d8	697	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Kojto	90:cb3d968589d8	698
Kojto	90:cb3d968589d8	699	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Kojto	90:cb3d968589d8	700	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Kojto	90:cb3d968589d8	701
Kojto	90:cb3d968589d8	702	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Kojto	90:cb3d968589d8	703	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Kojto	90:cb3d968589d8	704
Kojto	90:cb3d968589d8	705	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Kojto	90:cb3d968589d8	706	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
Kojto	90:cb3d968589d8	707
Kojto	90:cb3d968589d8	708	/* ITM Integration Write Register Definitions */
Kojto	90:cb3d968589d8	709	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Kojto	90:cb3d968589d8	710	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
Kojto	90:cb3d968589d8	711
Kojto	90:cb3d968589d8	712	/* ITM Integration Read Register Definitions */
Kojto	90:cb3d968589d8	713	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Kojto	90:cb3d968589d8	714	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
Kojto	90:cb3d968589d8	715
Kojto	90:cb3d968589d8	716	/* ITM Integration Mode Control Register Definitions */
Kojto	90:cb3d968589d8	717	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Kojto	90:cb3d968589d8	718	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
Kojto	90:cb3d968589d8	719
Kojto	90:cb3d968589d8	720	/* ITM Lock Status Register Definitions */
Kojto	90:cb3d968589d8	721	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Kojto	90:cb3d968589d8	722	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Kojto	90:cb3d968589d8	723
Kojto	90:cb3d968589d8	724	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Kojto	90:cb3d968589d8	725	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Kojto	90:cb3d968589d8	726
Kojto	90:cb3d968589d8	727	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Kojto	90:cb3d968589d8	728	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
Kojto	90:cb3d968589d8	729
Kojto	90:cb3d968589d8	730	/@}/ /* end of group CMSIS_ITM */
Kojto	90:cb3d968589d8	731
Kojto	90:cb3d968589d8	732
Kojto	90:cb3d968589d8	733	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	734	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Kojto	90:cb3d968589d8	735	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Kojto	90:cb3d968589d8	736	@{
Kojto	90:cb3d968589d8	737	*/
Kojto	90:cb3d968589d8	738
Kojto	90:cb3d968589d8	739	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Kojto	90:cb3d968589d8	740	*/
Kojto	90:cb3d968589d8	741	typedef struct
Kojto	90:cb3d968589d8	742	{
Kojto	90:cb3d968589d8	743	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Kojto	90:cb3d968589d8	744	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Kojto	90:cb3d968589d8	745	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Kojto	90:cb3d968589d8	746	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Kojto	90:cb3d968589d8	747	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Kojto	90:cb3d968589d8	748	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Kojto	90:cb3d968589d8	749	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Kojto	90:cb3d968589d8	750	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Kojto	90:cb3d968589d8	751	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Kojto	90:cb3d968589d8	752	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Kojto	90:cb3d968589d8	753	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Kojto	90:cb3d968589d8	754	uint32_t RESERVED0[1];
Kojto	90:cb3d968589d8	755	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Kojto	90:cb3d968589d8	756	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Kojto	90:cb3d968589d8	757	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Kojto	90:cb3d968589d8	758	uint32_t RESERVED1[1];
Kojto	90:cb3d968589d8	759	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Kojto	90:cb3d968589d8	760	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Kojto	90:cb3d968589d8	761	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Kojto	90:cb3d968589d8	762	uint32_t RESERVED2[1];
Kojto	90:cb3d968589d8	763	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Kojto	90:cb3d968589d8	764	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Kojto	90:cb3d968589d8	765	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Kojto	90:cb3d968589d8	766	} DWT_Type;
Kojto	90:cb3d968589d8	767
Kojto	90:cb3d968589d8	768	/* DWT Control Register Definitions */
Kojto	90:cb3d968589d8	769	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Kojto	90:cb3d968589d8	770	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Kojto	90:cb3d968589d8	771
Kojto	90:cb3d968589d8	772	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Kojto	90:cb3d968589d8	773	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Kojto	90:cb3d968589d8	774
Kojto	90:cb3d968589d8	775	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Kojto	90:cb3d968589d8	776	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Kojto	90:cb3d968589d8	777
Kojto	90:cb3d968589d8	778	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Kojto	90:cb3d968589d8	779	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Kojto	90:cb3d968589d8	780
Kojto	90:cb3d968589d8	781	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Kojto	90:cb3d968589d8	782	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Kojto	90:cb3d968589d8	783
Kojto	90:cb3d968589d8	784	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Kojto	90:cb3d968589d8	785	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Kojto	90:cb3d968589d8	786
Kojto	90:cb3d968589d8	787	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Kojto	90:cb3d968589d8	788	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Kojto	90:cb3d968589d8	789
Kojto	90:cb3d968589d8	790	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Kojto	90:cb3d968589d8	791	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Kojto	90:cb3d968589d8	792
Kojto	90:cb3d968589d8	793	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Kojto	90:cb3d968589d8	794	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Kojto	90:cb3d968589d8	795
Kojto	90:cb3d968589d8	796	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Kojto	90:cb3d968589d8	797	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Kojto	90:cb3d968589d8	798
Kojto	90:cb3d968589d8	799	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Kojto	90:cb3d968589d8	800	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Kojto	90:cb3d968589d8	801
Kojto	90:cb3d968589d8	802	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Kojto	90:cb3d968589d8	803	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Kojto	90:cb3d968589d8	804
Kojto	90:cb3d968589d8	805	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Kojto	90:cb3d968589d8	806	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Kojto	90:cb3d968589d8	807
Kojto	90:cb3d968589d8	808	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Kojto	90:cb3d968589d8	809	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Kojto	90:cb3d968589d8	810
Kojto	90:cb3d968589d8	811	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Kojto	90:cb3d968589d8	812	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Kojto	90:cb3d968589d8	813
Kojto	90:cb3d968589d8	814	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Kojto	90:cb3d968589d8	815	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Kojto	90:cb3d968589d8	816
Kojto	90:cb3d968589d8	817	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Kojto	90:cb3d968589d8	818	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Kojto	90:cb3d968589d8	819
Kojto	90:cb3d968589d8	820	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Kojto	90:cb3d968589d8	821	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
Kojto	90:cb3d968589d8	822
Kojto	90:cb3d968589d8	823	/* DWT CPI Count Register Definitions */
Kojto	90:cb3d968589d8	824	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Kojto	90:cb3d968589d8	825	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
Kojto	90:cb3d968589d8	826
Kojto	90:cb3d968589d8	827	/* DWT Exception Overhead Count Register Definitions */
Kojto	90:cb3d968589d8	828	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Kojto	90:cb3d968589d8	829	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
Kojto	90:cb3d968589d8	830
Kojto	90:cb3d968589d8	831	/* DWT Sleep Count Register Definitions */
Kojto	90:cb3d968589d8	832	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Kojto	90:cb3d968589d8	833	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Kojto	90:cb3d968589d8	834
Kojto	90:cb3d968589d8	835	/* DWT LSU Count Register Definitions */
Kojto	90:cb3d968589d8	836	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Kojto	90:cb3d968589d8	837	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
Kojto	90:cb3d968589d8	838
Kojto	90:cb3d968589d8	839	/* DWT Folded-instruction Count Register Definitions */
Kojto	90:cb3d968589d8	840	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Kojto	90:cb3d968589d8	841	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
Kojto	90:cb3d968589d8	842
Kojto	90:cb3d968589d8	843	/* DWT Comparator Mask Register Definitions */
Kojto	90:cb3d968589d8	844	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Kojto	90:cb3d968589d8	845	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
Kojto	90:cb3d968589d8	846
Kojto	90:cb3d968589d8	847	/* DWT Comparator Function Register Definitions */
Kojto	90:cb3d968589d8	848	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Kojto	90:cb3d968589d8	849	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Kojto	90:cb3d968589d8	850
Kojto	90:cb3d968589d8	851	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Kojto	90:cb3d968589d8	852	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Kojto	90:cb3d968589d8	853
Kojto	90:cb3d968589d8	854	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Kojto	90:cb3d968589d8	855	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Kojto	90:cb3d968589d8	856
Kojto	90:cb3d968589d8	857	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Kojto	90:cb3d968589d8	858	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Kojto	90:cb3d968589d8	859
Kojto	90:cb3d968589d8	860	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Kojto	90:cb3d968589d8	861	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Kojto	90:cb3d968589d8	862
Kojto	90:cb3d968589d8	863	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Kojto	90:cb3d968589d8	864	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Kojto	90:cb3d968589d8	865
Kojto	90:cb3d968589d8	866	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Kojto	90:cb3d968589d8	867	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Kojto	90:cb3d968589d8	868
Kojto	90:cb3d968589d8	869	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Kojto	90:cb3d968589d8	870	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Kojto	90:cb3d968589d8	871
Kojto	90:cb3d968589d8	872	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Kojto	90:cb3d968589d8	873	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
Kojto	90:cb3d968589d8	874
Kojto	90:cb3d968589d8	875	/@}/ /* end of group CMSIS_DWT */
Kojto	90:cb3d968589d8	876
Kojto	90:cb3d968589d8	877
Kojto	90:cb3d968589d8	878	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	879	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Kojto	90:cb3d968589d8	880	\brief Type definitions for the Trace Port Interface (TPI)
Kojto	90:cb3d968589d8	881	@{
Kojto	90:cb3d968589d8	882	*/
Kojto	90:cb3d968589d8	883
Kojto	90:cb3d968589d8	884	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Kojto	90:cb3d968589d8	885	*/
Kojto	90:cb3d968589d8	886	typedef struct
Kojto	90:cb3d968589d8	887	{
Kojto	90:cb3d968589d8	888	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Kojto	90:cb3d968589d8	889	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Kojto	90:cb3d968589d8	890	uint32_t RESERVED0[2];
Kojto	90:cb3d968589d8	891	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Kojto	90:cb3d968589d8	892	uint32_t RESERVED1[55];
Kojto	90:cb3d968589d8	893	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Kojto	90:cb3d968589d8	894	uint32_t RESERVED2[131];
Kojto	90:cb3d968589d8	895	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Kojto	90:cb3d968589d8	896	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Kojto	90:cb3d968589d8	897	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Kojto	90:cb3d968589d8	898	uint32_t RESERVED3[759];
Kojto	90:cb3d968589d8	899	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Kojto	90:cb3d968589d8	900	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Kojto	90:cb3d968589d8	901	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Kojto	90:cb3d968589d8	902	uint32_t RESERVED4[1];
Kojto	90:cb3d968589d8	903	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Kojto	90:cb3d968589d8	904	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Kojto	90:cb3d968589d8	905	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Kojto	90:cb3d968589d8	906	uint32_t RESERVED5[39];
Kojto	90:cb3d968589d8	907	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Kojto	90:cb3d968589d8	908	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Kojto	90:cb3d968589d8	909	uint32_t RESERVED7[8];
Kojto	90:cb3d968589d8	910	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Kojto	90:cb3d968589d8	911	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Kojto	90:cb3d968589d8	912	} TPI_Type;
Kojto	90:cb3d968589d8	913
Kojto	90:cb3d968589d8	914	/* TPI Asynchronous Clock Prescaler Register Definitions */
Kojto	90:cb3d968589d8	915	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Kojto	90:cb3d968589d8	916	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
Kojto	90:cb3d968589d8	917
Kojto	90:cb3d968589d8	918	/* TPI Selected Pin Protocol Register Definitions */
Kojto	90:cb3d968589d8	919	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Kojto	90:cb3d968589d8	920	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
Kojto	90:cb3d968589d8	921
Kojto	90:cb3d968589d8	922	/* TPI Formatter and Flush Status Register Definitions */
Kojto	90:cb3d968589d8	923	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Kojto	90:cb3d968589d8	924	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Kojto	90:cb3d968589d8	925
Kojto	90:cb3d968589d8	926	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Kojto	90:cb3d968589d8	927	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Kojto	90:cb3d968589d8	928
Kojto	90:cb3d968589d8	929	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Kojto	90:cb3d968589d8	930	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Kojto	90:cb3d968589d8	931
Kojto	90:cb3d968589d8	932	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Kojto	90:cb3d968589d8	933	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
Kojto	90:cb3d968589d8	934
Kojto	90:cb3d968589d8	935	/* TPI Formatter and Flush Control Register Definitions */
Kojto	90:cb3d968589d8	936	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Kojto	90:cb3d968589d8	937	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Kojto	90:cb3d968589d8	938
Kojto	90:cb3d968589d8	939	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Kojto	90:cb3d968589d8	940	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Kojto	90:cb3d968589d8	941
Kojto	90:cb3d968589d8	942	/* TPI TRIGGER Register Definitions */
Kojto	90:cb3d968589d8	943	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Kojto	90:cb3d968589d8	944	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
Kojto	90:cb3d968589d8	945
Kojto	90:cb3d968589d8	946	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Kojto	90:cb3d968589d8	947	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Kojto	90:cb3d968589d8	948	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Kojto	90:cb3d968589d8	949
Kojto	90:cb3d968589d8	950	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Kojto	90:cb3d968589d8	951	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Kojto	90:cb3d968589d8	952
Kojto	90:cb3d968589d8	953	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Kojto	90:cb3d968589d8	954	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Kojto	90:cb3d968589d8	955
Kojto	90:cb3d968589d8	956	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Kojto	90:cb3d968589d8	957	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Kojto	90:cb3d968589d8	958
Kojto	90:cb3d968589d8	959	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Kojto	90:cb3d968589d8	960	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Kojto	90:cb3d968589d8	961
Kojto	90:cb3d968589d8	962	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Kojto	90:cb3d968589d8	963	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Kojto	90:cb3d968589d8	964
Kojto	90:cb3d968589d8	965	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Kojto	90:cb3d968589d8	966	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
Kojto	90:cb3d968589d8	967
Kojto	90:cb3d968589d8	968	/* TPI ITATBCTR2 Register Definitions */
Kojto	90:cb3d968589d8	969	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Kojto	90:cb3d968589d8	970	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
Kojto	90:cb3d968589d8	971
Kojto	90:cb3d968589d8	972	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Kojto	90:cb3d968589d8	973	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Kojto	90:cb3d968589d8	974	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Kojto	90:cb3d968589d8	975
Kojto	90:cb3d968589d8	976	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Kojto	90:cb3d968589d8	977	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Kojto	90:cb3d968589d8	978
Kojto	90:cb3d968589d8	979	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Kojto	90:cb3d968589d8	980	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Kojto	90:cb3d968589d8	981
Kojto	90:cb3d968589d8	982	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Kojto	90:cb3d968589d8	983	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Kojto	90:cb3d968589d8	984
Kojto	90:cb3d968589d8	985	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Kojto	90:cb3d968589d8	986	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Kojto	90:cb3d968589d8	987
Kojto	90:cb3d968589d8	988	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Kojto	90:cb3d968589d8	989	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Kojto	90:cb3d968589d8	990
Kojto	90:cb3d968589d8	991	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Kojto	90:cb3d968589d8	992	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
Kojto	90:cb3d968589d8	993
Kojto	90:cb3d968589d8	994	/* TPI ITATBCTR0 Register Definitions */
Kojto	90:cb3d968589d8	995	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Kojto	90:cb3d968589d8	996	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
Kojto	90:cb3d968589d8	997
Kojto	90:cb3d968589d8	998	/* TPI Integration Mode Control Register Definitions */
Kojto	90:cb3d968589d8	999	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Kojto	90:cb3d968589d8	1000	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
Kojto	90:cb3d968589d8	1001
Kojto	90:cb3d968589d8	1002	/* TPI DEVID Register Definitions */
Kojto	90:cb3d968589d8	1003	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Kojto	90:cb3d968589d8	1004	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Kojto	90:cb3d968589d8	1005
Kojto	90:cb3d968589d8	1006	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Kojto	90:cb3d968589d8	1007	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Kojto	90:cb3d968589d8	1008
Kojto	90:cb3d968589d8	1009	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Kojto	90:cb3d968589d8	1010	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Kojto	90:cb3d968589d8	1011
Kojto	90:cb3d968589d8	1012	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Kojto	90:cb3d968589d8	1013	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Kojto	90:cb3d968589d8	1014
Kojto	90:cb3d968589d8	1015	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Kojto	90:cb3d968589d8	1016	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Kojto	90:cb3d968589d8	1017
Kojto	90:cb3d968589d8	1018	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Kojto	90:cb3d968589d8	1019	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
Kojto	90:cb3d968589d8	1020
Kojto	90:cb3d968589d8	1021	/* TPI DEVTYPE Register Definitions */
Kojto	90:cb3d968589d8	1022	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Kojto	90:cb3d968589d8	1023	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
Kojto	90:cb3d968589d8	1024
Kojto	90:cb3d968589d8	1025	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Kojto	90:cb3d968589d8	1026	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Kojto	90:cb3d968589d8	1027
Kojto	90:cb3d968589d8	1028	/@}/ /* end of group CMSIS_TPI */
Kojto	90:cb3d968589d8	1029
Kojto	90:cb3d968589d8	1030
Kojto	90:cb3d968589d8	1031	#if (__MPU_PRESENT == 1)
Kojto	90:cb3d968589d8	1032	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	1033	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Kojto	90:cb3d968589d8	1034	\brief Type definitions for the Memory Protection Unit (MPU)
Kojto	90:cb3d968589d8	1035	@{
Kojto	90:cb3d968589d8	1036	*/
Kojto	90:cb3d968589d8	1037
Kojto	90:cb3d968589d8	1038	/** \brief Structure type to access the Memory Protection Unit (MPU).
Kojto	90:cb3d968589d8	1039	*/
Kojto	90:cb3d968589d8	1040	typedef struct
Kojto	90:cb3d968589d8	1041	{
Kojto	90:cb3d968589d8	1042	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Kojto	90:cb3d968589d8	1043	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Kojto	90:cb3d968589d8	1044	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Kojto	90:cb3d968589d8	1045	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Kojto	90:cb3d968589d8	1046	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Kojto	90:cb3d968589d8	1047	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Kojto	90:cb3d968589d8	1048	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Kojto	90:cb3d968589d8	1049	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Kojto	90:cb3d968589d8	1050	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Kojto	90:cb3d968589d8	1051	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Kojto	90:cb3d968589d8	1052	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Kojto	90:cb3d968589d8	1053	} MPU_Type;
Kojto	90:cb3d968589d8	1054
Kojto	90:cb3d968589d8	1055	/* MPU Type Register */
Kojto	90:cb3d968589d8	1056	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Kojto	90:cb3d968589d8	1057	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Kojto	90:cb3d968589d8	1058
Kojto	90:cb3d968589d8	1059	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Kojto	90:cb3d968589d8	1060	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Kojto	90:cb3d968589d8	1061
Kojto	90:cb3d968589d8	1062	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Kojto	90:cb3d968589d8	1063	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
Kojto	90:cb3d968589d8	1064
Kojto	90:cb3d968589d8	1065	/* MPU Control Register */
Kojto	90:cb3d968589d8	1066	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Kojto	90:cb3d968589d8	1067	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Kojto	90:cb3d968589d8	1068
Kojto	90:cb3d968589d8	1069	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Kojto	90:cb3d968589d8	1070	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Kojto	90:cb3d968589d8	1071
Kojto	90:cb3d968589d8	1072	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Kojto	90:cb3d968589d8	1073	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
Kojto	90:cb3d968589d8	1074
Kojto	90:cb3d968589d8	1075	/* MPU Region Number Register */
Kojto	90:cb3d968589d8	1076	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Kojto	90:cb3d968589d8	1077	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
Kojto	90:cb3d968589d8	1078
Kojto	90:cb3d968589d8	1079	/* MPU Region Base Address Register */
Kojto	90:cb3d968589d8	1080	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Kojto	90:cb3d968589d8	1081	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Kojto	90:cb3d968589d8	1082
Kojto	90:cb3d968589d8	1083	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Kojto	90:cb3d968589d8	1084	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Kojto	90:cb3d968589d8	1085
Kojto	90:cb3d968589d8	1086	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Kojto	90:cb3d968589d8	1087	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
Kojto	90:cb3d968589d8	1088
Kojto	90:cb3d968589d8	1089	/* MPU Region Attribute and Size Register */
Kojto	90:cb3d968589d8	1090	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Kojto	90:cb3d968589d8	1091	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Kojto	90:cb3d968589d8	1092
Kojto	90:cb3d968589d8	1093	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Kojto	90:cb3d968589d8	1094	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Kojto	90:cb3d968589d8	1095
Kojto	90:cb3d968589d8	1096	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Kojto	90:cb3d968589d8	1097	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Kojto	90:cb3d968589d8	1098
Kojto	90:cb3d968589d8	1099	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Kojto	90:cb3d968589d8	1100	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Kojto	90:cb3d968589d8	1101
Kojto	90:cb3d968589d8	1102	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Kojto	90:cb3d968589d8	1103	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Kojto	90:cb3d968589d8	1104
Kojto	90:cb3d968589d8	1105	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Kojto	90:cb3d968589d8	1106	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Kojto	90:cb3d968589d8	1107
Kojto	90:cb3d968589d8	1108	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Kojto	90:cb3d968589d8	1109	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Kojto	90:cb3d968589d8	1110
Kojto	90:cb3d968589d8	1111	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Kojto	90:cb3d968589d8	1112	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Kojto	90:cb3d968589d8	1113
Kojto	90:cb3d968589d8	1114	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Kojto	90:cb3d968589d8	1115	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Kojto	90:cb3d968589d8	1116
Kojto	90:cb3d968589d8	1117	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Kojto	90:cb3d968589d8	1118	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
Kojto	90:cb3d968589d8	1119
Kojto	90:cb3d968589d8	1120	/@} end of group CMSIS_MPU /
Kojto	90:cb3d968589d8	1121	#endif
Kojto	90:cb3d968589d8	1122
Kojto	90:cb3d968589d8	1123
Kojto	90:cb3d968589d8	1124	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	1125	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Kojto	90:cb3d968589d8	1126	\brief Type definitions for the Core Debug Registers
Kojto	90:cb3d968589d8	1127	@{
Kojto	90:cb3d968589d8	1128	*/
Kojto	90:cb3d968589d8	1129
Kojto	90:cb3d968589d8	1130	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Kojto	90:cb3d968589d8	1131	*/
Kojto	90:cb3d968589d8	1132	typedef struct
Kojto	90:cb3d968589d8	1133	{
Kojto	90:cb3d968589d8	1134	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Kojto	90:cb3d968589d8	1135	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Kojto	90:cb3d968589d8	1136	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Kojto	90:cb3d968589d8	1137	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Kojto	90:cb3d968589d8	1138	} CoreDebug_Type;
Kojto	90:cb3d968589d8	1139
Kojto	90:cb3d968589d8	1140	/* Debug Halting Control and Status Register */
Kojto	90:cb3d968589d8	1141	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Kojto	90:cb3d968589d8	1142	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Kojto	90:cb3d968589d8	1143
Kojto	90:cb3d968589d8	1144	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Kojto	90:cb3d968589d8	1145	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Kojto	90:cb3d968589d8	1146
Kojto	90:cb3d968589d8	1147	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Kojto	90:cb3d968589d8	1148	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Kojto	90:cb3d968589d8	1149
Kojto	90:cb3d968589d8	1150	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Kojto	90:cb3d968589d8	1151	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Kojto	90:cb3d968589d8	1152
Kojto	90:cb3d968589d8	1153	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Kojto	90:cb3d968589d8	1154	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Kojto	90:cb3d968589d8	1155
Kojto	90:cb3d968589d8	1156	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Kojto	90:cb3d968589d8	1157	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Kojto	90:cb3d968589d8	1158
Kojto	90:cb3d968589d8	1159	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Kojto	90:cb3d968589d8	1160	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Kojto	90:cb3d968589d8	1161
Kojto	90:cb3d968589d8	1162	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Kojto	90:cb3d968589d8	1163	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Kojto	90:cb3d968589d8	1164
Kojto	90:cb3d968589d8	1165	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Kojto	90:cb3d968589d8	1166	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Kojto	90:cb3d968589d8	1167
Kojto	90:cb3d968589d8	1168	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Kojto	90:cb3d968589d8	1169	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Kojto	90:cb3d968589d8	1170
Kojto	90:cb3d968589d8	1171	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Kojto	90:cb3d968589d8	1172	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Kojto	90:cb3d968589d8	1173
Kojto	90:cb3d968589d8	1174	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Kojto	90:cb3d968589d8	1175	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Kojto	90:cb3d968589d8	1176
Kojto	90:cb3d968589d8	1177	/* Debug Core Register Selector Register */
Kojto	90:cb3d968589d8	1178	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Kojto	90:cb3d968589d8	1179	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Kojto	90:cb3d968589d8	1180
Kojto	90:cb3d968589d8	1181	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Kojto	90:cb3d968589d8	1182	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
Kojto	90:cb3d968589d8	1183
Kojto	90:cb3d968589d8	1184	/* Debug Exception and Monitor Control Register */
Kojto	90:cb3d968589d8	1185	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Kojto	90:cb3d968589d8	1186	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Kojto	90:cb3d968589d8	1187
Kojto	90:cb3d968589d8	1188	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Kojto	90:cb3d968589d8	1189	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Kojto	90:cb3d968589d8	1190
Kojto	90:cb3d968589d8	1191	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Kojto	90:cb3d968589d8	1192	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Kojto	90:cb3d968589d8	1193
Kojto	90:cb3d968589d8	1194	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Kojto	90:cb3d968589d8	1195	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Kojto	90:cb3d968589d8	1196
Kojto	90:cb3d968589d8	1197	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Kojto	90:cb3d968589d8	1198	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Kojto	90:cb3d968589d8	1199
Kojto	90:cb3d968589d8	1200	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Kojto	90:cb3d968589d8	1201	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Kojto	90:cb3d968589d8	1202
Kojto	90:cb3d968589d8	1203	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Kojto	90:cb3d968589d8	1204	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Kojto	90:cb3d968589d8	1205
Kojto	90:cb3d968589d8	1206	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Kojto	90:cb3d968589d8	1207	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Kojto	90:cb3d968589d8	1208
Kojto	90:cb3d968589d8	1209	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Kojto	90:cb3d968589d8	1210	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Kojto	90:cb3d968589d8	1211
Kojto	90:cb3d968589d8	1212	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Kojto	90:cb3d968589d8	1213	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Kojto	90:cb3d968589d8	1214
Kojto	90:cb3d968589d8	1215	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Kojto	90:cb3d968589d8	1216	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Kojto	90:cb3d968589d8	1217
Kojto	90:cb3d968589d8	1218	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Kojto	90:cb3d968589d8	1219	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Kojto	90:cb3d968589d8	1220
Kojto	90:cb3d968589d8	1221	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Kojto	90:cb3d968589d8	1222	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Kojto	90:cb3d968589d8	1223
Kojto	90:cb3d968589d8	1224	/@} end of group CMSIS_CoreDebug /
Kojto	90:cb3d968589d8	1225
Kojto	90:cb3d968589d8	1226
Kojto	90:cb3d968589d8	1227	/** \ingroup CMSIS_core_register
Kojto	90:cb3d968589d8	1228	\defgroup CMSIS_core_base Core Definitions
Kojto	90:cb3d968589d8	1229	\brief Definitions for base addresses, unions, and structures.
Kojto	90:cb3d968589d8	1230	@{
Kojto	90:cb3d968589d8	1231	*/
Kojto	90:cb3d968589d8	1232
Kojto	90:cb3d968589d8	1233	/* Memory mapping of Cortex-M3 Hardware */
Kojto	90:cb3d968589d8	1234	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Kojto	90:cb3d968589d8	1235	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Kojto	90:cb3d968589d8	1236	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Kojto	90:cb3d968589d8	1237	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Kojto	90:cb3d968589d8	1238	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Kojto	90:cb3d968589d8	1239	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Kojto	90:cb3d968589d8	1240	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Kojto	90:cb3d968589d8	1241	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Kojto	90:cb3d968589d8	1242
Kojto	90:cb3d968589d8	1243	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Kojto	90:cb3d968589d8	1244	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Kojto	90:cb3d968589d8	1245	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Kojto	90:cb3d968589d8	1246	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Kojto	90:cb3d968589d8	1247	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Kojto	90:cb3d968589d8	1248	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Kojto	90:cb3d968589d8	1249	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Kojto	90:cb3d968589d8	1250	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Kojto	90:cb3d968589d8	1251
Kojto	90:cb3d968589d8	1252	#if (__MPU_PRESENT == 1)
Kojto	90:cb3d968589d8	1253	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Kojto	90:cb3d968589d8	1254	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Kojto	90:cb3d968589d8	1255	#endif
Kojto	90:cb3d968589d8	1256
Kojto	90:cb3d968589d8	1257	/@} /
Kojto	90:cb3d968589d8	1258
Kojto	90:cb3d968589d8	1259
Kojto	90:cb3d968589d8	1260
Kojto	90:cb3d968589d8	1261	/*******************************************************************************
Kojto	90:cb3d968589d8	1262	* Hardware Abstraction Layer
Kojto	90:cb3d968589d8	1263	Core Function Interface contains:
Kojto	90:cb3d968589d8	1264	- Core NVIC Functions
Kojto	90:cb3d968589d8	1265	- Core SysTick Functions
Kojto	90:cb3d968589d8	1266	- Core Debug Functions
Kojto	90:cb3d968589d8	1267	- Core Register Access Functions
Kojto	90:cb3d968589d8	1268	******************************************************************************/
Kojto	90:cb3d968589d8	1269	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Kojto	90:cb3d968589d8	1270	*/
Kojto	90:cb3d968589d8	1271
Kojto	90:cb3d968589d8	1272
Kojto	90:cb3d968589d8	1273
Kojto	90:cb3d968589d8	1274	/* ########################## NVIC functions #################################### */
Kojto	90:cb3d968589d8	1275	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	90:cb3d968589d8	1276	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Kojto	90:cb3d968589d8	1277	\brief Functions that manage interrupts and exceptions via the NVIC.
Kojto	90:cb3d968589d8	1278	@{
Kojto	90:cb3d968589d8	1279	*/
Kojto	90:cb3d968589d8	1280
Kojto	90:cb3d968589d8	1281	/** \brief Set Priority Grouping
Kojto	90:cb3d968589d8	1282
Kojto	90:cb3d968589d8	1283	The function sets the priority grouping field using the required unlock sequence.
Kojto	90:cb3d968589d8	1284	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Kojto	90:cb3d968589d8	1285	Only values from 0..7 are used.
Kojto	90:cb3d968589d8	1286	In case of a conflict between priority grouping and available
Kojto	90:cb3d968589d8	1287	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Kojto	90:cb3d968589d8	1288
Kojto	90:cb3d968589d8	1289	\param [in] PriorityGroup Priority grouping field.
Kojto	90:cb3d968589d8	1290	*/
Kojto	90:cb3d968589d8	1291	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Kojto	90:cb3d968589d8	1292	{
Kojto	90:cb3d968589d8	1293	uint32_t reg_value;
Kojto	90:cb3d968589d8	1294	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
Kojto	90:cb3d968589d8	1295
Kojto	90:cb3d968589d8	1296	reg_value = SCB->AIRCR; /* read old register configuration */
Kojto	90:cb3d968589d8	1297	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
Kojto	90:cb3d968589d8	1298	reg_value = (reg_value \|
Kojto	90:cb3d968589d8	1299	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	90:cb3d968589d8	1300	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
Kojto	90:cb3d968589d8	1301	SCB->AIRCR = reg_value;
Kojto	90:cb3d968589d8	1302	}
Kojto	90:cb3d968589d8	1303
Kojto	90:cb3d968589d8	1304
Kojto	90:cb3d968589d8	1305	/** \brief Get Priority Grouping
Kojto	90:cb3d968589d8	1306
Kojto	90:cb3d968589d8	1307	The function reads the priority grouping field from the NVIC Interrupt Controller.
Kojto	90:cb3d968589d8	1308
Kojto	90:cb3d968589d8	1309	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Kojto	90:cb3d968589d8	1310	*/
Kojto	90:cb3d968589d8	1311	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Kojto	90:cb3d968589d8	1312	{
Kojto	90:cb3d968589d8	1313	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
Kojto	90:cb3d968589d8	1314	}
Kojto	90:cb3d968589d8	1315
Kojto	90:cb3d968589d8	1316
Kojto	90:cb3d968589d8	1317	/** \brief Enable External Interrupt
Kojto	90:cb3d968589d8	1318
Kojto	90:cb3d968589d8	1319	The function enables a device-specific interrupt in the NVIC interrupt controller.
Kojto	90:cb3d968589d8	1320
Kojto	90:cb3d968589d8	1321	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	90:cb3d968589d8	1322	*/
Kojto	90:cb3d968589d8	1323	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Kojto	90:cb3d968589d8	1324	{
Kojto	90:cb3d968589d8	1325	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
Kojto	90:cb3d968589d8	1326	}
Kojto	90:cb3d968589d8	1327
Kojto	90:cb3d968589d8	1328
Kojto	90:cb3d968589d8	1329	/** \brief Disable External Interrupt
Kojto	90:cb3d968589d8	1330
Kojto	90:cb3d968589d8	1331	The function disables a device-specific interrupt in the NVIC interrupt controller.
Kojto	90:cb3d968589d8	1332
Kojto	90:cb3d968589d8	1333	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	90:cb3d968589d8	1334	*/
Kojto	90:cb3d968589d8	1335	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Kojto	90:cb3d968589d8	1336	{
Kojto	90:cb3d968589d8	1337	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
Kojto	90:cb3d968589d8	1338	}
Kojto	90:cb3d968589d8	1339
Kojto	90:cb3d968589d8	1340
Kojto	90:cb3d968589d8	1341	/** \brief Get Pending Interrupt
Kojto	90:cb3d968589d8	1342
Kojto	90:cb3d968589d8	1343	The function reads the pending register in the NVIC and returns the pending bit
Kojto	90:cb3d968589d8	1344	for the specified interrupt.
Kojto	90:cb3d968589d8	1345
Kojto	90:cb3d968589d8	1346	\param [in] IRQn Interrupt number.
Kojto	90:cb3d968589d8	1347
Kojto	90:cb3d968589d8	1348	\return 0 Interrupt status is not pending.
Kojto	90:cb3d968589d8	1349	\return 1 Interrupt status is pending.
Kojto	90:cb3d968589d8	1350	*/
Kojto	90:cb3d968589d8	1351	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Kojto	90:cb3d968589d8	1352	{
Kojto	90:cb3d968589d8	1353	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
Kojto	90:cb3d968589d8	1354	}
Kojto	90:cb3d968589d8	1355
Kojto	90:cb3d968589d8	1356
Kojto	90:cb3d968589d8	1357	/** \brief Set Pending Interrupt
Kojto	90:cb3d968589d8	1358
Kojto	90:cb3d968589d8	1359	The function sets the pending bit of an external interrupt.
Kojto	90:cb3d968589d8	1360
Kojto	90:cb3d968589d8	1361	\param [in] IRQn Interrupt number. Value cannot be negative.
Kojto	90:cb3d968589d8	1362	*/
Kojto	90:cb3d968589d8	1363	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Kojto	90:cb3d968589d8	1364	{
Kojto	90:cb3d968589d8	1365	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
Kojto	90:cb3d968589d8	1366	}
Kojto	90:cb3d968589d8	1367
Kojto	90:cb3d968589d8	1368
Kojto	90:cb3d968589d8	1369	/** \brief Clear Pending Interrupt
Kojto	90:cb3d968589d8	1370
Kojto	90:cb3d968589d8	1371	The function clears the pending bit of an external interrupt.
Kojto	90:cb3d968589d8	1372
Kojto	90:cb3d968589d8	1373	\param [in] IRQn External interrupt number. Value cannot be negative.
Kojto	90:cb3d968589d8	1374	*/
Kojto	90:cb3d968589d8	1375	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Kojto	90:cb3d968589d8	1376	{
Kojto	90:cb3d968589d8	1377	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Kojto	90:cb3d968589d8	1378	}
Kojto	90:cb3d968589d8	1379
Kojto	90:cb3d968589d8	1380
Kojto	90:cb3d968589d8	1381	/** \brief Get Active Interrupt
Kojto	90:cb3d968589d8	1382
Kojto	90:cb3d968589d8	1383	The function reads the active register in NVIC and returns the active bit.
Kojto	90:cb3d968589d8	1384
Kojto	90:cb3d968589d8	1385	\param [in] IRQn Interrupt number.
Kojto	90:cb3d968589d8	1386
Kojto	90:cb3d968589d8	1387	\return 0 Interrupt status is not active.
Kojto	90:cb3d968589d8	1388	\return 1 Interrupt status is active.
Kojto	90:cb3d968589d8	1389	*/
Kojto	90:cb3d968589d8	1390	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Kojto	90:cb3d968589d8	1391	{
Kojto	90:cb3d968589d8	1392	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
Kojto	90:cb3d968589d8	1393	}
Kojto	90:cb3d968589d8	1394
Kojto	90:cb3d968589d8	1395
Kojto	90:cb3d968589d8	1396	/** \brief Set Interrupt Priority
Kojto	90:cb3d968589d8	1397
Kojto	90:cb3d968589d8	1398	The function sets the priority of an interrupt.
Kojto	90:cb3d968589d8	1399
Kojto	90:cb3d968589d8	1400	\note The priority cannot be set for every core interrupt.
Kojto	90:cb3d968589d8	1401
Kojto	90:cb3d968589d8	1402	\param [in] IRQn Interrupt number.
Kojto	90:cb3d968589d8	1403	\param [in] priority Priority to set.
Kojto	90:cb3d968589d8	1404	*/
Kojto	90:cb3d968589d8	1405	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Kojto	90:cb3d968589d8	1406	{
Kojto	90:cb3d968589d8	1407	if(IRQn < 0) {
Kojto	90:cb3d968589d8	1408	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
Kojto	90:cb3d968589d8	1409	else {
Kojto	90:cb3d968589d8	1410	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
Kojto	90:cb3d968589d8	1411	}
Kojto	90:cb3d968589d8	1412
Kojto	90:cb3d968589d8	1413
Kojto	90:cb3d968589d8	1414	/** \brief Get Interrupt Priority
Kojto	90:cb3d968589d8	1415
Kojto	90:cb3d968589d8	1416	The function reads the priority of an interrupt. The interrupt
Kojto	90:cb3d968589d8	1417	number can be positive to specify an external (device specific)
Kojto	90:cb3d968589d8	1418	interrupt, or negative to specify an internal (core) interrupt.
Kojto	90:cb3d968589d8	1419
Kojto	90:cb3d968589d8	1420
Kojto	90:cb3d968589d8	1421	\param [in] IRQn Interrupt number.
Kojto	90:cb3d968589d8	1422	\return Interrupt Priority. Value is aligned automatically to the implemented
Kojto	90:cb3d968589d8	1423	priority bits of the microcontroller.
Kojto	90:cb3d968589d8	1424	*/
Kojto	90:cb3d968589d8	1425	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Kojto	90:cb3d968589d8	1426	{
Kojto	90:cb3d968589d8	1427
Kojto	90:cb3d968589d8	1428	if(IRQn < 0) {
Kojto	90:cb3d968589d8	1429	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
Kojto	90:cb3d968589d8	1430	else {
Kojto	90:cb3d968589d8	1431	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Kojto	90:cb3d968589d8	1432	}
Kojto	90:cb3d968589d8	1433
Kojto	90:cb3d968589d8	1434
Kojto	90:cb3d968589d8	1435	/** \brief Encode Priority
Kojto	90:cb3d968589d8	1436
Kojto	90:cb3d968589d8	1437	The function encodes the priority for an interrupt with the given priority group,
Kojto	90:cb3d968589d8	1438	preemptive priority value, and subpriority value.
Kojto	90:cb3d968589d8	1439	In case of a conflict between priority grouping and available
Kojto	90:cb3d968589d8	1440	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
Kojto	90:cb3d968589d8	1441
Kojto	90:cb3d968589d8	1442	\param [in] PriorityGroup Used priority group.
Kojto	90:cb3d968589d8	1443	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Kojto	90:cb3d968589d8	1444	\param [in] SubPriority Subpriority value (starting from 0).
Kojto	90:cb3d968589d8	1445	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Kojto	90:cb3d968589d8	1446	*/
Kojto	90:cb3d968589d8	1447	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Kojto	90:cb3d968589d8	1448	{
Kojto	90:cb3d968589d8	1449	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kojto	90:cb3d968589d8	1450	uint32_t PreemptPriorityBits;
Kojto	90:cb3d968589d8	1451	uint32_t SubPriorityBits;
Kojto	90:cb3d968589d8	1452
Kojto	90:cb3d968589d8	1453	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kojto	90:cb3d968589d8	1454	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kojto	90:cb3d968589d8	1455
Kojto	90:cb3d968589d8	1456	return (
Kojto	90:cb3d968589d8	1457	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
Kojto	90:cb3d968589d8	1458	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
Kojto	90:cb3d968589d8	1459	);
Kojto	90:cb3d968589d8	1460	}
Kojto	90:cb3d968589d8	1461
Kojto	90:cb3d968589d8	1462
Kojto	90:cb3d968589d8	1463	/** \brief Decode Priority
Kojto	90:cb3d968589d8	1464
Kojto	90:cb3d968589d8	1465	The function decodes an interrupt priority value with a given priority group to
Kojto	90:cb3d968589d8	1466	preemptive priority value and subpriority value.
Kojto	90:cb3d968589d8	1467	In case of a conflict between priority grouping and available
Kojto	90:cb3d968589d8	1468	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Kojto	90:cb3d968589d8	1469
Kojto	90:cb3d968589d8	1470	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Kojto	90:cb3d968589d8	1471	\param [in] PriorityGroup Used priority group.
Kojto	90:cb3d968589d8	1472	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Kojto	90:cb3d968589d8	1473	\param [out] pSubPriority Subpriority value (starting from 0).
Kojto	90:cb3d968589d8	1474	*/
Kojto	90:cb3d968589d8	1475	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Kojto	90:cb3d968589d8	1476	{
Kojto	90:cb3d968589d8	1477	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Kojto	90:cb3d968589d8	1478	uint32_t PreemptPriorityBits;
Kojto	90:cb3d968589d8	1479	uint32_t SubPriorityBits;
Kojto	90:cb3d968589d8	1480
Kojto	90:cb3d968589d8	1481	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Kojto	90:cb3d968589d8	1482	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Kojto	90:cb3d968589d8	1483
Kojto	90:cb3d968589d8	1484	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
Kojto	90:cb3d968589d8	1485	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
Kojto	90:cb3d968589d8	1486	}
Kojto	90:cb3d968589d8	1487
Kojto	90:cb3d968589d8	1488
Kojto	90:cb3d968589d8	1489	/** \brief System Reset
Kojto	90:cb3d968589d8	1490
Kojto	90:cb3d968589d8	1491	The function initiates a system reset request to reset the MCU.
Kojto	90:cb3d968589d8	1492	*/
Kojto	90:cb3d968589d8	1493	__STATIC_INLINE void NVIC_SystemReset(void)
Kojto	90:cb3d968589d8	1494	{
Kojto	90:cb3d968589d8	1495	__DSB(); /* Ensure all outstanding memory accesses included
Kojto	90:cb3d968589d8	1496	buffered write are completed before reset */
Kojto	90:cb3d968589d8	1497	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
Kojto	90:cb3d968589d8	1498	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Kojto	90:cb3d968589d8	1499	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
Kojto	90:cb3d968589d8	1500	__DSB(); /* Ensure completion of memory access */
Kojto	90:cb3d968589d8	1501	while(1); /* wait until reset */
Kojto	90:cb3d968589d8	1502	}
Kojto	90:cb3d968589d8	1503
Kojto	90:cb3d968589d8	1504	/@} end of CMSIS_Core_NVICFunctions /
Kojto	90:cb3d968589d8	1505
Kojto	90:cb3d968589d8	1506
Kojto	90:cb3d968589d8	1507
Kojto	90:cb3d968589d8	1508	/* ################################## SysTick function ############################################ */
Kojto	90:cb3d968589d8	1509	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	90:cb3d968589d8	1510	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Kojto	90:cb3d968589d8	1511	\brief Functions that configure the System.
Kojto	90:cb3d968589d8	1512	@{
Kojto	90:cb3d968589d8	1513	*/
Kojto	90:cb3d968589d8	1514
Kojto	90:cb3d968589d8	1515	#if (__Vendor_SysTickConfig == 0)
Kojto	90:cb3d968589d8	1516
Kojto	90:cb3d968589d8	1517	/** \brief System Tick Configuration
Kojto	90:cb3d968589d8	1518
Kojto	90:cb3d968589d8	1519	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Kojto	90:cb3d968589d8	1520	Counter is in free running mode to generate periodic interrupts.
Kojto	90:cb3d968589d8	1521
Kojto	90:cb3d968589d8	1522	\param [in] ticks Number of ticks between two interrupts.
Kojto	90:cb3d968589d8	1523
Kojto	90:cb3d968589d8	1524	\return 0 Function succeeded.
Kojto	90:cb3d968589d8	1525	\return 1 Function failed.
Kojto	90:cb3d968589d8	1526
Kojto	90:cb3d968589d8	1527	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Kojto	90:cb3d968589d8	1528	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Kojto	90:cb3d968589d8	1529	must contain a vendor-specific implementation of this function.
Kojto	90:cb3d968589d8	1530
Kojto	90:cb3d968589d8	1531	*/
Kojto	90:cb3d968589d8	1532	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Kojto	90:cb3d968589d8	1533	{
Kojto	90:cb3d968589d8	1534	if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Kojto	90:cb3d968589d8	1535
Kojto	90:cb3d968589d8	1536	SysTick->LOAD = ticks - 1; /* set reload register */
Kojto	90:cb3d968589d8	1537	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Kojto	90:cb3d968589d8	1538	SysTick->VAL = 0; /* Load the SysTick Counter Value */
Kojto	90:cb3d968589d8	1539	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Kojto	90:cb3d968589d8	1540	SysTick_CTRL_TICKINT_Msk \|
Kojto	90:cb3d968589d8	1541	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto	90:cb3d968589d8	1542	return (0); /* Function successful */
Kojto	90:cb3d968589d8	1543	}
Kojto	90:cb3d968589d8	1544
Kojto	90:cb3d968589d8	1545	#endif
Kojto	90:cb3d968589d8	1546
Kojto	90:cb3d968589d8	1547	/@} end of CMSIS_Core_SysTickFunctions /
Kojto	90:cb3d968589d8	1548
Kojto	90:cb3d968589d8	1549
Kojto	90:cb3d968589d8	1550
Kojto	90:cb3d968589d8	1551	/* ##################################### Debug In/Output function ########################################### */
Kojto	90:cb3d968589d8	1552	/** \ingroup CMSIS_Core_FunctionInterface
Kojto	90:cb3d968589d8	1553	\defgroup CMSIS_core_DebugFunctions ITM Functions
Kojto	90:cb3d968589d8	1554	\brief Functions that access the ITM debug interface.
Kojto	90:cb3d968589d8	1555	@{
Kojto	90:cb3d968589d8	1556	*/
Kojto	90:cb3d968589d8	1557
Kojto	90:cb3d968589d8	1558	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Kojto	90:cb3d968589d8	1559	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Kojto	90:cb3d968589d8	1560
Kojto	90:cb3d968589d8	1561
Kojto	90:cb3d968589d8	1562	/** \brief ITM Send Character
Kojto	90:cb3d968589d8	1563
Kojto	90:cb3d968589d8	1564	The function transmits a character via the ITM channel 0, and
Kojto	90:cb3d968589d8	1565	\li Just returns when no debugger is connected that has booked the output.
Kojto	90:cb3d968589d8	1566	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Kojto	90:cb3d968589d8	1567
Kojto	90:cb3d968589d8	1568	\param [in] ch Character to transmit.
Kojto	90:cb3d968589d8	1569
Kojto	90:cb3d968589d8	1570	\returns Character to transmit.
Kojto	90:cb3d968589d8	1571	*/
Kojto	90:cb3d968589d8	1572	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Kojto	90:cb3d968589d8	1573	{
Kojto	90:cb3d968589d8	1574	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
Kojto	90:cb3d968589d8	1575	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
Kojto	90:cb3d968589d8	1576	{
Kojto	90:cb3d968589d8	1577	while (ITM->PORT[0].u32 == 0);
Kojto	90:cb3d968589d8	1578	ITM->PORT[0].u8 = (uint8_t) ch;
Kojto	90:cb3d968589d8	1579	}
Kojto	90:cb3d968589d8	1580	return (ch);
Kojto	90:cb3d968589d8	1581	}
Kojto	90:cb3d968589d8	1582
Kojto	90:cb3d968589d8	1583
Kojto	90:cb3d968589d8	1584	/** \brief ITM Receive Character
Kojto	90:cb3d968589d8	1585
Kojto	90:cb3d968589d8	1586	The function inputs a character via the external variable \ref ITM_RxBuffer.
Kojto	90:cb3d968589d8	1587
Kojto	90:cb3d968589d8	1588	\return Received character.
Kojto	90:cb3d968589d8	1589	\return -1 No character pending.
Kojto	90:cb3d968589d8	1590	*/
Kojto	90:cb3d968589d8	1591	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Kojto	90:cb3d968589d8	1592	int32_t ch = -1; /* no character available */
Kojto	90:cb3d968589d8	1593
Kojto	90:cb3d968589d8	1594	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Kojto	90:cb3d968589d8	1595	ch = ITM_RxBuffer;
Kojto	90:cb3d968589d8	1596	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Kojto	90:cb3d968589d8	1597	}
Kojto	90:cb3d968589d8	1598
Kojto	90:cb3d968589d8	1599	return (ch);
Kojto	90:cb3d968589d8	1600	}
Kojto	90:cb3d968589d8	1601
Kojto	90:cb3d968589d8	1602
Kojto	90:cb3d968589d8	1603	/** \brief ITM Check Character
Kojto	90:cb3d968589d8	1604
Kojto	90:cb3d968589d8	1605	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Kojto	90:cb3d968589d8	1606
Kojto	90:cb3d968589d8	1607	\return 0 No character available.
Kojto	90:cb3d968589d8	1608	\return 1 Character available.
Kojto	90:cb3d968589d8	1609	*/
Kojto	90:cb3d968589d8	1610	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Kojto	90:cb3d968589d8	1611
Kojto	90:cb3d968589d8	1612	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Kojto	90:cb3d968589d8	1613	return (0); /* no character available */
Kojto	90:cb3d968589d8	1614	} else {
Kojto	90:cb3d968589d8	1615	return (1); /* character available */
Kojto	90:cb3d968589d8	1616	}
Kojto	90:cb3d968589d8	1617	}
Kojto	90:cb3d968589d8	1618
Kojto	90:cb3d968589d8	1619	/@} end of CMSIS_core_DebugFunctions /
Kojto	90:cb3d968589d8	1620
Kojto	90:cb3d968589d8	1621	#endif /* __CORE_CM3_H_DEPENDANT */
Kojto	90:cb3d968589d8	1622
Kojto	90:cb3d968589d8	1623	#endif /* __CMSIS_GENERIC */
Kojto	90:cb3d968589d8	1624
Kojto	90:cb3d968589d8	1625	#ifdef __cplusplus
Kojto	90:cb3d968589d8	1626	}
Kojto	90:cb3d968589d8	1627	#endif

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Type:	Program
Created:	03 May 2015
Imports:	4
Forks:	0
Commits:	100
Dependents:	0
Dependencies:	0
Followers:	2

TARGET_LPC824/core_cm3.h@90:cb3d968589d8, 2014-10-28 (annotated)

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