Egor Rumjantsev / mbed

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TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:
emilmont
Date:
Fri Feb 14 14:36:43 2014 +0000
Revision:
77:869cf507173a
Child:
81:7d30d6019079
Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_pwr.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.0.0RC2
emilmont 77:869cf507173a 6 * @date 04-February-2014
emilmont 77:869cf507173a 7 * @brief Header file of PWR HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_PWR_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_PWR_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup PWR
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58 /**
emilmont 77:869cf507173a 59 * @brief PWR PVD configuration structure definition
emilmont 77:869cf507173a 60 */
emilmont 77:869cf507173a 61 typedef struct
emilmont 77:869cf507173a 62 {
emilmont 77:869cf507173a 63 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
emilmont 77:869cf507173a 64 This parameter can be a value of @ref PWR_PVD_detection_level */
emilmont 77:869cf507173a 65
emilmont 77:869cf507173a 66 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
emilmont 77:869cf507173a 67 This parameter can be a value of @ref PWR_PVD_Mode */
emilmont 77:869cf507173a 68 }PWR_PVDTypeDef;
emilmont 77:869cf507173a 69
emilmont 77:869cf507173a 70 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 71 /* ------------- PWR registers bit address in the alias region ---------------*/
emilmont 77:869cf507173a 72 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
emilmont 77:869cf507173a 73
emilmont 77:869cf507173a 74 /* --- CR Register ---*/
emilmont 77:869cf507173a 75 /* Alias word address of DBP bit */
emilmont 77:869cf507173a 76 #define CR_OFFSET (PWR_OFFSET + 0x00)
emilmont 77:869cf507173a 77 #define DBP_BitNumber 0x08
emilmont 77:869cf507173a 78 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
emilmont 77:869cf507173a 79
emilmont 77:869cf507173a 80 /* Alias word address of PVDE bit */
emilmont 77:869cf507173a 81 #define PVDE_BitNumber 0x04
emilmont 77:869cf507173a 82 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
emilmont 77:869cf507173a 83
emilmont 77:869cf507173a 84 /* Alias word address of FPDS bit */
emilmont 77:869cf507173a 85 #define FPDS_BitNumber 0x09
emilmont 77:869cf507173a 86 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 /* Alias word address of PMODE bit */
emilmont 77:869cf507173a 89 #define PMODE_BitNumber 0x0E
emilmont 77:869cf507173a 90 #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
emilmont 77:869cf507173a 91
emilmont 77:869cf507173a 92 /* --- CSR Register ---*/
emilmont 77:869cf507173a 93 /* Alias word address of EWUP bit */
emilmont 77:869cf507173a 94 #define CSR_OFFSET (PWR_OFFSET + 0x04)
emilmont 77:869cf507173a 95 #define EWUP_BitNumber 0x08
emilmont 77:869cf507173a 96 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
emilmont 77:869cf507173a 97
emilmont 77:869cf507173a 98 /* Alias word address of BRE bit */
emilmont 77:869cf507173a 99 #define BRE_BitNumber 0x09
emilmont 77:869cf507173a 100 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
emilmont 77:869cf507173a 101
emilmont 77:869cf507173a 102 /** @defgroup PWR_Exported_Constants
emilmont 77:869cf507173a 103 * @{
emilmont 77:869cf507173a 104 */
emilmont 77:869cf507173a 105
emilmont 77:869cf507173a 106 /** @defgroup PWR_WakeUp_Pins
emilmont 77:869cf507173a 107 * @{
emilmont 77:869cf507173a 108 */
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
emilmont 77:869cf507173a 111 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
emilmont 77:869cf507173a 112 /**
emilmont 77:869cf507173a 113 * @}
emilmont 77:869cf507173a 114 */
emilmont 77:869cf507173a 115
emilmont 77:869cf507173a 116 /** @defgroup PWR_PVD_detection_level
emilmont 77:869cf507173a 117 * @{
emilmont 77:869cf507173a 118 */
emilmont 77:869cf507173a 119 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
emilmont 77:869cf507173a 120 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
emilmont 77:869cf507173a 121 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
emilmont 77:869cf507173a 122 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
emilmont 77:869cf507173a 123 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
emilmont 77:869cf507173a 124 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
emilmont 77:869cf507173a 125 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
emilmont 77:869cf507173a 126 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
emilmont 77:869cf507173a 127 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
emilmont 77:869cf507173a 128 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
emilmont 77:869cf507173a 129 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
emilmont 77:869cf507173a 130 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
emilmont 77:869cf507173a 131 /**
emilmont 77:869cf507173a 132 * @}
emilmont 77:869cf507173a 133 */
emilmont 77:869cf507173a 134
emilmont 77:869cf507173a 135 /** @defgroup PWR_PVD_Mode
emilmont 77:869cf507173a 136 * @{
emilmont 77:869cf507173a 137 */
emilmont 77:869cf507173a 138 #define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */
emilmont 77:869cf507173a 139 #define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */
emilmont 77:869cf507173a 140 #define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */
emilmont 77:869cf507173a 141 #define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
emilmont 77:869cf507173a 142 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \
emilmont 77:869cf507173a 143 ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING))
emilmont 77:869cf507173a 144 /**
emilmont 77:869cf507173a 145 * @}
emilmont 77:869cf507173a 146 */
emilmont 77:869cf507173a 147
emilmont 77:869cf507173a 148 /** @defgroup PWR_Regulator_state_in_STOP_mode
emilmont 77:869cf507173a 149 * @{
emilmont 77:869cf507173a 150 */
emilmont 77:869cf507173a 151 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
emilmont 77:869cf507173a 152 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
emilmont 77:869cf507173a 153
emilmont 77:869cf507173a 154 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
emilmont 77:869cf507173a 155 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
emilmont 77:869cf507173a 156 /**
emilmont 77:869cf507173a 157 * @}
emilmont 77:869cf507173a 158 */
emilmont 77:869cf507173a 159
emilmont 77:869cf507173a 160 /** @defgroup PWR_SLEEP_mode_entry
emilmont 77:869cf507173a 161 * @{
emilmont 77:869cf507173a 162 */
emilmont 77:869cf507173a 163 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
emilmont 77:869cf507173a 164 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
emilmont 77:869cf507173a 165 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
emilmont 77:869cf507173a 166 /**
emilmont 77:869cf507173a 167 * @}
emilmont 77:869cf507173a 168 */
emilmont 77:869cf507173a 169
emilmont 77:869cf507173a 170 /** @defgroup PWR_STOP_mode_entry
emilmont 77:869cf507173a 171 * @{
emilmont 77:869cf507173a 172 */
emilmont 77:869cf507173a 173 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
emilmont 77:869cf507173a 174 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
emilmont 77:869cf507173a 175 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
emilmont 77:869cf507173a 176 /**
emilmont 77:869cf507173a 177 * @}
emilmont 77:869cf507173a 178 */
emilmont 77:869cf507173a 179
emilmont 77:869cf507173a 180 /** @defgroup PWR_Regulator_Voltage_Scale
emilmont 77:869cf507173a 181 * @{
emilmont 77:869cf507173a 182 */
emilmont 77:869cf507173a 183 #define PWR_REGULATOR_VOLTAGE_SCALE1 ((uint32_t)0x0000C000)
emilmont 77:869cf507173a 184 #define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 185 #define PWR_REGULATOR_VOLTAGE_SCALE3 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 186 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
emilmont 77:869cf507173a 187 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
emilmont 77:869cf507173a 188 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
emilmont 77:869cf507173a 189 /**
emilmont 77:869cf507173a 190 * @}
emilmont 77:869cf507173a 191 */
emilmont 77:869cf507173a 192
emilmont 77:869cf507173a 193 /** @defgroup PWR_Flag
emilmont 77:869cf507173a 194 * @{
emilmont 77:869cf507173a 195 */
emilmont 77:869cf507173a 196 #define PWR_FLAG_WU PWR_CSR_WUF
emilmont 77:869cf507173a 197 #define PWR_FLAG_SB PWR_CSR_SBF
emilmont 77:869cf507173a 198 #define PWR_FLAG_PVDO PWR_CSR_PVDO
emilmont 77:869cf507173a 199 #define PWR_FLAG_BRR PWR_CSR_BRR
emilmont 77:869cf507173a 200 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
emilmont 77:869cf507173a 201
emilmont 77:869cf507173a 202 /**
emilmont 77:869cf507173a 203 * @}
emilmont 77:869cf507173a 204 */
emilmont 77:869cf507173a 205
emilmont 77:869cf507173a 206 /**
emilmont 77:869cf507173a 207 * @}
emilmont 77:869cf507173a 208 */
emilmont 77:869cf507173a 209
emilmont 77:869cf507173a 210 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 211
emilmont 77:869cf507173a 212 /** @brief macros configure the main internal regulator output voltage.
emilmont 77:869cf507173a 213 * @param __REGULATOR__: specifies the regulator output voltage to achieve
emilmont 77:869cf507173a 214 * a tradeoff between performance and power consumption when the device does
emilmont 77:869cf507173a 215 * not operate at the maximum frequency (refer to the datasheets for more details).
emilmont 77:869cf507173a 216 * This parameter can be one of the following values:
emilmont 77:869cf507173a 217 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
emilmont 77:869cf507173a 218 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
emilmont 77:869cf507173a 219 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
emilmont 77:869cf507173a 220 * @retval None
emilmont 77:869cf507173a 221 */
emilmont 77:869cf507173a 222 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
emilmont 77:869cf507173a 223
emilmont 77:869cf507173a 224 /** @brief Check PWR flag is set or not.
emilmont 77:869cf507173a 225 * @param __FLAG__: specifies the flag to check.
emilmont 77:869cf507173a 226 * This parameter can be one of the following values:
emilmont 77:869cf507173a 227 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
emilmont 77:869cf507173a 228 * was received from the WKUP pin or from the RTC alarm (Alarm A
emilmont 77:869cf507173a 229 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
emilmont 77:869cf507173a 230 * An additional wakeup event is detected if the WKUP pin is enabled
emilmont 77:869cf507173a 231 * (by setting the EWUP bit) when the WKUP pin level is already high.
emilmont 77:869cf507173a 232 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
emilmont 77:869cf507173a 233 * resumed from StandBy mode.
emilmont 77:869cf507173a 234 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
emilmont 77:869cf507173a 235 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
emilmont 77:869cf507173a 236 * For this reason, this bit is equal to 0 after Standby or reset
emilmont 77:869cf507173a 237 * until the PVDE bit is set.
emilmont 77:869cf507173a 238 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
emilmont 77:869cf507173a 239 * when the device wakes up from Standby mode or by a system reset
emilmont 77:869cf507173a 240 * or power reset.
emilmont 77:869cf507173a 241 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
emilmont 77:869cf507173a 242 * scaling output selection is ready.
emilmont 77:869cf507173a 243 * @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont 77:869cf507173a 244 */
emilmont 77:869cf507173a 245 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
emilmont 77:869cf507173a 246
emilmont 77:869cf507173a 247 /** @brief Clear the PWR's pending flags.
emilmont 77:869cf507173a 248 * @param __FLAG__: specifies the flag to clear.
emilmont 77:869cf507173a 249 * This parameter can be one of the following values:
emilmont 77:869cf507173a 250 * @arg PWR_FLAG_WU: Wake Up flag
emilmont 77:869cf507173a 251 * @arg PWR_FLAG_SB: StandBy flag
emilmont 77:869cf507173a 252 */
emilmont 77:869cf507173a 253 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
emilmont 77:869cf507173a 254
emilmont 77:869cf507173a 255 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
emilmont 77:869cf507173a 256 /**
emilmont 77:869cf507173a 257 * @brief Enable the PVD Exti Line.
emilmont 77:869cf507173a 258 * @param __EXTILINE__: specifies the PVD Exti sources to be enabled.
emilmont 77:869cf507173a 259 * This parameter can be:
emilmont 77:869cf507173a 260 * @arg PWR_EXTI_LINE_PVD
emilmont 77:869cf507173a 261 * @retval None.
emilmont 77:869cf507173a 262 */
emilmont 77:869cf507173a 263 #define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__))
emilmont 77:869cf507173a 264
emilmont 77:869cf507173a 265 /**
emilmont 77:869cf507173a 266 * @brief Disable the PVD EXTI Line.
emilmont 77:869cf507173a 267 * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled.
emilmont 77:869cf507173a 268 * This parameter can be:
emilmont 77:869cf507173a 269 * @arg PWR_EXTI_LINE_PVD
emilmont 77:869cf507173a 270 * @retval None.
emilmont 77:869cf507173a 271 */
emilmont 77:869cf507173a 272 #define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__))
emilmont 77:869cf507173a 273
emilmont 77:869cf507173a 274 /**
emilmont 77:869cf507173a 275 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
emilmont 77:869cf507173a 276 * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
emilmont 77:869cf507173a 277 * This parameter can be:
emilmont 77:869cf507173a 278 * @arg PWR_EXTI_LINE_PVD
emilmont 77:869cf507173a 279 * @retval EXTI PVD Line Status.
emilmont 77:869cf507173a 280 */
emilmont 77:869cf507173a 281 #define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__))
emilmont 77:869cf507173a 282
emilmont 77:869cf507173a 283 /**
emilmont 77:869cf507173a 284 * @brief Clear the PVD Exti flag.
emilmont 77:869cf507173a 285 * @param __EXTILINE__: specifies the PVD Exti sources to be cleared.
emilmont 77:869cf507173a 286 * This parameter can be:
emilmont 77:869cf507173a 287 * @arg PWR_EXTI_LINE_PVD
emilmont 77:869cf507173a 288 * @retval None.
emilmont 77:869cf507173a 289 */
emilmont 77:869cf507173a 290 #define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__))
emilmont 77:869cf507173a 291
emilmont 77:869cf507173a 292
emilmont 77:869cf507173a 293 /* Include PWR HAL Extension module */
emilmont 77:869cf507173a 294 #include "stm32f4xx_hal_pwr_ex.h"
emilmont 77:869cf507173a 295
emilmont 77:869cf507173a 296 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 297
emilmont 77:869cf507173a 298 /* Initialization and de-initialization functions *******************************/
emilmont 77:869cf507173a 299 void HAL_PWR_DeInit(void);
emilmont 77:869cf507173a 300 void HAL_PWR_EnableBkUpAccess(void);
emilmont 77:869cf507173a 301 void HAL_PWR_DisableBkUpAccess(void);
emilmont 77:869cf507173a 302
emilmont 77:869cf507173a 303 /* Peripheral Control functions ************************************************/
emilmont 77:869cf507173a 304 void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
emilmont 77:869cf507173a 305 void HAL_PWR_EnablePVD(void);
emilmont 77:869cf507173a 306 void HAL_PWR_DisablePVD(void);
emilmont 77:869cf507173a 307 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
emilmont 77:869cf507173a 308 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
emilmont 77:869cf507173a 309
emilmont 77:869cf507173a 310 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
emilmont 77:869cf507173a 311 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
emilmont 77:869cf507173a 312 void HAL_PWR_EnterSTANDBYMode(void);
emilmont 77:869cf507173a 313
emilmont 77:869cf507173a 314 void HAL_PWR_PVD_IRQHandler(void);
emilmont 77:869cf507173a 315 __weak void HAL_PWR_PVDCallback(void);
emilmont 77:869cf507173a 316
emilmont 77:869cf507173a 317
emilmont 77:869cf507173a 318 /**
emilmont 77:869cf507173a 319 * @}
emilmont 77:869cf507173a 320 */
emilmont 77:869cf507173a 321
emilmont 77:869cf507173a 322 /**
emilmont 77:869cf507173a 323 * @}
emilmont 77:869cf507173a 324 */
emilmont 77:869cf507173a 325
emilmont 77:869cf507173a 326 #ifdef __cplusplus
emilmont 77:869cf507173a 327 }
emilmont 77:869cf507173a 328 #endif
emilmont 77:869cf507173a 329
emilmont 77:869cf507173a 330
emilmont 77:869cf507173a 331 #endif /* __STM32F4xx_HAL_PWR_H */
emilmont 77:869cf507173a 332
emilmont 77:869cf507173a 333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/