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TARGET_RZ_A1H/pl310.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
92:4fc01daae5a5 
12

Who changed what in which revision?

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bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file pl310.h
bogdanm 92:4fc01daae5a5 3 * @brief Implementation of pl310 functions
bogdanm 92:4fc01daae5a5 4 * @version
bogdanm 92:4fc01daae5a5 5 * @date 11 June 2013
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
bogdanm 92:4fc01daae5a5 10 /* Copyright (c) 2011 - 2013 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37 #ifndef __PL310
bogdanm 92:4fc01daae5a5 38 #define __PL310
bogdanm 92:4fc01daae5a5 39
bogdanm 92:4fc01daae5a5 40 typedef struct
bogdanm 92:4fc01daae5a5 41 {
bogdanm 92:4fc01daae5a5 42 __I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */
bogdanm 92:4fc01daae5a5 43 __I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */
bogdanm 92:4fc01daae5a5 44 uint32_t RESERVED0[0x3e];
bogdanm 92:4fc01daae5a5 45 __IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */
bogdanm 92:4fc01daae5a5 46 __IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */
bogdanm 92:4fc01daae5a5 47 uint32_t RESERVED1[0x3e];
bogdanm 92:4fc01daae5a5 48 __IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */
bogdanm 92:4fc01daae5a5 49 __IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */
bogdanm 92:4fc01daae5a5 50 __IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */
bogdanm 92:4fc01daae5a5 51 uint32_t RESERVED2[0x2];
bogdanm 92:4fc01daae5a5 52 __IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */
bogdanm 92:4fc01daae5a5 53 __I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */
bogdanm 92:4fc01daae5a5 54 __I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */
bogdanm 92:4fc01daae5a5 55 __O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */
bogdanm 92:4fc01daae5a5 56 uint32_t RESERVED3[0x143];
bogdanm 92:4fc01daae5a5 57 __IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */
bogdanm 92:4fc01daae5a5 58 uint32_t RESERVED4[0xf];
bogdanm 92:4fc01daae5a5 59 __IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */
bogdanm 92:4fc01daae5a5 60 uint32_t RESERVED6[2];
bogdanm 92:4fc01daae5a5 61 __IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */
bogdanm 92:4fc01daae5a5 62 uint32_t RESERVED5[0xc];
bogdanm 92:4fc01daae5a5 63 __IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */
bogdanm 92:4fc01daae5a5 64 uint32_t RESERVED7[1];
bogdanm 92:4fc01daae5a5 65 __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */
bogdanm 92:4fc01daae5a5 66 __IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */
bogdanm 92:4fc01daae5a5 67 uint32_t RESERVED8[0xc];
bogdanm 92:4fc01daae5a5 68 __IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */
bogdanm 92:4fc01daae5a5 69 uint32_t RESERVED9[1];
bogdanm 92:4fc01daae5a5 70 __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
bogdanm 92:4fc01daae5a5 71 __IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */
bogdanm 92:4fc01daae5a5 72 uint32_t RESERVED10[0x40];
bogdanm 92:4fc01daae5a5 73 __IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */
bogdanm 92:4fc01daae5a5 74 __IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */
bogdanm 92:4fc01daae5a5 75 __IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */
bogdanm 92:4fc01daae5a5 76 __IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */
bogdanm 92:4fc01daae5a5 77 __IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */
bogdanm 92:4fc01daae5a5 78 __IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */
bogdanm 92:4fc01daae5a5 79 __IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */
bogdanm 92:4fc01daae5a5 80 __IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */
bogdanm 92:4fc01daae5a5 81 __IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */
bogdanm 92:4fc01daae5a5 82 __IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */
bogdanm 92:4fc01daae5a5 83 __IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */
bogdanm 92:4fc01daae5a5 84 __IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */
bogdanm 92:4fc01daae5a5 85 __IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */
bogdanm 92:4fc01daae5a5 86 __IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */
bogdanm 92:4fc01daae5a5 87 __IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */
bogdanm 92:4fc01daae5a5 88 __IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */
bogdanm 92:4fc01daae5a5 89 uint32_t RESERVED11[0x4];
bogdanm 92:4fc01daae5a5 90 __IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */
bogdanm 92:4fc01daae5a5 91 __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */
bogdanm 92:4fc01daae5a5 92 uint32_t RESERVED12[0xaa];
bogdanm 92:4fc01daae5a5 93 __IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */
bogdanm 92:4fc01daae5a5 94 __IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */
bogdanm 92:4fc01daae5a5 95 uint32_t RESERVED13[0xce];
bogdanm 92:4fc01daae5a5 96 __IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */
bogdanm 92:4fc01daae5a5 97
bogdanm 92:4fc01daae5a5 98 } PL310_TypeDef;
bogdanm 92:4fc01daae5a5 99
bogdanm 92:4fc01daae5a5 100 #define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102 extern int PL310_GetID (void);
bogdanm 92:4fc01daae5a5 103 extern int PL310_GetType (void);
bogdanm 92:4fc01daae5a5 104 extern void PL310_InvAllByWay (void);
bogdanm 92:4fc01daae5a5 105 extern void PL310_CleanInvAllByWay(void);
bogdanm 92:4fc01daae5a5 106 extern void PL310_Enable(void);
bogdanm 92:4fc01daae5a5 107 extern void PL310_Disable(void);
bogdanm 92:4fc01daae5a5 108 extern void PL310_InvPa (void *);
bogdanm 92:4fc01daae5a5 109 extern void PL310_CleanPa (void *);
bogdanm 92:4fc01daae5a5 110 extern void PL310_CleanInvPa (void *);
bogdanm 92:4fc01daae5a5 111
bogdanm 92:4fc01daae5a5 112 #endif
bogdanm 92:4fc01daae5a5 113
bogdanm 92:4fc01daae5a5 114