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TARGET_RZ_A1H/pfv_iodefine.h@99:7f6c6de930c0, 2015-05-03 (annotated)
- Committer:
- Mikchel
- Date:
- Sun May 03 16:04:42 2015 +0000
- Revision:
- 99:7f6c6de930c0
- Parent:
- 92:4fc01daae5a5
12
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 92:4fc01daae5a5 | 1 | /******************************************************************************* |
bogdanm | 92:4fc01daae5a5 | 2 | * DISCLAIMER |
bogdanm | 92:4fc01daae5a5 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
bogdanm | 92:4fc01daae5a5 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
bogdanm | 92:4fc01daae5a5 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
bogdanm | 92:4fc01daae5a5 | 6 | * all applicable laws, including copyright laws. |
bogdanm | 92:4fc01daae5a5 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
bogdanm | 92:4fc01daae5a5 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
bogdanm | 92:4fc01daae5a5 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
bogdanm | 92:4fc01daae5a5 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
bogdanm | 92:4fc01daae5a5 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
bogdanm | 92:4fc01daae5a5 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
bogdanm | 92:4fc01daae5a5 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
bogdanm | 92:4fc01daae5a5 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
bogdanm | 92:4fc01daae5a5 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
bogdanm | 92:4fc01daae5a5 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
bogdanm | 92:4fc01daae5a5 | 17 | * and to discontinue the availability of this software. By using this software, |
bogdanm | 92:4fc01daae5a5 | 18 | * you agree to the additional terms and conditions found by accessing the |
bogdanm | 92:4fc01daae5a5 | 19 | * following link: |
bogdanm | 92:4fc01daae5a5 | 20 | * http://www.renesas.com/disclaimer* |
bogdanm | 92:4fc01daae5a5 | 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. |
bogdanm | 92:4fc01daae5a5 | 22 | *******************************************************************************/ |
bogdanm | 92:4fc01daae5a5 | 23 | /******************************************************************************* |
bogdanm | 92:4fc01daae5a5 | 24 | * File Name : pfv_iodefine.h |
bogdanm | 92:4fc01daae5a5 | 25 | * $Rev: $ |
bogdanm | 92:4fc01daae5a5 | 26 | * $Date:: $ |
bogdanm | 92:4fc01daae5a5 | 27 | * Description : Definition of I/O Register (V1.00a) |
bogdanm | 92:4fc01daae5a5 | 28 | ******************************************************************************/ |
bogdanm | 92:4fc01daae5a5 | 29 | #ifndef PFV_IODEFINE_H |
bogdanm | 92:4fc01daae5a5 | 30 | #define PFV_IODEFINE_H |
bogdanm | 92:4fc01daae5a5 | 31 | /* ->SEC M1.10.1 : Not magic number */ |
bogdanm | 92:4fc01daae5a5 | 32 | |
bogdanm | 92:4fc01daae5a5 | 33 | struct st_pfv |
bogdanm | 92:4fc01daae5a5 | 34 | { /* PFV */ |
bogdanm | 92:4fc01daae5a5 | 35 | volatile uint32_t PFVCR; /* PFVCR */ |
bogdanm | 92:4fc01daae5a5 | 36 | volatile uint32_t PFVICR; /* PFVICR */ |
bogdanm | 92:4fc01daae5a5 | 37 | volatile uint32_t PFVISR; /* PFVISR */ |
bogdanm | 92:4fc01daae5a5 | 38 | volatile uint8_t dummy1[20]; /* */ |
bogdanm | 92:4fc01daae5a5 | 39 | #define PFVID_COUNT 8 |
bogdanm | 92:4fc01daae5a5 | 40 | volatile uint32_t PFVID0; /* PFVID0 */ |
bogdanm | 92:4fc01daae5a5 | 41 | volatile uint32_t PFVID1; /* PFVID1 */ |
bogdanm | 92:4fc01daae5a5 | 42 | volatile uint32_t PFVID2; /* PFVID2 */ |
bogdanm | 92:4fc01daae5a5 | 43 | volatile uint32_t PFVID3; /* PFVID3 */ |
bogdanm | 92:4fc01daae5a5 | 44 | volatile uint32_t PFVID4; /* PFVID4 */ |
bogdanm | 92:4fc01daae5a5 | 45 | volatile uint32_t PFVID5; /* PFVID5 */ |
bogdanm | 92:4fc01daae5a5 | 46 | volatile uint32_t PFVID6; /* PFVID6 */ |
bogdanm | 92:4fc01daae5a5 | 47 | volatile uint32_t PFVID7; /* PFVID7 */ |
bogdanm | 92:4fc01daae5a5 | 48 | #define PFVOD_COUNT 8 |
bogdanm | 92:4fc01daae5a5 | 49 | volatile uint32_t PFVOD0; /* PFVOD0 */ |
bogdanm | 92:4fc01daae5a5 | 50 | volatile uint32_t PFVOD1; /* PFVOD1 */ |
bogdanm | 92:4fc01daae5a5 | 51 | volatile uint32_t PFVOD2; /* PFVOD2 */ |
bogdanm | 92:4fc01daae5a5 | 52 | volatile uint32_t PFVOD3; /* PFVOD3 */ |
bogdanm | 92:4fc01daae5a5 | 53 | volatile uint32_t PFVOD4; /* PFVOD4 */ |
bogdanm | 92:4fc01daae5a5 | 54 | volatile uint32_t PFVOD5; /* PFVOD5 */ |
bogdanm | 92:4fc01daae5a5 | 55 | volatile uint32_t PFVOD6; /* PFVOD6 */ |
bogdanm | 92:4fc01daae5a5 | 56 | volatile uint32_t PFVOD7; /* PFVOD7 */ |
bogdanm | 92:4fc01daae5a5 | 57 | volatile uint8_t dummy2[4]; /* */ |
bogdanm | 92:4fc01daae5a5 | 58 | volatile uint32_t PFVIFSR; /* PFVIFSR */ |
bogdanm | 92:4fc01daae5a5 | 59 | volatile uint32_t PFVOFSR; /* PFVOFSR */ |
bogdanm | 92:4fc01daae5a5 | 60 | volatile uint32_t PFVACR; /* PFVACR */ |
bogdanm | 92:4fc01daae5a5 | 61 | volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */ |
bogdanm | 92:4fc01daae5a5 | 62 | volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */ |
bogdanm | 92:4fc01daae5a5 | 63 | volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */ |
bogdanm | 92:4fc01daae5a5 | 64 | volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */ |
bogdanm | 92:4fc01daae5a5 | 65 | volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */ |
bogdanm | 92:4fc01daae5a5 | 66 | volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */ |
bogdanm | 92:4fc01daae5a5 | 67 | volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */ |
bogdanm | 92:4fc01daae5a5 | 68 | volatile uint32_t PFVSZR; /* PFVSZR */ |
bogdanm | 92:4fc01daae5a5 | 69 | }; |
bogdanm | 92:4fc01daae5a5 | 70 | |
bogdanm | 92:4fc01daae5a5 | 71 | |
bogdanm | 92:4fc01daae5a5 | 72 | #define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ |
bogdanm | 92:4fc01daae5a5 | 73 | #define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ |
bogdanm | 92:4fc01daae5a5 | 74 | |
bogdanm | 92:4fc01daae5a5 | 75 | |
bogdanm | 92:4fc01daae5a5 | 76 | /* Start of channnel array defines of PFV */ |
bogdanm | 92:4fc01daae5a5 | 77 | |
bogdanm | 92:4fc01daae5a5 | 78 | /* Channnel array defines of PFV */ |
bogdanm | 92:4fc01daae5a5 | 79 | /*(Sample) value = PFV[ channel ]->PFVCR; */ |
bogdanm | 92:4fc01daae5a5 | 80 | #define PFV_COUNT 2 |
bogdanm | 92:4fc01daae5a5 | 81 | #define PFV_ADDRESS_LIST \ |
bogdanm | 92:4fc01daae5a5 | 82 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
bogdanm | 92:4fc01daae5a5 | 83 | &PFV0, &PFV1 \ |
bogdanm | 92:4fc01daae5a5 | 84 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
bogdanm | 92:4fc01daae5a5 | 85 | |
bogdanm | 92:4fc01daae5a5 | 86 | /* End of channnel array defines of PFV */ |
bogdanm | 92:4fc01daae5a5 | 87 | |
bogdanm | 92:4fc01daae5a5 | 88 | |
bogdanm | 92:4fc01daae5a5 | 89 | #define PFV0PFVCR PFV0.PFVCR |
bogdanm | 92:4fc01daae5a5 | 90 | #define PFV0PFVICR PFV0.PFVICR |
bogdanm | 92:4fc01daae5a5 | 91 | #define PFV0PFVISR PFV0.PFVISR |
bogdanm | 92:4fc01daae5a5 | 92 | #define PFV0PFVID0 PFV0.PFVID0 |
bogdanm | 92:4fc01daae5a5 | 93 | #define PFV0PFVID1 PFV0.PFVID1 |
bogdanm | 92:4fc01daae5a5 | 94 | #define PFV0PFVID2 PFV0.PFVID2 |
bogdanm | 92:4fc01daae5a5 | 95 | #define PFV0PFVID3 PFV0.PFVID3 |
bogdanm | 92:4fc01daae5a5 | 96 | #define PFV0PFVID4 PFV0.PFVID4 |
bogdanm | 92:4fc01daae5a5 | 97 | #define PFV0PFVID5 PFV0.PFVID5 |
bogdanm | 92:4fc01daae5a5 | 98 | #define PFV0PFVID6 PFV0.PFVID6 |
bogdanm | 92:4fc01daae5a5 | 99 | #define PFV0PFVID7 PFV0.PFVID7 |
bogdanm | 92:4fc01daae5a5 | 100 | #define PFV0PFVOD0 PFV0.PFVOD0 |
bogdanm | 92:4fc01daae5a5 | 101 | #define PFV0PFVOD1 PFV0.PFVOD1 |
bogdanm | 92:4fc01daae5a5 | 102 | #define PFV0PFVOD2 PFV0.PFVOD2 |
bogdanm | 92:4fc01daae5a5 | 103 | #define PFV0PFVOD3 PFV0.PFVOD3 |
bogdanm | 92:4fc01daae5a5 | 104 | #define PFV0PFVOD4 PFV0.PFVOD4 |
bogdanm | 92:4fc01daae5a5 | 105 | #define PFV0PFVOD5 PFV0.PFVOD5 |
bogdanm | 92:4fc01daae5a5 | 106 | #define PFV0PFVOD6 PFV0.PFVOD6 |
bogdanm | 92:4fc01daae5a5 | 107 | #define PFV0PFVOD7 PFV0.PFVOD7 |
bogdanm | 92:4fc01daae5a5 | 108 | #define PFV0PFVIFSR PFV0.PFVIFSR |
bogdanm | 92:4fc01daae5a5 | 109 | #define PFV0PFVOFSR PFV0.PFVOFSR |
bogdanm | 92:4fc01daae5a5 | 110 | #define PFV0PFVACR PFV0.PFVACR |
bogdanm | 92:4fc01daae5a5 | 111 | #define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE |
bogdanm | 92:4fc01daae5a5 | 112 | #define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0 |
bogdanm | 92:4fc01daae5a5 | 113 | #define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1 |
bogdanm | 92:4fc01daae5a5 | 114 | #define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0 |
bogdanm | 92:4fc01daae5a5 | 115 | #define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1 |
bogdanm | 92:4fc01daae5a5 | 116 | #define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0 |
bogdanm | 92:4fc01daae5a5 | 117 | #define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1 |
bogdanm | 92:4fc01daae5a5 | 118 | #define PFV0PFVSZR PFV0.PFVSZR |
bogdanm | 92:4fc01daae5a5 | 119 | #define PFV1PFVCR PFV1.PFVCR |
bogdanm | 92:4fc01daae5a5 | 120 | #define PFV1PFVICR PFV1.PFVICR |
bogdanm | 92:4fc01daae5a5 | 121 | #define PFV1PFVISR PFV1.PFVISR |
bogdanm | 92:4fc01daae5a5 | 122 | #define PFV1PFVID0 PFV1.PFVID0 |
bogdanm | 92:4fc01daae5a5 | 123 | #define PFV1PFVID1 PFV1.PFVID1 |
bogdanm | 92:4fc01daae5a5 | 124 | #define PFV1PFVID2 PFV1.PFVID2 |
bogdanm | 92:4fc01daae5a5 | 125 | #define PFV1PFVID3 PFV1.PFVID3 |
bogdanm | 92:4fc01daae5a5 | 126 | #define PFV1PFVID4 PFV1.PFVID4 |
bogdanm | 92:4fc01daae5a5 | 127 | #define PFV1PFVID5 PFV1.PFVID5 |
bogdanm | 92:4fc01daae5a5 | 128 | #define PFV1PFVID6 PFV1.PFVID6 |
bogdanm | 92:4fc01daae5a5 | 129 | #define PFV1PFVID7 PFV1.PFVID7 |
bogdanm | 92:4fc01daae5a5 | 130 | #define PFV1PFVOD0 PFV1.PFVOD0 |
bogdanm | 92:4fc01daae5a5 | 131 | #define PFV1PFVOD1 PFV1.PFVOD1 |
bogdanm | 92:4fc01daae5a5 | 132 | #define PFV1PFVOD2 PFV1.PFVOD2 |
bogdanm | 92:4fc01daae5a5 | 133 | #define PFV1PFVOD3 PFV1.PFVOD3 |
bogdanm | 92:4fc01daae5a5 | 134 | #define PFV1PFVOD4 PFV1.PFVOD4 |
bogdanm | 92:4fc01daae5a5 | 135 | #define PFV1PFVOD5 PFV1.PFVOD5 |
bogdanm | 92:4fc01daae5a5 | 136 | #define PFV1PFVOD6 PFV1.PFVOD6 |
bogdanm | 92:4fc01daae5a5 | 137 | #define PFV1PFVOD7 PFV1.PFVOD7 |
bogdanm | 92:4fc01daae5a5 | 138 | #define PFV1PFVIFSR PFV1.PFVIFSR |
bogdanm | 92:4fc01daae5a5 | 139 | #define PFV1PFVOFSR PFV1.PFVOFSR |
bogdanm | 92:4fc01daae5a5 | 140 | #define PFV1PFVACR PFV1.PFVACR |
bogdanm | 92:4fc01daae5a5 | 141 | #define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE |
bogdanm | 92:4fc01daae5a5 | 142 | #define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0 |
bogdanm | 92:4fc01daae5a5 | 143 | #define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1 |
bogdanm | 92:4fc01daae5a5 | 144 | #define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0 |
bogdanm | 92:4fc01daae5a5 | 145 | #define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1 |
bogdanm | 92:4fc01daae5a5 | 146 | #define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0 |
bogdanm | 92:4fc01daae5a5 | 147 | #define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1 |
bogdanm | 92:4fc01daae5a5 | 148 | #define PFV1PFVSZR PFV1.PFVSZR |
bogdanm | 92:4fc01daae5a5 | 149 | /* <-SEC M1.10.1 */ |
bogdanm | 92:4fc01daae5a5 | 150 | #endif |