Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

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TARGET_RZ_A1H/mtu2_iodefine.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
92:4fc01daae5a5 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer*
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : mtu2_iodefine.h
bogdanm 92:4fc01daae5a5 25 * $Rev: $
bogdanm 92:4fc01daae5a5 26 * $Date:: $
bogdanm 92:4fc01daae5a5 27 * Description : Definition of I/O Register (V1.00a)
bogdanm 92:4fc01daae5a5 28 ******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef MTU2_IODEFINE_H
bogdanm 92:4fc01daae5a5 30 #define MTU2_IODEFINE_H
bogdanm 92:4fc01daae5a5 31 /* ->SEC M1.10.1 : Not magic number */
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 struct st_mtu2
bogdanm 92:4fc01daae5a5 34 { /* MTU2 */
bogdanm 92:4fc01daae5a5 35 volatile uint8_t TCR_2; /* TCR_2 */
bogdanm 92:4fc01daae5a5 36 volatile uint8_t TMDR_2; /* TMDR_2 */
bogdanm 92:4fc01daae5a5 37 volatile uint8_t TIOR_2; /* TIOR_2 */
bogdanm 92:4fc01daae5a5 38 volatile uint8_t dummy520[1]; /* */
bogdanm 92:4fc01daae5a5 39 volatile uint8_t TIER_2; /* TIER_2 */
bogdanm 92:4fc01daae5a5 40 volatile uint8_t TSR_2; /* TSR_2 */
bogdanm 92:4fc01daae5a5 41 volatile uint16_t TCNT_2; /* TCNT_2 */
bogdanm 92:4fc01daae5a5 42 volatile uint16_t TGRA_2; /* TGRA_2 */
bogdanm 92:4fc01daae5a5 43 volatile uint16_t TGRB_2; /* TGRB_2 */
bogdanm 92:4fc01daae5a5 44 volatile uint8_t dummy521[500]; /* */
bogdanm 92:4fc01daae5a5 45 volatile uint8_t TCR_3; /* TCR_3 */
bogdanm 92:4fc01daae5a5 46 volatile uint8_t TCR_4; /* TCR_4 */
bogdanm 92:4fc01daae5a5 47 volatile uint8_t TMDR_3; /* TMDR_3 */
bogdanm 92:4fc01daae5a5 48 volatile uint8_t TMDR_4; /* TMDR_4 */
bogdanm 92:4fc01daae5a5 49 volatile uint8_t TIORH_3; /* TIORH_3 */
bogdanm 92:4fc01daae5a5 50 volatile uint8_t TIORL_3; /* TIORL_3 */
bogdanm 92:4fc01daae5a5 51 volatile uint8_t TIORH_4; /* TIORH_4 */
bogdanm 92:4fc01daae5a5 52 volatile uint8_t TIORL_4; /* TIORL_4 */
bogdanm 92:4fc01daae5a5 53 volatile uint8_t TIER_3; /* TIER_3 */
bogdanm 92:4fc01daae5a5 54 volatile uint8_t TIER_4; /* TIER_4 */
bogdanm 92:4fc01daae5a5 55 volatile uint8_t TOER; /* TOER */
bogdanm 92:4fc01daae5a5 56 volatile uint8_t dummy522[2]; /* */
bogdanm 92:4fc01daae5a5 57 volatile uint8_t TGCR; /* TGCR */
bogdanm 92:4fc01daae5a5 58 volatile uint8_t TOCR1; /* TOCR1 */
bogdanm 92:4fc01daae5a5 59 volatile uint8_t TOCR2; /* TOCR2 */
bogdanm 92:4fc01daae5a5 60 volatile uint16_t TCNT_3; /* TCNT_3 */
bogdanm 92:4fc01daae5a5 61 volatile uint16_t TCNT_4; /* TCNT_4 */
bogdanm 92:4fc01daae5a5 62 volatile uint16_t TCDR; /* TCDR */
bogdanm 92:4fc01daae5a5 63 volatile uint16_t TDDR; /* TDDR */
bogdanm 92:4fc01daae5a5 64 volatile uint16_t TGRA_3; /* TGRA_3 */
bogdanm 92:4fc01daae5a5 65 volatile uint16_t TGRB_3; /* TGRB_3 */
bogdanm 92:4fc01daae5a5 66 volatile uint16_t TGRA_4; /* TGRA_4 */
bogdanm 92:4fc01daae5a5 67 volatile uint16_t TGRB_4; /* TGRB_4 */
bogdanm 92:4fc01daae5a5 68 volatile uint16_t TCNTS; /* TCNTS */
bogdanm 92:4fc01daae5a5 69 volatile uint16_t TCBR; /* TCBR */
bogdanm 92:4fc01daae5a5 70 volatile uint16_t TGRC_3; /* TGRC_3 */
bogdanm 92:4fc01daae5a5 71 volatile uint16_t TGRD_3; /* TGRD_3 */
bogdanm 92:4fc01daae5a5 72 volatile uint16_t TGRC_4; /* TGRC_4 */
bogdanm 92:4fc01daae5a5 73 volatile uint16_t TGRD_4; /* TGRD_4 */
bogdanm 92:4fc01daae5a5 74 volatile uint8_t TSR_3; /* TSR_3 */
bogdanm 92:4fc01daae5a5 75 volatile uint8_t TSR_4; /* TSR_4 */
bogdanm 92:4fc01daae5a5 76 volatile uint8_t dummy523[2]; /* */
bogdanm 92:4fc01daae5a5 77 volatile uint8_t TITCR; /* TITCR */
bogdanm 92:4fc01daae5a5 78 volatile uint8_t TITCNT; /* TITCNT */
bogdanm 92:4fc01daae5a5 79 volatile uint8_t TBTER; /* TBTER */
bogdanm 92:4fc01daae5a5 80 volatile uint8_t dummy524[1]; /* */
bogdanm 92:4fc01daae5a5 81 volatile uint8_t TDER; /* TDER */
bogdanm 92:4fc01daae5a5 82 volatile uint8_t dummy525[1]; /* */
bogdanm 92:4fc01daae5a5 83 volatile uint8_t TOLBR; /* TOLBR */
bogdanm 92:4fc01daae5a5 84 volatile uint8_t dummy526[1]; /* */
bogdanm 92:4fc01daae5a5 85 volatile uint8_t TBTM_3; /* TBTM_3 */
bogdanm 92:4fc01daae5a5 86 volatile uint8_t TBTM_4; /* TBTM_4 */
bogdanm 92:4fc01daae5a5 87 volatile uint8_t dummy527[6]; /* */
bogdanm 92:4fc01daae5a5 88 volatile uint16_t TADCR; /* TADCR */
bogdanm 92:4fc01daae5a5 89 volatile uint8_t dummy528[2]; /* */
bogdanm 92:4fc01daae5a5 90 volatile uint16_t TADCORA_4; /* TADCORA_4 */
bogdanm 92:4fc01daae5a5 91 volatile uint16_t TADCORB_4; /* TADCORB_4 */
bogdanm 92:4fc01daae5a5 92 volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */
bogdanm 92:4fc01daae5a5 93 volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */
bogdanm 92:4fc01daae5a5 94 volatile uint8_t dummy529[20]; /* */
bogdanm 92:4fc01daae5a5 95 volatile uint8_t TWCR; /* TWCR */
bogdanm 92:4fc01daae5a5 96 volatile uint8_t dummy530[31]; /* */
bogdanm 92:4fc01daae5a5 97 volatile uint8_t TSTR; /* TSTR */
bogdanm 92:4fc01daae5a5 98 volatile uint8_t TSYR; /* TSYR */
bogdanm 92:4fc01daae5a5 99 volatile uint8_t dummy531[2]; /* */
bogdanm 92:4fc01daae5a5 100 volatile uint8_t TRWER; /* TRWER */
bogdanm 92:4fc01daae5a5 101 volatile uint8_t dummy532[123]; /* */
bogdanm 92:4fc01daae5a5 102 volatile uint8_t TCR_0; /* TCR_0 */
bogdanm 92:4fc01daae5a5 103 volatile uint8_t TMDR_0; /* TMDR_0 */
bogdanm 92:4fc01daae5a5 104 volatile uint8_t TIORH_0; /* TIORH_0 */
bogdanm 92:4fc01daae5a5 105 volatile uint8_t TIORL_0; /* TIORL_0 */
bogdanm 92:4fc01daae5a5 106 volatile uint8_t TIER_0; /* TIER_0 */
bogdanm 92:4fc01daae5a5 107 volatile uint8_t TSR_0; /* TSR_0 */
bogdanm 92:4fc01daae5a5 108 volatile uint16_t TCNT_0; /* TCNT_0 */
bogdanm 92:4fc01daae5a5 109 volatile uint16_t TGRA_0; /* TGRA_0 */
bogdanm 92:4fc01daae5a5 110 volatile uint16_t TGRB_0; /* TGRB_0 */
bogdanm 92:4fc01daae5a5 111 volatile uint16_t TGRC_0; /* TGRC_0 */
bogdanm 92:4fc01daae5a5 112 volatile uint16_t TGRD_0; /* TGRD_0 */
bogdanm 92:4fc01daae5a5 113 volatile uint8_t dummy533[16]; /* */
bogdanm 92:4fc01daae5a5 114 volatile uint16_t TGRE_0; /* TGRE_0 */
bogdanm 92:4fc01daae5a5 115 volatile uint16_t TGRF_0; /* TGRF_0 */
bogdanm 92:4fc01daae5a5 116 volatile uint8_t TIER2_0; /* TIER2_0 */
bogdanm 92:4fc01daae5a5 117 volatile uint8_t TSR2_0; /* TSR2_0 */
bogdanm 92:4fc01daae5a5 118 volatile uint8_t TBTM_0; /* TBTM_0 */
bogdanm 92:4fc01daae5a5 119 volatile uint8_t dummy534[89]; /* */
bogdanm 92:4fc01daae5a5 120 volatile uint8_t TCR_1; /* TCR_1 */
bogdanm 92:4fc01daae5a5 121 volatile uint8_t TMDR_1; /* TMDR_1 */
bogdanm 92:4fc01daae5a5 122 volatile uint8_t TIOR_1; /* TIOR_1 */
bogdanm 92:4fc01daae5a5 123 volatile uint8_t dummy535[1]; /* */
bogdanm 92:4fc01daae5a5 124 volatile uint8_t TIER_1; /* TIER_1 */
bogdanm 92:4fc01daae5a5 125 volatile uint8_t TSR_1; /* TSR_1 */
bogdanm 92:4fc01daae5a5 126 volatile uint16_t TCNT_1; /* TCNT_1 */
bogdanm 92:4fc01daae5a5 127 volatile uint16_t TGRA_1; /* TGRA_1 */
bogdanm 92:4fc01daae5a5 128 volatile uint16_t TGRB_1; /* TGRB_1 */
bogdanm 92:4fc01daae5a5 129 volatile uint8_t dummy536[4]; /* */
bogdanm 92:4fc01daae5a5 130 volatile uint8_t TICCR; /* TICCR */
bogdanm 92:4fc01daae5a5 131 };
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133
bogdanm 92:4fc01daae5a5 134 #define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 #define MTU2TCR_2 MTU2.TCR_2
bogdanm 92:4fc01daae5a5 138 #define MTU2TMDR_2 MTU2.TMDR_2
bogdanm 92:4fc01daae5a5 139 #define MTU2TIOR_2 MTU2.TIOR_2
bogdanm 92:4fc01daae5a5 140 #define MTU2TIER_2 MTU2.TIER_2
bogdanm 92:4fc01daae5a5 141 #define MTU2TSR_2 MTU2.TSR_2
bogdanm 92:4fc01daae5a5 142 #define MTU2TCNT_2 MTU2.TCNT_2
bogdanm 92:4fc01daae5a5 143 #define MTU2TGRA_2 MTU2.TGRA_2
bogdanm 92:4fc01daae5a5 144 #define MTU2TGRB_2 MTU2.TGRB_2
bogdanm 92:4fc01daae5a5 145 #define MTU2TCR_3 MTU2.TCR_3
bogdanm 92:4fc01daae5a5 146 #define MTU2TCR_4 MTU2.TCR_4
bogdanm 92:4fc01daae5a5 147 #define MTU2TMDR_3 MTU2.TMDR_3
bogdanm 92:4fc01daae5a5 148 #define MTU2TMDR_4 MTU2.TMDR_4
bogdanm 92:4fc01daae5a5 149 #define MTU2TIORH_3 MTU2.TIORH_3
bogdanm 92:4fc01daae5a5 150 #define MTU2TIORL_3 MTU2.TIORL_3
bogdanm 92:4fc01daae5a5 151 #define MTU2TIORH_4 MTU2.TIORH_4
bogdanm 92:4fc01daae5a5 152 #define MTU2TIORL_4 MTU2.TIORL_4
bogdanm 92:4fc01daae5a5 153 #define MTU2TIER_3 MTU2.TIER_3
bogdanm 92:4fc01daae5a5 154 #define MTU2TIER_4 MTU2.TIER_4
bogdanm 92:4fc01daae5a5 155 #define MTU2TOER MTU2.TOER
bogdanm 92:4fc01daae5a5 156 #define MTU2TGCR MTU2.TGCR
bogdanm 92:4fc01daae5a5 157 #define MTU2TOCR1 MTU2.TOCR1
bogdanm 92:4fc01daae5a5 158 #define MTU2TOCR2 MTU2.TOCR2
bogdanm 92:4fc01daae5a5 159 #define MTU2TCNT_3 MTU2.TCNT_3
bogdanm 92:4fc01daae5a5 160 #define MTU2TCNT_4 MTU2.TCNT_4
bogdanm 92:4fc01daae5a5 161 #define MTU2TCDR MTU2.TCDR
bogdanm 92:4fc01daae5a5 162 #define MTU2TDDR MTU2.TDDR
bogdanm 92:4fc01daae5a5 163 #define MTU2TGRA_3 MTU2.TGRA_3
bogdanm 92:4fc01daae5a5 164 #define MTU2TGRB_3 MTU2.TGRB_3
bogdanm 92:4fc01daae5a5 165 #define MTU2TGRA_4 MTU2.TGRA_4
bogdanm 92:4fc01daae5a5 166 #define MTU2TGRB_4 MTU2.TGRB_4
bogdanm 92:4fc01daae5a5 167 #define MTU2TCNTS MTU2.TCNTS
bogdanm 92:4fc01daae5a5 168 #define MTU2TCBR MTU2.TCBR
bogdanm 92:4fc01daae5a5 169 #define MTU2TGRC_3 MTU2.TGRC_3
bogdanm 92:4fc01daae5a5 170 #define MTU2TGRD_3 MTU2.TGRD_3
bogdanm 92:4fc01daae5a5 171 #define MTU2TGRC_4 MTU2.TGRC_4
bogdanm 92:4fc01daae5a5 172 #define MTU2TGRD_4 MTU2.TGRD_4
bogdanm 92:4fc01daae5a5 173 #define MTU2TSR_3 MTU2.TSR_3
bogdanm 92:4fc01daae5a5 174 #define MTU2TSR_4 MTU2.TSR_4
bogdanm 92:4fc01daae5a5 175 #define MTU2TITCR MTU2.TITCR
bogdanm 92:4fc01daae5a5 176 #define MTU2TITCNT MTU2.TITCNT
bogdanm 92:4fc01daae5a5 177 #define MTU2TBTER MTU2.TBTER
bogdanm 92:4fc01daae5a5 178 #define MTU2TDER MTU2.TDER
bogdanm 92:4fc01daae5a5 179 #define MTU2TOLBR MTU2.TOLBR
bogdanm 92:4fc01daae5a5 180 #define MTU2TBTM_3 MTU2.TBTM_3
bogdanm 92:4fc01daae5a5 181 #define MTU2TBTM_4 MTU2.TBTM_4
bogdanm 92:4fc01daae5a5 182 #define MTU2TADCR MTU2.TADCR
bogdanm 92:4fc01daae5a5 183 #define MTU2TADCORA_4 MTU2.TADCORA_4
bogdanm 92:4fc01daae5a5 184 #define MTU2TADCORB_4 MTU2.TADCORB_4
bogdanm 92:4fc01daae5a5 185 #define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
bogdanm 92:4fc01daae5a5 186 #define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
bogdanm 92:4fc01daae5a5 187 #define MTU2TWCR MTU2.TWCR
bogdanm 92:4fc01daae5a5 188 #define MTU2TSTR MTU2.TSTR
bogdanm 92:4fc01daae5a5 189 #define MTU2TSYR MTU2.TSYR
bogdanm 92:4fc01daae5a5 190 #define MTU2TRWER MTU2.TRWER
bogdanm 92:4fc01daae5a5 191 #define MTU2TCR_0 MTU2.TCR_0
bogdanm 92:4fc01daae5a5 192 #define MTU2TMDR_0 MTU2.TMDR_0
bogdanm 92:4fc01daae5a5 193 #define MTU2TIORH_0 MTU2.TIORH_0
bogdanm 92:4fc01daae5a5 194 #define MTU2TIORL_0 MTU2.TIORL_0
bogdanm 92:4fc01daae5a5 195 #define MTU2TIER_0 MTU2.TIER_0
bogdanm 92:4fc01daae5a5 196 #define MTU2TSR_0 MTU2.TSR_0
bogdanm 92:4fc01daae5a5 197 #define MTU2TCNT_0 MTU2.TCNT_0
bogdanm 92:4fc01daae5a5 198 #define MTU2TGRA_0 MTU2.TGRA_0
bogdanm 92:4fc01daae5a5 199 #define MTU2TGRB_0 MTU2.TGRB_0
bogdanm 92:4fc01daae5a5 200 #define MTU2TGRC_0 MTU2.TGRC_0
bogdanm 92:4fc01daae5a5 201 #define MTU2TGRD_0 MTU2.TGRD_0
bogdanm 92:4fc01daae5a5 202 #define MTU2TGRE_0 MTU2.TGRE_0
bogdanm 92:4fc01daae5a5 203 #define MTU2TGRF_0 MTU2.TGRF_0
bogdanm 92:4fc01daae5a5 204 #define MTU2TIER2_0 MTU2.TIER2_0
bogdanm 92:4fc01daae5a5 205 #define MTU2TSR2_0 MTU2.TSR2_0
bogdanm 92:4fc01daae5a5 206 #define MTU2TBTM_0 MTU2.TBTM_0
bogdanm 92:4fc01daae5a5 207 #define MTU2TCR_1 MTU2.TCR_1
bogdanm 92:4fc01daae5a5 208 #define MTU2TMDR_1 MTU2.TMDR_1
bogdanm 92:4fc01daae5a5 209 #define MTU2TIOR_1 MTU2.TIOR_1
bogdanm 92:4fc01daae5a5 210 #define MTU2TIER_1 MTU2.TIER_1
bogdanm 92:4fc01daae5a5 211 #define MTU2TSR_1 MTU2.TSR_1
bogdanm 92:4fc01daae5a5 212 #define MTU2TCNT_1 MTU2.TCNT_1
bogdanm 92:4fc01daae5a5 213 #define MTU2TGRA_1 MTU2.TGRA_1
bogdanm 92:4fc01daae5a5 214 #define MTU2TGRB_1 MTU2.TGRB_1
bogdanm 92:4fc01daae5a5 215 #define MTU2TICCR MTU2.TICCR
bogdanm 92:4fc01daae5a5 216 /* <-SEC M1.10.1 */
bogdanm 92:4fc01daae5a5 217 #endif