Egor Rumjantsev / mbed

The official mbed C/C SDK provides the software platform and libraries to build your applications.

Fork of mbed by mbed official

TARGET_NUCLEO_F411RE/stm32f4xx_hal_tim.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
86:04dd9b1680ae 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f4xx_hal_tim.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.1.0
bogdanm 86:04dd9b1680ae 6 * @date 19-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of TIM HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F4xx_HAL_TIM_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F4xx_HAL_TIM_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f4xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F4xx_HAL
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup TIM
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59 /**
bogdanm 86:04dd9b1680ae 60 * @brief TIM Time base Configuration Structure definition
bogdanm 86:04dd9b1680ae 61 */
bogdanm 86:04dd9b1680ae 62 typedef struct
bogdanm 86:04dd9b1680ae 63 {
bogdanm 86:04dd9b1680ae 64 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm 86:04dd9b1680ae 65 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 86:04dd9b1680ae 66
bogdanm 86:04dd9b1680ae 67 uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm 86:04dd9b1680ae 68 This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm 86:04dd9b1680ae 69
bogdanm 86:04dd9b1680ae 70 uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm 86:04dd9b1680ae 71 Auto-Reload Register at the next update event.
bogdanm 86:04dd9b1680ae 72 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm 86:04dd9b1680ae 73
bogdanm 86:04dd9b1680ae 74 uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm 86:04dd9b1680ae 75 This parameter can be a value of @ref TIM_ClockDivision */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm 86:04dd9b1680ae 78 reaches zero, an update event is generated and counting restarts
bogdanm 86:04dd9b1680ae 79 from the RCR value (N).
bogdanm 86:04dd9b1680ae 80 This means in PWM mode that (N+1) corresponds to:
bogdanm 86:04dd9b1680ae 81 - the number of PWM periods in edge-aligned mode
bogdanm 86:04dd9b1680ae 82 - the number of half PWM period in center-aligned mode
bogdanm 86:04dd9b1680ae 83 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm 86:04dd9b1680ae 84 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 85 } TIM_Base_InitTypeDef;
bogdanm 86:04dd9b1680ae 86
bogdanm 86:04dd9b1680ae 87 /**
bogdanm 86:04dd9b1680ae 88 * @brief TIM Output Compare Configuration Structure definition
bogdanm 86:04dd9b1680ae 89 */
bogdanm 86:04dd9b1680ae 90
bogdanm 86:04dd9b1680ae 91 typedef struct
bogdanm 86:04dd9b1680ae 92 {
bogdanm 86:04dd9b1680ae 93 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 86:04dd9b1680ae 94 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 86:04dd9b1680ae 95
bogdanm 86:04dd9b1680ae 96 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 86:04dd9b1680ae 97 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 86:04dd9b1680ae 98
bogdanm 86:04dd9b1680ae 99 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 86:04dd9b1680ae 100 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 86:04dd9b1680ae 101
bogdanm 86:04dd9b1680ae 102 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 86:04dd9b1680ae 103 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 86:04dd9b1680ae 104 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 105
bogdanm 86:04dd9b1680ae 106 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm 86:04dd9b1680ae 107 This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm 86:04dd9b1680ae 108 @note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm 86:04dd9b1680ae 109
bogdanm 86:04dd9b1680ae 110
bogdanm 86:04dd9b1680ae 111 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 86:04dd9b1680ae 112 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 86:04dd9b1680ae 113 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 114
bogdanm 86:04dd9b1680ae 115 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 86:04dd9b1680ae 116 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 86:04dd9b1680ae 117 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 118 } TIM_OC_InitTypeDef;
bogdanm 86:04dd9b1680ae 119
bogdanm 86:04dd9b1680ae 120 /**
bogdanm 86:04dd9b1680ae 121 * @brief TIM One Pulse Mode Configuration Structure definition
bogdanm 86:04dd9b1680ae 122 */
bogdanm 86:04dd9b1680ae 123 typedef struct
bogdanm 86:04dd9b1680ae 124 {
bogdanm 86:04dd9b1680ae 125 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 86:04dd9b1680ae 126 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm 86:04dd9b1680ae 127
bogdanm 86:04dd9b1680ae 128 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 86:04dd9b1680ae 129 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 86:04dd9b1680ae 130
bogdanm 86:04dd9b1680ae 131 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 86:04dd9b1680ae 132 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 86:04dd9b1680ae 133
bogdanm 86:04dd9b1680ae 134 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 86:04dd9b1680ae 135 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 86:04dd9b1680ae 136 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 137
bogdanm 86:04dd9b1680ae 138 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 86:04dd9b1680ae 139 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 86:04dd9b1680ae 140 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 141
bogdanm 86:04dd9b1680ae 142 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 86:04dd9b1680ae 143 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 86:04dd9b1680ae 144 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 145
bogdanm 86:04dd9b1680ae 146 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 147 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 148
bogdanm 86:04dd9b1680ae 149 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 86:04dd9b1680ae 150 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 86:04dd9b1680ae 151
bogdanm 86:04dd9b1680ae 152 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 153 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 154 } TIM_OnePulse_InitTypeDef;
bogdanm 86:04dd9b1680ae 155
bogdanm 86:04dd9b1680ae 156
bogdanm 86:04dd9b1680ae 157 /**
bogdanm 86:04dd9b1680ae 158 * @brief TIM Input Capture Configuration Structure definition
bogdanm 86:04dd9b1680ae 159 */
bogdanm 86:04dd9b1680ae 160
bogdanm 86:04dd9b1680ae 161 typedef struct
bogdanm 86:04dd9b1680ae 162 {
bogdanm 86:04dd9b1680ae 163 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 164 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 165
bogdanm 86:04dd9b1680ae 166 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 86:04dd9b1680ae 167 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 86:04dd9b1680ae 168
bogdanm 86:04dd9b1680ae 169 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 86:04dd9b1680ae 170 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 86:04dd9b1680ae 171
bogdanm 86:04dd9b1680ae 172 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 173 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 174 } TIM_IC_InitTypeDef;
bogdanm 86:04dd9b1680ae 175
bogdanm 86:04dd9b1680ae 176 /**
bogdanm 86:04dd9b1680ae 177 * @brief TIM Encoder Configuration Structure definition
bogdanm 86:04dd9b1680ae 178 */
bogdanm 86:04dd9b1680ae 179
bogdanm 86:04dd9b1680ae 180 typedef struct
bogdanm 86:04dd9b1680ae 181 {
bogdanm 86:04dd9b1680ae 182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 183 This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm 86:04dd9b1680ae 184
bogdanm 86:04dd9b1680ae 185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 187
bogdanm 86:04dd9b1680ae 188 uint32_t IC1Selection; /*!< Specifies the input.
bogdanm 86:04dd9b1680ae 189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 86:04dd9b1680ae 190
bogdanm 86:04dd9b1680ae 191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 86:04dd9b1680ae 192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 86:04dd9b1680ae 193
bogdanm 86:04dd9b1680ae 194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 196
bogdanm 86:04dd9b1680ae 197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 199
bogdanm 86:04dd9b1680ae 200 uint32_t IC2Selection; /*!< Specifies the input.
bogdanm 86:04dd9b1680ae 201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 86:04dd9b1680ae 202
bogdanm 86:04dd9b1680ae 203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 86:04dd9b1680ae 204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 86:04dd9b1680ae 205
bogdanm 86:04dd9b1680ae 206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 208 } TIM_Encoder_InitTypeDef;
bogdanm 86:04dd9b1680ae 209
bogdanm 86:04dd9b1680ae 210 /**
bogdanm 86:04dd9b1680ae 211 * @brief Clock Configuration Handle Structure definition
bogdanm 86:04dd9b1680ae 212 */
bogdanm 86:04dd9b1680ae 213 typedef struct
bogdanm 86:04dd9b1680ae 214 {
bogdanm 86:04dd9b1680ae 215 uint32_t ClockSource; /*!< TIM clock sources.
bogdanm 86:04dd9b1680ae 216 This parameter can be a value of @ref TIM_Clock_Source */
bogdanm 86:04dd9b1680ae 217 uint32_t ClockPolarity; /*!< TIM clock polarity.
bogdanm 86:04dd9b1680ae 218 This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm 86:04dd9b1680ae 219 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
bogdanm 86:04dd9b1680ae 220 This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm 86:04dd9b1680ae 221 uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm 86:04dd9b1680ae 222 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 223 }TIM_ClockConfigTypeDef;
bogdanm 86:04dd9b1680ae 224
bogdanm 86:04dd9b1680ae 225 /**
bogdanm 86:04dd9b1680ae 226 * @brief Clear Input Configuration Handle Structure definition
bogdanm 86:04dd9b1680ae 227 */
bogdanm 86:04dd9b1680ae 228 typedef struct
bogdanm 86:04dd9b1680ae 229 {
bogdanm 86:04dd9b1680ae 230 uint32_t ClearInputState; /*!< TIM clear Input state.
bogdanm 86:04dd9b1680ae 231 This parameter can be ENABLE or DISABLE */
bogdanm 86:04dd9b1680ae 232 uint32_t ClearInputSource; /*!< TIM clear Input sources.
bogdanm 86:04dd9b1680ae 233 This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm 86:04dd9b1680ae 234 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
bogdanm 86:04dd9b1680ae 235 This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm 86:04dd9b1680ae 236 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
bogdanm 86:04dd9b1680ae 237 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm 86:04dd9b1680ae 238 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm 86:04dd9b1680ae 239 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 240 }TIM_ClearInputConfigTypeDef;
bogdanm 86:04dd9b1680ae 241
bogdanm 86:04dd9b1680ae 242 /**
bogdanm 86:04dd9b1680ae 243 * @brief TIM Slave configuration Structure definition
bogdanm 86:04dd9b1680ae 244 */
bogdanm 86:04dd9b1680ae 245 typedef struct {
bogdanm 86:04dd9b1680ae 246 uint32_t SlaveMode; /*!< Slave mode selection
bogdanm 86:04dd9b1680ae 247 This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm 86:04dd9b1680ae 248 uint32_t InputTrigger; /*!< Input Trigger source
bogdanm 86:04dd9b1680ae 249 This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm 86:04dd9b1680ae 250 uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm 86:04dd9b1680ae 251 This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm 86:04dd9b1680ae 252 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm 86:04dd9b1680ae 253 This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm 86:04dd9b1680ae 254 uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm 86:04dd9b1680ae 255 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 256
bogdanm 86:04dd9b1680ae 257 }TIM_SlaveConfigTypeDef;
bogdanm 86:04dd9b1680ae 258
bogdanm 86:04dd9b1680ae 259 /**
bogdanm 86:04dd9b1680ae 260 * @brief HAL State structures definition
bogdanm 86:04dd9b1680ae 261 */
bogdanm 86:04dd9b1680ae 262 typedef enum
bogdanm 86:04dd9b1680ae 263 {
bogdanm 86:04dd9b1680ae 264 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
bogdanm 86:04dd9b1680ae 265 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 86:04dd9b1680ae 266 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
bogdanm 86:04dd9b1680ae 267 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 86:04dd9b1680ae 268 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
bogdanm 86:04dd9b1680ae 269 }HAL_TIM_StateTypeDef;
bogdanm 86:04dd9b1680ae 270
bogdanm 86:04dd9b1680ae 271 /**
bogdanm 86:04dd9b1680ae 272 * @brief HAL Active channel structures definition
bogdanm 86:04dd9b1680ae 273 */
bogdanm 86:04dd9b1680ae 274 typedef enum
bogdanm 86:04dd9b1680ae 275 {
bogdanm 86:04dd9b1680ae 276 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
bogdanm 86:04dd9b1680ae 277 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
bogdanm 86:04dd9b1680ae 278 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
bogdanm 86:04dd9b1680ae 279 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
bogdanm 86:04dd9b1680ae 280 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
bogdanm 86:04dd9b1680ae 281 }HAL_TIM_ActiveChannel;
bogdanm 86:04dd9b1680ae 282
bogdanm 86:04dd9b1680ae 283 /**
bogdanm 86:04dd9b1680ae 284 * @brief TIM Time Base Handle Structure definition
bogdanm 86:04dd9b1680ae 285 */
bogdanm 86:04dd9b1680ae 286 typedef struct
bogdanm 86:04dd9b1680ae 287 {
bogdanm 86:04dd9b1680ae 288 TIM_TypeDef *Instance; /*!< Register base address */
bogdanm 86:04dd9b1680ae 289 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
bogdanm 86:04dd9b1680ae 290 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
bogdanm 86:04dd9b1680ae 291 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
bogdanm 86:04dd9b1680ae 292 This array is accessed by a @ref DMA_Handle_index */
bogdanm 86:04dd9b1680ae 293 HAL_LockTypeDef Lock; /*!< Locking object */
bogdanm 86:04dd9b1680ae 294 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
bogdanm 86:04dd9b1680ae 295 }TIM_HandleTypeDef;
bogdanm 86:04dd9b1680ae 296
bogdanm 86:04dd9b1680ae 297 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 298 /** @defgroup TIM_Exported_Constants
bogdanm 86:04dd9b1680ae 299 * @{
bogdanm 86:04dd9b1680ae 300 */
bogdanm 86:04dd9b1680ae 301
bogdanm 86:04dd9b1680ae 302 /** @defgroup TIM_Input_Channel_Polarity
bogdanm 86:04dd9b1680ae 303 * @{
bogdanm 86:04dd9b1680ae 304 */
bogdanm 86:04dd9b1680ae 305 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
bogdanm 86:04dd9b1680ae 306 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
bogdanm 86:04dd9b1680ae 307 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
bogdanm 86:04dd9b1680ae 308 /**
bogdanm 86:04dd9b1680ae 309 * @}
bogdanm 86:04dd9b1680ae 310 */
bogdanm 86:04dd9b1680ae 311
bogdanm 86:04dd9b1680ae 312 /** @defgroup TIM_ETR_Polarity
bogdanm 86:04dd9b1680ae 313 * @{
bogdanm 86:04dd9b1680ae 314 */
bogdanm 86:04dd9b1680ae 315 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
bogdanm 86:04dd9b1680ae 316 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
bogdanm 86:04dd9b1680ae 317 /**
bogdanm 86:04dd9b1680ae 318 * @}
bogdanm 86:04dd9b1680ae 319 */
bogdanm 86:04dd9b1680ae 320
bogdanm 86:04dd9b1680ae 321 /** @defgroup TIM_ETR_Prescaler
bogdanm 86:04dd9b1680ae 322 * @{
bogdanm 86:04dd9b1680ae 323 */
bogdanm 86:04dd9b1680ae 324 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
bogdanm 86:04dd9b1680ae 325 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
bogdanm 86:04dd9b1680ae 326 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
bogdanm 86:04dd9b1680ae 327 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
bogdanm 86:04dd9b1680ae 328 /**
bogdanm 86:04dd9b1680ae 329 * @}
bogdanm 86:04dd9b1680ae 330 */
bogdanm 86:04dd9b1680ae 331
bogdanm 86:04dd9b1680ae 332 /** @defgroup TIM_Counter_Mode
bogdanm 86:04dd9b1680ae 333 * @{
bogdanm 86:04dd9b1680ae 334 */
bogdanm 86:04dd9b1680ae 335 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 336 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm 86:04dd9b1680ae 337 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm 86:04dd9b1680ae 338 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm 86:04dd9b1680ae 339 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm 86:04dd9b1680ae 340
bogdanm 86:04dd9b1680ae 341 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
bogdanm 86:04dd9b1680ae 342 ((MODE) == TIM_COUNTERMODE_DOWN) || \
bogdanm 86:04dd9b1680ae 343 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
bogdanm 86:04dd9b1680ae 344 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
bogdanm 86:04dd9b1680ae 345 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm 86:04dd9b1680ae 346 /**
bogdanm 86:04dd9b1680ae 347 * @}
bogdanm 86:04dd9b1680ae 348 */
bogdanm 86:04dd9b1680ae 349
bogdanm 86:04dd9b1680ae 350 /** @defgroup TIM_ClockDivision
bogdanm 86:04dd9b1680ae 351 * @{
bogdanm 86:04dd9b1680ae 352 */
bogdanm 86:04dd9b1680ae 353 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 354 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm 86:04dd9b1680ae 355 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm 86:04dd9b1680ae 356
bogdanm 86:04dd9b1680ae 357 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
bogdanm 86:04dd9b1680ae 358 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
bogdanm 86:04dd9b1680ae 359 ((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm 86:04dd9b1680ae 360 /**
bogdanm 86:04dd9b1680ae 361 * @}
bogdanm 86:04dd9b1680ae 362 */
bogdanm 86:04dd9b1680ae 363
bogdanm 86:04dd9b1680ae 364 /** @defgroup TIM_Output_Compare_and_PWM_modes
bogdanm 86:04dd9b1680ae 365 * @{
bogdanm 86:04dd9b1680ae 366 */
bogdanm 86:04dd9b1680ae 367 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 368 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm 86:04dd9b1680ae 369 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm 86:04dd9b1680ae 370 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
bogdanm 86:04dd9b1680ae 371 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 372 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm 86:04dd9b1680ae 373 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 374 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm 86:04dd9b1680ae 375
bogdanm 86:04dd9b1680ae 376 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
bogdanm 86:04dd9b1680ae 377 ((MODE) == TIM_OCMODE_PWM2))
bogdanm 86:04dd9b1680ae 378
bogdanm 86:04dd9b1680ae 379 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
bogdanm 86:04dd9b1680ae 380 ((MODE) == TIM_OCMODE_ACTIVE) || \
bogdanm 86:04dd9b1680ae 381 ((MODE) == TIM_OCMODE_INACTIVE) || \
bogdanm 86:04dd9b1680ae 382 ((MODE) == TIM_OCMODE_TOGGLE) || \
bogdanm 86:04dd9b1680ae 383 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
bogdanm 86:04dd9b1680ae 384 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm 86:04dd9b1680ae 385 /**
bogdanm 86:04dd9b1680ae 386 * @}
bogdanm 86:04dd9b1680ae 387 */
bogdanm 86:04dd9b1680ae 388
bogdanm 86:04dd9b1680ae 389 /** @defgroup TIM_Output_Compare_State
bogdanm 86:04dd9b1680ae 390 * @{
bogdanm 86:04dd9b1680ae 391 */
bogdanm 86:04dd9b1680ae 392 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 393 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm 86:04dd9b1680ae 394
bogdanm 86:04dd9b1680ae 395 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
bogdanm 86:04dd9b1680ae 396 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm 86:04dd9b1680ae 397 /**
bogdanm 86:04dd9b1680ae 398 * @}
bogdanm 86:04dd9b1680ae 399 */
bogdanm 86:04dd9b1680ae 400
bogdanm 86:04dd9b1680ae 401 /** @defgroup TIM_Output_Fast_State
bogdanm 86:04dd9b1680ae 402 * @{
bogdanm 86:04dd9b1680ae 403 */
bogdanm 86:04dd9b1680ae 404 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 405 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm 86:04dd9b1680ae 406
bogdanm 86:04dd9b1680ae 407 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
bogdanm 86:04dd9b1680ae 408 ((STATE) == TIM_OCFAST_ENABLE))
bogdanm 86:04dd9b1680ae 409 /**
bogdanm 86:04dd9b1680ae 410 * @}
bogdanm 86:04dd9b1680ae 411 */
bogdanm 86:04dd9b1680ae 412
bogdanm 86:04dd9b1680ae 413 /** @defgroup TIM_Output_Compare_N_State
bogdanm 86:04dd9b1680ae 414 * @{
bogdanm 86:04dd9b1680ae 415 */
bogdanm 86:04dd9b1680ae 416 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 417 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm 86:04dd9b1680ae 418
bogdanm 86:04dd9b1680ae 419 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
bogdanm 86:04dd9b1680ae 420 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm 86:04dd9b1680ae 421 /**
bogdanm 86:04dd9b1680ae 422 * @}
bogdanm 86:04dd9b1680ae 423 */
bogdanm 86:04dd9b1680ae 424
bogdanm 86:04dd9b1680ae 425 /** @defgroup TIM_Output_Compare_Polarity
bogdanm 86:04dd9b1680ae 426 * @{
bogdanm 86:04dd9b1680ae 427 */
bogdanm 86:04dd9b1680ae 428 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 429 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm 86:04dd9b1680ae 430
bogdanm 86:04dd9b1680ae 431 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
bogdanm 86:04dd9b1680ae 432 ((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm 86:04dd9b1680ae 433 /**
bogdanm 86:04dd9b1680ae 434 * @}
bogdanm 86:04dd9b1680ae 435 */
bogdanm 86:04dd9b1680ae 436
bogdanm 86:04dd9b1680ae 437 /** @defgroup TIM_Output_Compare_N_Polarity
bogdanm 86:04dd9b1680ae 438 * @{
bogdanm 86:04dd9b1680ae 439 */
bogdanm 86:04dd9b1680ae 440 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 441 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm 86:04dd9b1680ae 442
bogdanm 86:04dd9b1680ae 443 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
bogdanm 86:04dd9b1680ae 444 ((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm 86:04dd9b1680ae 445 /**
bogdanm 86:04dd9b1680ae 446 * @}
bogdanm 86:04dd9b1680ae 447 */
bogdanm 86:04dd9b1680ae 448
bogdanm 86:04dd9b1680ae 449 /** @defgroup TIM_Output_Compare_Idle_State
bogdanm 86:04dd9b1680ae 450 * @{
bogdanm 86:04dd9b1680ae 451 */
bogdanm 86:04dd9b1680ae 452 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm 86:04dd9b1680ae 453 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 454 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
bogdanm 86:04dd9b1680ae 455 ((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm 86:04dd9b1680ae 456 /**
bogdanm 86:04dd9b1680ae 457 * @}
bogdanm 86:04dd9b1680ae 458 */
bogdanm 86:04dd9b1680ae 459
bogdanm 86:04dd9b1680ae 460 /** @defgroup TIM_Output_Compare_N_Idle_State
bogdanm 86:04dd9b1680ae 461 * @{
bogdanm 86:04dd9b1680ae 462 */
bogdanm 86:04dd9b1680ae 463 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm 86:04dd9b1680ae 464 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 465 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
bogdanm 86:04dd9b1680ae 466 ((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm 86:04dd9b1680ae 467 /**
bogdanm 86:04dd9b1680ae 468 * @}
bogdanm 86:04dd9b1680ae 469 */
bogdanm 86:04dd9b1680ae 470
bogdanm 86:04dd9b1680ae 471 /** @defgroup TIM_Channel
bogdanm 86:04dd9b1680ae 472 * @{
bogdanm 86:04dd9b1680ae 473 */
bogdanm 86:04dd9b1680ae 474 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 475 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm 86:04dd9b1680ae 476 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm 86:04dd9b1680ae 477 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm 86:04dd9b1680ae 478 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm 86:04dd9b1680ae 479
bogdanm 86:04dd9b1680ae 480 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 481 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 482 ((CHANNEL) == TIM_CHANNEL_3) || \
bogdanm 86:04dd9b1680ae 483 ((CHANNEL) == TIM_CHANNEL_4) || \
bogdanm 86:04dd9b1680ae 484 ((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm 86:04dd9b1680ae 485
bogdanm 86:04dd9b1680ae 486 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 487 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 86:04dd9b1680ae 488
bogdanm 86:04dd9b1680ae 489 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 490 ((CHANNEL) == TIM_CHANNEL_2))
bogdanm 86:04dd9b1680ae 491
bogdanm 86:04dd9b1680ae 492 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
bogdanm 86:04dd9b1680ae 493 ((CHANNEL) == TIM_CHANNEL_2) || \
bogdanm 86:04dd9b1680ae 494 ((CHANNEL) == TIM_CHANNEL_3))
bogdanm 86:04dd9b1680ae 495 /**
bogdanm 86:04dd9b1680ae 496 * @}
bogdanm 86:04dd9b1680ae 497 */
bogdanm 86:04dd9b1680ae 498
bogdanm 86:04dd9b1680ae 499 /** @defgroup TIM_Input_Capture_Polarity
bogdanm 86:04dd9b1680ae 500 * @{
bogdanm 86:04dd9b1680ae 501 */
bogdanm 86:04dd9b1680ae 502 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm 86:04dd9b1680ae 503 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm 86:04dd9b1680ae 504 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm 86:04dd9b1680ae 505
bogdanm 86:04dd9b1680ae 506 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
bogdanm 86:04dd9b1680ae 507 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
bogdanm 86:04dd9b1680ae 508 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm 86:04dd9b1680ae 509 /**
bogdanm 86:04dd9b1680ae 510 * @}
bogdanm 86:04dd9b1680ae 511 */
bogdanm 86:04dd9b1680ae 512
bogdanm 86:04dd9b1680ae 513 /** @defgroup TIM_Input_Capture_Selection
bogdanm 86:04dd9b1680ae 514 * @{
bogdanm 86:04dd9b1680ae 515 */
bogdanm 86:04dd9b1680ae 516 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 86:04dd9b1680ae 517 connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm 86:04dd9b1680ae 518 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 86:04dd9b1680ae 519 connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm 86:04dd9b1680ae 520 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
bogdanm 86:04dd9b1680ae 521
bogdanm 86:04dd9b1680ae 522 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
bogdanm 86:04dd9b1680ae 523 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
bogdanm 86:04dd9b1680ae 524 ((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm 86:04dd9b1680ae 525 /**
bogdanm 86:04dd9b1680ae 526 * @}
bogdanm 86:04dd9b1680ae 527 */
bogdanm 86:04dd9b1680ae 528
bogdanm 86:04dd9b1680ae 529 /** @defgroup TIM_Input_Capture_Prescaler
bogdanm 86:04dd9b1680ae 530 * @{
bogdanm 86:04dd9b1680ae 531 */
bogdanm 86:04dd9b1680ae 532 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
bogdanm 86:04dd9b1680ae 533 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
bogdanm 86:04dd9b1680ae 534 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
bogdanm 86:04dd9b1680ae 535 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
bogdanm 86:04dd9b1680ae 536
bogdanm 86:04dd9b1680ae 537 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
bogdanm 86:04dd9b1680ae 538 ((PRESCALER) == TIM_ICPSC_DIV2) || \
bogdanm 86:04dd9b1680ae 539 ((PRESCALER) == TIM_ICPSC_DIV4) || \
bogdanm 86:04dd9b1680ae 540 ((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm 86:04dd9b1680ae 541 /**
bogdanm 86:04dd9b1680ae 542 * @}
bogdanm 86:04dd9b1680ae 543 */
bogdanm 86:04dd9b1680ae 544
bogdanm 86:04dd9b1680ae 545 /** @defgroup TIM_One_Pulse_Mode
bogdanm 86:04dd9b1680ae 546 * @{
bogdanm 86:04dd9b1680ae 547 */
bogdanm 86:04dd9b1680ae 548 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm 86:04dd9b1680ae 549 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 550 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
bogdanm 86:04dd9b1680ae 551 ((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm 86:04dd9b1680ae 552 /**
bogdanm 86:04dd9b1680ae 553 * @}
bogdanm 86:04dd9b1680ae 554 */
bogdanm 86:04dd9b1680ae 555
bogdanm 86:04dd9b1680ae 556 /** @defgroup TIM_Encoder_Mode
bogdanm 86:04dd9b1680ae 557 * @{
bogdanm 86:04dd9b1680ae 558 */
bogdanm 86:04dd9b1680ae 559 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm 86:04dd9b1680ae 560 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm 86:04dd9b1680ae 561 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
bogdanm 86:04dd9b1680ae 562 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
bogdanm 86:04dd9b1680ae 563 ((MODE) == TIM_ENCODERMODE_TI2) || \
bogdanm 86:04dd9b1680ae 564 ((MODE) == TIM_ENCODERMODE_TI12))
bogdanm 86:04dd9b1680ae 565 /**
bogdanm 86:04dd9b1680ae 566 * @}
bogdanm 86:04dd9b1680ae 567 */
bogdanm 86:04dd9b1680ae 568
bogdanm 86:04dd9b1680ae 569 /** @defgroup TIM_Interrupt_definition
bogdanm 86:04dd9b1680ae 570 * @{
bogdanm 86:04dd9b1680ae 571 */
bogdanm 86:04dd9b1680ae 572 #define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm 86:04dd9b1680ae 573 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm 86:04dd9b1680ae 574 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm 86:04dd9b1680ae 575 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm 86:04dd9b1680ae 576 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm 86:04dd9b1680ae 577 #define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm 86:04dd9b1680ae 578 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm 86:04dd9b1680ae 579 #define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm 86:04dd9b1680ae 580
bogdanm 86:04dd9b1680ae 581 #define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
bogdanm 86:04dd9b1680ae 582
bogdanm 86:04dd9b1680ae 583 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
bogdanm 86:04dd9b1680ae 584 ((IT) == TIM_IT_CC1) || \
bogdanm 86:04dd9b1680ae 585 ((IT) == TIM_IT_CC2) || \
bogdanm 86:04dd9b1680ae 586 ((IT) == TIM_IT_CC3) || \
bogdanm 86:04dd9b1680ae 587 ((IT) == TIM_IT_CC4) || \
bogdanm 86:04dd9b1680ae 588 ((IT) == TIM_IT_COM) || \
bogdanm 86:04dd9b1680ae 589 ((IT) == TIM_IT_TRIGGER) || \
bogdanm 86:04dd9b1680ae 590 ((IT) == TIM_IT_BREAK))
bogdanm 86:04dd9b1680ae 591 /**
bogdanm 86:04dd9b1680ae 592 * @}
bogdanm 86:04dd9b1680ae 593 */
bogdanm 86:04dd9b1680ae 594 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm 86:04dd9b1680ae 595 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 596
bogdanm 86:04dd9b1680ae 597 /** @defgroup TIM_DMA_sources
bogdanm 86:04dd9b1680ae 598 * @{
bogdanm 86:04dd9b1680ae 599 */
bogdanm 86:04dd9b1680ae 600 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm 86:04dd9b1680ae 601 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm 86:04dd9b1680ae 602 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm 86:04dd9b1680ae 603 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm 86:04dd9b1680ae 604 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm 86:04dd9b1680ae 605 #define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm 86:04dd9b1680ae 606 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm 86:04dd9b1680ae 607 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 86:04dd9b1680ae 608 /**
bogdanm 86:04dd9b1680ae 609 * @}
bogdanm 86:04dd9b1680ae 610 */
bogdanm 86:04dd9b1680ae 611
bogdanm 86:04dd9b1680ae 612 /** @defgroup TIM_Event_Source
bogdanm 86:04dd9b1680ae 613 * @{
bogdanm 86:04dd9b1680ae 614 */
bogdanm 86:04dd9b1680ae 615 #define TIM_EventSource_Update TIM_EGR_UG
bogdanm 86:04dd9b1680ae 616 #define TIM_EventSource_CC1 TIM_EGR_CC1G
bogdanm 86:04dd9b1680ae 617 #define TIM_EventSource_CC2 TIM_EGR_CC2G
bogdanm 86:04dd9b1680ae 618 #define TIM_EventSource_CC3 TIM_EGR_CC3G
bogdanm 86:04dd9b1680ae 619 #define TIM_EventSource_CC4 TIM_EGR_CC4G
bogdanm 86:04dd9b1680ae 620 #define TIM_EventSource_COM TIM_EGR_COMG
bogdanm 86:04dd9b1680ae 621 #define TIM_EventSource_Trigger TIM_EGR_TG
bogdanm 86:04dd9b1680ae 622 #define TIM_EventSource_Break TIM_EGR_BG
bogdanm 86:04dd9b1680ae 623 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 86:04dd9b1680ae 624 /**
bogdanm 86:04dd9b1680ae 625 * @}
bogdanm 86:04dd9b1680ae 626 */
bogdanm 86:04dd9b1680ae 627
bogdanm 86:04dd9b1680ae 628 /** @defgroup TIM_Flag_definition
bogdanm 86:04dd9b1680ae 629 * @{
bogdanm 86:04dd9b1680ae 630 */
bogdanm 86:04dd9b1680ae 631 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm 86:04dd9b1680ae 632 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm 86:04dd9b1680ae 633 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm 86:04dd9b1680ae 634 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm 86:04dd9b1680ae 635 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm 86:04dd9b1680ae 636 #define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm 86:04dd9b1680ae 637 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm 86:04dd9b1680ae 638 #define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm 86:04dd9b1680ae 639 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm 86:04dd9b1680ae 640 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm 86:04dd9b1680ae 641 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm 86:04dd9b1680ae 642 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm 86:04dd9b1680ae 643
bogdanm 86:04dd9b1680ae 644 #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
bogdanm 86:04dd9b1680ae 645 ((FLAG) == TIM_FLAG_CC1) || \
bogdanm 86:04dd9b1680ae 646 ((FLAG) == TIM_FLAG_CC2) || \
bogdanm 86:04dd9b1680ae 647 ((FLAG) == TIM_FLAG_CC3) || \
bogdanm 86:04dd9b1680ae 648 ((FLAG) == TIM_FLAG_CC4) || \
bogdanm 86:04dd9b1680ae 649 ((FLAG) == TIM_FLAG_COM) || \
bogdanm 86:04dd9b1680ae 650 ((FLAG) == TIM_FLAG_TRIGGER) || \
bogdanm 86:04dd9b1680ae 651 ((FLAG) == TIM_FLAG_BREAK) || \
bogdanm 86:04dd9b1680ae 652 ((FLAG) == TIM_FLAG_CC1OF) || \
bogdanm 86:04dd9b1680ae 653 ((FLAG) == TIM_FLAG_CC2OF) || \
bogdanm 86:04dd9b1680ae 654 ((FLAG) == TIM_FLAG_CC3OF) || \
bogdanm 86:04dd9b1680ae 655 ((FLAG) == TIM_FLAG_CC4OF))
bogdanm 86:04dd9b1680ae 656 /**
bogdanm 86:04dd9b1680ae 657 * @}
bogdanm 86:04dd9b1680ae 658 */
bogdanm 86:04dd9b1680ae 659
bogdanm 86:04dd9b1680ae 660 /** @defgroup TIM_Clock_Source
bogdanm 86:04dd9b1680ae 661 * @{
bogdanm 86:04dd9b1680ae 662 */
bogdanm 86:04dd9b1680ae 663 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm 86:04dd9b1680ae 664 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm 86:04dd9b1680ae 665 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 666 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm 86:04dd9b1680ae 667 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm 86:04dd9b1680ae 668 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
bogdanm 86:04dd9b1680ae 669 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm 86:04dd9b1680ae 670 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
bogdanm 86:04dd9b1680ae 671 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
bogdanm 86:04dd9b1680ae 672 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm 86:04dd9b1680ae 673
bogdanm 86:04dd9b1680ae 674 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
bogdanm 86:04dd9b1680ae 675 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
bogdanm 86:04dd9b1680ae 676 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
bogdanm 86:04dd9b1680ae 677 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
bogdanm 86:04dd9b1680ae 678 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
bogdanm 86:04dd9b1680ae 679 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
bogdanm 86:04dd9b1680ae 680 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
bogdanm 86:04dd9b1680ae 681 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
bogdanm 86:04dd9b1680ae 682 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
bogdanm 86:04dd9b1680ae 683 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm 86:04dd9b1680ae 684 /**
bogdanm 86:04dd9b1680ae 685 * @}
bogdanm 86:04dd9b1680ae 686 */
bogdanm 86:04dd9b1680ae 687
bogdanm 86:04dd9b1680ae 688 /** @defgroup TIM_Clock_Polarity
bogdanm 86:04dd9b1680ae 689 * @{
bogdanm 86:04dd9b1680ae 690 */
bogdanm 86:04dd9b1680ae 691 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
bogdanm 86:04dd9b1680ae 692 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
bogdanm 86:04dd9b1680ae 693 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
bogdanm 86:04dd9b1680ae 694 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
bogdanm 86:04dd9b1680ae 695 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
bogdanm 86:04dd9b1680ae 696
bogdanm 86:04dd9b1680ae 697 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
bogdanm 86:04dd9b1680ae 698 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
bogdanm 86:04dd9b1680ae 699 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
bogdanm 86:04dd9b1680ae 700 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
bogdanm 86:04dd9b1680ae 701 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm 86:04dd9b1680ae 702 /**
bogdanm 86:04dd9b1680ae 703 * @}
bogdanm 86:04dd9b1680ae 704 */
bogdanm 86:04dd9b1680ae 705
bogdanm 86:04dd9b1680ae 706 /** @defgroup TIM_Clock_Prescaler
bogdanm 86:04dd9b1680ae 707 * @{
bogdanm 86:04dd9b1680ae 708 */
bogdanm 86:04dd9b1680ae 709 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 86:04dd9b1680ae 710 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
bogdanm 86:04dd9b1680ae 711 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
bogdanm 86:04dd9b1680ae 712 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
bogdanm 86:04dd9b1680ae 713
bogdanm 86:04dd9b1680ae 714 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 715 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 716 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 717 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm 86:04dd9b1680ae 718 /**
bogdanm 86:04dd9b1680ae 719 * @}
bogdanm 86:04dd9b1680ae 720 */
bogdanm 86:04dd9b1680ae 721
bogdanm 86:04dd9b1680ae 722 /** @defgroup TIM_Clock_Filter
bogdanm 86:04dd9b1680ae 723 * @{
bogdanm 86:04dd9b1680ae 724 */
bogdanm 86:04dd9b1680ae 725 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 726 /**
bogdanm 86:04dd9b1680ae 727 * @}
bogdanm 86:04dd9b1680ae 728 */
bogdanm 86:04dd9b1680ae 729
bogdanm 86:04dd9b1680ae 730 /** @defgroup TIM_ClearInput_Source
bogdanm 86:04dd9b1680ae 731 * @{
bogdanm 86:04dd9b1680ae 732 */
bogdanm 86:04dd9b1680ae 733 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm 86:04dd9b1680ae 734 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 735
bogdanm 86:04dd9b1680ae 736 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
bogdanm 86:04dd9b1680ae 737 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm 86:04dd9b1680ae 738 /**
bogdanm 86:04dd9b1680ae 739 * @}
bogdanm 86:04dd9b1680ae 740 */
bogdanm 86:04dd9b1680ae 741
bogdanm 86:04dd9b1680ae 742 /** @defgroup TIM_ClearInput_Polarity
bogdanm 86:04dd9b1680ae 743 * @{
bogdanm 86:04dd9b1680ae 744 */
bogdanm 86:04dd9b1680ae 745 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
bogdanm 86:04dd9b1680ae 746 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
bogdanm 86:04dd9b1680ae 747 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
bogdanm 86:04dd9b1680ae 748 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm 86:04dd9b1680ae 749 /**
bogdanm 86:04dd9b1680ae 750 * @}
bogdanm 86:04dd9b1680ae 751 */
bogdanm 86:04dd9b1680ae 752
bogdanm 86:04dd9b1680ae 753 /** @defgroup TIM_ClearInput_Prescaler
bogdanm 86:04dd9b1680ae 754 * @{
bogdanm 86:04dd9b1680ae 755 */
bogdanm 86:04dd9b1680ae 756 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 86:04dd9b1680ae 757 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
bogdanm 86:04dd9b1680ae 758 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
bogdanm 86:04dd9b1680ae 759 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
bogdanm 86:04dd9b1680ae 760 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 761 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 762 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 763 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm 86:04dd9b1680ae 764 /**
bogdanm 86:04dd9b1680ae 765 * @}
bogdanm 86:04dd9b1680ae 766 */
bogdanm 86:04dd9b1680ae 767
bogdanm 86:04dd9b1680ae 768 /** @defgroup TIM_ClearInput_Filter
bogdanm 86:04dd9b1680ae 769 * @{
bogdanm 86:04dd9b1680ae 770 */
bogdanm 86:04dd9b1680ae 771 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 772 /**
bogdanm 86:04dd9b1680ae 773 * @}
bogdanm 86:04dd9b1680ae 774 */
bogdanm 86:04dd9b1680ae 775
bogdanm 86:04dd9b1680ae 776 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
bogdanm 86:04dd9b1680ae 777 * @{
bogdanm 86:04dd9b1680ae 778 */
bogdanm 86:04dd9b1680ae 779 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm 86:04dd9b1680ae 780 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 781
bogdanm 86:04dd9b1680ae 782 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
bogdanm 86:04dd9b1680ae 783 ((STATE) == TIM_OSSR_DISABLE))
bogdanm 86:04dd9b1680ae 784 /**
bogdanm 86:04dd9b1680ae 785 * @}
bogdanm 86:04dd9b1680ae 786 */
bogdanm 86:04dd9b1680ae 787
bogdanm 86:04dd9b1680ae 788 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
bogdanm 86:04dd9b1680ae 789 * @{
bogdanm 86:04dd9b1680ae 790 */
bogdanm 86:04dd9b1680ae 791 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm 86:04dd9b1680ae 792 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 793
bogdanm 86:04dd9b1680ae 794 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
bogdanm 86:04dd9b1680ae 795 ((STATE) == TIM_OSSI_DISABLE))
bogdanm 86:04dd9b1680ae 796 /**
bogdanm 86:04dd9b1680ae 797 * @}
bogdanm 86:04dd9b1680ae 798 */
bogdanm 86:04dd9b1680ae 799 /** @defgroup TIM_Lock_level
bogdanm 86:04dd9b1680ae 800 * @{
bogdanm 86:04dd9b1680ae 801 */
bogdanm 86:04dd9b1680ae 802 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 803 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm 86:04dd9b1680ae 804 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm 86:04dd9b1680ae 805 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm 86:04dd9b1680ae 806
bogdanm 86:04dd9b1680ae 807 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
bogdanm 86:04dd9b1680ae 808 ((LEVEL) == TIM_LOCKLEVEL_1) || \
bogdanm 86:04dd9b1680ae 809 ((LEVEL) == TIM_LOCKLEVEL_2) || \
bogdanm 86:04dd9b1680ae 810 ((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm 86:04dd9b1680ae 811 /**
bogdanm 86:04dd9b1680ae 812 * @}
bogdanm 86:04dd9b1680ae 813 */
bogdanm 86:04dd9b1680ae 814 /** @defgroup TIM_Break_Input_enable_disable
bogdanm 86:04dd9b1680ae 815 * @{
bogdanm 86:04dd9b1680ae 816 */
bogdanm 86:04dd9b1680ae 817 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm 86:04dd9b1680ae 818 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 819
bogdanm 86:04dd9b1680ae 820 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
bogdanm 86:04dd9b1680ae 821 ((STATE) == TIM_BREAK_DISABLE))
bogdanm 86:04dd9b1680ae 822 /**
bogdanm 86:04dd9b1680ae 823 * @}
bogdanm 86:04dd9b1680ae 824 */
bogdanm 86:04dd9b1680ae 825 /** @defgroup TIM_Break_Polarity
bogdanm 86:04dd9b1680ae 826 * @{
bogdanm 86:04dd9b1680ae 827 */
bogdanm 86:04dd9b1680ae 828 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 829 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm 86:04dd9b1680ae 830
bogdanm 86:04dd9b1680ae 831 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
bogdanm 86:04dd9b1680ae 832 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm 86:04dd9b1680ae 833 /**
bogdanm 86:04dd9b1680ae 834 * @}
bogdanm 86:04dd9b1680ae 835 */
bogdanm 86:04dd9b1680ae 836 /** @defgroup TIM_AOE_Bit_Set_Reset
bogdanm 86:04dd9b1680ae 837 * @{
bogdanm 86:04dd9b1680ae 838 */
bogdanm 86:04dd9b1680ae 839 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm 86:04dd9b1680ae 840 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 841
bogdanm 86:04dd9b1680ae 842 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
bogdanm 86:04dd9b1680ae 843 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm 86:04dd9b1680ae 844 /**
bogdanm 86:04dd9b1680ae 845 * @}
bogdanm 86:04dd9b1680ae 846 */
bogdanm 86:04dd9b1680ae 847
bogdanm 86:04dd9b1680ae 848 /** @defgroup TIM_Master_Mode_Selection
bogdanm 86:04dd9b1680ae 849 * @{
bogdanm 86:04dd9b1680ae 850 */
bogdanm 86:04dd9b1680ae 851 #define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 852 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm 86:04dd9b1680ae 853 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm 86:04dd9b1680ae 854 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 86:04dd9b1680ae 855 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm 86:04dd9b1680ae 856 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
bogdanm 86:04dd9b1680ae 857 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
bogdanm 86:04dd9b1680ae 858 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 86:04dd9b1680ae 859
bogdanm 86:04dd9b1680ae 860 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
bogdanm 86:04dd9b1680ae 861 ((SOURCE) == TIM_TRGO_ENABLE) || \
bogdanm 86:04dd9b1680ae 862 ((SOURCE) == TIM_TRGO_UPDATE) || \
bogdanm 86:04dd9b1680ae 863 ((SOURCE) == TIM_TRGO_OC1) || \
bogdanm 86:04dd9b1680ae 864 ((SOURCE) == TIM_TRGO_OC1REF) || \
bogdanm 86:04dd9b1680ae 865 ((SOURCE) == TIM_TRGO_OC2REF) || \
bogdanm 86:04dd9b1680ae 866 ((SOURCE) == TIM_TRGO_OC3REF) || \
bogdanm 86:04dd9b1680ae 867 ((SOURCE) == TIM_TRGO_OC4REF))
bogdanm 86:04dd9b1680ae 868
bogdanm 86:04dd9b1680ae 869
bogdanm 86:04dd9b1680ae 870 /**
bogdanm 86:04dd9b1680ae 871 * @}
bogdanm 86:04dd9b1680ae 872 */
bogdanm 86:04dd9b1680ae 873 /** @defgroup TIM_Slave_Mode
bogdanm 86:04dd9b1680ae 874 * @{
bogdanm 86:04dd9b1680ae 875 */
bogdanm 86:04dd9b1680ae 876 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 877 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm 86:04dd9b1680ae 878 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm 86:04dd9b1680ae 879 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm 86:04dd9b1680ae 880 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm 86:04dd9b1680ae 881
bogdanm 86:04dd9b1680ae 882 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
bogdanm 86:04dd9b1680ae 883 ((MODE) == TIM_SLAVEMODE_GATED) || \
bogdanm 86:04dd9b1680ae 884 ((MODE) == TIM_SLAVEMODE_RESET) || \
bogdanm 86:04dd9b1680ae 885 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
bogdanm 86:04dd9b1680ae 886 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm 86:04dd9b1680ae 887 /**
bogdanm 86:04dd9b1680ae 888 * @}
bogdanm 86:04dd9b1680ae 889 */
bogdanm 86:04dd9b1680ae 890
bogdanm 86:04dd9b1680ae 891 /** @defgroup TIM_Master_Slave_Mode
bogdanm 86:04dd9b1680ae 892 * @{
bogdanm 86:04dd9b1680ae 893 */
bogdanm 86:04dd9b1680ae 894
bogdanm 86:04dd9b1680ae 895 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm 86:04dd9b1680ae 896 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 897 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
bogdanm 86:04dd9b1680ae 898 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm 86:04dd9b1680ae 899 /**
bogdanm 86:04dd9b1680ae 900 * @}
bogdanm 86:04dd9b1680ae 901 */
bogdanm 86:04dd9b1680ae 902 /** @defgroup TIM_Trigger_Selection
bogdanm 86:04dd9b1680ae 903 * @{
bogdanm 86:04dd9b1680ae 904 */
bogdanm 86:04dd9b1680ae 905 #define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 906 #define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm 86:04dd9b1680ae 907 #define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm 86:04dd9b1680ae 908 #define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm 86:04dd9b1680ae 909 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm 86:04dd9b1680ae 910 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm 86:04dd9b1680ae 911 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm 86:04dd9b1680ae 912 #define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm 86:04dd9b1680ae 913 #define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm 86:04dd9b1680ae 914 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 86:04dd9b1680ae 915 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 86:04dd9b1680ae 916 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 86:04dd9b1680ae 917 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 86:04dd9b1680ae 918 ((SELECTION) == TIM_TS_TI1F_ED) || \
bogdanm 86:04dd9b1680ae 919 ((SELECTION) == TIM_TS_TI1FP1) || \
bogdanm 86:04dd9b1680ae 920 ((SELECTION) == TIM_TS_TI2FP2) || \
bogdanm 86:04dd9b1680ae 921 ((SELECTION) == TIM_TS_ETRF))
bogdanm 86:04dd9b1680ae 922 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 86:04dd9b1680ae 923 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 86:04dd9b1680ae 924 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 86:04dd9b1680ae 925 ((SELECTION) == TIM_TS_ITR3))
bogdanm 86:04dd9b1680ae 926 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 86:04dd9b1680ae 927 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 86:04dd9b1680ae 928 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 86:04dd9b1680ae 929 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 86:04dd9b1680ae 930 ((SELECTION) == TIM_TS_NONE))
bogdanm 86:04dd9b1680ae 931 /**
bogdanm 86:04dd9b1680ae 932 * @}
bogdanm 86:04dd9b1680ae 933 */
bogdanm 86:04dd9b1680ae 934
bogdanm 86:04dd9b1680ae 935 /** @defgroup TIM_Trigger_Polarity
bogdanm 86:04dd9b1680ae 936 * @{
bogdanm 86:04dd9b1680ae 937 */
bogdanm 86:04dd9b1680ae 938 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 86:04dd9b1680ae 939 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 86:04dd9b1680ae 940 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 86:04dd9b1680ae 941 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 86:04dd9b1680ae 942 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 86:04dd9b1680ae 943
bogdanm 86:04dd9b1680ae 944 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
bogdanm 86:04dd9b1680ae 945 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
bogdanm 86:04dd9b1680ae 946 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
bogdanm 86:04dd9b1680ae 947 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
bogdanm 86:04dd9b1680ae 948 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm 86:04dd9b1680ae 949 /**
bogdanm 86:04dd9b1680ae 950 * @}
bogdanm 86:04dd9b1680ae 951 */
bogdanm 86:04dd9b1680ae 952
bogdanm 86:04dd9b1680ae 953 /** @defgroup TIM_Trigger_Prescaler
bogdanm 86:04dd9b1680ae 954 * @{
bogdanm 86:04dd9b1680ae 955 */
bogdanm 86:04dd9b1680ae 956 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 86:04dd9b1680ae 957 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
bogdanm 86:04dd9b1680ae 958 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
bogdanm 86:04dd9b1680ae 959 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
bogdanm 86:04dd9b1680ae 960
bogdanm 86:04dd9b1680ae 961 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 962 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 963 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 964 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm 86:04dd9b1680ae 965 /**
bogdanm 86:04dd9b1680ae 966 * @}
bogdanm 86:04dd9b1680ae 967 */
bogdanm 86:04dd9b1680ae 968
bogdanm 86:04dd9b1680ae 969 /** @defgroup TIM_Trigger_Filter
bogdanm 86:04dd9b1680ae 970 * @{
bogdanm 86:04dd9b1680ae 971 */
bogdanm 86:04dd9b1680ae 972 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 973 /**
bogdanm 86:04dd9b1680ae 974 * @}
bogdanm 86:04dd9b1680ae 975 */
bogdanm 86:04dd9b1680ae 976
bogdanm 86:04dd9b1680ae 977 /** @defgroup TIM_TI1_Selection
bogdanm 86:04dd9b1680ae 978 * @{
bogdanm 86:04dd9b1680ae 979 */
bogdanm 86:04dd9b1680ae 980 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 981 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm 86:04dd9b1680ae 982
bogdanm 86:04dd9b1680ae 983 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
bogdanm 86:04dd9b1680ae 984 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm 86:04dd9b1680ae 985 /**
bogdanm 86:04dd9b1680ae 986 * @}
bogdanm 86:04dd9b1680ae 987 */
bogdanm 86:04dd9b1680ae 988
bogdanm 86:04dd9b1680ae 989 /** @defgroup TIM_DMA_Base_address
bogdanm 86:04dd9b1680ae 990 * @{
bogdanm 86:04dd9b1680ae 991 */
bogdanm 86:04dd9b1680ae 992 #define TIM_DMABase_CR1 (0x00000000)
bogdanm 86:04dd9b1680ae 993 #define TIM_DMABase_CR2 (0x00000001)
bogdanm 86:04dd9b1680ae 994 #define TIM_DMABase_SMCR (0x00000002)
bogdanm 86:04dd9b1680ae 995 #define TIM_DMABase_DIER (0x00000003)
bogdanm 86:04dd9b1680ae 996 #define TIM_DMABase_SR (0x00000004)
bogdanm 86:04dd9b1680ae 997 #define TIM_DMABase_EGR (0x00000005)
bogdanm 86:04dd9b1680ae 998 #define TIM_DMABase_CCMR1 (0x00000006)
bogdanm 86:04dd9b1680ae 999 #define TIM_DMABase_CCMR2 (0x00000007)
bogdanm 86:04dd9b1680ae 1000 #define TIM_DMABase_CCER (0x00000008)
bogdanm 86:04dd9b1680ae 1001 #define TIM_DMABase_CNT (0x00000009)
bogdanm 86:04dd9b1680ae 1002 #define TIM_DMABase_PSC (0x0000000A)
bogdanm 86:04dd9b1680ae 1003 #define TIM_DMABase_ARR (0x0000000B)
bogdanm 86:04dd9b1680ae 1004 #define TIM_DMABase_RCR (0x0000000C)
bogdanm 86:04dd9b1680ae 1005 #define TIM_DMABase_CCR1 (0x0000000D)
bogdanm 86:04dd9b1680ae 1006 #define TIM_DMABase_CCR2 (0x0000000E)
bogdanm 86:04dd9b1680ae 1007 #define TIM_DMABase_CCR3 (0x0000000F)
bogdanm 86:04dd9b1680ae 1008 #define TIM_DMABase_CCR4 (0x00000010)
bogdanm 86:04dd9b1680ae 1009 #define TIM_DMABase_BDTR (0x00000011)
bogdanm 86:04dd9b1680ae 1010 #define TIM_DMABase_DCR (0x00000012)
bogdanm 86:04dd9b1680ae 1011 #define TIM_DMABase_OR (0x00000013)
bogdanm 86:04dd9b1680ae 1012 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
bogdanm 86:04dd9b1680ae 1013 ((BASE) == TIM_DMABase_CR2) || \
bogdanm 86:04dd9b1680ae 1014 ((BASE) == TIM_DMABase_SMCR) || \
bogdanm 86:04dd9b1680ae 1015 ((BASE) == TIM_DMABase_DIER) || \
bogdanm 86:04dd9b1680ae 1016 ((BASE) == TIM_DMABase_SR) || \
bogdanm 86:04dd9b1680ae 1017 ((BASE) == TIM_DMABase_EGR) || \
bogdanm 86:04dd9b1680ae 1018 ((BASE) == TIM_DMABase_CCMR1) || \
bogdanm 86:04dd9b1680ae 1019 ((BASE) == TIM_DMABase_CCMR2) || \
bogdanm 86:04dd9b1680ae 1020 ((BASE) == TIM_DMABase_CCER) || \
bogdanm 86:04dd9b1680ae 1021 ((BASE) == TIM_DMABase_CNT) || \
bogdanm 86:04dd9b1680ae 1022 ((BASE) == TIM_DMABase_PSC) || \
bogdanm 86:04dd9b1680ae 1023 ((BASE) == TIM_DMABase_ARR) || \
bogdanm 86:04dd9b1680ae 1024 ((BASE) == TIM_DMABase_RCR) || \
bogdanm 86:04dd9b1680ae 1025 ((BASE) == TIM_DMABase_CCR1) || \
bogdanm 86:04dd9b1680ae 1026 ((BASE) == TIM_DMABase_CCR2) || \
bogdanm 86:04dd9b1680ae 1027 ((BASE) == TIM_DMABase_CCR3) || \
bogdanm 86:04dd9b1680ae 1028 ((BASE) == TIM_DMABase_CCR4) || \
bogdanm 86:04dd9b1680ae 1029 ((BASE) == TIM_DMABase_BDTR) || \
bogdanm 86:04dd9b1680ae 1030 ((BASE) == TIM_DMABase_DCR) || \
bogdanm 86:04dd9b1680ae 1031 ((BASE) == TIM_DMABase_OR))
bogdanm 86:04dd9b1680ae 1032 /**
bogdanm 86:04dd9b1680ae 1033 * @}
bogdanm 86:04dd9b1680ae 1034 */
bogdanm 86:04dd9b1680ae 1035
bogdanm 86:04dd9b1680ae 1036 /** @defgroup TIM_DMA_Burst_Length
bogdanm 86:04dd9b1680ae 1037 * @{
bogdanm 86:04dd9b1680ae 1038 */
bogdanm 86:04dd9b1680ae 1039 #define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm 86:04dd9b1680ae 1040 #define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm 86:04dd9b1680ae 1041 #define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm 86:04dd9b1680ae 1042 #define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm 86:04dd9b1680ae 1043 #define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm 86:04dd9b1680ae 1044 #define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm 86:04dd9b1680ae 1045 #define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm 86:04dd9b1680ae 1046 #define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm 86:04dd9b1680ae 1047 #define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm 86:04dd9b1680ae 1048 #define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm 86:04dd9b1680ae 1049 #define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm 86:04dd9b1680ae 1050 #define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm 86:04dd9b1680ae 1051 #define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm 86:04dd9b1680ae 1052 #define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm 86:04dd9b1680ae 1053 #define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm 86:04dd9b1680ae 1054 #define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm 86:04dd9b1680ae 1055 #define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm 86:04dd9b1680ae 1056 #define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm 86:04dd9b1680ae 1057 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
bogdanm 86:04dd9b1680ae 1058 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
bogdanm 86:04dd9b1680ae 1059 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
bogdanm 86:04dd9b1680ae 1060 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
bogdanm 86:04dd9b1680ae 1061 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
bogdanm 86:04dd9b1680ae 1062 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
bogdanm 86:04dd9b1680ae 1063 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
bogdanm 86:04dd9b1680ae 1064 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
bogdanm 86:04dd9b1680ae 1065 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
bogdanm 86:04dd9b1680ae 1066 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
bogdanm 86:04dd9b1680ae 1067 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
bogdanm 86:04dd9b1680ae 1068 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
bogdanm 86:04dd9b1680ae 1069 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
bogdanm 86:04dd9b1680ae 1070 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
bogdanm 86:04dd9b1680ae 1071 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
bogdanm 86:04dd9b1680ae 1072 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
bogdanm 86:04dd9b1680ae 1073 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
bogdanm 86:04dd9b1680ae 1074 ((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm 86:04dd9b1680ae 1075 /**
bogdanm 86:04dd9b1680ae 1076 * @}
bogdanm 86:04dd9b1680ae 1077 */
bogdanm 86:04dd9b1680ae 1078
bogdanm 86:04dd9b1680ae 1079 /** @defgroup TIM_Input_Capture_Filer_Value
bogdanm 86:04dd9b1680ae 1080 * @{
bogdanm 86:04dd9b1680ae 1081 */
bogdanm 86:04dd9b1680ae 1082 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 1083 /**
bogdanm 86:04dd9b1680ae 1084 * @}
bogdanm 86:04dd9b1680ae 1085 */
bogdanm 86:04dd9b1680ae 1086
bogdanm 86:04dd9b1680ae 1087 /** @defgroup DMA_Handle_index
bogdanm 86:04dd9b1680ae 1088 * @{
bogdanm 86:04dd9b1680ae 1089 */
bogdanm 86:04dd9b1680ae 1090 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
bogdanm 86:04dd9b1680ae 1091 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
bogdanm 86:04dd9b1680ae 1092 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
bogdanm 86:04dd9b1680ae 1093 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
bogdanm 86:04dd9b1680ae 1094 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
bogdanm 86:04dd9b1680ae 1095 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
bogdanm 86:04dd9b1680ae 1096 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
bogdanm 86:04dd9b1680ae 1097 /**
bogdanm 86:04dd9b1680ae 1098 * @}
bogdanm 86:04dd9b1680ae 1099 */
bogdanm 86:04dd9b1680ae 1100
bogdanm 86:04dd9b1680ae 1101 /** @defgroup Channel_CC_State
bogdanm 86:04dd9b1680ae 1102 * @{
bogdanm 86:04dd9b1680ae 1103 */
bogdanm 86:04dd9b1680ae 1104 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm 86:04dd9b1680ae 1105 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 1106 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm 86:04dd9b1680ae 1107 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 1108 /**
bogdanm 86:04dd9b1680ae 1109 * @}
bogdanm 86:04dd9b1680ae 1110 */
bogdanm 86:04dd9b1680ae 1111
bogdanm 86:04dd9b1680ae 1112 /**
bogdanm 86:04dd9b1680ae 1113 * @}
bogdanm 86:04dd9b1680ae 1114 */
bogdanm 86:04dd9b1680ae 1115
bogdanm 86:04dd9b1680ae 1116 /* Exported macro ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 1117
bogdanm 86:04dd9b1680ae 1118 /** @brief Reset TIM handle state
bogdanm 86:04dd9b1680ae 1119 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1120 * @retval None
bogdanm 86:04dd9b1680ae 1121 */
bogdanm 86:04dd9b1680ae 1122 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm 86:04dd9b1680ae 1123
bogdanm 86:04dd9b1680ae 1124 /**
bogdanm 86:04dd9b1680ae 1125 * @brief Enable the TIM peripheral.
bogdanm 86:04dd9b1680ae 1126 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1127 * @retval None
bogdanm 86:04dd9b1680ae 1128 */
bogdanm 86:04dd9b1680ae 1129 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
bogdanm 86:04dd9b1680ae 1130
bogdanm 86:04dd9b1680ae 1131 /**
bogdanm 86:04dd9b1680ae 1132 * @brief Enable the TIM main Output.
bogdanm 86:04dd9b1680ae 1133 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1134 * @retval None
bogdanm 86:04dd9b1680ae 1135 */
bogdanm 86:04dd9b1680ae 1136 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
bogdanm 86:04dd9b1680ae 1137
bogdanm 86:04dd9b1680ae 1138
bogdanm 86:04dd9b1680ae 1139 /* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm 86:04dd9b1680ae 1140 channels have been disabled */
bogdanm 86:04dd9b1680ae 1141 #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
bogdanm 86:04dd9b1680ae 1142 #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
bogdanm 86:04dd9b1680ae 1143
bogdanm 86:04dd9b1680ae 1144 /**
bogdanm 86:04dd9b1680ae 1145 * @brief Disable the TIM peripheral.
bogdanm 86:04dd9b1680ae 1146 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1147 * @retval None
bogdanm 86:04dd9b1680ae 1148 */
bogdanm 86:04dd9b1680ae 1149 #define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm 86:04dd9b1680ae 1150 do { \
bogdanm 86:04dd9b1680ae 1151 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm 86:04dd9b1680ae 1152 { \
bogdanm 86:04dd9b1680ae 1153 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm 86:04dd9b1680ae 1154 { \
bogdanm 86:04dd9b1680ae 1155 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm 86:04dd9b1680ae 1156 } \
bogdanm 86:04dd9b1680ae 1157 } \
bogdanm 86:04dd9b1680ae 1158 } while(0)
bogdanm 86:04dd9b1680ae 1159
bogdanm 86:04dd9b1680ae 1160 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
bogdanm 86:04dd9b1680ae 1161 channels have been disabled */
bogdanm 86:04dd9b1680ae 1162 /**
bogdanm 86:04dd9b1680ae 1163 * @brief Disable the TIM main Output.
bogdanm 86:04dd9b1680ae 1164 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1165 * @retval None
bogdanm 86:04dd9b1680ae 1166 */
bogdanm 86:04dd9b1680ae 1167 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm 86:04dd9b1680ae 1168 do { \
bogdanm 86:04dd9b1680ae 1169 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm 86:04dd9b1680ae 1170 { \
bogdanm 86:04dd9b1680ae 1171 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm 86:04dd9b1680ae 1172 { \
bogdanm 86:04dd9b1680ae 1173 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm 86:04dd9b1680ae 1174 } \
bogdanm 86:04dd9b1680ae 1175 } \
bogdanm 86:04dd9b1680ae 1176 } while(0)
bogdanm 86:04dd9b1680ae 1177
bogdanm 86:04dd9b1680ae 1178 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1179 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
bogdanm 86:04dd9b1680ae 1180 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1181 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm 86:04dd9b1680ae 1182 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm 86:04dd9b1680ae 1183 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm 86:04dd9b1680ae 1184
bogdanm 86:04dd9b1680ae 1185 #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 86:04dd9b1680ae 1186 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1187
bogdanm 86:04dd9b1680ae 1188 #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm 86:04dd9b1680ae 1189 #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm 86:04dd9b1680ae 1190
bogdanm 86:04dd9b1680ae 1191 #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 86:04dd9b1680ae 1192 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
bogdanm 86:04dd9b1680ae 1193 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
bogdanm 86:04dd9b1680ae 1194 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
bogdanm 86:04dd9b1680ae 1195 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
bogdanm 86:04dd9b1680ae 1196
bogdanm 86:04dd9b1680ae 1197 #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm 86:04dd9b1680ae 1198 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm 86:04dd9b1680ae 1199 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm 86:04dd9b1680ae 1200 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm 86:04dd9b1680ae 1201 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm 86:04dd9b1680ae 1202
bogdanm 86:04dd9b1680ae 1203 /**
bogdanm 86:04dd9b1680ae 1204 * @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm 86:04dd9b1680ae 1205 * calling another time ConfigChannel function.
bogdanm 86:04dd9b1680ae 1206 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1207 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 86:04dd9b1680ae 1208 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1209 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 86:04dd9b1680ae 1210 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 86:04dd9b1680ae 1211 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 86:04dd9b1680ae 1212 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 86:04dd9b1680ae 1213 * @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm 86:04dd9b1680ae 1214 * @retval None
bogdanm 86:04dd9b1680ae 1215 */
bogdanm 86:04dd9b1680ae 1216 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm 86:04dd9b1680ae 1217 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm 86:04dd9b1680ae 1218
bogdanm 86:04dd9b1680ae 1219 /**
bogdanm 86:04dd9b1680ae 1220 * @brief Gets the TIM Capture Compare Register value on runtime
bogdanm 86:04dd9b1680ae 1221 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1222 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm 86:04dd9b1680ae 1223 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1224 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm 86:04dd9b1680ae 1225 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm 86:04dd9b1680ae 1226 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm 86:04dd9b1680ae 1227 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm 86:04dd9b1680ae 1228 * @retval None
bogdanm 86:04dd9b1680ae 1229 */
bogdanm 86:04dd9b1680ae 1230 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm 86:04dd9b1680ae 1231 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm 86:04dd9b1680ae 1232
bogdanm 86:04dd9b1680ae 1233 /**
bogdanm 86:04dd9b1680ae 1234 * @brief Sets the TIM Counter Register value on runtime.
bogdanm 86:04dd9b1680ae 1235 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1236 * @param __COUNTER__: specifies the Counter register new value.
bogdanm 86:04dd9b1680ae 1237 * @retval None
bogdanm 86:04dd9b1680ae 1238 */
bogdanm 86:04dd9b1680ae 1239 #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm 86:04dd9b1680ae 1240
bogdanm 86:04dd9b1680ae 1241 /**
bogdanm 86:04dd9b1680ae 1242 * @brief Gets the TIM Counter Register value on runtime.
bogdanm 86:04dd9b1680ae 1243 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1244 * @retval None
bogdanm 86:04dd9b1680ae 1245 */
bogdanm 86:04dd9b1680ae 1246 #define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
bogdanm 86:04dd9b1680ae 1247
bogdanm 86:04dd9b1680ae 1248 /**
bogdanm 86:04dd9b1680ae 1249 * @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm 86:04dd9b1680ae 1250 * another time any Init function.
bogdanm 86:04dd9b1680ae 1251 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1252 * @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm 86:04dd9b1680ae 1253 * @retval None
bogdanm 86:04dd9b1680ae 1254 */
bogdanm 86:04dd9b1680ae 1255 #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm 86:04dd9b1680ae 1256 do{ \
bogdanm 86:04dd9b1680ae 1257 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm 86:04dd9b1680ae 1258 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm 86:04dd9b1680ae 1259 } while(0)
bogdanm 86:04dd9b1680ae 1260 /**
bogdanm 86:04dd9b1680ae 1261 * @brief Gets the TIM Autoreload Register value on runtime
bogdanm 86:04dd9b1680ae 1262 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1263 * @retval None
bogdanm 86:04dd9b1680ae 1264 */
bogdanm 86:04dd9b1680ae 1265 #define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
bogdanm 86:04dd9b1680ae 1266
bogdanm 86:04dd9b1680ae 1267 /**
bogdanm 86:04dd9b1680ae 1268 * @brief Sets the TIM Clock Division value on runtime without calling
bogdanm 86:04dd9b1680ae 1269 * another time any Init function.
bogdanm 86:04dd9b1680ae 1270 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1271 * @param __CKD__: specifies the clock division value.
bogdanm 86:04dd9b1680ae 1272 * This parameter can be one of the following value:
bogdanm 86:04dd9b1680ae 1273 * @arg TIM_CLOCKDIVISION_DIV1
bogdanm 86:04dd9b1680ae 1274 * @arg TIM_CLOCKDIVISION_DIV2
bogdanm 86:04dd9b1680ae 1275 * @arg TIM_CLOCKDIVISION_DIV4
bogdanm 86:04dd9b1680ae 1276 * @retval None
bogdanm 86:04dd9b1680ae 1277 */
bogdanm 86:04dd9b1680ae 1278 #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm 86:04dd9b1680ae 1279 do{ \
bogdanm 86:04dd9b1680ae 1280 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm 86:04dd9b1680ae 1281 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
bogdanm 86:04dd9b1680ae 1282 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm 86:04dd9b1680ae 1283 } while(0)
bogdanm 86:04dd9b1680ae 1284 /**
bogdanm 86:04dd9b1680ae 1285 * @brief Gets the TIM Clock Division value on runtime
bogdanm 86:04dd9b1680ae 1286 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1287 * @retval None
bogdanm 86:04dd9b1680ae 1288 */
bogdanm 86:04dd9b1680ae 1289 #define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm 86:04dd9b1680ae 1290
bogdanm 86:04dd9b1680ae 1291 /**
bogdanm 86:04dd9b1680ae 1292 * @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm 86:04dd9b1680ae 1293 * another time HAL_TIM_IC_ConfigChannel() function.
bogdanm 86:04dd9b1680ae 1294 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1295 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 86:04dd9b1680ae 1296 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1297 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 86:04dd9b1680ae 1298 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 86:04dd9b1680ae 1299 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 86:04dd9b1680ae 1300 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 86:04dd9b1680ae 1301 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm 86:04dd9b1680ae 1302 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1303 * @arg TIM_ICPSC_DIV1: no prescaler
bogdanm 86:04dd9b1680ae 1304 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm 86:04dd9b1680ae 1305 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm 86:04dd9b1680ae 1306 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm 86:04dd9b1680ae 1307 * @retval None
bogdanm 86:04dd9b1680ae 1308 */
bogdanm 86:04dd9b1680ae 1309 #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 86:04dd9b1680ae 1310 do{ \
bogdanm 86:04dd9b1680ae 1311 __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm 86:04dd9b1680ae 1312 __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm 86:04dd9b1680ae 1313 } while(0)
bogdanm 86:04dd9b1680ae 1314
bogdanm 86:04dd9b1680ae 1315 /**
bogdanm 86:04dd9b1680ae 1316 * @brief Gets the TIM Input Capture prescaler on runtime
bogdanm 86:04dd9b1680ae 1317 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1318 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 86:04dd9b1680ae 1319 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1320 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm 86:04dd9b1680ae 1321 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm 86:04dd9b1680ae 1322 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm 86:04dd9b1680ae 1323 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm 86:04dd9b1680ae 1324 * @retval None
bogdanm 86:04dd9b1680ae 1325 */
bogdanm 86:04dd9b1680ae 1326 #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm 86:04dd9b1680ae 1327 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm 86:04dd9b1680ae 1328 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm 86:04dd9b1680ae 1329 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm 86:04dd9b1680ae 1330 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm 86:04dd9b1680ae 1331 /**
bogdanm 86:04dd9b1680ae 1332 * @}
bogdanm 86:04dd9b1680ae 1333 */
bogdanm 86:04dd9b1680ae 1334
bogdanm 86:04dd9b1680ae 1335 /* Include TIM HAL Extension module */
bogdanm 86:04dd9b1680ae 1336 #include "stm32f4xx_hal_tim_ex.h"
bogdanm 86:04dd9b1680ae 1337
bogdanm 86:04dd9b1680ae 1338 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 1339
bogdanm 86:04dd9b1680ae 1340 /* Time Base functions ********************************************************/
bogdanm 86:04dd9b1680ae 1341 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1342 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1343 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1344 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1345 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1346 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1347 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1348 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1349 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1350 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1351 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1352 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 1353 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1354
bogdanm 86:04dd9b1680ae 1355 /* Timer Output Compare functions **********************************************/
bogdanm 86:04dd9b1680ae 1356 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1357 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1358 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1359 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1360 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1361 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1362 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1363 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1364 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1365 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1366 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1367 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 1368 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1369
bogdanm 86:04dd9b1680ae 1370 /* Timer PWM functions *********************************************************/
bogdanm 86:04dd9b1680ae 1371 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1372 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1373 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1374 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1375 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1376 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1377 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1378 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1379 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1380 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1381 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1382 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 1383 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1384
bogdanm 86:04dd9b1680ae 1385 /* Timer Input Capture functions ***********************************************/
bogdanm 86:04dd9b1680ae 1386 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1387 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1388 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1389 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1390 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1391 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1392 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1393 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1394 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1395 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1396 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1397 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 1398 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1399
bogdanm 86:04dd9b1680ae 1400 /* Timer One Pulse functions ***************************************************/
bogdanm 86:04dd9b1680ae 1401 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm 86:04dd9b1680ae 1402 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1403 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1404 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1405 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1406 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 1407 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 1408
bogdanm 86:04dd9b1680ae 1409 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1410 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 1411 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 1412
bogdanm 86:04dd9b1680ae 1413 /* Timer Encoder functions *****************************************************/
bogdanm 86:04dd9b1680ae 1414 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
bogdanm 86:04dd9b1680ae 1415 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1416 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1417 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1418 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1419 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1420 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1421 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1422 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1423 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1424 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1425 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
bogdanm 86:04dd9b1680ae 1426 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1427
bogdanm 86:04dd9b1680ae 1428 /* Interrupt Handler functions **********************************************/
bogdanm 86:04dd9b1680ae 1429 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1430
bogdanm 86:04dd9b1680ae 1431 /* Control functions *********************************************************/
bogdanm 86:04dd9b1680ae 1432 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1433 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1434 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1435 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm 86:04dd9b1680ae 1436 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1437 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
bogdanm 86:04dd9b1680ae 1438 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm 86:04dd9b1680ae 1439 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm 86:04dd9b1680ae 1440 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 86:04dd9b1680ae 1441 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 86:04dd9b1680ae 1442 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 86:04dd9b1680ae 1443 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 86:04dd9b1680ae 1444 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 86:04dd9b1680ae 1445 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 86:04dd9b1680ae 1446 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm 86:04dd9b1680ae 1447 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1448
bogdanm 86:04dd9b1680ae 1449 /* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm 86:04dd9b1680ae 1450 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1451 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1452 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1453 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1454 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1455 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1456
bogdanm 86:04dd9b1680ae 1457 /* Peripheral State functions **************************************************/
bogdanm 86:04dd9b1680ae 1458 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1459 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1460 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1461 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1462 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1463 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1464
bogdanm 86:04dd9b1680ae 1465 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
bogdanm 86:04dd9b1680ae 1466 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm 86:04dd9b1680ae 1467 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 86:04dd9b1680ae 1468 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 1469 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 1470 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 1471 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm 86:04dd9b1680ae 1472
bogdanm 86:04dd9b1680ae 1473 /**
bogdanm 86:04dd9b1680ae 1474 * @}
bogdanm 86:04dd9b1680ae 1475 */
bogdanm 86:04dd9b1680ae 1476
bogdanm 86:04dd9b1680ae 1477 /**
bogdanm 86:04dd9b1680ae 1478 * @}
bogdanm 86:04dd9b1680ae 1479 */
bogdanm 86:04dd9b1680ae 1480
bogdanm 86:04dd9b1680ae 1481 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 1482 }
bogdanm 86:04dd9b1680ae 1483 #endif
bogdanm 86:04dd9b1680ae 1484
bogdanm 86:04dd9b1680ae 1485 #endif /* __STM32F4xx_HAL_TIM_H */
bogdanm 86:04dd9b1680ae 1486
bogdanm 86:04dd9b1680ae 1487 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/