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TARGET_NUCLEO_F401RE/stm32f4xx_hal_sram.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
90:cb3d968589d8 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_sram.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.1.0
Kojto 90:cb3d968589d8 6 * @date 19-June-2014
emilmont 77:869cf507173a 7 * @brief Header file of SRAM HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_SRAM_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_SRAM_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 48 #include "stm32f4xx_ll_fsmc.h"
emilmont 77:869cf507173a 49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 52 #include "stm32f4xx_ll_fmc.h"
emilmont 77:869cf507173a 53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55
emilmont 77:869cf507173a 56 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 57 * @{
emilmont 77:869cf507173a 58 */
emilmont 77:869cf507173a 59
emilmont 77:869cf507173a 60 /** @addtogroup SRAM
emilmont 77:869cf507173a 61 * @{
emilmont 77:869cf507173a 62 */
emilmont 77:869cf507173a 63
emilmont 77:869cf507173a 64 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
emilmont 77:869cf507173a 65
emilmont 77:869cf507173a 66 /* Exported typedef ----------------------------------------------------------*/
emilmont 77:869cf507173a 67
emilmont 77:869cf507173a 68 /**
emilmont 77:869cf507173a 69 * @brief HAL SRAM State structures definition
emilmont 77:869cf507173a 70 */
emilmont 77:869cf507173a 71 typedef enum
emilmont 77:869cf507173a 72 {
emilmont 77:869cf507173a 73 HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */
emilmont 77:869cf507173a 74 HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */
emilmont 77:869cf507173a 75 HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */
emilmont 77:869cf507173a 76 HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */
emilmont 77:869cf507173a 77 HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */
emilmont 77:869cf507173a 78
emilmont 77:869cf507173a 79 }HAL_SRAM_StateTypeDef;
emilmont 77:869cf507173a 80
emilmont 77:869cf507173a 81 /**
emilmont 77:869cf507173a 82 * @brief SRAM handle Structure definition
emilmont 77:869cf507173a 83 */
emilmont 77:869cf507173a 84 typedef struct
emilmont 77:869cf507173a 85 {
emilmont 77:869cf507173a 86 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
emilmont 77:869cf507173a 89
emilmont 77:869cf507173a 90 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
emilmont 77:869cf507173a 91
emilmont 77:869cf507173a 92 HAL_LockTypeDef Lock; /*!< SRAM locking object */
emilmont 77:869cf507173a 93
emilmont 77:869cf507173a 94 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
emilmont 77:869cf507173a 95
emilmont 77:869cf507173a 96 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
emilmont 77:869cf507173a 97
emilmont 77:869cf507173a 98 }SRAM_HandleTypeDef;
emilmont 77:869cf507173a 99
bogdanm 85:024bf7f99721 100 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 101 /* Exported macro ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 102
bogdanm 85:024bf7f99721 103 /** @brief Reset SRAM handle state
bogdanm 85:024bf7f99721 104 * @param __HANDLE__: SRAM handle
bogdanm 85:024bf7f99721 105 * @retval None
bogdanm 85:024bf7f99721 106 */
bogdanm 85:024bf7f99721 107 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
bogdanm 85:024bf7f99721 108
emilmont 77:869cf507173a 109 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 110
emilmont 77:869cf507173a 111 /* Initialization/de-initialization functions **********************************/
emilmont 77:869cf507173a 112 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
emilmont 77:869cf507173a 113 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
bogdanm 81:7d30d6019079 114 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
bogdanm 81:7d30d6019079 115 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
emilmont 77:869cf507173a 116
emilmont 77:869cf507173a 117 /* I/O operation functions *****************************************************/
emilmont 77:869cf507173a 118 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 119 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 120 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 121 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 122 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 123 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 124 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 125 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 126
bogdanm 81:7d30d6019079 127 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
bogdanm 81:7d30d6019079 128 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 129
emilmont 77:869cf507173a 130 /* SRAM Control functions ******************************************************/
emilmont 77:869cf507173a 131 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
emilmont 77:869cf507173a 132 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
emilmont 77:869cf507173a 133
emilmont 77:869cf507173a 134 /* SRAM State functions *********************************************************/
emilmont 77:869cf507173a 135 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
emilmont 77:869cf507173a 136
emilmont 77:869cf507173a 137 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 138 /**
emilmont 77:869cf507173a 139 * @}
emilmont 77:869cf507173a 140 */
emilmont 77:869cf507173a 141
emilmont 77:869cf507173a 142 /**
emilmont 77:869cf507173a 143 * @}
emilmont 77:869cf507173a 144 */
emilmont 77:869cf507173a 145
emilmont 77:869cf507173a 146 #ifdef __cplusplus
emilmont 77:869cf507173a 147 }
emilmont 77:869cf507173a 148 #endif
emilmont 77:869cf507173a 149
emilmont 77:869cf507173a 150 #endif /* __STM32F4xx_HAL_SRAM_H */
emilmont 77:869cf507173a 151
emilmont 77:869cf507173a 152 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/