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TARGET_NUCLEO_F401RE/stm32f4xx_hal_sdram.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
90:cb3d968589d8 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_sdram.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.1.0
Kojto 90:cb3d968589d8 6 * @date 19-June-2014
emilmont 77:869cf507173a 7 * @brief Header file of SDRAM HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_SDRAM_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_SDRAM_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 49 #include "stm32f4xx_ll_fmc.h"
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 52 * @{
emilmont 77:869cf507173a 53 */
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55 /** @addtogroup SDRAM
emilmont 77:869cf507173a 56 * @{
emilmont 77:869cf507173a 57 */
emilmont 77:869cf507173a 58
emilmont 77:869cf507173a 59 /* Exported typedef ----------------------------------------------------------*/
emilmont 77:869cf507173a 60
emilmont 77:869cf507173a 61 /**
emilmont 77:869cf507173a 62 * @brief HAL SDRAM State structure definition
emilmont 77:869cf507173a 63 */
emilmont 77:869cf507173a 64 typedef enum
emilmont 77:869cf507173a 65 {
emilmont 77:869cf507173a 66 HAL_SDRAM_STATE_RESET = 0x00, /*!< SDRAM not yet initialized or disabled */
emilmont 77:869cf507173a 67 HAL_SDRAM_STATE_READY = 0x01, /*!< SDRAM initialized and ready for use */
emilmont 77:869cf507173a 68 HAL_SDRAM_STATE_BUSY = 0x02, /*!< SDRAM internal process is ongoing */
emilmont 77:869cf507173a 69 HAL_SDRAM_STATE_ERROR = 0x03, /*!< SDRAM error state */
emilmont 77:869cf507173a 70 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, /*!< SDRAM device write protected */
emilmont 77:869cf507173a 71 HAL_SDRAM_STATE_PRECHARGED = 0x05 /*!< SDRAM device precharged */
emilmont 77:869cf507173a 72
emilmont 77:869cf507173a 73 }HAL_SDRAM_StateTypeDef;
emilmont 77:869cf507173a 74
emilmont 77:869cf507173a 75 /**
emilmont 77:869cf507173a 76 * @brief SDRAM handle Structure definition
emilmont 77:869cf507173a 77 */
emilmont 77:869cf507173a 78 typedef struct
emilmont 77:869cf507173a 79 {
emilmont 77:869cf507173a 80 FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
emilmont 77:869cf507173a 81
emilmont 77:869cf507173a 82 FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
emilmont 77:869cf507173a 83
emilmont 77:869cf507173a 84 __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 HAL_LockTypeDef Lock; /*!< SDRAM locking object */
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
emilmont 77:869cf507173a 89
emilmont 77:869cf507173a 90 }SDRAM_HandleTypeDef;
emilmont 77:869cf507173a 91
bogdanm 85:024bf7f99721 92 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 93 /* Exported macro ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 94
bogdanm 85:024bf7f99721 95 /** @brief Reset SDRAM handle state
bogdanm 85:024bf7f99721 96 * @param __HANDLE__: specifies the SDRAM handle.
bogdanm 85:024bf7f99721 97 * @retval None
bogdanm 85:024bf7f99721 98 */
bogdanm 85:024bf7f99721 99 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
bogdanm 85:024bf7f99721 100
emilmont 77:869cf507173a 101 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 102
emilmont 77:869cf507173a 103 /* Initialization/de-initialization functions **********************************/
emilmont 77:869cf507173a 104 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
emilmont 77:869cf507173a 105 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 81:7d30d6019079 106 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 81:7d30d6019079 107 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
emilmont 77:869cf507173a 108
emilmont 77:869cf507173a 109 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
bogdanm 81:7d30d6019079 110 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
bogdanm 81:7d30d6019079 111 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
bogdanm 81:7d30d6019079 112 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
emilmont 77:869cf507173a 113
emilmont 77:869cf507173a 114 /* I/O operation functions *****************************************************/
emilmont 77:869cf507173a 115 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 116 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 117 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 118 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 119 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 120 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 121
emilmont 77:869cf507173a 122 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 123 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
emilmont 77:869cf507173a 124
emilmont 77:869cf507173a 125 /* SDRAM Control functions *****************************************************/
emilmont 77:869cf507173a 126 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
emilmont 77:869cf507173a 127 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
emilmont 77:869cf507173a 128 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
emilmont 77:869cf507173a 129 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
emilmont 77:869cf507173a 130 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
emilmont 77:869cf507173a 131 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
emilmont 77:869cf507173a 132
emilmont 77:869cf507173a 133 /* SDRAM State functions ********************************************************/
emilmont 77:869cf507173a 134 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 137 /**
emilmont 77:869cf507173a 138 * @}
emilmont 77:869cf507173a 139 */
emilmont 77:869cf507173a 140
emilmont 77:869cf507173a 141 /**
emilmont 77:869cf507173a 142 * @}
emilmont 77:869cf507173a 143 */
emilmont 77:869cf507173a 144
emilmont 77:869cf507173a 145 #ifdef __cplusplus
emilmont 77:869cf507173a 146 }
emilmont 77:869cf507173a 147 #endif
emilmont 77:869cf507173a 148
emilmont 77:869cf507173a 149 #endif /* __STM32F4xx_HAL_SDRAM_H */
emilmont 77:869cf507173a 150
emilmont 77:869cf507173a 151 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/