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TARGET_NUCLEO_F303RE/stm32f3xx_hal_rcc_ex.h@99:7f6c6de930c0, 2015-05-03 (annotated)
- Committer:
- Mikchel
- Date:
- Sun May 03 16:04:42 2015 +0000
- Revision:
- 99:7f6c6de930c0
- Parent:
- 93:e188a91d3eaa
12
Who changed what in which revision?
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Kojto | 93:e188a91d3eaa | 1 | /** |
Kojto | 93:e188a91d3eaa | 2 | ****************************************************************************** |
Kojto | 93:e188a91d3eaa | 3 | * @file stm32f3xx_hal_rcc_ex.h |
Kojto | 93:e188a91d3eaa | 4 | * @author MCD Application Team |
Kojto | 93:e188a91d3eaa | 5 | * @version V1.1.0 |
Kojto | 93:e188a91d3eaa | 6 | * @date 12-Sept-2014 |
Kojto | 93:e188a91d3eaa | 7 | * @brief Header file of RCC HAL Extended module. |
Kojto | 93:e188a91d3eaa | 8 | ****************************************************************************** |
Kojto | 93:e188a91d3eaa | 9 | * @attention |
Kojto | 93:e188a91d3eaa | 10 | * |
Kojto | 93:e188a91d3eaa | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
Kojto | 93:e188a91d3eaa | 12 | * |
Kojto | 93:e188a91d3eaa | 13 | * Redistribution and use in source and binary forms, with or without modification, |
Kojto | 93:e188a91d3eaa | 14 | * are permitted provided that the following conditions are met: |
Kojto | 93:e188a91d3eaa | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
Kojto | 93:e188a91d3eaa | 16 | * this list of conditions and the following disclaimer. |
Kojto | 93:e188a91d3eaa | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
Kojto | 93:e188a91d3eaa | 18 | * this list of conditions and the following disclaimer in the documentation |
Kojto | 93:e188a91d3eaa | 19 | * and/or other materials provided with the distribution. |
Kojto | 93:e188a91d3eaa | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
Kojto | 93:e188a91d3eaa | 21 | * may be used to endorse or promote products derived from this software |
Kojto | 93:e188a91d3eaa | 22 | * without specific prior written permission. |
Kojto | 93:e188a91d3eaa | 23 | * |
Kojto | 93:e188a91d3eaa | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
Kojto | 93:e188a91d3eaa | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
Kojto | 93:e188a91d3eaa | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
Kojto | 93:e188a91d3eaa | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
Kojto | 93:e188a91d3eaa | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
Kojto | 93:e188a91d3eaa | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
Kojto | 93:e188a91d3eaa | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
Kojto | 93:e188a91d3eaa | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
Kojto | 93:e188a91d3eaa | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
Kojto | 93:e188a91d3eaa | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Kojto | 93:e188a91d3eaa | 34 | * |
Kojto | 93:e188a91d3eaa | 35 | ****************************************************************************** |
Kojto | 93:e188a91d3eaa | 36 | */ |
Kojto | 93:e188a91d3eaa | 37 | |
Kojto | 93:e188a91d3eaa | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
Kojto | 93:e188a91d3eaa | 39 | #ifndef __STM32F3xx_HAL_RCC_EX_H |
Kojto | 93:e188a91d3eaa | 40 | #define __STM32F3xx_HAL_RCC_EX_H |
Kojto | 93:e188a91d3eaa | 41 | |
Kojto | 93:e188a91d3eaa | 42 | #ifdef __cplusplus |
Kojto | 93:e188a91d3eaa | 43 | extern "C" { |
Kojto | 93:e188a91d3eaa | 44 | #endif |
Kojto | 93:e188a91d3eaa | 45 | |
Kojto | 93:e188a91d3eaa | 46 | /* Includes ------------------------------------------------------------------*/ |
Kojto | 93:e188a91d3eaa | 47 | #include "stm32f3xx_hal_def.h" |
Kojto | 93:e188a91d3eaa | 48 | |
Kojto | 93:e188a91d3eaa | 49 | /** @addtogroup STM32F3xx_HAL_Driver |
Kojto | 93:e188a91d3eaa | 50 | * @{ |
Kojto | 93:e188a91d3eaa | 51 | */ |
Kojto | 93:e188a91d3eaa | 52 | |
Kojto | 93:e188a91d3eaa | 53 | /** @addtogroup RCCEx |
Kojto | 93:e188a91d3eaa | 54 | * @{ |
Kojto | 93:e188a91d3eaa | 55 | */ |
Kojto | 93:e188a91d3eaa | 56 | |
Kojto | 93:e188a91d3eaa | 57 | /* Exported types ------------------------------------------------------------*/ |
Kojto | 93:e188a91d3eaa | 58 | |
Kojto | 93:e188a91d3eaa | 59 | /** @defgroup RCCEx_Exported_Types RCC Extended Exported Types |
Kojto | 93:e188a91d3eaa | 60 | * @{ |
Kojto | 93:e188a91d3eaa | 61 | */ |
Kojto | 93:e188a91d3eaa | 62 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 63 | /** |
Kojto | 93:e188a91d3eaa | 64 | * @brief RCC PLL configuration structure definition |
Kojto | 93:e188a91d3eaa | 65 | */ |
Kojto | 93:e188a91d3eaa | 66 | typedef struct |
Kojto | 93:e188a91d3eaa | 67 | { |
Kojto | 93:e188a91d3eaa | 68 | uint32_t PLLState; /*!< PLLState: The new state of the PLL. |
Kojto | 93:e188a91d3eaa | 69 | This parameter can be a value of @ref RCC_PLL_Config */ |
Kojto | 93:e188a91d3eaa | 70 | |
Kojto | 93:e188a91d3eaa | 71 | uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. |
Kojto | 93:e188a91d3eaa | 72 | This parameter must be a value of @ref RCCEx_PLL_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 73 | |
Kojto | 93:e188a91d3eaa | 74 | uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock |
Kojto | 93:e188a91d3eaa | 75 | This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ |
Kojto | 93:e188a91d3eaa | 76 | |
Kojto | 93:e188a91d3eaa | 77 | uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock |
Kojto | 93:e188a91d3eaa | 78 | This parameter must be a value of @ref RCCEx_PLL_Prediv_Factor */ |
Kojto | 93:e188a91d3eaa | 79 | |
Kojto | 93:e188a91d3eaa | 80 | }RCC_PLLInitTypeDef; |
Kojto | 93:e188a91d3eaa | 81 | |
Kojto | 93:e188a91d3eaa | 82 | /** |
Kojto | 93:e188a91d3eaa | 83 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
Kojto | 93:e188a91d3eaa | 84 | */ |
Kojto | 93:e188a91d3eaa | 85 | typedef struct |
Kojto | 93:e188a91d3eaa | 86 | { |
Kojto | 93:e188a91d3eaa | 87 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
Kojto | 93:e188a91d3eaa | 88 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
Kojto | 93:e188a91d3eaa | 89 | |
Kojto | 93:e188a91d3eaa | 90 | uint32_t HSEState; /*!< The new state of the HSE. |
Kojto | 93:e188a91d3eaa | 91 | This parameter can be a value of @ref RCC_HSE_Config */ |
Kojto | 93:e188a91d3eaa | 92 | |
Kojto | 93:e188a91d3eaa | 93 | uint32_t LSEState; /*!< The new state of the LSE. |
Kojto | 93:e188a91d3eaa | 94 | This parameter can be a value of @ref RCC_LSE_Config */ |
Kojto | 93:e188a91d3eaa | 95 | |
Kojto | 93:e188a91d3eaa | 96 | uint32_t HSIState; /*!< The new state of the HSI. |
Kojto | 93:e188a91d3eaa | 97 | This parameter can be a value of @ref RCC_HSI_Config */ |
Kojto | 93:e188a91d3eaa | 98 | |
Kojto | 93:e188a91d3eaa | 99 | uint32_t HSICalibrationValue; /*!< The calibration trimming value. |
Kojto | 93:e188a91d3eaa | 100 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
Kojto | 93:e188a91d3eaa | 101 | |
Kojto | 93:e188a91d3eaa | 102 | uint32_t LSIState; /*!< The new state of the LSI. |
Kojto | 93:e188a91d3eaa | 103 | This parameter can be a value of @ref RCC_LSI_Config */ |
Kojto | 93:e188a91d3eaa | 104 | |
Kojto | 93:e188a91d3eaa | 105 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
Kojto | 93:e188a91d3eaa | 106 | |
Kojto | 93:e188a91d3eaa | 107 | }RCC_OscInitTypeDef; |
Kojto | 93:e188a91d3eaa | 108 | |
Kojto | 93:e188a91d3eaa | 109 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 110 | |
Kojto | 93:e188a91d3eaa | 111 | #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 112 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 113 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
Kojto | 93:e188a91d3eaa | 114 | defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 115 | /** |
Kojto | 93:e188a91d3eaa | 116 | * @brief RCC PLL configuration structure definition |
Kojto | 93:e188a91d3eaa | 117 | */ |
Kojto | 93:e188a91d3eaa | 118 | typedef struct |
Kojto | 93:e188a91d3eaa | 119 | { |
Kojto | 93:e188a91d3eaa | 120 | uint32_t PLLState; /*!< PLLState: The new state of the PLL. |
Kojto | 93:e188a91d3eaa | 121 | This parameter can be a value of @ref RCC_PLL_Config */ |
Kojto | 93:e188a91d3eaa | 122 | |
Kojto | 93:e188a91d3eaa | 123 | uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. |
Kojto | 93:e188a91d3eaa | 124 | This parameter must be a value of @ref RCCEx_PLL_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 125 | |
Kojto | 93:e188a91d3eaa | 126 | uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock |
Kojto | 93:e188a91d3eaa | 127 | This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ |
Kojto | 93:e188a91d3eaa | 128 | |
Kojto | 93:e188a91d3eaa | 129 | }RCC_PLLInitTypeDef; |
Kojto | 93:e188a91d3eaa | 130 | |
Kojto | 93:e188a91d3eaa | 131 | /** |
Kojto | 93:e188a91d3eaa | 132 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
Kojto | 93:e188a91d3eaa | 133 | */ |
Kojto | 93:e188a91d3eaa | 134 | typedef struct |
Kojto | 93:e188a91d3eaa | 135 | { |
Kojto | 93:e188a91d3eaa | 136 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
Kojto | 93:e188a91d3eaa | 137 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
Kojto | 93:e188a91d3eaa | 138 | |
Kojto | 93:e188a91d3eaa | 139 | uint32_t HSEState; /*!< The new state of the HSE. |
Kojto | 93:e188a91d3eaa | 140 | This parameter can be a value of @ref RCC_HSE_Config */ |
Kojto | 93:e188a91d3eaa | 141 | |
Kojto | 93:e188a91d3eaa | 142 | uint32_t HSEPredivValue; /*!< The HSE predivision factor value. |
Kojto | 93:e188a91d3eaa | 143 | This parameter can be a value of @ref RCCEx_HSE_Predivision_Factor */ |
Kojto | 93:e188a91d3eaa | 144 | |
Kojto | 93:e188a91d3eaa | 145 | uint32_t LSEState; /*!< The new state of the LSE. |
Kojto | 93:e188a91d3eaa | 146 | This parameter can be a value of @ref RCC_LSE_Config */ |
Kojto | 93:e188a91d3eaa | 147 | |
Kojto | 93:e188a91d3eaa | 148 | uint32_t HSIState; /*!< The new state of the HSI. |
Kojto | 93:e188a91d3eaa | 149 | This parameter can be a value of @ref RCC_HSI_Config */ |
Kojto | 93:e188a91d3eaa | 150 | |
Kojto | 93:e188a91d3eaa | 151 | uint32_t HSICalibrationValue; /*!< The calibration trimming value. |
Kojto | 93:e188a91d3eaa | 152 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
Kojto | 93:e188a91d3eaa | 153 | |
Kojto | 93:e188a91d3eaa | 154 | uint32_t LSIState; /*!< The new state of the LSI. |
Kojto | 93:e188a91d3eaa | 155 | This parameter can be a value of @ref RCC_LSI_Config */ |
Kojto | 93:e188a91d3eaa | 156 | |
Kojto | 93:e188a91d3eaa | 157 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
Kojto | 93:e188a91d3eaa | 158 | |
Kojto | 93:e188a91d3eaa | 159 | }RCC_OscInitTypeDef; |
Kojto | 93:e188a91d3eaa | 160 | #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 161 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 162 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 163 | /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 164 | |
Kojto | 93:e188a91d3eaa | 165 | /** |
Kojto | 93:e188a91d3eaa | 166 | * @brief RCC extended clocks structure definition |
Kojto | 93:e188a91d3eaa | 167 | */ |
Kojto | 93:e188a91d3eaa | 168 | #if defined(STM32F301x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 169 | typedef struct |
Kojto | 93:e188a91d3eaa | 170 | { |
Kojto | 93:e188a91d3eaa | 171 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 172 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 173 | |
Kojto | 93:e188a91d3eaa | 174 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 175 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 176 | |
Kojto | 93:e188a91d3eaa | 177 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 178 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 179 | |
Kojto | 93:e188a91d3eaa | 180 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 181 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 182 | |
Kojto | 93:e188a91d3eaa | 183 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 184 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 185 | |
Kojto | 93:e188a91d3eaa | 186 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 187 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 188 | |
Kojto | 93:e188a91d3eaa | 189 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 190 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 191 | |
Kojto | 93:e188a91d3eaa | 192 | uint32_t I2c3ClockSelection; /*!< I2C3 clock source |
Kojto | 93:e188a91d3eaa | 193 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 194 | |
Kojto | 93:e188a91d3eaa | 195 | uint32_t Adc1ClockSelection; /*!< ADC1 clock source |
Kojto | 93:e188a91d3eaa | 196 | This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 197 | |
Kojto | 93:e188a91d3eaa | 198 | uint32_t I2sClockSelection; /*!< I2S clock source |
Kojto | 93:e188a91d3eaa | 199 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 200 | |
Kojto | 93:e188a91d3eaa | 201 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 202 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 203 | |
Kojto | 93:e188a91d3eaa | 204 | uint32_t Tim15ClockSelection; /*!< TIM15 clock source |
Kojto | 93:e188a91d3eaa | 205 | This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 206 | |
Kojto | 93:e188a91d3eaa | 207 | uint32_t Tim16ClockSelection; /*!< TIM16 clock source |
Kojto | 93:e188a91d3eaa | 208 | This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 209 | |
Kojto | 93:e188a91d3eaa | 210 | uint32_t Tim17ClockSelection; /*!< TIM17 clock source |
Kojto | 93:e188a91d3eaa | 211 | This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 212 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 213 | #endif /* STM32F301x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 214 | |
Kojto | 93:e188a91d3eaa | 215 | #if defined(STM32F302x8) |
Kojto | 93:e188a91d3eaa | 216 | typedef struct |
Kojto | 93:e188a91d3eaa | 217 | { |
Kojto | 93:e188a91d3eaa | 218 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 219 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 220 | |
Kojto | 93:e188a91d3eaa | 221 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 222 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 223 | |
Kojto | 93:e188a91d3eaa | 224 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 225 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 226 | |
Kojto | 93:e188a91d3eaa | 227 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 228 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 229 | |
Kojto | 93:e188a91d3eaa | 230 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 231 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 232 | |
Kojto | 93:e188a91d3eaa | 233 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 234 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 235 | |
Kojto | 93:e188a91d3eaa | 236 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 237 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 238 | |
Kojto | 93:e188a91d3eaa | 239 | uint32_t I2c3ClockSelection; /*!< I2C3 clock source |
Kojto | 93:e188a91d3eaa | 240 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 241 | |
Kojto | 93:e188a91d3eaa | 242 | uint32_t Adc1ClockSelection; /*!< ADC1 clock source |
Kojto | 93:e188a91d3eaa | 243 | This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 244 | |
Kojto | 93:e188a91d3eaa | 245 | uint32_t I2sClockSelection; /*!< I2S clock source |
Kojto | 93:e188a91d3eaa | 246 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 247 | |
Kojto | 93:e188a91d3eaa | 248 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 249 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 250 | |
Kojto | 93:e188a91d3eaa | 251 | uint32_t Tim15ClockSelection; /*!< TIM15 clock source |
Kojto | 93:e188a91d3eaa | 252 | This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 253 | |
Kojto | 93:e188a91d3eaa | 254 | uint32_t Tim16ClockSelection; /*!< TIM16 clock source |
Kojto | 93:e188a91d3eaa | 255 | This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 256 | |
Kojto | 93:e188a91d3eaa | 257 | uint32_t Tim17ClockSelection; /*!< TIM17 clock source |
Kojto | 93:e188a91d3eaa | 258 | This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 259 | |
Kojto | 93:e188a91d3eaa | 260 | uint32_t USBClockSelection; /*!< USB clock source |
Kojto | 93:e188a91d3eaa | 261 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 262 | |
Kojto | 93:e188a91d3eaa | 263 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 264 | #endif /* STM32F302x8 */ |
Kojto | 93:e188a91d3eaa | 265 | |
Kojto | 93:e188a91d3eaa | 266 | #if defined(STM32F302xC) |
Kojto | 93:e188a91d3eaa | 267 | typedef struct |
Kojto | 93:e188a91d3eaa | 268 | { |
Kojto | 93:e188a91d3eaa | 269 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 270 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 271 | |
Kojto | 93:e188a91d3eaa | 272 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 273 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 274 | |
Kojto | 93:e188a91d3eaa | 275 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 276 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 277 | |
Kojto | 93:e188a91d3eaa | 278 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 279 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 280 | |
Kojto | 93:e188a91d3eaa | 281 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 282 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 283 | |
Kojto | 93:e188a91d3eaa | 284 | uint32_t Uart4ClockSelection; /*!< UART4 clock source |
Kojto | 93:e188a91d3eaa | 285 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 286 | |
Kojto | 93:e188a91d3eaa | 287 | uint32_t Uart5ClockSelection; /*!< UART5 clock source |
Kojto | 93:e188a91d3eaa | 288 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 289 | |
Kojto | 93:e188a91d3eaa | 290 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 291 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 292 | |
Kojto | 93:e188a91d3eaa | 293 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 294 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 295 | |
Kojto | 93:e188a91d3eaa | 296 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 297 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 298 | |
Kojto | 93:e188a91d3eaa | 299 | uint32_t I2sClockSelection; /*!< I2S clock source |
Kojto | 93:e188a91d3eaa | 300 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 301 | |
Kojto | 93:e188a91d3eaa | 302 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 303 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 304 | |
Kojto | 93:e188a91d3eaa | 305 | uint32_t USBClockSelection; /*!< USB clock source |
Kojto | 93:e188a91d3eaa | 306 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 307 | |
Kojto | 93:e188a91d3eaa | 308 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 309 | #endif /* STM32F302xC */ |
Kojto | 93:e188a91d3eaa | 310 | |
Kojto | 93:e188a91d3eaa | 311 | #if defined(STM32F303xC) |
Kojto | 93:e188a91d3eaa | 312 | typedef struct |
Kojto | 93:e188a91d3eaa | 313 | { |
Kojto | 93:e188a91d3eaa | 314 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 315 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 316 | |
Kojto | 93:e188a91d3eaa | 317 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 318 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 319 | |
Kojto | 93:e188a91d3eaa | 320 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 321 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 322 | |
Kojto | 93:e188a91d3eaa | 323 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 324 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 325 | |
Kojto | 93:e188a91d3eaa | 326 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 327 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 328 | |
Kojto | 93:e188a91d3eaa | 329 | uint32_t Uart4ClockSelection; /*!< UART4 clock source |
Kojto | 93:e188a91d3eaa | 330 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 331 | |
Kojto | 93:e188a91d3eaa | 332 | uint32_t Uart5ClockSelection; /*!< UART5 clock source |
Kojto | 93:e188a91d3eaa | 333 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 334 | |
Kojto | 93:e188a91d3eaa | 335 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 336 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 337 | |
Kojto | 93:e188a91d3eaa | 338 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 339 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 340 | |
Kojto | 93:e188a91d3eaa | 341 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 342 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 343 | |
Kojto | 93:e188a91d3eaa | 344 | uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source |
Kojto | 93:e188a91d3eaa | 345 | This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 346 | |
Kojto | 93:e188a91d3eaa | 347 | uint32_t I2sClockSelection; /*!< I2S clock source |
Kojto | 93:e188a91d3eaa | 348 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 349 | |
Kojto | 93:e188a91d3eaa | 350 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 351 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 352 | |
Kojto | 93:e188a91d3eaa | 353 | uint32_t Tim8ClockSelection; /*!< TIM8 clock source |
Kojto | 93:e188a91d3eaa | 354 | This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 355 | |
Kojto | 93:e188a91d3eaa | 356 | uint32_t USBClockSelection; /*!< USB clock source |
Kojto | 93:e188a91d3eaa | 357 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 358 | |
Kojto | 93:e188a91d3eaa | 359 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 360 | #endif /* STM32F303xC */ |
Kojto | 93:e188a91d3eaa | 361 | |
Kojto | 93:e188a91d3eaa | 362 | #if defined(STM32F302xE) |
Kojto | 93:e188a91d3eaa | 363 | typedef struct |
Kojto | 93:e188a91d3eaa | 364 | { |
Kojto | 93:e188a91d3eaa | 365 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 366 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 367 | |
Kojto | 93:e188a91d3eaa | 368 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 369 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 370 | |
Kojto | 93:e188a91d3eaa | 371 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 372 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 373 | |
Kojto | 93:e188a91d3eaa | 374 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 375 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 376 | |
Kojto | 93:e188a91d3eaa | 377 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 378 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 379 | |
Kojto | 93:e188a91d3eaa | 380 | uint32_t Uart4ClockSelection; /*!< UART4 clock source |
Kojto | 93:e188a91d3eaa | 381 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 382 | |
Kojto | 93:e188a91d3eaa | 383 | uint32_t Uart5ClockSelection; /*!< UART5 clock source |
Kojto | 93:e188a91d3eaa | 384 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 385 | |
Kojto | 93:e188a91d3eaa | 386 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 387 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 388 | |
Kojto | 93:e188a91d3eaa | 389 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 390 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 391 | |
Kojto | 93:e188a91d3eaa | 392 | uint32_t I2c3ClockSelection; /*!< I2C3 clock source |
Kojto | 93:e188a91d3eaa | 393 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 394 | |
Kojto | 93:e188a91d3eaa | 395 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 396 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 397 | |
Kojto | 93:e188a91d3eaa | 398 | uint32_t I2sClockSelection; /*!< I2S clock source |
Kojto | 93:e188a91d3eaa | 399 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 400 | |
Kojto | 93:e188a91d3eaa | 401 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 402 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 403 | |
Kojto | 93:e188a91d3eaa | 404 | uint32_t Tim2ClockSelection; /*!< TIM2 clock source |
Kojto | 93:e188a91d3eaa | 405 | This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 406 | |
Kojto | 93:e188a91d3eaa | 407 | uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source |
Kojto | 93:e188a91d3eaa | 408 | This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 409 | |
Kojto | 93:e188a91d3eaa | 410 | uint32_t Tim15ClockSelection; /*!< TIM15 clock source |
Kojto | 93:e188a91d3eaa | 411 | This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 412 | |
Kojto | 93:e188a91d3eaa | 413 | uint32_t Tim16ClockSelection; /*!< TIM16 clock source |
Kojto | 93:e188a91d3eaa | 414 | This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 415 | |
Kojto | 93:e188a91d3eaa | 416 | uint32_t Tim17ClockSelection; /*!< TIM17 clock source |
Kojto | 93:e188a91d3eaa | 417 | This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 418 | |
Kojto | 93:e188a91d3eaa | 419 | uint32_t USBClockSelection; /*!< USB clock source |
Kojto | 93:e188a91d3eaa | 420 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 421 | |
Kojto | 93:e188a91d3eaa | 422 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 423 | #endif /* STM32F302xE */ |
Kojto | 93:e188a91d3eaa | 424 | |
Kojto | 93:e188a91d3eaa | 425 | #if defined(STM32F303xE) |
Kojto | 93:e188a91d3eaa | 426 | typedef struct |
Kojto | 93:e188a91d3eaa | 427 | { |
Kojto | 93:e188a91d3eaa | 428 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 429 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 430 | |
Kojto | 93:e188a91d3eaa | 431 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 432 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 433 | |
Kojto | 93:e188a91d3eaa | 434 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 435 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 436 | |
Kojto | 93:e188a91d3eaa | 437 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 438 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 439 | |
Kojto | 93:e188a91d3eaa | 440 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 441 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 442 | |
Kojto | 93:e188a91d3eaa | 443 | uint32_t Uart4ClockSelection; /*!< UART4 clock source |
Kojto | 93:e188a91d3eaa | 444 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 445 | |
Kojto | 93:e188a91d3eaa | 446 | uint32_t Uart5ClockSelection; /*!< UART5 clock source |
Kojto | 93:e188a91d3eaa | 447 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 448 | |
Kojto | 93:e188a91d3eaa | 449 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 450 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 451 | |
Kojto | 93:e188a91d3eaa | 452 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 453 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 454 | |
Kojto | 93:e188a91d3eaa | 455 | uint32_t I2c3ClockSelection; /*!< I2C3 clock source |
Kojto | 93:e188a91d3eaa | 456 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 457 | |
Kojto | 93:e188a91d3eaa | 458 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 459 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 460 | |
Kojto | 93:e188a91d3eaa | 461 | uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source |
Kojto | 93:e188a91d3eaa | 462 | This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 463 | |
Kojto | 93:e188a91d3eaa | 464 | uint32_t I2sClockSelection; /*!< I2S clock source |
Kojto | 93:e188a91d3eaa | 465 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 466 | |
Kojto | 93:e188a91d3eaa | 467 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 468 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 469 | |
Kojto | 93:e188a91d3eaa | 470 | uint32_t Tim2ClockSelection; /*!< TIM2 clock source |
Kojto | 93:e188a91d3eaa | 471 | This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 472 | |
Kojto | 93:e188a91d3eaa | 473 | uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source |
Kojto | 93:e188a91d3eaa | 474 | This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 475 | |
Kojto | 93:e188a91d3eaa | 476 | uint32_t Tim8ClockSelection; /*!< TIM8 clock source |
Kojto | 93:e188a91d3eaa | 477 | This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 478 | |
Kojto | 93:e188a91d3eaa | 479 | uint32_t Tim15ClockSelection; /*!< TIM15 clock source |
Kojto | 93:e188a91d3eaa | 480 | This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 481 | |
Kojto | 93:e188a91d3eaa | 482 | uint32_t Tim16ClockSelection; /*!< TIM16 clock source |
Kojto | 93:e188a91d3eaa | 483 | This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 484 | |
Kojto | 93:e188a91d3eaa | 485 | uint32_t Tim17ClockSelection; /*!< TIM17 clock source |
Kojto | 93:e188a91d3eaa | 486 | This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 487 | |
Kojto | 93:e188a91d3eaa | 488 | uint32_t Tim20ClockSelection; /*!< TIM20 clock source |
Kojto | 93:e188a91d3eaa | 489 | This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 490 | |
Kojto | 93:e188a91d3eaa | 491 | uint32_t USBClockSelection; /*!< USB clock source |
Kojto | 93:e188a91d3eaa | 492 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 493 | |
Kojto | 93:e188a91d3eaa | 494 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 495 | #endif /* STM32F303xE */ |
Kojto | 93:e188a91d3eaa | 496 | |
Kojto | 93:e188a91d3eaa | 497 | #if defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 498 | typedef struct |
Kojto | 93:e188a91d3eaa | 499 | { |
Kojto | 93:e188a91d3eaa | 500 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 501 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 502 | |
Kojto | 93:e188a91d3eaa | 503 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 504 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 505 | |
Kojto | 93:e188a91d3eaa | 506 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 507 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 508 | |
Kojto | 93:e188a91d3eaa | 509 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 510 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 511 | |
Kojto | 93:e188a91d3eaa | 512 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 513 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 514 | |
Kojto | 93:e188a91d3eaa | 515 | uint32_t Uart4ClockSelection; /*!< UART4 clock source |
Kojto | 93:e188a91d3eaa | 516 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 517 | |
Kojto | 93:e188a91d3eaa | 518 | uint32_t Uart5ClockSelection; /*!< UART5 clock source |
Kojto | 93:e188a91d3eaa | 519 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 520 | |
Kojto | 93:e188a91d3eaa | 521 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 522 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 523 | |
Kojto | 93:e188a91d3eaa | 524 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 525 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 526 | |
Kojto | 93:e188a91d3eaa | 527 | uint32_t I2c3ClockSelection; /*!< I2C3 clock source |
Kojto | 93:e188a91d3eaa | 528 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 529 | |
Kojto | 93:e188a91d3eaa | 530 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 531 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 532 | |
Kojto | 93:e188a91d3eaa | 533 | uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source |
Kojto | 93:e188a91d3eaa | 534 | This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 535 | |
Kojto | 93:e188a91d3eaa | 536 | uint32_t I2sClockSelection; /*!< I2S clock source |
Kojto | 93:e188a91d3eaa | 537 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 538 | |
Kojto | 93:e188a91d3eaa | 539 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 540 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 541 | |
Kojto | 93:e188a91d3eaa | 542 | uint32_t Tim2ClockSelection; /*!< TIM2 clock source |
Kojto | 93:e188a91d3eaa | 543 | This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 544 | |
Kojto | 93:e188a91d3eaa | 545 | uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source |
Kojto | 93:e188a91d3eaa | 546 | This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 547 | |
Kojto | 93:e188a91d3eaa | 548 | uint32_t Tim8ClockSelection; /*!< TIM8 clock source |
Kojto | 93:e188a91d3eaa | 549 | This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 550 | |
Kojto | 93:e188a91d3eaa | 551 | uint32_t Tim15ClockSelection; /*!< TIM15 clock source |
Kojto | 93:e188a91d3eaa | 552 | This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 553 | |
Kojto | 93:e188a91d3eaa | 554 | uint32_t Tim16ClockSelection; /*!< TIM16 clock source |
Kojto | 93:e188a91d3eaa | 555 | This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 556 | |
Kojto | 93:e188a91d3eaa | 557 | uint32_t Tim17ClockSelection; /*!< TIM17 clock source |
Kojto | 93:e188a91d3eaa | 558 | This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 559 | |
Kojto | 93:e188a91d3eaa | 560 | uint32_t Tim20ClockSelection; /*!< TIM20 clock source |
Kojto | 93:e188a91d3eaa | 561 | This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 562 | |
Kojto | 93:e188a91d3eaa | 563 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 564 | #endif /* STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 565 | |
Kojto | 93:e188a91d3eaa | 566 | #if defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 567 | typedef struct |
Kojto | 93:e188a91d3eaa | 568 | { |
Kojto | 93:e188a91d3eaa | 569 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 570 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 571 | |
Kojto | 93:e188a91d3eaa | 572 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 573 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 574 | |
Kojto | 93:e188a91d3eaa | 575 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 576 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 577 | |
Kojto | 93:e188a91d3eaa | 578 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 579 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 580 | |
Kojto | 93:e188a91d3eaa | 581 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 582 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 583 | |
Kojto | 93:e188a91d3eaa | 584 | uint32_t Uart4ClockSelection; /*!< UART4 clock source |
Kojto | 93:e188a91d3eaa | 585 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 586 | |
Kojto | 93:e188a91d3eaa | 587 | uint32_t Uart5ClockSelection; /*!< UART5 clock source |
Kojto | 93:e188a91d3eaa | 588 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 589 | |
Kojto | 93:e188a91d3eaa | 590 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 591 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 592 | |
Kojto | 93:e188a91d3eaa | 593 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 594 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 595 | |
Kojto | 93:e188a91d3eaa | 596 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 597 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 598 | |
Kojto | 93:e188a91d3eaa | 599 | uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source |
Kojto | 93:e188a91d3eaa | 600 | This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 601 | |
Kojto | 93:e188a91d3eaa | 602 | uint32_t I2sClockSelection; /*!< I2S clock source |
Kojto | 93:e188a91d3eaa | 603 | This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 604 | |
Kojto | 93:e188a91d3eaa | 605 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 606 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 607 | |
Kojto | 93:e188a91d3eaa | 608 | uint32_t Tim8ClockSelection; /*!< TIM8 clock source |
Kojto | 93:e188a91d3eaa | 609 | This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 610 | |
Kojto | 93:e188a91d3eaa | 611 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 612 | #endif /* STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 613 | |
Kojto | 93:e188a91d3eaa | 614 | #if defined(STM32F303x8) |
Kojto | 93:e188a91d3eaa | 615 | typedef struct |
Kojto | 93:e188a91d3eaa | 616 | { |
Kojto | 93:e188a91d3eaa | 617 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 618 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 619 | |
Kojto | 93:e188a91d3eaa | 620 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 621 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 622 | |
Kojto | 93:e188a91d3eaa | 623 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 624 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 625 | |
Kojto | 93:e188a91d3eaa | 626 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 627 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 628 | |
Kojto | 93:e188a91d3eaa | 629 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 630 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 631 | |
Kojto | 93:e188a91d3eaa | 632 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 633 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 634 | |
Kojto | 93:e188a91d3eaa | 635 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 636 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 637 | |
Kojto | 93:e188a91d3eaa | 638 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 639 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 640 | |
Kojto | 93:e188a91d3eaa | 641 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 642 | #endif /* STM32F303x8 */ |
Kojto | 93:e188a91d3eaa | 643 | |
Kojto | 93:e188a91d3eaa | 644 | #if defined(STM32F334x8) |
Kojto | 93:e188a91d3eaa | 645 | typedef struct |
Kojto | 93:e188a91d3eaa | 646 | { |
Kojto | 93:e188a91d3eaa | 647 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 648 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 649 | |
Kojto | 93:e188a91d3eaa | 650 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 651 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 652 | |
Kojto | 93:e188a91d3eaa | 653 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 654 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 655 | |
Kojto | 93:e188a91d3eaa | 656 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 657 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 658 | |
Kojto | 93:e188a91d3eaa | 659 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 660 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 661 | |
Kojto | 93:e188a91d3eaa | 662 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 663 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 664 | |
Kojto | 93:e188a91d3eaa | 665 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 666 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 667 | |
Kojto | 93:e188a91d3eaa | 668 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 669 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 670 | |
Kojto | 93:e188a91d3eaa | 671 | uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source |
Kojto | 93:e188a91d3eaa | 672 | This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 673 | |
Kojto | 93:e188a91d3eaa | 674 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 675 | #endif /* STM32F334x8 */ |
Kojto | 93:e188a91d3eaa | 676 | |
Kojto | 93:e188a91d3eaa | 677 | #if defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 678 | typedef struct |
Kojto | 93:e188a91d3eaa | 679 | { |
Kojto | 93:e188a91d3eaa | 680 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 681 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 682 | |
Kojto | 93:e188a91d3eaa | 683 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 684 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 685 | |
Kojto | 93:e188a91d3eaa | 686 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 687 | This parameter can be a value of @ref RCC_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 688 | |
Kojto | 93:e188a91d3eaa | 689 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 690 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 691 | |
Kojto | 93:e188a91d3eaa | 692 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 693 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 694 | |
Kojto | 93:e188a91d3eaa | 695 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 696 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 697 | |
Kojto | 93:e188a91d3eaa | 698 | uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source |
Kojto | 93:e188a91d3eaa | 699 | This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 700 | |
Kojto | 93:e188a91d3eaa | 701 | uint32_t Tim1ClockSelection; /*!< TIM1 clock source |
Kojto | 93:e188a91d3eaa | 702 | This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 703 | |
Kojto | 93:e188a91d3eaa | 704 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 705 | #endif /* STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 706 | |
Kojto | 93:e188a91d3eaa | 707 | #if defined(STM32F373xC) |
Kojto | 93:e188a91d3eaa | 708 | typedef struct |
Kojto | 93:e188a91d3eaa | 709 | { |
Kojto | 93:e188a91d3eaa | 710 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 711 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 712 | |
Kojto | 93:e188a91d3eaa | 713 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 714 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 715 | |
Kojto | 93:e188a91d3eaa | 716 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 717 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 718 | |
Kojto | 93:e188a91d3eaa | 719 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 720 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 721 | |
Kojto | 93:e188a91d3eaa | 722 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 723 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 724 | |
Kojto | 93:e188a91d3eaa | 725 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 726 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 727 | |
Kojto | 93:e188a91d3eaa | 728 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 729 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 730 | |
Kojto | 93:e188a91d3eaa | 731 | uint32_t Adc1ClockSelection; /*!< ADC1 clock source |
Kojto | 93:e188a91d3eaa | 732 | This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 733 | |
Kojto | 93:e188a91d3eaa | 734 | uint32_t SdadcClockSelection; /*!< SDADC clock prescaler |
Kojto | 93:e188a91d3eaa | 735 | This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */ |
Kojto | 93:e188a91d3eaa | 736 | |
Kojto | 93:e188a91d3eaa | 737 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
Kojto | 93:e188a91d3eaa | 738 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 739 | |
Kojto | 93:e188a91d3eaa | 740 | uint32_t USBClockSelection; /*!< USB clock source |
Kojto | 93:e188a91d3eaa | 741 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 742 | |
Kojto | 93:e188a91d3eaa | 743 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 744 | #endif /* STM32F373xC */ |
Kojto | 93:e188a91d3eaa | 745 | |
Kojto | 93:e188a91d3eaa | 746 | #if defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 747 | typedef struct |
Kojto | 93:e188a91d3eaa | 748 | { |
Kojto | 93:e188a91d3eaa | 749 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
Kojto | 93:e188a91d3eaa | 750 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
Kojto | 93:e188a91d3eaa | 751 | |
Kojto | 93:e188a91d3eaa | 752 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection |
Kojto | 93:e188a91d3eaa | 753 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 754 | |
Kojto | 93:e188a91d3eaa | 755 | uint32_t Usart1ClockSelection; /*!< USART1 clock source |
Kojto | 93:e188a91d3eaa | 756 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 757 | |
Kojto | 93:e188a91d3eaa | 758 | uint32_t Usart2ClockSelection; /*!< USART2 clock source |
Kojto | 93:e188a91d3eaa | 759 | This parameter can be a value of @ref RCC_USART2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 760 | |
Kojto | 93:e188a91d3eaa | 761 | uint32_t Usart3ClockSelection; /*!< USART3 clock source |
Kojto | 93:e188a91d3eaa | 762 | This parameter can be a value of @ref RCC_USART3_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 763 | |
Kojto | 93:e188a91d3eaa | 764 | uint32_t I2c1ClockSelection; /*!< I2C1 clock source |
Kojto | 93:e188a91d3eaa | 765 | This parameter can be a value of @ref RCC_I2C1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 766 | |
Kojto | 93:e188a91d3eaa | 767 | uint32_t I2c2ClockSelection; /*!< I2C2 clock source |
Kojto | 93:e188a91d3eaa | 768 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 769 | |
Kojto | 93:e188a91d3eaa | 770 | uint32_t Adc1ClockSelection; /*!< ADC1 clock source |
Kojto | 93:e188a91d3eaa | 771 | This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 772 | |
Kojto | 93:e188a91d3eaa | 773 | uint32_t SdadcClockSelection; /*!< SDADC clock prescaler |
Kojto | 93:e188a91d3eaa | 774 | This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */ |
Kojto | 93:e188a91d3eaa | 775 | |
Kojto | 93:e188a91d3eaa | 776 | uint32_t CecClockSelection; /*!< HDMI CEC clock source |
Kojto | 93:e188a91d3eaa | 777 | This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ |
Kojto | 93:e188a91d3eaa | 778 | |
Kojto | 93:e188a91d3eaa | 779 | }RCC_PeriphCLKInitTypeDef; |
Kojto | 93:e188a91d3eaa | 780 | #endif /* STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 781 | |
Kojto | 93:e188a91d3eaa | 782 | /** |
Kojto | 93:e188a91d3eaa | 783 | * @} |
Kojto | 93:e188a91d3eaa | 784 | */ |
Kojto | 93:e188a91d3eaa | 785 | |
Kojto | 93:e188a91d3eaa | 786 | /* Exported constants --------------------------------------------------------*/ |
Kojto | 93:e188a91d3eaa | 787 | /** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants |
Kojto | 93:e188a91d3eaa | 788 | * @{ |
Kojto | 93:e188a91d3eaa | 789 | */ |
Kojto | 93:e188a91d3eaa | 790 | #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 791 | defined(STM32F334x8) || \ |
Kojto | 93:e188a91d3eaa | 792 | defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 793 | /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source |
Kojto | 93:e188a91d3eaa | 794 | * @{ |
Kojto | 93:e188a91d3eaa | 795 | */ |
Kojto | 93:e188a91d3eaa | 796 | #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK |
Kojto | 93:e188a91d3eaa | 797 | #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI |
Kojto | 93:e188a91d3eaa | 798 | #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE |
Kojto | 93:e188a91d3eaa | 799 | #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK |
Kojto | 93:e188a91d3eaa | 800 | #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI |
Kojto | 93:e188a91d3eaa | 801 | #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE |
Kojto | 93:e188a91d3eaa | 802 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL |
Kojto | 93:e188a91d3eaa | 803 | |
Kojto | 93:e188a91d3eaa | 804 | #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ |
Kojto | 93:e188a91d3eaa | 805 | ((SOURCE) == RCC_MCOSOURCE_LSI) || \ |
Kojto | 93:e188a91d3eaa | 806 | ((SOURCE) == RCC_MCOSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 807 | ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 808 | ((SOURCE) == RCC_MCOSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 809 | ((SOURCE) == RCC_MCOSOURCE_HSE) || \ |
Kojto | 93:e188a91d3eaa | 810 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2)) |
Kojto | 93:e188a91d3eaa | 811 | /** |
Kojto | 93:e188a91d3eaa | 812 | * @} |
Kojto | 93:e188a91d3eaa | 813 | */ |
Kojto | 93:e188a91d3eaa | 814 | #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 815 | /* STM32F334x8 */ |
Kojto | 93:e188a91d3eaa | 816 | /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 817 | |
Kojto | 93:e188a91d3eaa | 818 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 819 | defined(STM32F303x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 820 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 821 | /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source |
Kojto | 93:e188a91d3eaa | 822 | * @{ |
Kojto | 93:e188a91d3eaa | 823 | */ |
Kojto | 93:e188a91d3eaa | 824 | #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK |
Kojto | 93:e188a91d3eaa | 825 | #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI |
Kojto | 93:e188a91d3eaa | 826 | #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE |
Kojto | 93:e188a91d3eaa | 827 | #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK |
Kojto | 93:e188a91d3eaa | 828 | #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI |
Kojto | 93:e188a91d3eaa | 829 | #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE |
Kojto | 93:e188a91d3eaa | 830 | #define RCC_MCOSOURCE_PLLCLK_DIV1 (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL) |
Kojto | 93:e188a91d3eaa | 831 | #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL |
Kojto | 93:e188a91d3eaa | 832 | |
Kojto | 93:e188a91d3eaa | 833 | #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \ |
Kojto | 93:e188a91d3eaa | 834 | ((SOURCE) == RCC_MCOSOURCE_LSI) || \ |
Kojto | 93:e188a91d3eaa | 835 | ((SOURCE) == RCC_MCOSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 836 | ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 837 | ((SOURCE) == RCC_MCOSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 838 | ((SOURCE) == RCC_MCOSOURCE_HSE) || \ |
Kojto | 93:e188a91d3eaa | 839 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV1) || \ |
Kojto | 93:e188a91d3eaa | 840 | ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2)) |
Kojto | 93:e188a91d3eaa | 841 | /** |
Kojto | 93:e188a91d3eaa | 842 | * @} |
Kojto | 93:e188a91d3eaa | 843 | */ |
Kojto | 93:e188a91d3eaa | 844 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 845 | /* STM32F303x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 846 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 847 | |
Kojto | 93:e188a91d3eaa | 848 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 849 | /** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source |
Kojto | 93:e188a91d3eaa | 850 | * @{ |
Kojto | 93:e188a91d3eaa | 851 | */ |
Kojto | 93:e188a91d3eaa | 852 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV |
Kojto | 93:e188a91d3eaa | 853 | #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV |
Kojto | 93:e188a91d3eaa | 854 | |
Kojto | 93:e188a91d3eaa | 855 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 856 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
Kojto | 93:e188a91d3eaa | 857 | /** |
Kojto | 93:e188a91d3eaa | 858 | * @} |
Kojto | 93:e188a91d3eaa | 859 | */ |
Kojto | 93:e188a91d3eaa | 860 | |
Kojto | 93:e188a91d3eaa | 861 | /** @defgroup RCCEx_PLL_Prediv_Factor RCC Extended PLL Prediv Factor |
Kojto | 93:e188a91d3eaa | 862 | * @{ |
Kojto | 93:e188a91d3eaa | 863 | */ |
Kojto | 93:e188a91d3eaa | 864 | #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 |
Kojto | 93:e188a91d3eaa | 865 | #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 |
Kojto | 93:e188a91d3eaa | 866 | #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 |
Kojto | 93:e188a91d3eaa | 867 | #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 |
Kojto | 93:e188a91d3eaa | 868 | #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 |
Kojto | 93:e188a91d3eaa | 869 | #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 |
Kojto | 93:e188a91d3eaa | 870 | #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 |
Kojto | 93:e188a91d3eaa | 871 | #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 |
Kojto | 93:e188a91d3eaa | 872 | #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 |
Kojto | 93:e188a91d3eaa | 873 | #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 |
Kojto | 93:e188a91d3eaa | 874 | #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 |
Kojto | 93:e188a91d3eaa | 875 | #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 |
Kojto | 93:e188a91d3eaa | 876 | #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 |
Kojto | 93:e188a91d3eaa | 877 | #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 |
Kojto | 93:e188a91d3eaa | 878 | #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 |
Kojto | 93:e188a91d3eaa | 879 | #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 |
Kojto | 93:e188a91d3eaa | 880 | |
Kojto | 93:e188a91d3eaa | 881 | #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \ |
Kojto | 93:e188a91d3eaa | 882 | ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \ |
Kojto | 93:e188a91d3eaa | 883 | ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \ |
Kojto | 93:e188a91d3eaa | 884 | ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \ |
Kojto | 93:e188a91d3eaa | 885 | ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \ |
Kojto | 93:e188a91d3eaa | 886 | ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \ |
Kojto | 93:e188a91d3eaa | 887 | ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \ |
Kojto | 93:e188a91d3eaa | 888 | ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16)) |
Kojto | 93:e188a91d3eaa | 889 | /** |
Kojto | 93:e188a91d3eaa | 890 | * @} |
Kojto | 93:e188a91d3eaa | 891 | */ |
Kojto | 93:e188a91d3eaa | 892 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 893 | |
Kojto | 93:e188a91d3eaa | 894 | #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 895 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 896 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
Kojto | 93:e188a91d3eaa | 897 | defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 898 | /** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source |
Kojto | 93:e188a91d3eaa | 899 | * @{ |
Kojto | 93:e188a91d3eaa | 900 | */ |
Kojto | 93:e188a91d3eaa | 901 | #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2 |
Kojto | 93:e188a91d3eaa | 902 | #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV |
Kojto | 93:e188a91d3eaa | 903 | |
Kojto | 93:e188a91d3eaa | 904 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 905 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
Kojto | 93:e188a91d3eaa | 906 | /** |
Kojto | 93:e188a91d3eaa | 907 | * @} |
Kojto | 93:e188a91d3eaa | 908 | */ |
Kojto | 93:e188a91d3eaa | 909 | |
Kojto | 93:e188a91d3eaa | 910 | /** @defgroup RCCEx_HSE_Predivision_Factor RCC Extended HSE Predivision Factor |
Kojto | 93:e188a91d3eaa | 911 | * @{ |
Kojto | 93:e188a91d3eaa | 912 | */ |
Kojto | 93:e188a91d3eaa | 913 | |
Kojto | 93:e188a91d3eaa | 914 | #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1 |
Kojto | 93:e188a91d3eaa | 915 | #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2 |
Kojto | 93:e188a91d3eaa | 916 | #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3 |
Kojto | 93:e188a91d3eaa | 917 | #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4 |
Kojto | 93:e188a91d3eaa | 918 | #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5 |
Kojto | 93:e188a91d3eaa | 919 | #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6 |
Kojto | 93:e188a91d3eaa | 920 | #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7 |
Kojto | 93:e188a91d3eaa | 921 | #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8 |
Kojto | 93:e188a91d3eaa | 922 | #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9 |
Kojto | 93:e188a91d3eaa | 923 | #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10 |
Kojto | 93:e188a91d3eaa | 924 | #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11 |
Kojto | 93:e188a91d3eaa | 925 | #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12 |
Kojto | 93:e188a91d3eaa | 926 | #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13 |
Kojto | 93:e188a91d3eaa | 927 | #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14 |
Kojto | 93:e188a91d3eaa | 928 | #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15 |
Kojto | 93:e188a91d3eaa | 929 | #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16 |
Kojto | 93:e188a91d3eaa | 930 | |
Kojto | 93:e188a91d3eaa | 931 | #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \ |
Kojto | 93:e188a91d3eaa | 932 | ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \ |
Kojto | 93:e188a91d3eaa | 933 | ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \ |
Kojto | 93:e188a91d3eaa | 934 | ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \ |
Kojto | 93:e188a91d3eaa | 935 | ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \ |
Kojto | 93:e188a91d3eaa | 936 | ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \ |
Kojto | 93:e188a91d3eaa | 937 | ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \ |
Kojto | 93:e188a91d3eaa | 938 | ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16)) |
Kojto | 93:e188a91d3eaa | 939 | /** |
Kojto | 93:e188a91d3eaa | 940 | * @} |
Kojto | 93:e188a91d3eaa | 941 | */ |
Kojto | 93:e188a91d3eaa | 942 | #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 943 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 944 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 945 | /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 946 | |
Kojto | 93:e188a91d3eaa | 947 | /** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection |
Kojto | 93:e188a91d3eaa | 948 | * @{ |
Kojto | 93:e188a91d3eaa | 949 | */ |
Kojto | 93:e188a91d3eaa | 950 | #if defined(STM32F301x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 951 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 952 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 953 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 954 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 955 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 956 | #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 957 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) |
Kojto | 93:e188a91d3eaa | 958 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 959 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000) |
Kojto | 93:e188a91d3eaa | 960 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 961 | #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000) |
Kojto | 93:e188a91d3eaa | 962 | #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000) |
Kojto | 93:e188a91d3eaa | 963 | #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000) |
Kojto | 93:e188a91d3eaa | 964 | |
Kojto | 93:e188a91d3eaa | 965 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 966 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 967 | RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \ |
Kojto | 93:e188a91d3eaa | 968 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \ |
Kojto | 93:e188a91d3eaa | 969 | RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ |
Kojto | 93:e188a91d3eaa | 970 | RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC)) |
Kojto | 93:e188a91d3eaa | 971 | #endif /* STM32F301x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 972 | |
Kojto | 93:e188a91d3eaa | 973 | #if defined(STM32F302x8) |
Kojto | 93:e188a91d3eaa | 974 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 975 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 976 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 977 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 978 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 979 | #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 980 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) |
Kojto | 93:e188a91d3eaa | 981 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 982 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000) |
Kojto | 93:e188a91d3eaa | 983 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 984 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) |
Kojto | 93:e188a91d3eaa | 985 | #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000) |
Kojto | 93:e188a91d3eaa | 986 | #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000) |
Kojto | 93:e188a91d3eaa | 987 | #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000) |
Kojto | 93:e188a91d3eaa | 988 | |
Kojto | 93:e188a91d3eaa | 989 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 990 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 991 | RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \ |
Kojto | 93:e188a91d3eaa | 992 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \ |
Kojto | 93:e188a91d3eaa | 993 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ |
Kojto | 93:e188a91d3eaa | 994 | RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ |
Kojto | 93:e188a91d3eaa | 995 | RCC_PERIPHCLK_TIM17)) |
Kojto | 93:e188a91d3eaa | 996 | #endif /* STM32F302x8 */ |
Kojto | 93:e188a91d3eaa | 997 | |
Kojto | 93:e188a91d3eaa | 998 | #if defined(STM32F302xC) |
Kojto | 93:e188a91d3eaa | 999 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1000 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1001 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1002 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) |
Kojto | 93:e188a91d3eaa | 1003 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) |
Kojto | 93:e188a91d3eaa | 1004 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1005 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 1006 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1007 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) |
Kojto | 93:e188a91d3eaa | 1008 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1009 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1010 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) |
Kojto | 93:e188a91d3eaa | 1011 | |
Kojto | 93:e188a91d3eaa | 1012 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1013 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ |
Kojto | 93:e188a91d3eaa | 1014 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 1015 | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \ |
Kojto | 93:e188a91d3eaa | 1016 | RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \ |
Kojto | 93:e188a91d3eaa | 1017 | RCC_PERIPHCLK_USB)) |
Kojto | 93:e188a91d3eaa | 1018 | #endif /* STM32F302xC */ |
Kojto | 93:e188a91d3eaa | 1019 | |
Kojto | 93:e188a91d3eaa | 1020 | #if defined(STM32F303xC) |
Kojto | 93:e188a91d3eaa | 1021 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1022 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1023 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1024 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) |
Kojto | 93:e188a91d3eaa | 1025 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) |
Kojto | 93:e188a91d3eaa | 1026 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1027 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 1028 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1029 | #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100) |
Kojto | 93:e188a91d3eaa | 1030 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) |
Kojto | 93:e188a91d3eaa | 1031 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1032 | #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000) |
Kojto | 93:e188a91d3eaa | 1033 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1034 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) |
Kojto | 93:e188a91d3eaa | 1035 | |
Kojto | 93:e188a91d3eaa | 1036 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1037 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ |
Kojto | 93:e188a91d3eaa | 1038 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 1039 | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ |
Kojto | 93:e188a91d3eaa | 1040 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ |
Kojto | 93:e188a91d3eaa | 1041 | RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ |
Kojto | 93:e188a91d3eaa | 1042 | RCC_PERIPHCLK_USB)) |
Kojto | 93:e188a91d3eaa | 1043 | #endif /* STM32F303xC */ |
Kojto | 93:e188a91d3eaa | 1044 | |
Kojto | 93:e188a91d3eaa | 1045 | #if defined(STM32F302xE) |
Kojto | 93:e188a91d3eaa | 1046 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1047 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1048 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1049 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) |
Kojto | 93:e188a91d3eaa | 1050 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) |
Kojto | 93:e188a91d3eaa | 1051 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1052 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 1053 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1054 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) |
Kojto | 93:e188a91d3eaa | 1055 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1056 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1057 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) |
Kojto | 93:e188a91d3eaa | 1058 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000) |
Kojto | 93:e188a91d3eaa | 1059 | #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000) |
Kojto | 93:e188a91d3eaa | 1060 | #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000) |
Kojto | 93:e188a91d3eaa | 1061 | #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000) |
Kojto | 93:e188a91d3eaa | 1062 | #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000) |
Kojto | 93:e188a91d3eaa | 1063 | #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000) |
Kojto | 93:e188a91d3eaa | 1064 | |
Kojto | 93:e188a91d3eaa | 1065 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1066 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ |
Kojto | 93:e188a91d3eaa | 1067 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 1068 | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \ |
Kojto | 93:e188a91d3eaa | 1069 | RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \ |
Kojto | 93:e188a91d3eaa | 1070 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \ |
Kojto | 93:e188a91d3eaa | 1071 | RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \ |
Kojto | 93:e188a91d3eaa | 1072 | RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ |
Kojto | 93:e188a91d3eaa | 1073 | RCC_PERIPHCLK_TIM17)) |
Kojto | 93:e188a91d3eaa | 1074 | #endif /* STM32F302xE */ |
Kojto | 93:e188a91d3eaa | 1075 | |
Kojto | 93:e188a91d3eaa | 1076 | #if defined(STM32F303xE) |
Kojto | 93:e188a91d3eaa | 1077 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1078 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1079 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1080 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) |
Kojto | 93:e188a91d3eaa | 1081 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) |
Kojto | 93:e188a91d3eaa | 1082 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1083 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 1084 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1085 | #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100) |
Kojto | 93:e188a91d3eaa | 1086 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) |
Kojto | 93:e188a91d3eaa | 1087 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1088 | #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000) |
Kojto | 93:e188a91d3eaa | 1089 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1090 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) |
Kojto | 93:e188a91d3eaa | 1091 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000) |
Kojto | 93:e188a91d3eaa | 1092 | #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000) |
Kojto | 93:e188a91d3eaa | 1093 | #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000) |
Kojto | 93:e188a91d3eaa | 1094 | #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000) |
Kojto | 93:e188a91d3eaa | 1095 | #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000) |
Kojto | 93:e188a91d3eaa | 1096 | #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000) |
Kojto | 93:e188a91d3eaa | 1097 | #define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000) |
Kojto | 93:e188a91d3eaa | 1098 | |
Kojto | 93:e188a91d3eaa | 1099 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1100 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ |
Kojto | 93:e188a91d3eaa | 1101 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 1102 | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ |
Kojto | 93:e188a91d3eaa | 1103 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ |
Kojto | 93:e188a91d3eaa | 1104 | RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ |
Kojto | 93:e188a91d3eaa | 1105 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \ |
Kojto | 93:e188a91d3eaa | 1106 | RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \ |
Kojto | 93:e188a91d3eaa | 1107 | RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \ |
Kojto | 93:e188a91d3eaa | 1108 | RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20)) |
Kojto | 93:e188a91d3eaa | 1109 | #endif /* STM32F303xE */ |
Kojto | 93:e188a91d3eaa | 1110 | |
Kojto | 93:e188a91d3eaa | 1111 | #if defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 1112 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1113 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1114 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1115 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) |
Kojto | 93:e188a91d3eaa | 1116 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) |
Kojto | 93:e188a91d3eaa | 1117 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1118 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 1119 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1120 | #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100) |
Kojto | 93:e188a91d3eaa | 1121 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) |
Kojto | 93:e188a91d3eaa | 1122 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1123 | #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000) |
Kojto | 93:e188a91d3eaa | 1124 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1125 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000) |
Kojto | 93:e188a91d3eaa | 1126 | #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000) |
Kojto | 93:e188a91d3eaa | 1127 | #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000) |
Kojto | 93:e188a91d3eaa | 1128 | #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000) |
Kojto | 93:e188a91d3eaa | 1129 | #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000) |
Kojto | 93:e188a91d3eaa | 1130 | #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000) |
Kojto | 93:e188a91d3eaa | 1131 | #define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000) |
Kojto | 93:e188a91d3eaa | 1132 | |
Kojto | 93:e188a91d3eaa | 1133 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1134 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ |
Kojto | 93:e188a91d3eaa | 1135 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 1136 | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ |
Kojto | 93:e188a91d3eaa | 1137 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ |
Kojto | 93:e188a91d3eaa | 1138 | RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \ |
Kojto | 93:e188a91d3eaa | 1139 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \ |
Kojto | 93:e188a91d3eaa | 1140 | RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \ |
Kojto | 93:e188a91d3eaa | 1141 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \ |
Kojto | 93:e188a91d3eaa | 1142 | RCC_PERIPHCLK_TIM20)) |
Kojto | 93:e188a91d3eaa | 1143 | #endif /* STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 1144 | |
Kojto | 93:e188a91d3eaa | 1145 | #if defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 1146 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1147 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1148 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1149 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) |
Kojto | 93:e188a91d3eaa | 1150 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) |
Kojto | 93:e188a91d3eaa | 1151 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1152 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 1153 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1154 | #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100) |
Kojto | 93:e188a91d3eaa | 1155 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200) |
Kojto | 93:e188a91d3eaa | 1156 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1157 | #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000) |
Kojto | 93:e188a91d3eaa | 1158 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1159 | |
Kojto | 93:e188a91d3eaa | 1160 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1161 | RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \ |
Kojto | 93:e188a91d3eaa | 1162 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 1163 | RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \ |
Kojto | 93:e188a91d3eaa | 1164 | RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \ |
Kojto | 93:e188a91d3eaa | 1165 | RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC)) |
Kojto | 93:e188a91d3eaa | 1166 | #endif /* STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 1167 | |
Kojto | 93:e188a91d3eaa | 1168 | #if defined(STM32F303x8) |
Kojto | 93:e188a91d3eaa | 1169 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1170 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1171 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1172 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1173 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1174 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1175 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1176 | |
Kojto | 93:e188a91d3eaa | 1177 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1178 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ |
Kojto | 93:e188a91d3eaa | 1179 | RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC)) |
Kojto | 93:e188a91d3eaa | 1180 | #endif /* STM32F303x8 */ |
Kojto | 93:e188a91d3eaa | 1181 | |
Kojto | 93:e188a91d3eaa | 1182 | #if defined(STM32F334x8) |
Kojto | 93:e188a91d3eaa | 1183 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1184 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1185 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1186 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1187 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1188 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1189 | #define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000) |
Kojto | 93:e188a91d3eaa | 1190 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1191 | |
Kojto | 93:e188a91d3eaa | 1192 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1193 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ |
Kojto | 93:e188a91d3eaa | 1194 | RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \ |
Kojto | 93:e188a91d3eaa | 1195 | RCC_PERIPHCLK_RTC)) |
Kojto | 93:e188a91d3eaa | 1196 | #endif /* STM32F334x8 */ |
Kojto | 93:e188a91d3eaa | 1197 | |
Kojto | 93:e188a91d3eaa | 1198 | #if defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 1199 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1200 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1201 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1202 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1203 | #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1204 | #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000) |
Kojto | 93:e188a91d3eaa | 1205 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1206 | |
Kojto | 93:e188a91d3eaa | 1207 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1208 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \ |
Kojto | 93:e188a91d3eaa | 1209 | RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC)) |
Kojto | 93:e188a91d3eaa | 1210 | #endif /* STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 1211 | |
Kojto | 93:e188a91d3eaa | 1212 | #if defined(STM32F373xC) |
Kojto | 93:e188a91d3eaa | 1213 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1214 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1215 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1216 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1217 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 1218 | #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1219 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) |
Kojto | 93:e188a91d3eaa | 1220 | #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800) |
Kojto | 93:e188a91d3eaa | 1221 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1222 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000) |
Kojto | 93:e188a91d3eaa | 1223 | |
Kojto | 93:e188a91d3eaa | 1224 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1225 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 1226 | RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \ |
Kojto | 93:e188a91d3eaa | 1227 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \ |
Kojto | 93:e188a91d3eaa | 1228 | RCC_PERIPHCLK_USB)) |
Kojto | 93:e188a91d3eaa | 1229 | #endif /* STM32F373xC */ |
Kojto | 93:e188a91d3eaa | 1230 | |
Kojto | 93:e188a91d3eaa | 1231 | #if defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 1232 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
Kojto | 93:e188a91d3eaa | 1233 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
Kojto | 93:e188a91d3eaa | 1234 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
Kojto | 93:e188a91d3eaa | 1235 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020) |
Kojto | 93:e188a91d3eaa | 1236 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040) |
Kojto | 93:e188a91d3eaa | 1237 | #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080) |
Kojto | 93:e188a91d3eaa | 1238 | #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400) |
Kojto | 93:e188a91d3eaa | 1239 | #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800) |
Kojto | 93:e188a91d3eaa | 1240 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000) |
Kojto | 93:e188a91d3eaa | 1241 | |
Kojto | 93:e188a91d3eaa | 1242 | #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ |
Kojto | 93:e188a91d3eaa | 1243 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ |
Kojto | 93:e188a91d3eaa | 1244 | RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \ |
Kojto | 93:e188a91d3eaa | 1245 | RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC)) |
Kojto | 93:e188a91d3eaa | 1246 | #endif /* STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 1247 | /** |
Kojto | 93:e188a91d3eaa | 1248 | * @} |
Kojto | 93:e188a91d3eaa | 1249 | */ |
Kojto | 93:e188a91d3eaa | 1250 | |
Kojto | 93:e188a91d3eaa | 1251 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 1252 | |
Kojto | 93:e188a91d3eaa | 1253 | /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source |
Kojto | 93:e188a91d3eaa | 1254 | * @{ |
Kojto | 93:e188a91d3eaa | 1255 | */ |
Kojto | 93:e188a91d3eaa | 1256 | #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK |
Kojto | 93:e188a91d3eaa | 1257 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1258 | #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE |
Kojto | 93:e188a91d3eaa | 1259 | #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI |
Kojto | 93:e188a91d3eaa | 1260 | |
Kojto | 93:e188a91d3eaa | 1261 | #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ |
Kojto | 93:e188a91d3eaa | 1262 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1263 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1264 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1265 | /** |
Kojto | 93:e188a91d3eaa | 1266 | * @} |
Kojto | 93:e188a91d3eaa | 1267 | */ |
Kojto | 93:e188a91d3eaa | 1268 | |
Kojto | 93:e188a91d3eaa | 1269 | /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source |
Kojto | 93:e188a91d3eaa | 1270 | * @{ |
Kojto | 93:e188a91d3eaa | 1271 | */ |
Kojto | 93:e188a91d3eaa | 1272 | #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI |
Kojto | 93:e188a91d3eaa | 1273 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1274 | |
Kojto | 93:e188a91d3eaa | 1275 | #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 1276 | ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) |
Kojto | 93:e188a91d3eaa | 1277 | /** |
Kojto | 93:e188a91d3eaa | 1278 | * @} |
Kojto | 93:e188a91d3eaa | 1279 | */ |
Kojto | 93:e188a91d3eaa | 1280 | |
Kojto | 93:e188a91d3eaa | 1281 | /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source |
Kojto | 93:e188a91d3eaa | 1282 | * @{ |
Kojto | 93:e188a91d3eaa | 1283 | */ |
Kojto | 93:e188a91d3eaa | 1284 | #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI |
Kojto | 93:e188a91d3eaa | 1285 | #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1286 | |
Kojto | 93:e188a91d3eaa | 1287 | #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 1288 | ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)) |
Kojto | 93:e188a91d3eaa | 1289 | /** |
Kojto | 93:e188a91d3eaa | 1290 | * @} |
Kojto | 93:e188a91d3eaa | 1291 | */ |
Kojto | 93:e188a91d3eaa | 1292 | |
Kojto | 93:e188a91d3eaa | 1293 | /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source |
Kojto | 93:e188a91d3eaa | 1294 | * @{ |
Kojto | 93:e188a91d3eaa | 1295 | */ |
Kojto | 93:e188a91d3eaa | 1296 | #define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO |
Kojto | 93:e188a91d3eaa | 1297 | #define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1 |
Kojto | 93:e188a91d3eaa | 1298 | #define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2 |
Kojto | 93:e188a91d3eaa | 1299 | #define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4 |
Kojto | 93:e188a91d3eaa | 1300 | #define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6 |
Kojto | 93:e188a91d3eaa | 1301 | #define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8 |
Kojto | 93:e188a91d3eaa | 1302 | #define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10 |
Kojto | 93:e188a91d3eaa | 1303 | #define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12 |
Kojto | 93:e188a91d3eaa | 1304 | #define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16 |
Kojto | 93:e188a91d3eaa | 1305 | #define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32 |
Kojto | 93:e188a91d3eaa | 1306 | #define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64 |
Kojto | 93:e188a91d3eaa | 1307 | #define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128 |
Kojto | 93:e188a91d3eaa | 1308 | #define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256 |
Kojto | 93:e188a91d3eaa | 1309 | |
Kojto | 93:e188a91d3eaa | 1310 | #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \ |
Kojto | 93:e188a91d3eaa | 1311 | ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \ |
Kojto | 93:e188a91d3eaa | 1312 | ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \ |
Kojto | 93:e188a91d3eaa | 1313 | ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \ |
Kojto | 93:e188a91d3eaa | 1314 | ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \ |
Kojto | 93:e188a91d3eaa | 1315 | ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \ |
Kojto | 93:e188a91d3eaa | 1316 | ((ADCCLK) == RCC_ADC1PLLCLK_DIV256)) |
Kojto | 93:e188a91d3eaa | 1317 | /** |
Kojto | 93:e188a91d3eaa | 1318 | * @} |
Kojto | 93:e188a91d3eaa | 1319 | */ |
Kojto | 93:e188a91d3eaa | 1320 | |
Kojto | 93:e188a91d3eaa | 1321 | /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source |
Kojto | 93:e188a91d3eaa | 1322 | * @{ |
Kojto | 93:e188a91d3eaa | 1323 | */ |
Kojto | 93:e188a91d3eaa | 1324 | #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK |
Kojto | 93:e188a91d3eaa | 1325 | #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT |
Kojto | 93:e188a91d3eaa | 1326 | |
Kojto | 93:e188a91d3eaa | 1327 | #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1328 | ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) |
Kojto | 93:e188a91d3eaa | 1329 | /** |
Kojto | 93:e188a91d3eaa | 1330 | * @} |
Kojto | 93:e188a91d3eaa | 1331 | */ |
Kojto | 93:e188a91d3eaa | 1332 | |
Kojto | 93:e188a91d3eaa | 1333 | /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source |
Kojto | 93:e188a91d3eaa | 1334 | * @{ |
Kojto | 93:e188a91d3eaa | 1335 | */ |
Kojto | 93:e188a91d3eaa | 1336 | #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK |
Kojto | 93:e188a91d3eaa | 1337 | #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL |
Kojto | 93:e188a91d3eaa | 1338 | |
Kojto | 93:e188a91d3eaa | 1339 | #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1340 | ((SOURCE) == RCC_TIM1CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1341 | /** |
Kojto | 93:e188a91d3eaa | 1342 | * @} |
Kojto | 93:e188a91d3eaa | 1343 | */ |
Kojto | 93:e188a91d3eaa | 1344 | |
Kojto | 93:e188a91d3eaa | 1345 | /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source |
Kojto | 93:e188a91d3eaa | 1346 | * @{ |
Kojto | 93:e188a91d3eaa | 1347 | */ |
Kojto | 93:e188a91d3eaa | 1348 | #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK |
Kojto | 93:e188a91d3eaa | 1349 | #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL |
Kojto | 93:e188a91d3eaa | 1350 | |
Kojto | 93:e188a91d3eaa | 1351 | #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1352 | ((SOURCE) == RCC_TIM15CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1353 | /** |
Kojto | 93:e188a91d3eaa | 1354 | * @} |
Kojto | 93:e188a91d3eaa | 1355 | */ |
Kojto | 93:e188a91d3eaa | 1356 | |
Kojto | 93:e188a91d3eaa | 1357 | /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source |
Kojto | 93:e188a91d3eaa | 1358 | * @{ |
Kojto | 93:e188a91d3eaa | 1359 | */ |
Kojto | 93:e188a91d3eaa | 1360 | #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK |
Kojto | 93:e188a91d3eaa | 1361 | #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL |
Kojto | 93:e188a91d3eaa | 1362 | |
Kojto | 93:e188a91d3eaa | 1363 | #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1364 | ((SOURCE) == RCC_TIM16CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1365 | /** |
Kojto | 93:e188a91d3eaa | 1366 | * @} |
Kojto | 93:e188a91d3eaa | 1367 | */ |
Kojto | 93:e188a91d3eaa | 1368 | |
Kojto | 93:e188a91d3eaa | 1369 | /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source |
Kojto | 93:e188a91d3eaa | 1370 | * @{ |
Kojto | 93:e188a91d3eaa | 1371 | */ |
Kojto | 93:e188a91d3eaa | 1372 | #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK |
Kojto | 93:e188a91d3eaa | 1373 | #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL |
Kojto | 93:e188a91d3eaa | 1374 | |
Kojto | 93:e188a91d3eaa | 1375 | #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1376 | ((SOURCE) == RCC_TIM17CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1377 | /** |
Kojto | 93:e188a91d3eaa | 1378 | * @} |
Kojto | 93:e188a91d3eaa | 1379 | */ |
Kojto | 93:e188a91d3eaa | 1380 | |
Kojto | 93:e188a91d3eaa | 1381 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 1382 | |
Kojto | 93:e188a91d3eaa | 1383 | #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 1384 | |
Kojto | 93:e188a91d3eaa | 1385 | /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source |
Kojto | 93:e188a91d3eaa | 1386 | * @{ |
Kojto | 93:e188a91d3eaa | 1387 | */ |
Kojto | 93:e188a91d3eaa | 1388 | #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK |
Kojto | 93:e188a91d3eaa | 1389 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1390 | #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE |
Kojto | 93:e188a91d3eaa | 1391 | #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI |
Kojto | 93:e188a91d3eaa | 1392 | |
Kojto | 93:e188a91d3eaa | 1393 | #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ |
Kojto | 93:e188a91d3eaa | 1394 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1395 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1396 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1397 | /** |
Kojto | 93:e188a91d3eaa | 1398 | * @} |
Kojto | 93:e188a91d3eaa | 1399 | */ |
Kojto | 93:e188a91d3eaa | 1400 | |
Kojto | 93:e188a91d3eaa | 1401 | /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source |
Kojto | 93:e188a91d3eaa | 1402 | * @{ |
Kojto | 93:e188a91d3eaa | 1403 | */ |
Kojto | 93:e188a91d3eaa | 1404 | #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI |
Kojto | 93:e188a91d3eaa | 1405 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1406 | |
Kojto | 93:e188a91d3eaa | 1407 | #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 1408 | ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) |
Kojto | 93:e188a91d3eaa | 1409 | /** |
Kojto | 93:e188a91d3eaa | 1410 | * @} |
Kojto | 93:e188a91d3eaa | 1411 | */ |
Kojto | 93:e188a91d3eaa | 1412 | |
Kojto | 93:e188a91d3eaa | 1413 | /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source |
Kojto | 93:e188a91d3eaa | 1414 | * @{ |
Kojto | 93:e188a91d3eaa | 1415 | */ |
Kojto | 93:e188a91d3eaa | 1416 | |
Kojto | 93:e188a91d3eaa | 1417 | /* ADC1 & ADC2 */ |
Kojto | 93:e188a91d3eaa | 1418 | #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO |
Kojto | 93:e188a91d3eaa | 1419 | #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 |
Kojto | 93:e188a91d3eaa | 1420 | #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 |
Kojto | 93:e188a91d3eaa | 1421 | #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 |
Kojto | 93:e188a91d3eaa | 1422 | #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 |
Kojto | 93:e188a91d3eaa | 1423 | #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 |
Kojto | 93:e188a91d3eaa | 1424 | #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 |
Kojto | 93:e188a91d3eaa | 1425 | #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 |
Kojto | 93:e188a91d3eaa | 1426 | #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 |
Kojto | 93:e188a91d3eaa | 1427 | #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 |
Kojto | 93:e188a91d3eaa | 1428 | #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 |
Kojto | 93:e188a91d3eaa | 1429 | #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 |
Kojto | 93:e188a91d3eaa | 1430 | #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 |
Kojto | 93:e188a91d3eaa | 1431 | |
Kojto | 93:e188a91d3eaa | 1432 | #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ |
Kojto | 93:e188a91d3eaa | 1433 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ |
Kojto | 93:e188a91d3eaa | 1434 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ |
Kojto | 93:e188a91d3eaa | 1435 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ |
Kojto | 93:e188a91d3eaa | 1436 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ |
Kojto | 93:e188a91d3eaa | 1437 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ |
Kojto | 93:e188a91d3eaa | 1438 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) |
Kojto | 93:e188a91d3eaa | 1439 | /** |
Kojto | 93:e188a91d3eaa | 1440 | * @} |
Kojto | 93:e188a91d3eaa | 1441 | */ |
Kojto | 93:e188a91d3eaa | 1442 | |
Kojto | 93:e188a91d3eaa | 1443 | /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source |
Kojto | 93:e188a91d3eaa | 1444 | * @{ |
Kojto | 93:e188a91d3eaa | 1445 | */ |
Kojto | 93:e188a91d3eaa | 1446 | #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK |
Kojto | 93:e188a91d3eaa | 1447 | #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT |
Kojto | 93:e188a91d3eaa | 1448 | |
Kojto | 93:e188a91d3eaa | 1449 | #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1450 | ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) |
Kojto | 93:e188a91d3eaa | 1451 | /** |
Kojto | 93:e188a91d3eaa | 1452 | * @} |
Kojto | 93:e188a91d3eaa | 1453 | */ |
Kojto | 93:e188a91d3eaa | 1454 | /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source |
Kojto | 93:e188a91d3eaa | 1455 | * @{ |
Kojto | 93:e188a91d3eaa | 1456 | */ |
Kojto | 93:e188a91d3eaa | 1457 | #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK |
Kojto | 93:e188a91d3eaa | 1458 | #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL |
Kojto | 93:e188a91d3eaa | 1459 | |
Kojto | 93:e188a91d3eaa | 1460 | #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1461 | ((SOURCE) == RCC_TIM1CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1462 | /** |
Kojto | 93:e188a91d3eaa | 1463 | * @} |
Kojto | 93:e188a91d3eaa | 1464 | */ |
Kojto | 93:e188a91d3eaa | 1465 | |
Kojto | 93:e188a91d3eaa | 1466 | /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source |
Kojto | 93:e188a91d3eaa | 1467 | * @{ |
Kojto | 93:e188a91d3eaa | 1468 | */ |
Kojto | 93:e188a91d3eaa | 1469 | #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK |
Kojto | 93:e188a91d3eaa | 1470 | #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1471 | #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE |
Kojto | 93:e188a91d3eaa | 1472 | #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI |
Kojto | 93:e188a91d3eaa | 1473 | |
Kojto | 93:e188a91d3eaa | 1474 | #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ |
Kojto | 93:e188a91d3eaa | 1475 | ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1476 | ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1477 | ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1478 | /** |
Kojto | 93:e188a91d3eaa | 1479 | * @} |
Kojto | 93:e188a91d3eaa | 1480 | */ |
Kojto | 93:e188a91d3eaa | 1481 | |
Kojto | 93:e188a91d3eaa | 1482 | /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source |
Kojto | 93:e188a91d3eaa | 1483 | * @{ |
Kojto | 93:e188a91d3eaa | 1484 | */ |
Kojto | 93:e188a91d3eaa | 1485 | #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK |
Kojto | 93:e188a91d3eaa | 1486 | #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1487 | #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE |
Kojto | 93:e188a91d3eaa | 1488 | #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI |
Kojto | 93:e188a91d3eaa | 1489 | |
Kojto | 93:e188a91d3eaa | 1490 | #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ |
Kojto | 93:e188a91d3eaa | 1491 | ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1492 | ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1493 | ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1494 | /** |
Kojto | 93:e188a91d3eaa | 1495 | * @} |
Kojto | 93:e188a91d3eaa | 1496 | */ |
Kojto | 93:e188a91d3eaa | 1497 | |
Kojto | 93:e188a91d3eaa | 1498 | #endif /* STM32F302xC || STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 1499 | |
Kojto | 93:e188a91d3eaa | 1500 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 1501 | |
Kojto | 93:e188a91d3eaa | 1502 | /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source |
Kojto | 93:e188a91d3eaa | 1503 | * @{ |
Kojto | 93:e188a91d3eaa | 1504 | */ |
Kojto | 93:e188a91d3eaa | 1505 | #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK |
Kojto | 93:e188a91d3eaa | 1506 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1507 | #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE |
Kojto | 93:e188a91d3eaa | 1508 | #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI |
Kojto | 93:e188a91d3eaa | 1509 | |
Kojto | 93:e188a91d3eaa | 1510 | #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ |
Kojto | 93:e188a91d3eaa | 1511 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1512 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1513 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1514 | /** |
Kojto | 93:e188a91d3eaa | 1515 | * @} |
Kojto | 93:e188a91d3eaa | 1516 | */ |
Kojto | 93:e188a91d3eaa | 1517 | |
Kojto | 93:e188a91d3eaa | 1518 | /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source |
Kojto | 93:e188a91d3eaa | 1519 | * @{ |
Kojto | 93:e188a91d3eaa | 1520 | */ |
Kojto | 93:e188a91d3eaa | 1521 | #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI |
Kojto | 93:e188a91d3eaa | 1522 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1523 | |
Kojto | 93:e188a91d3eaa | 1524 | #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 1525 | ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) |
Kojto | 93:e188a91d3eaa | 1526 | /** |
Kojto | 93:e188a91d3eaa | 1527 | * @} |
Kojto | 93:e188a91d3eaa | 1528 | */ |
Kojto | 93:e188a91d3eaa | 1529 | |
Kojto | 93:e188a91d3eaa | 1530 | /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source |
Kojto | 93:e188a91d3eaa | 1531 | * @{ |
Kojto | 93:e188a91d3eaa | 1532 | */ |
Kojto | 93:e188a91d3eaa | 1533 | #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI |
Kojto | 93:e188a91d3eaa | 1534 | #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1535 | |
Kojto | 93:e188a91d3eaa | 1536 | #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 1537 | ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)) |
Kojto | 93:e188a91d3eaa | 1538 | /** |
Kojto | 93:e188a91d3eaa | 1539 | * @} |
Kojto | 93:e188a91d3eaa | 1540 | */ |
Kojto | 93:e188a91d3eaa | 1541 | |
Kojto | 93:e188a91d3eaa | 1542 | /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source |
Kojto | 93:e188a91d3eaa | 1543 | * @{ |
Kojto | 93:e188a91d3eaa | 1544 | */ |
Kojto | 93:e188a91d3eaa | 1545 | |
Kojto | 93:e188a91d3eaa | 1546 | /* ADC1 & ADC2 */ |
Kojto | 93:e188a91d3eaa | 1547 | #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO |
Kojto | 93:e188a91d3eaa | 1548 | #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 |
Kojto | 93:e188a91d3eaa | 1549 | #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 |
Kojto | 93:e188a91d3eaa | 1550 | #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 |
Kojto | 93:e188a91d3eaa | 1551 | #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 |
Kojto | 93:e188a91d3eaa | 1552 | #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 |
Kojto | 93:e188a91d3eaa | 1553 | #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 |
Kojto | 93:e188a91d3eaa | 1554 | #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 |
Kojto | 93:e188a91d3eaa | 1555 | #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 |
Kojto | 93:e188a91d3eaa | 1556 | #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 |
Kojto | 93:e188a91d3eaa | 1557 | #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 |
Kojto | 93:e188a91d3eaa | 1558 | #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 |
Kojto | 93:e188a91d3eaa | 1559 | #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 |
Kojto | 93:e188a91d3eaa | 1560 | |
Kojto | 93:e188a91d3eaa | 1561 | #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ |
Kojto | 93:e188a91d3eaa | 1562 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ |
Kojto | 93:e188a91d3eaa | 1563 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ |
Kojto | 93:e188a91d3eaa | 1564 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ |
Kojto | 93:e188a91d3eaa | 1565 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ |
Kojto | 93:e188a91d3eaa | 1566 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ |
Kojto | 93:e188a91d3eaa | 1567 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) |
Kojto | 93:e188a91d3eaa | 1568 | /** |
Kojto | 93:e188a91d3eaa | 1569 | * @} |
Kojto | 93:e188a91d3eaa | 1570 | */ |
Kojto | 93:e188a91d3eaa | 1571 | |
Kojto | 93:e188a91d3eaa | 1572 | /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source |
Kojto | 93:e188a91d3eaa | 1573 | * @{ |
Kojto | 93:e188a91d3eaa | 1574 | */ |
Kojto | 93:e188a91d3eaa | 1575 | #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK |
Kojto | 93:e188a91d3eaa | 1576 | #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT |
Kojto | 93:e188a91d3eaa | 1577 | |
Kojto | 93:e188a91d3eaa | 1578 | #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1579 | ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) |
Kojto | 93:e188a91d3eaa | 1580 | /** |
Kojto | 93:e188a91d3eaa | 1581 | * @} |
Kojto | 93:e188a91d3eaa | 1582 | */ |
Kojto | 93:e188a91d3eaa | 1583 | |
Kojto | 93:e188a91d3eaa | 1584 | /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source |
Kojto | 93:e188a91d3eaa | 1585 | * @{ |
Kojto | 93:e188a91d3eaa | 1586 | */ |
Kojto | 93:e188a91d3eaa | 1587 | #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK |
Kojto | 93:e188a91d3eaa | 1588 | #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL |
Kojto | 93:e188a91d3eaa | 1589 | |
Kojto | 93:e188a91d3eaa | 1590 | #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1591 | ((SOURCE) == RCC_TIM1CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1592 | /** |
Kojto | 93:e188a91d3eaa | 1593 | * @} |
Kojto | 93:e188a91d3eaa | 1594 | */ |
Kojto | 93:e188a91d3eaa | 1595 | |
Kojto | 93:e188a91d3eaa | 1596 | /** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source |
Kojto | 93:e188a91d3eaa | 1597 | * @{ |
Kojto | 93:e188a91d3eaa | 1598 | */ |
Kojto | 93:e188a91d3eaa | 1599 | #define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK |
Kojto | 93:e188a91d3eaa | 1600 | #define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL |
Kojto | 93:e188a91d3eaa | 1601 | |
Kojto | 93:e188a91d3eaa | 1602 | #define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1603 | ((SOURCE) == RCC_TIM2CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1604 | /** |
Kojto | 93:e188a91d3eaa | 1605 | * @} |
Kojto | 93:e188a91d3eaa | 1606 | */ |
Kojto | 93:e188a91d3eaa | 1607 | |
Kojto | 93:e188a91d3eaa | 1608 | /** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source |
Kojto | 93:e188a91d3eaa | 1609 | * @{ |
Kojto | 93:e188a91d3eaa | 1610 | */ |
Kojto | 93:e188a91d3eaa | 1611 | #define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK |
Kojto | 93:e188a91d3eaa | 1612 | #define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL |
Kojto | 93:e188a91d3eaa | 1613 | |
Kojto | 93:e188a91d3eaa | 1614 | #define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1615 | ((SOURCE) == RCC_TIM34CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1616 | /** |
Kojto | 93:e188a91d3eaa | 1617 | * @} |
Kojto | 93:e188a91d3eaa | 1618 | */ |
Kojto | 93:e188a91d3eaa | 1619 | |
Kojto | 93:e188a91d3eaa | 1620 | /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source |
Kojto | 93:e188a91d3eaa | 1621 | * @{ |
Kojto | 93:e188a91d3eaa | 1622 | */ |
Kojto | 93:e188a91d3eaa | 1623 | #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK |
Kojto | 93:e188a91d3eaa | 1624 | #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL |
Kojto | 93:e188a91d3eaa | 1625 | |
Kojto | 93:e188a91d3eaa | 1626 | #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1627 | ((SOURCE) == RCC_TIM15CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1628 | /** |
Kojto | 93:e188a91d3eaa | 1629 | * @} |
Kojto | 93:e188a91d3eaa | 1630 | */ |
Kojto | 93:e188a91d3eaa | 1631 | |
Kojto | 93:e188a91d3eaa | 1632 | /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source |
Kojto | 93:e188a91d3eaa | 1633 | * @{ |
Kojto | 93:e188a91d3eaa | 1634 | */ |
Kojto | 93:e188a91d3eaa | 1635 | #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK |
Kojto | 93:e188a91d3eaa | 1636 | #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL |
Kojto | 93:e188a91d3eaa | 1637 | |
Kojto | 93:e188a91d3eaa | 1638 | #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1639 | ((SOURCE) == RCC_TIM16CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1640 | /** |
Kojto | 93:e188a91d3eaa | 1641 | * @} |
Kojto | 93:e188a91d3eaa | 1642 | */ |
Kojto | 93:e188a91d3eaa | 1643 | |
Kojto | 93:e188a91d3eaa | 1644 | /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source |
Kojto | 93:e188a91d3eaa | 1645 | * @{ |
Kojto | 93:e188a91d3eaa | 1646 | */ |
Kojto | 93:e188a91d3eaa | 1647 | #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK |
Kojto | 93:e188a91d3eaa | 1648 | #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL |
Kojto | 93:e188a91d3eaa | 1649 | |
Kojto | 93:e188a91d3eaa | 1650 | #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1651 | ((SOURCE) == RCC_TIM17CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1652 | /** |
Kojto | 93:e188a91d3eaa | 1653 | * @} |
Kojto | 93:e188a91d3eaa | 1654 | */ |
Kojto | 93:e188a91d3eaa | 1655 | |
Kojto | 93:e188a91d3eaa | 1656 | /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source |
Kojto | 93:e188a91d3eaa | 1657 | * @{ |
Kojto | 93:e188a91d3eaa | 1658 | */ |
Kojto | 93:e188a91d3eaa | 1659 | #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK |
Kojto | 93:e188a91d3eaa | 1660 | #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1661 | #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE |
Kojto | 93:e188a91d3eaa | 1662 | #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI |
Kojto | 93:e188a91d3eaa | 1663 | |
Kojto | 93:e188a91d3eaa | 1664 | #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ |
Kojto | 93:e188a91d3eaa | 1665 | ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1666 | ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1667 | ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1668 | /** |
Kojto | 93:e188a91d3eaa | 1669 | * @} |
Kojto | 93:e188a91d3eaa | 1670 | */ |
Kojto | 93:e188a91d3eaa | 1671 | |
Kojto | 93:e188a91d3eaa | 1672 | /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source |
Kojto | 93:e188a91d3eaa | 1673 | * @{ |
Kojto | 93:e188a91d3eaa | 1674 | */ |
Kojto | 93:e188a91d3eaa | 1675 | #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK |
Kojto | 93:e188a91d3eaa | 1676 | #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1677 | #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE |
Kojto | 93:e188a91d3eaa | 1678 | #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI |
Kojto | 93:e188a91d3eaa | 1679 | |
Kojto | 93:e188a91d3eaa | 1680 | #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ |
Kojto | 93:e188a91d3eaa | 1681 | ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1682 | ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1683 | ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1684 | /** |
Kojto | 93:e188a91d3eaa | 1685 | * @} |
Kojto | 93:e188a91d3eaa | 1686 | */ |
Kojto | 93:e188a91d3eaa | 1687 | |
Kojto | 93:e188a91d3eaa | 1688 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 1689 | |
Kojto | 93:e188a91d3eaa | 1690 | #if defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 1691 | /** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source |
Kojto | 93:e188a91d3eaa | 1692 | * @{ |
Kojto | 93:e188a91d3eaa | 1693 | */ |
Kojto | 93:e188a91d3eaa | 1694 | #define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK |
Kojto | 93:e188a91d3eaa | 1695 | #define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL |
Kojto | 93:e188a91d3eaa | 1696 | |
Kojto | 93:e188a91d3eaa | 1697 | #define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1698 | ((SOURCE) == RCC_TIM20CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1699 | /** |
Kojto | 93:e188a91d3eaa | 1700 | * @} |
Kojto | 93:e188a91d3eaa | 1701 | */ |
Kojto | 93:e188a91d3eaa | 1702 | #endif /* STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 1703 | |
Kojto | 93:e188a91d3eaa | 1704 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 1705 | defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 1706 | |
Kojto | 93:e188a91d3eaa | 1707 | /** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source |
Kojto | 93:e188a91d3eaa | 1708 | * @{ |
Kojto | 93:e188a91d3eaa | 1709 | */ |
Kojto | 93:e188a91d3eaa | 1710 | |
Kojto | 93:e188a91d3eaa | 1711 | /* ADC3 & ADC4 */ |
Kojto | 93:e188a91d3eaa | 1712 | #define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO |
Kojto | 93:e188a91d3eaa | 1713 | #define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1 |
Kojto | 93:e188a91d3eaa | 1714 | #define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2 |
Kojto | 93:e188a91d3eaa | 1715 | #define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4 |
Kojto | 93:e188a91d3eaa | 1716 | #define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6 |
Kojto | 93:e188a91d3eaa | 1717 | #define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8 |
Kojto | 93:e188a91d3eaa | 1718 | #define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10 |
Kojto | 93:e188a91d3eaa | 1719 | #define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12 |
Kojto | 93:e188a91d3eaa | 1720 | #define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16 |
Kojto | 93:e188a91d3eaa | 1721 | #define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32 |
Kojto | 93:e188a91d3eaa | 1722 | #define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64 |
Kojto | 93:e188a91d3eaa | 1723 | #define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128 |
Kojto | 93:e188a91d3eaa | 1724 | #define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256 |
Kojto | 93:e188a91d3eaa | 1725 | |
Kojto | 93:e188a91d3eaa | 1726 | #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \ |
Kojto | 93:e188a91d3eaa | 1727 | ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \ |
Kojto | 93:e188a91d3eaa | 1728 | ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \ |
Kojto | 93:e188a91d3eaa | 1729 | ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \ |
Kojto | 93:e188a91d3eaa | 1730 | ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \ |
Kojto | 93:e188a91d3eaa | 1731 | ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \ |
Kojto | 93:e188a91d3eaa | 1732 | ((ADCCLK) == RCC_ADC34PLLCLK_DIV256)) |
Kojto | 93:e188a91d3eaa | 1733 | /** |
Kojto | 93:e188a91d3eaa | 1734 | * @} |
Kojto | 93:e188a91d3eaa | 1735 | */ |
Kojto | 93:e188a91d3eaa | 1736 | |
Kojto | 93:e188a91d3eaa | 1737 | /** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source |
Kojto | 93:e188a91d3eaa | 1738 | * @{ |
Kojto | 93:e188a91d3eaa | 1739 | */ |
Kojto | 93:e188a91d3eaa | 1740 | #define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK |
Kojto | 93:e188a91d3eaa | 1741 | #define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL |
Kojto | 93:e188a91d3eaa | 1742 | |
Kojto | 93:e188a91d3eaa | 1743 | #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1744 | ((SOURCE) == RCC_TIM8CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1745 | /** |
Kojto | 93:e188a91d3eaa | 1746 | * @} |
Kojto | 93:e188a91d3eaa | 1747 | */ |
Kojto | 93:e188a91d3eaa | 1748 | |
Kojto | 93:e188a91d3eaa | 1749 | #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 1750 | |
Kojto | 93:e188a91d3eaa | 1751 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 1752 | |
Kojto | 93:e188a91d3eaa | 1753 | /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source |
Kojto | 93:e188a91d3eaa | 1754 | * @{ |
Kojto | 93:e188a91d3eaa | 1755 | */ |
Kojto | 93:e188a91d3eaa | 1756 | #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK |
Kojto | 93:e188a91d3eaa | 1757 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1758 | #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE |
Kojto | 93:e188a91d3eaa | 1759 | #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI |
Kojto | 93:e188a91d3eaa | 1760 | |
Kojto | 93:e188a91d3eaa | 1761 | #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \ |
Kojto | 93:e188a91d3eaa | 1762 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1763 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1764 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1765 | /** |
Kojto | 93:e188a91d3eaa | 1766 | * @} |
Kojto | 93:e188a91d3eaa | 1767 | */ |
Kojto | 93:e188a91d3eaa | 1768 | |
Kojto | 93:e188a91d3eaa | 1769 | /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source |
Kojto | 93:e188a91d3eaa | 1770 | * @{ |
Kojto | 93:e188a91d3eaa | 1771 | */ |
Kojto | 93:e188a91d3eaa | 1772 | /* ADC1 & ADC2 */ |
Kojto | 93:e188a91d3eaa | 1773 | #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO |
Kojto | 93:e188a91d3eaa | 1774 | #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1 |
Kojto | 93:e188a91d3eaa | 1775 | #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2 |
Kojto | 93:e188a91d3eaa | 1776 | #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4 |
Kojto | 93:e188a91d3eaa | 1777 | #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6 |
Kojto | 93:e188a91d3eaa | 1778 | #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8 |
Kojto | 93:e188a91d3eaa | 1779 | #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10 |
Kojto | 93:e188a91d3eaa | 1780 | #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12 |
Kojto | 93:e188a91d3eaa | 1781 | #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16 |
Kojto | 93:e188a91d3eaa | 1782 | #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32 |
Kojto | 93:e188a91d3eaa | 1783 | #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64 |
Kojto | 93:e188a91d3eaa | 1784 | #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128 |
Kojto | 93:e188a91d3eaa | 1785 | #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256 |
Kojto | 93:e188a91d3eaa | 1786 | |
Kojto | 93:e188a91d3eaa | 1787 | #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \ |
Kojto | 93:e188a91d3eaa | 1788 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \ |
Kojto | 93:e188a91d3eaa | 1789 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \ |
Kojto | 93:e188a91d3eaa | 1790 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \ |
Kojto | 93:e188a91d3eaa | 1791 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \ |
Kojto | 93:e188a91d3eaa | 1792 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \ |
Kojto | 93:e188a91d3eaa | 1793 | ((ADCCLK) == RCC_ADC12PLLCLK_DIV256)) |
Kojto | 93:e188a91d3eaa | 1794 | /** |
Kojto | 93:e188a91d3eaa | 1795 | * @} |
Kojto | 93:e188a91d3eaa | 1796 | */ |
Kojto | 93:e188a91d3eaa | 1797 | |
Kojto | 93:e188a91d3eaa | 1798 | /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source |
Kojto | 93:e188a91d3eaa | 1799 | * @{ |
Kojto | 93:e188a91d3eaa | 1800 | */ |
Kojto | 93:e188a91d3eaa | 1801 | #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK |
Kojto | 93:e188a91d3eaa | 1802 | #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL |
Kojto | 93:e188a91d3eaa | 1803 | |
Kojto | 93:e188a91d3eaa | 1804 | #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1805 | ((SOURCE) == RCC_TIM1CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1806 | /** |
Kojto | 93:e188a91d3eaa | 1807 | * @} |
Kojto | 93:e188a91d3eaa | 1808 | */ |
Kojto | 93:e188a91d3eaa | 1809 | |
Kojto | 93:e188a91d3eaa | 1810 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 1811 | |
Kojto | 93:e188a91d3eaa | 1812 | #if defined(STM32F334x8) |
Kojto | 93:e188a91d3eaa | 1813 | |
Kojto | 93:e188a91d3eaa | 1814 | /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source |
Kojto | 93:e188a91d3eaa | 1815 | * @{ |
Kojto | 93:e188a91d3eaa | 1816 | */ |
Kojto | 93:e188a91d3eaa | 1817 | #define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK |
Kojto | 93:e188a91d3eaa | 1818 | #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL |
Kojto | 93:e188a91d3eaa | 1819 | |
Kojto | 93:e188a91d3eaa | 1820 | #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \ |
Kojto | 93:e188a91d3eaa | 1821 | ((SOURCE) == RCC_HRTIM1CLK_PLLCLK)) |
Kojto | 93:e188a91d3eaa | 1822 | /** |
Kojto | 93:e188a91d3eaa | 1823 | * @} |
Kojto | 93:e188a91d3eaa | 1824 | */ |
Kojto | 93:e188a91d3eaa | 1825 | |
Kojto | 93:e188a91d3eaa | 1826 | #endif /* STM32F334x8 */ |
Kojto | 93:e188a91d3eaa | 1827 | |
Kojto | 93:e188a91d3eaa | 1828 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 1829 | |
Kojto | 93:e188a91d3eaa | 1830 | /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source |
Kojto | 93:e188a91d3eaa | 1831 | * @{ |
Kojto | 93:e188a91d3eaa | 1832 | */ |
Kojto | 93:e188a91d3eaa | 1833 | #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK |
Kojto | 93:e188a91d3eaa | 1834 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1835 | #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE |
Kojto | 93:e188a91d3eaa | 1836 | #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI |
Kojto | 93:e188a91d3eaa | 1837 | |
Kojto | 93:e188a91d3eaa | 1838 | #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ |
Kojto | 93:e188a91d3eaa | 1839 | ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
Kojto | 93:e188a91d3eaa | 1840 | ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ |
Kojto | 93:e188a91d3eaa | 1841 | ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) |
Kojto | 93:e188a91d3eaa | 1842 | /** |
Kojto | 93:e188a91d3eaa | 1843 | * @} |
Kojto | 93:e188a91d3eaa | 1844 | */ |
Kojto | 93:e188a91d3eaa | 1845 | |
Kojto | 93:e188a91d3eaa | 1846 | /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source |
Kojto | 93:e188a91d3eaa | 1847 | * @{ |
Kojto | 93:e188a91d3eaa | 1848 | */ |
Kojto | 93:e188a91d3eaa | 1849 | #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI |
Kojto | 93:e188a91d3eaa | 1850 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK |
Kojto | 93:e188a91d3eaa | 1851 | |
Kojto | 93:e188a91d3eaa | 1852 | #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 1853 | ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)) |
Kojto | 93:e188a91d3eaa | 1854 | /** |
Kojto | 93:e188a91d3eaa | 1855 | * @} |
Kojto | 93:e188a91d3eaa | 1856 | */ |
Kojto | 93:e188a91d3eaa | 1857 | |
Kojto | 93:e188a91d3eaa | 1858 | /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source |
Kojto | 93:e188a91d3eaa | 1859 | * @{ |
Kojto | 93:e188a91d3eaa | 1860 | */ |
Kojto | 93:e188a91d3eaa | 1861 | |
Kojto | 93:e188a91d3eaa | 1862 | /* ADC1 */ |
Kojto | 93:e188a91d3eaa | 1863 | #define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2 |
Kojto | 93:e188a91d3eaa | 1864 | #define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4 |
Kojto | 93:e188a91d3eaa | 1865 | #define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6 |
Kojto | 93:e188a91d3eaa | 1866 | #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8 |
Kojto | 93:e188a91d3eaa | 1867 | |
Kojto | 93:e188a91d3eaa | 1868 | #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \ |
Kojto | 93:e188a91d3eaa | 1869 | ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8)) |
Kojto | 93:e188a91d3eaa | 1870 | /** |
Kojto | 93:e188a91d3eaa | 1871 | * @} |
Kojto | 93:e188a91d3eaa | 1872 | */ |
Kojto | 93:e188a91d3eaa | 1873 | |
Kojto | 93:e188a91d3eaa | 1874 | /** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source |
Kojto | 93:e188a91d3eaa | 1875 | * @{ |
Kojto | 93:e188a91d3eaa | 1876 | */ |
Kojto | 93:e188a91d3eaa | 1877 | #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244 |
Kojto | 93:e188a91d3eaa | 1878 | #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE |
Kojto | 93:e188a91d3eaa | 1879 | |
Kojto | 93:e188a91d3eaa | 1880 | #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ |
Kojto | 93:e188a91d3eaa | 1881 | ((SOURCE) == RCC_CECCLKSOURCE_LSE)) |
Kojto | 93:e188a91d3eaa | 1882 | /** |
Kojto | 93:e188a91d3eaa | 1883 | * @} |
Kojto | 93:e188a91d3eaa | 1884 | */ |
Kojto | 93:e188a91d3eaa | 1885 | |
Kojto | 93:e188a91d3eaa | 1886 | /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler |
Kojto | 93:e188a91d3eaa | 1887 | * @{ |
Kojto | 93:e188a91d3eaa | 1888 | */ |
Kojto | 93:e188a91d3eaa | 1889 | #define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1 |
Kojto | 93:e188a91d3eaa | 1890 | #define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2 |
Kojto | 93:e188a91d3eaa | 1891 | #define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4 |
Kojto | 93:e188a91d3eaa | 1892 | #define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6 |
Kojto | 93:e188a91d3eaa | 1893 | #define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8 |
Kojto | 93:e188a91d3eaa | 1894 | #define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10 |
Kojto | 93:e188a91d3eaa | 1895 | #define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12 |
Kojto | 93:e188a91d3eaa | 1896 | #define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14 |
Kojto | 93:e188a91d3eaa | 1897 | #define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16 |
Kojto | 93:e188a91d3eaa | 1898 | #define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20 |
Kojto | 93:e188a91d3eaa | 1899 | #define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24 |
Kojto | 93:e188a91d3eaa | 1900 | #define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28 |
Kojto | 93:e188a91d3eaa | 1901 | #define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32 |
Kojto | 93:e188a91d3eaa | 1902 | #define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36 |
Kojto | 93:e188a91d3eaa | 1903 | #define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40 |
Kojto | 93:e188a91d3eaa | 1904 | #define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44 |
Kojto | 93:e188a91d3eaa | 1905 | #define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48 |
Kojto | 93:e188a91d3eaa | 1906 | |
Kojto | 93:e188a91d3eaa | 1907 | #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \ |
Kojto | 93:e188a91d3eaa | 1908 | ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \ |
Kojto | 93:e188a91d3eaa | 1909 | ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \ |
Kojto | 93:e188a91d3eaa | 1910 | ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \ |
Kojto | 93:e188a91d3eaa | 1911 | ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \ |
Kojto | 93:e188a91d3eaa | 1912 | ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \ |
Kojto | 93:e188a91d3eaa | 1913 | ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \ |
Kojto | 93:e188a91d3eaa | 1914 | ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \ |
Kojto | 93:e188a91d3eaa | 1915 | ((DIV) == RCC_SDADCSYSCLK_DIV48)) |
Kojto | 93:e188a91d3eaa | 1916 | /** |
Kojto | 93:e188a91d3eaa | 1917 | * @} |
Kojto | 93:e188a91d3eaa | 1918 | */ |
Kojto | 93:e188a91d3eaa | 1919 | |
Kojto | 93:e188a91d3eaa | 1920 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 1921 | |
Kojto | 93:e188a91d3eaa | 1922 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ |
Kojto | 93:e188a91d3eaa | 1923 | defined(STM32F302xC) || defined(STM32F303xC) || \ |
Kojto | 93:e188a91d3eaa | 1924 | defined(STM32F302x8) || \ |
Kojto | 93:e188a91d3eaa | 1925 | defined(STM32F373xC) |
Kojto | 93:e188a91d3eaa | 1926 | /** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source |
Kojto | 93:e188a91d3eaa | 1927 | * @{ |
Kojto | 93:e188a91d3eaa | 1928 | */ |
Kojto | 93:e188a91d3eaa | 1929 | #define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1 |
Kojto | 93:e188a91d3eaa | 1930 | #define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5 |
Kojto | 93:e188a91d3eaa | 1931 | |
Kojto | 93:e188a91d3eaa | 1932 | #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) || \ |
Kojto | 93:e188a91d3eaa | 1933 | ((SOURCE) == RCC_USBPLLCLK_DIV1_5)) |
Kojto | 93:e188a91d3eaa | 1934 | /** |
Kojto | 93:e188a91d3eaa | 1935 | * @} |
Kojto | 93:e188a91d3eaa | 1936 | */ |
Kojto | 93:e188a91d3eaa | 1937 | |
Kojto | 93:e188a91d3eaa | 1938 | #endif /* STM32F302xE || STM32F303xE || */ |
Kojto | 93:e188a91d3eaa | 1939 | /* STM32F302xC || STM32F303xC || */ |
Kojto | 93:e188a91d3eaa | 1940 | /* STM32F302x8 || */ |
Kojto | 93:e188a91d3eaa | 1941 | /* STM32F373xC */ |
Kojto | 93:e188a91d3eaa | 1942 | |
Kojto | 93:e188a91d3eaa | 1943 | #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 1944 | defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 1945 | /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler |
Kojto | 93:e188a91d3eaa | 1946 | * @{ |
Kojto | 93:e188a91d3eaa | 1947 | */ |
Kojto | 93:e188a91d3eaa | 1948 | #define RCC_MCO_NODIV ((uint32_t)0x00000000) |
Kojto | 93:e188a91d3eaa | 1949 | |
Kojto | 93:e188a91d3eaa | 1950 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV)) |
Kojto | 93:e188a91d3eaa | 1951 | /** |
Kojto | 93:e188a91d3eaa | 1952 | * @} |
Kojto | 93:e188a91d3eaa | 1953 | */ |
Kojto | 93:e188a91d3eaa | 1954 | #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 1955 | /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 1956 | |
Kojto | 93:e188a91d3eaa | 1957 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 1958 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 1959 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 1960 | |
Kojto | 93:e188a91d3eaa | 1961 | /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler |
Kojto | 93:e188a91d3eaa | 1962 | * @{ |
Kojto | 93:e188a91d3eaa | 1963 | */ |
Kojto | 93:e188a91d3eaa | 1964 | #define RCC_MCO_DIV1 ((uint32_t)0x00000000) |
Kojto | 93:e188a91d3eaa | 1965 | #define RCC_MCO_DIV2 ((uint32_t)0x10000000) |
Kojto | 93:e188a91d3eaa | 1966 | #define RCC_MCO_DIV4 ((uint32_t)0x20000000) |
Kojto | 93:e188a91d3eaa | 1967 | #define RCC_MCO_DIV8 ((uint32_t)0x30000000) |
Kojto | 93:e188a91d3eaa | 1968 | #define RCC_MCO_DIV16 ((uint32_t)0x40000000) |
Kojto | 93:e188a91d3eaa | 1969 | #define RCC_MCO_DIV32 ((uint32_t)0x50000000) |
Kojto | 93:e188a91d3eaa | 1970 | #define RCC_MCO_DIV64 ((uint32_t)0x60000000) |
Kojto | 93:e188a91d3eaa | 1971 | #define RCC_MCO_DIV128 ((uint32_t)0x70000000) |
Kojto | 93:e188a91d3eaa | 1972 | |
Kojto | 93:e188a91d3eaa | 1973 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \ |
Kojto | 93:e188a91d3eaa | 1974 | ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \ |
Kojto | 93:e188a91d3eaa | 1975 | ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \ |
Kojto | 93:e188a91d3eaa | 1976 | ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128)) |
Kojto | 93:e188a91d3eaa | 1977 | /** |
Kojto | 93:e188a91d3eaa | 1978 | * @} |
Kojto | 93:e188a91d3eaa | 1979 | */ |
Kojto | 93:e188a91d3eaa | 1980 | |
Kojto | 93:e188a91d3eaa | 1981 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 1982 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 1983 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 1984 | |
Kojto | 93:e188a91d3eaa | 1985 | /** |
Kojto | 93:e188a91d3eaa | 1986 | * @} |
Kojto | 93:e188a91d3eaa | 1987 | */ |
Kojto | 93:e188a91d3eaa | 1988 | |
Kojto | 93:e188a91d3eaa | 1989 | /* Exported macro ------------------------------------------------------------*/ |
Kojto | 93:e188a91d3eaa | 1990 | /** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros |
Kojto | 93:e188a91d3eaa | 1991 | * @{ |
Kojto | 93:e188a91d3eaa | 1992 | */ |
Kojto | 93:e188a91d3eaa | 1993 | |
Kojto | 93:e188a91d3eaa | 1994 | /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration |
Kojto | 93:e188a91d3eaa | 1995 | * @{ |
Kojto | 93:e188a91d3eaa | 1996 | */ |
Kojto | 93:e188a91d3eaa | 1997 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 1998 | /** @brief Macro to configure the PLL clock source, multiplication and division factors. |
Kojto | 93:e188a91d3eaa | 1999 | * @note This macro must be used only when the PLL is disabled. |
Kojto | 93:e188a91d3eaa | 2000 | * |
Kojto | 93:e188a91d3eaa | 2001 | * @param __RCC_PLLSource__: specifies the PLL entry clock source. |
Kojto | 93:e188a91d3eaa | 2002 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2003 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
Kojto | 93:e188a91d3eaa | 2004 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
Kojto | 93:e188a91d3eaa | 2005 | * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock |
Kojto | 93:e188a91d3eaa | 2006 | * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16. |
Kojto | 93:e188a91d3eaa | 2007 | * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock |
Kojto | 93:e188a91d3eaa | 2008 | * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. |
Kojto | 93:e188a91d3eaa | 2009 | * |
Kojto | 93:e188a91d3eaa | 2010 | */ |
Kojto | 93:e188a91d3eaa | 2011 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \ |
Kojto | 93:e188a91d3eaa | 2012 | do { \ |
Kojto | 93:e188a91d3eaa | 2013 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \ |
Kojto | 93:e188a91d3eaa | 2014 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \ |
Kojto | 93:e188a91d3eaa | 2015 | } while(0) |
Kojto | 93:e188a91d3eaa | 2016 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2017 | |
Kojto | 93:e188a91d3eaa | 2018 | #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 2019 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 2020 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
Kojto | 93:e188a91d3eaa | 2021 | defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2022 | /** @brief Macro to configure the PLL clock source and multiplication factor. |
Kojto | 93:e188a91d3eaa | 2023 | * @note This macro must be used only when the PLL is disabled. |
Kojto | 93:e188a91d3eaa | 2024 | * |
Kojto | 93:e188a91d3eaa | 2025 | * @param __RCC_PLLSource__: specifies the PLL entry clock source. |
Kojto | 93:e188a91d3eaa | 2026 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2027 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
Kojto | 93:e188a91d3eaa | 2028 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
Kojto | 93:e188a91d3eaa | 2029 | * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock |
Kojto | 93:e188a91d3eaa | 2030 | * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16. |
Kojto | 93:e188a91d3eaa | 2031 | * |
Kojto | 93:e188a91d3eaa | 2032 | */ |
Kojto | 93:e188a91d3eaa | 2033 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \ |
Kojto | 93:e188a91d3eaa | 2034 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))) |
Kojto | 93:e188a91d3eaa | 2035 | #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 2036 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 2037 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2038 | /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2039 | /** |
Kojto | 93:e188a91d3eaa | 2040 | * @} |
Kojto | 93:e188a91d3eaa | 2041 | */ |
Kojto | 93:e188a91d3eaa | 2042 | |
Kojto | 93:e188a91d3eaa | 2043 | #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 2044 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 2045 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \ |
Kojto | 93:e188a91d3eaa | 2046 | defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2047 | /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration |
Kojto | 93:e188a91d3eaa | 2048 | * @{ |
Kojto | 93:e188a91d3eaa | 2049 | */ |
Kojto | 93:e188a91d3eaa | 2050 | |
Kojto | 93:e188a91d3eaa | 2051 | /** |
Kojto | 93:e188a91d3eaa | 2052 | * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL. |
Kojto | 93:e188a91d3eaa | 2053 | * @note Predivision factor can not be changed if PLL is used as system clock |
Kojto | 93:e188a91d3eaa | 2054 | * In this case, you have to select another source of the system clock, disable the PLL and |
Kojto | 93:e188a91d3eaa | 2055 | * then change the HSE predivision factor. |
Kojto | 93:e188a91d3eaa | 2056 | * @param __HSEPredivValue__: specifies the division value applied to HSE. |
Kojto | 93:e188a91d3eaa | 2057 | * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16. |
Kojto | 93:e188a91d3eaa | 2058 | */ |
Kojto | 93:e188a91d3eaa | 2059 | #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \ |
Kojto | 93:e188a91d3eaa | 2060 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__)) |
Kojto | 93:e188a91d3eaa | 2061 | /** |
Kojto | 93:e188a91d3eaa | 2062 | * @} |
Kojto | 93:e188a91d3eaa | 2063 | */ |
Kojto | 93:e188a91d3eaa | 2064 | #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 2065 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 2066 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2067 | /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2068 | |
Kojto | 93:e188a91d3eaa | 2069 | /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable |
Kojto | 93:e188a91d3eaa | 2070 | * @brief Enable or disable the AHB peripheral clock. |
Kojto | 93:e188a91d3eaa | 2071 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 93:e188a91d3eaa | 2072 | * is disabled and the application software has to enable this clock before |
Kojto | 93:e188a91d3eaa | 2073 | * using it. |
Kojto | 93:e188a91d3eaa | 2074 | * @{ |
Kojto | 93:e188a91d3eaa | 2075 | */ |
Kojto | 93:e188a91d3eaa | 2076 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 2077 | #define __ADC1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC1EN)) |
Kojto | 93:e188a91d3eaa | 2078 | |
Kojto | 93:e188a91d3eaa | 2079 | #define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN)) |
Kojto | 93:e188a91d3eaa | 2080 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2081 | |
Kojto | 93:e188a91d3eaa | 2082 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2083 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2084 | #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN)) |
Kojto | 93:e188a91d3eaa | 2085 | #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) |
Kojto | 93:e188a91d3eaa | 2086 | #define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN)) |
Kojto | 93:e188a91d3eaa | 2087 | /* Aliases for STM32 F3 compatibility */ |
Kojto | 93:e188a91d3eaa | 2088 | #define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE() |
Kojto | 93:e188a91d3eaa | 2089 | #define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE() |
Kojto | 93:e188a91d3eaa | 2090 | |
Kojto | 93:e188a91d3eaa | 2091 | #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
Kojto | 93:e188a91d3eaa | 2092 | #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
Kojto | 93:e188a91d3eaa | 2093 | #define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN)) |
Kojto | 93:e188a91d3eaa | 2094 | /* Aliases for STM32 F3 compatibility */ |
Kojto | 93:e188a91d3eaa | 2095 | #define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE() |
Kojto | 93:e188a91d3eaa | 2096 | #define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE() |
Kojto | 93:e188a91d3eaa | 2097 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2098 | /* STM32F302xC || STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2099 | |
Kojto | 93:e188a91d3eaa | 2100 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2101 | defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2102 | #define __ADC34_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC34EN)) |
Kojto | 93:e188a91d3eaa | 2103 | |
Kojto | 93:e188a91d3eaa | 2104 | #define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN)) |
Kojto | 93:e188a91d3eaa | 2105 | #endif /* STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2106 | /* STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2107 | |
Kojto | 93:e188a91d3eaa | 2108 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 2109 | #define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN)) |
Kojto | 93:e188a91d3eaa | 2110 | /* Aliases for STM32 F3 compatibility */ |
Kojto | 93:e188a91d3eaa | 2111 | #define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE() |
Kojto | 93:e188a91d3eaa | 2112 | #define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE() |
Kojto | 93:e188a91d3eaa | 2113 | |
Kojto | 93:e188a91d3eaa | 2114 | #define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN)) |
Kojto | 93:e188a91d3eaa | 2115 | /* Aliases for STM32 F3 compatibility */ |
Kojto | 93:e188a91d3eaa | 2116 | #define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE() |
Kojto | 93:e188a91d3eaa | 2117 | #define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE() |
Kojto | 93:e188a91d3eaa | 2118 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 2119 | |
Kojto | 93:e188a91d3eaa | 2120 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2121 | #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN)) |
Kojto | 93:e188a91d3eaa | 2122 | #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN)) |
Kojto | 93:e188a91d3eaa | 2123 | |
Kojto | 93:e188a91d3eaa | 2124 | #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) |
Kojto | 93:e188a91d3eaa | 2125 | #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) |
Kojto | 93:e188a91d3eaa | 2126 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2127 | |
Kojto | 93:e188a91d3eaa | 2128 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 2129 | #define __FMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FMCEN)) |
Kojto | 93:e188a91d3eaa | 2130 | #define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN)) |
Kojto | 93:e188a91d3eaa | 2131 | #define __GPIOH_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN)) |
Kojto | 93:e188a91d3eaa | 2132 | |
Kojto | 93:e188a91d3eaa | 2133 | #define __FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN)) |
Kojto | 93:e188a91d3eaa | 2134 | #define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) |
Kojto | 93:e188a91d3eaa | 2135 | #define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) |
Kojto | 93:e188a91d3eaa | 2136 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2137 | /** |
Kojto | 93:e188a91d3eaa | 2138 | * @} |
Kojto | 93:e188a91d3eaa | 2139 | */ |
Kojto | 93:e188a91d3eaa | 2140 | |
Kojto | 93:e188a91d3eaa | 2141 | /** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable |
Kojto | 93:e188a91d3eaa | 2142 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
Kojto | 93:e188a91d3eaa | 2143 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 93:e188a91d3eaa | 2144 | * is disabled and the application software has to enable this clock before |
Kojto | 93:e188a91d3eaa | 2145 | * using it. |
Kojto | 93:e188a91d3eaa | 2146 | * @{ |
Kojto | 93:e188a91d3eaa | 2147 | */ |
Kojto | 93:e188a91d3eaa | 2148 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 2149 | #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) |
Kojto | 93:e188a91d3eaa | 2150 | #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN)) |
Kojto | 93:e188a91d3eaa | 2151 | #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) |
Kojto | 93:e188a91d3eaa | 2152 | #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN)) |
Kojto | 93:e188a91d3eaa | 2153 | |
Kojto | 93:e188a91d3eaa | 2154 | #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
Kojto | 93:e188a91d3eaa | 2155 | #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
Kojto | 93:e188a91d3eaa | 2156 | #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
Kojto | 93:e188a91d3eaa | 2157 | #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
Kojto | 93:e188a91d3eaa | 2158 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2159 | |
Kojto | 93:e188a91d3eaa | 2160 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2161 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2162 | #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) |
Kojto | 93:e188a91d3eaa | 2163 | #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN)) |
Kojto | 93:e188a91d3eaa | 2164 | #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) |
Kojto | 93:e188a91d3eaa | 2165 | #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN)) |
Kojto | 93:e188a91d3eaa | 2166 | #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN)) |
Kojto | 93:e188a91d3eaa | 2167 | #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN)) |
Kojto | 93:e188a91d3eaa | 2168 | #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) |
Kojto | 93:e188a91d3eaa | 2169 | |
Kojto | 93:e188a91d3eaa | 2170 | #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
Kojto | 93:e188a91d3eaa | 2171 | #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
Kojto | 93:e188a91d3eaa | 2172 | #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
Kojto | 93:e188a91d3eaa | 2173 | #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
Kojto | 93:e188a91d3eaa | 2174 | #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) |
Kojto | 93:e188a91d3eaa | 2175 | #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) |
Kojto | 93:e188a91d3eaa | 2176 | #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
Kojto | 93:e188a91d3eaa | 2177 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2178 | /* STM32F302xC || STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2179 | |
Kojto | 93:e188a91d3eaa | 2180 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 2181 | #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) |
Kojto | 93:e188a91d3eaa | 2182 | #define __DAC2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC2EN)) |
Kojto | 93:e188a91d3eaa | 2183 | |
Kojto | 93:e188a91d3eaa | 2184 | #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
Kojto | 93:e188a91d3eaa | 2185 | #define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) |
Kojto | 93:e188a91d3eaa | 2186 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 2187 | |
Kojto | 93:e188a91d3eaa | 2188 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2189 | #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) |
Kojto | 93:e188a91d3eaa | 2190 | #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN)) |
Kojto | 93:e188a91d3eaa | 2191 | #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN)) |
Kojto | 93:e188a91d3eaa | 2192 | #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN)) |
Kojto | 93:e188a91d3eaa | 2193 | #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN)) |
Kojto | 93:e188a91d3eaa | 2194 | #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN)) |
Kojto | 93:e188a91d3eaa | 2195 | #define __TIM18_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM18EN)) |
Kojto | 93:e188a91d3eaa | 2196 | #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) |
Kojto | 93:e188a91d3eaa | 2197 | #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN)) |
Kojto | 93:e188a91d3eaa | 2198 | #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) |
Kojto | 93:e188a91d3eaa | 2199 | #define __DAC2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC2EN)) |
Kojto | 93:e188a91d3eaa | 2200 | #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN)) |
Kojto | 93:e188a91d3eaa | 2201 | |
Kojto | 93:e188a91d3eaa | 2202 | #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
Kojto | 93:e188a91d3eaa | 2203 | #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) |
Kojto | 93:e188a91d3eaa | 2204 | #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) |
Kojto | 93:e188a91d3eaa | 2205 | #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) |
Kojto | 93:e188a91d3eaa | 2206 | #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) |
Kojto | 93:e188a91d3eaa | 2207 | #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) |
Kojto | 93:e188a91d3eaa | 2208 | #define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN)) |
Kojto | 93:e188a91d3eaa | 2209 | #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) |
Kojto | 93:e188a91d3eaa | 2210 | #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) |
Kojto | 93:e188a91d3eaa | 2211 | #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) |
Kojto | 93:e188a91d3eaa | 2212 | #define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN)) |
Kojto | 93:e188a91d3eaa | 2213 | #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) |
Kojto | 93:e188a91d3eaa | 2214 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2215 | |
Kojto | 93:e188a91d3eaa | 2216 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2217 | defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 2218 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 2219 | defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2220 | #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) |
Kojto | 93:e188a91d3eaa | 2221 | |
Kojto | 93:e188a91d3eaa | 2222 | #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) |
Kojto | 93:e188a91d3eaa | 2223 | #endif /* STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2224 | /* STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 2225 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 2226 | /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2227 | |
Kojto | 93:e188a91d3eaa | 2228 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ |
Kojto | 93:e188a91d3eaa | 2229 | defined(STM32F302xC) || defined(STM32F303xC) || \ |
Kojto | 93:e188a91d3eaa | 2230 | defined(STM32F302x8) || \ |
Kojto | 93:e188a91d3eaa | 2231 | defined(STM32F373xC) |
Kojto | 93:e188a91d3eaa | 2232 | #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) |
Kojto | 93:e188a91d3eaa | 2233 | |
Kojto | 93:e188a91d3eaa | 2234 | #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) |
Kojto | 93:e188a91d3eaa | 2235 | #endif /* STM32F302xE || STM32F303xE || */ |
Kojto | 93:e188a91d3eaa | 2236 | /* STM32F302xC || STM32F303xC || */ |
Kojto | 93:e188a91d3eaa | 2237 | /* STM32F302x8 || */ |
Kojto | 93:e188a91d3eaa | 2238 | /* STM32F373xC */ |
Kojto | 93:e188a91d3eaa | 2239 | |
Kojto | 93:e188a91d3eaa | 2240 | #if !defined(STM32F301x8) |
Kojto | 93:e188a91d3eaa | 2241 | #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN)) |
Kojto | 93:e188a91d3eaa | 2242 | |
Kojto | 93:e188a91d3eaa | 2243 | #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN)) |
Kojto | 93:e188a91d3eaa | 2244 | #endif /* STM32F301x8*/ |
Kojto | 93:e188a91d3eaa | 2245 | |
Kojto | 93:e188a91d3eaa | 2246 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 2247 | #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN)) |
Kojto | 93:e188a91d3eaa | 2248 | |
Kojto | 93:e188a91d3eaa | 2249 | #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) |
Kojto | 93:e188a91d3eaa | 2250 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2251 | /** |
Kojto | 93:e188a91d3eaa | 2252 | * @} |
Kojto | 93:e188a91d3eaa | 2253 | */ |
Kojto | 93:e188a91d3eaa | 2254 | |
Kojto | 93:e188a91d3eaa | 2255 | /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable |
Kojto | 93:e188a91d3eaa | 2256 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
Kojto | 93:e188a91d3eaa | 2257 | * @note After reset, the peripheral clock (used for registers read/write access) |
Kojto | 93:e188a91d3eaa | 2258 | * is disabled and the application software has to enable this clock before |
Kojto | 93:e188a91d3eaa | 2259 | * using it. |
Kojto | 93:e188a91d3eaa | 2260 | * @{ |
Kojto | 93:e188a91d3eaa | 2261 | */ |
Kojto | 93:e188a91d3eaa | 2262 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2263 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2264 | #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) |
Kojto | 93:e188a91d3eaa | 2265 | |
Kojto | 93:e188a91d3eaa | 2266 | #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
Kojto | 93:e188a91d3eaa | 2267 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2268 | /* STM32F302xC || STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2269 | |
Kojto | 93:e188a91d3eaa | 2270 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2271 | defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2272 | #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN)) |
Kojto | 93:e188a91d3eaa | 2273 | |
Kojto | 93:e188a91d3eaa | 2274 | #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) |
Kojto | 93:e188a91d3eaa | 2275 | #endif /* STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2276 | /* STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2277 | |
Kojto | 93:e188a91d3eaa | 2278 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 2279 | #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) |
Kojto | 93:e188a91d3eaa | 2280 | |
Kojto | 93:e188a91d3eaa | 2281 | #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
Kojto | 93:e188a91d3eaa | 2282 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 2283 | |
Kojto | 93:e188a91d3eaa | 2284 | #if defined(STM32F334x8) |
Kojto | 93:e188a91d3eaa | 2285 | #define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_HRTIM1EN)) |
Kojto | 93:e188a91d3eaa | 2286 | |
Kojto | 93:e188a91d3eaa | 2287 | #define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN)) |
Kojto | 93:e188a91d3eaa | 2288 | #endif /* STM32F334x8 */ |
Kojto | 93:e188a91d3eaa | 2289 | |
Kojto | 93:e188a91d3eaa | 2290 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2291 | #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) |
Kojto | 93:e188a91d3eaa | 2292 | #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) |
Kojto | 93:e188a91d3eaa | 2293 | #define __TIM19_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM19EN)) |
Kojto | 93:e188a91d3eaa | 2294 | #define __SDADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC1EN)) |
Kojto | 93:e188a91d3eaa | 2295 | #define __SDADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC2EN)) |
Kojto | 93:e188a91d3eaa | 2296 | #define __SDADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC3EN)) |
Kojto | 93:e188a91d3eaa | 2297 | |
Kojto | 93:e188a91d3eaa | 2298 | #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
Kojto | 93:e188a91d3eaa | 2299 | #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
Kojto | 93:e188a91d3eaa | 2300 | #define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN)) |
Kojto | 93:e188a91d3eaa | 2301 | #define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN)) |
Kojto | 93:e188a91d3eaa | 2302 | #define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN)) |
Kojto | 93:e188a91d3eaa | 2303 | #define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN)) |
Kojto | 93:e188a91d3eaa | 2304 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2305 | |
Kojto | 93:e188a91d3eaa | 2306 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2307 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 2308 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 2309 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 2310 | #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN)) |
Kojto | 93:e188a91d3eaa | 2311 | |
Kojto | 93:e188a91d3eaa | 2312 | #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
Kojto | 93:e188a91d3eaa | 2313 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2314 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 2315 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 2316 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2317 | |
Kojto | 93:e188a91d3eaa | 2318 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 2319 | #define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN)) |
Kojto | 93:e188a91d3eaa | 2320 | |
Kojto | 93:e188a91d3eaa | 2321 | #define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) |
Kojto | 93:e188a91d3eaa | 2322 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2323 | |
Kojto | 93:e188a91d3eaa | 2324 | #if defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 2325 | #define __TIM20_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM20EN)) |
Kojto | 93:e188a91d3eaa | 2326 | |
Kojto | 93:e188a91d3eaa | 2327 | #define __TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN)) |
Kojto | 93:e188a91d3eaa | 2328 | #endif /* STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2329 | |
Kojto | 93:e188a91d3eaa | 2330 | /** |
Kojto | 93:e188a91d3eaa | 2331 | * @} |
Kojto | 93:e188a91d3eaa | 2332 | */ |
Kojto | 93:e188a91d3eaa | 2333 | |
Kojto | 93:e188a91d3eaa | 2334 | /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset |
Kojto | 93:e188a91d3eaa | 2335 | * @brief Force or release AHB peripheral reset. |
Kojto | 93:e188a91d3eaa | 2336 | * @{ |
Kojto | 93:e188a91d3eaa | 2337 | */ |
Kojto | 93:e188a91d3eaa | 2338 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 2339 | #define __ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST)) |
Kojto | 93:e188a91d3eaa | 2340 | |
Kojto | 93:e188a91d3eaa | 2341 | #define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST)) |
Kojto | 93:e188a91d3eaa | 2342 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2343 | |
Kojto | 93:e188a91d3eaa | 2344 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2345 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2346 | #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
Kojto | 93:e188a91d3eaa | 2347 | #define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST)) |
Kojto | 93:e188a91d3eaa | 2348 | /* Aliases for STM32 F3 compatibility */ |
Kojto | 93:e188a91d3eaa | 2349 | #define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET() |
Kojto | 93:e188a91d3eaa | 2350 | #define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET() |
Kojto | 93:e188a91d3eaa | 2351 | |
Kojto | 93:e188a91d3eaa | 2352 | #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
Kojto | 93:e188a91d3eaa | 2353 | #define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST)) |
Kojto | 93:e188a91d3eaa | 2354 | /* Aliases for STM32 F3 compatibility */ |
Kojto | 93:e188a91d3eaa | 2355 | #define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET() |
Kojto | 93:e188a91d3eaa | 2356 | #define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET() |
Kojto | 93:e188a91d3eaa | 2357 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2358 | /* STM32F302xC || STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2359 | |
Kojto | 93:e188a91d3eaa | 2360 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2361 | defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2362 | #define __ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST)) |
Kojto | 93:e188a91d3eaa | 2363 | |
Kojto | 93:e188a91d3eaa | 2364 | #define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST)) |
Kojto | 93:e188a91d3eaa | 2365 | #endif /* STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2366 | /* STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2367 | |
Kojto | 93:e188a91d3eaa | 2368 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 2369 | #define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST)) |
Kojto | 93:e188a91d3eaa | 2370 | /* Aliases for STM32 F3 compatibility */ |
Kojto | 93:e188a91d3eaa | 2371 | #define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET() |
Kojto | 93:e188a91d3eaa | 2372 | #define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET() |
Kojto | 93:e188a91d3eaa | 2373 | |
Kojto | 93:e188a91d3eaa | 2374 | #define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST)) |
Kojto | 93:e188a91d3eaa | 2375 | /* Aliases for STM32 F3 compatibility */ |
Kojto | 93:e188a91d3eaa | 2376 | #define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET() |
Kojto | 93:e188a91d3eaa | 2377 | #define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET() |
Kojto | 93:e188a91d3eaa | 2378 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 2379 | |
Kojto | 93:e188a91d3eaa | 2380 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2381 | #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) |
Kojto | 93:e188a91d3eaa | 2382 | |
Kojto | 93:e188a91d3eaa | 2383 | #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) |
Kojto | 93:e188a91d3eaa | 2384 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2385 | |
Kojto | 93:e188a91d3eaa | 2386 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 2387 | #define __FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST)) |
Kojto | 93:e188a91d3eaa | 2388 | #define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) |
Kojto | 93:e188a91d3eaa | 2389 | #define __GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) |
Kojto | 93:e188a91d3eaa | 2390 | |
Kojto | 93:e188a91d3eaa | 2391 | #define __FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST)) |
Kojto | 93:e188a91d3eaa | 2392 | #define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) |
Kojto | 93:e188a91d3eaa | 2393 | #define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) |
Kojto | 93:e188a91d3eaa | 2394 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2395 | /** |
Kojto | 93:e188a91d3eaa | 2396 | * @} |
Kojto | 93:e188a91d3eaa | 2397 | */ |
Kojto | 93:e188a91d3eaa | 2398 | |
Kojto | 93:e188a91d3eaa | 2399 | /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset |
Kojto | 93:e188a91d3eaa | 2400 | * @brief Force or release APB1 peripheral reset. |
Kojto | 93:e188a91d3eaa | 2401 | * @{ |
Kojto | 93:e188a91d3eaa | 2402 | */ |
Kojto | 93:e188a91d3eaa | 2403 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 2404 | #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
Kojto | 93:e188a91d3eaa | 2405 | #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
Kojto | 93:e188a91d3eaa | 2406 | #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
Kojto | 93:e188a91d3eaa | 2407 | #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) |
Kojto | 93:e188a91d3eaa | 2408 | |
Kojto | 93:e188a91d3eaa | 2409 | #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
Kojto | 93:e188a91d3eaa | 2410 | #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
Kojto | 93:e188a91d3eaa | 2411 | #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
Kojto | 93:e188a91d3eaa | 2412 | #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) |
Kojto | 93:e188a91d3eaa | 2413 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2414 | |
Kojto | 93:e188a91d3eaa | 2415 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2416 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2417 | #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
Kojto | 93:e188a91d3eaa | 2418 | #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) |
Kojto | 93:e188a91d3eaa | 2419 | #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
Kojto | 93:e188a91d3eaa | 2420 | #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
Kojto | 93:e188a91d3eaa | 2421 | #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) |
Kojto | 93:e188a91d3eaa | 2422 | #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) |
Kojto | 93:e188a91d3eaa | 2423 | #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
Kojto | 93:e188a91d3eaa | 2424 | |
Kojto | 93:e188a91d3eaa | 2425 | #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
Kojto | 93:e188a91d3eaa | 2426 | #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) |
Kojto | 93:e188a91d3eaa | 2427 | #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
Kojto | 93:e188a91d3eaa | 2428 | #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
Kojto | 93:e188a91d3eaa | 2429 | #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) |
Kojto | 93:e188a91d3eaa | 2430 | #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) |
Kojto | 93:e188a91d3eaa | 2431 | #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
Kojto | 93:e188a91d3eaa | 2432 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2433 | /* STM32F302xC || STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2434 | |
Kojto | 93:e188a91d3eaa | 2435 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 2436 | #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
Kojto | 93:e188a91d3eaa | 2437 | #define __DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST)) |
Kojto | 93:e188a91d3eaa | 2438 | |
Kojto | 93:e188a91d3eaa | 2439 | #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
Kojto | 93:e188a91d3eaa | 2440 | #define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST)) |
Kojto | 93:e188a91d3eaa | 2441 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 2442 | |
Kojto | 93:e188a91d3eaa | 2443 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2444 | #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
Kojto | 93:e188a91d3eaa | 2445 | #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) |
Kojto | 93:e188a91d3eaa | 2446 | #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) |
Kojto | 93:e188a91d3eaa | 2447 | #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) |
Kojto | 93:e188a91d3eaa | 2448 | #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) |
Kojto | 93:e188a91d3eaa | 2449 | #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) |
Kojto | 93:e188a91d3eaa | 2450 | #define __TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST)) |
Kojto | 93:e188a91d3eaa | 2451 | #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) |
Kojto | 93:e188a91d3eaa | 2452 | #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) |
Kojto | 93:e188a91d3eaa | 2453 | #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) |
Kojto | 93:e188a91d3eaa | 2454 | #define __DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST)) |
Kojto | 93:e188a91d3eaa | 2455 | #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) |
Kojto | 93:e188a91d3eaa | 2456 | |
Kojto | 93:e188a91d3eaa | 2457 | #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
Kojto | 93:e188a91d3eaa | 2458 | #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) |
Kojto | 93:e188a91d3eaa | 2459 | #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) |
Kojto | 93:e188a91d3eaa | 2460 | #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) |
Kojto | 93:e188a91d3eaa | 2461 | #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) |
Kojto | 93:e188a91d3eaa | 2462 | #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) |
Kojto | 93:e188a91d3eaa | 2463 | #define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST)) |
Kojto | 93:e188a91d3eaa | 2464 | #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) |
Kojto | 93:e188a91d3eaa | 2465 | #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) |
Kojto | 93:e188a91d3eaa | 2466 | #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) |
Kojto | 93:e188a91d3eaa | 2467 | #define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST)) |
Kojto | 93:e188a91d3eaa | 2468 | #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) |
Kojto | 93:e188a91d3eaa | 2469 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2470 | |
Kojto | 93:e188a91d3eaa | 2471 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2472 | defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 2473 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 2474 | defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2475 | #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) |
Kojto | 93:e188a91d3eaa | 2476 | |
Kojto | 93:e188a91d3eaa | 2477 | #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) |
Kojto | 93:e188a91d3eaa | 2478 | #endif /* STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2479 | /* STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 2480 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 2481 | /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2482 | |
Kojto | 93:e188a91d3eaa | 2483 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ |
Kojto | 93:e188a91d3eaa | 2484 | defined(STM32F302xC) || defined(STM32F303xC) || \ |
Kojto | 93:e188a91d3eaa | 2485 | defined(STM32F302x8) || \ |
Kojto | 93:e188a91d3eaa | 2486 | defined(STM32F373xC) |
Kojto | 93:e188a91d3eaa | 2487 | #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) |
Kojto | 93:e188a91d3eaa | 2488 | |
Kojto | 93:e188a91d3eaa | 2489 | #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) |
Kojto | 93:e188a91d3eaa | 2490 | #endif /* STM32F302xE || STM32F303xE || */ |
Kojto | 93:e188a91d3eaa | 2491 | /* STM32F302xC || STM32F303xC || */ |
Kojto | 93:e188a91d3eaa | 2492 | /* STM32F302x8 || */ |
Kojto | 93:e188a91d3eaa | 2493 | /* STM32F373xC */ |
Kojto | 93:e188a91d3eaa | 2494 | |
Kojto | 93:e188a91d3eaa | 2495 | #if !defined(STM32F301x8) |
Kojto | 93:e188a91d3eaa | 2496 | #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST)) |
Kojto | 93:e188a91d3eaa | 2497 | |
Kojto | 93:e188a91d3eaa | 2498 | #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST)) |
Kojto | 93:e188a91d3eaa | 2499 | #endif /* STM32F301x8*/ |
Kojto | 93:e188a91d3eaa | 2500 | |
Kojto | 93:e188a91d3eaa | 2501 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 2502 | #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) |
Kojto | 93:e188a91d3eaa | 2503 | |
Kojto | 93:e188a91d3eaa | 2504 | #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) |
Kojto | 93:e188a91d3eaa | 2505 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2506 | /** |
Kojto | 93:e188a91d3eaa | 2507 | * @} |
Kojto | 93:e188a91d3eaa | 2508 | */ |
Kojto | 93:e188a91d3eaa | 2509 | |
Kojto | 93:e188a91d3eaa | 2510 | /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset |
Kojto | 93:e188a91d3eaa | 2511 | * @brief Force or release APB2 peripheral reset. |
Kojto | 93:e188a91d3eaa | 2512 | * @{ |
Kojto | 93:e188a91d3eaa | 2513 | */ |
Kojto | 93:e188a91d3eaa | 2514 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2515 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2516 | #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
Kojto | 93:e188a91d3eaa | 2517 | |
Kojto | 93:e188a91d3eaa | 2518 | #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
Kojto | 93:e188a91d3eaa | 2519 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2520 | /* STM32F302xC || STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2521 | |
Kojto | 93:e188a91d3eaa | 2522 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2523 | defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2524 | #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) |
Kojto | 93:e188a91d3eaa | 2525 | |
Kojto | 93:e188a91d3eaa | 2526 | #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) |
Kojto | 93:e188a91d3eaa | 2527 | #endif /* STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2528 | /* STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2529 | |
Kojto | 93:e188a91d3eaa | 2530 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 2531 | #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
Kojto | 93:e188a91d3eaa | 2532 | |
Kojto | 93:e188a91d3eaa | 2533 | #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
Kojto | 93:e188a91d3eaa | 2534 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 2535 | |
Kojto | 93:e188a91d3eaa | 2536 | #if defined(STM32F334x8) |
Kojto | 93:e188a91d3eaa | 2537 | #define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST)) |
Kojto | 93:e188a91d3eaa | 2538 | |
Kojto | 93:e188a91d3eaa | 2539 | #define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST)) |
Kojto | 93:e188a91d3eaa | 2540 | #endif /* STM32F334x8 */ |
Kojto | 93:e188a91d3eaa | 2541 | |
Kojto | 93:e188a91d3eaa | 2542 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 2543 | #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) |
Kojto | 93:e188a91d3eaa | 2544 | #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
Kojto | 93:e188a91d3eaa | 2545 | #define __TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST)) |
Kojto | 93:e188a91d3eaa | 2546 | #define __SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST)) |
Kojto | 93:e188a91d3eaa | 2547 | #define __SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST)) |
Kojto | 93:e188a91d3eaa | 2548 | #define __SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST)) |
Kojto | 93:e188a91d3eaa | 2549 | |
Kojto | 93:e188a91d3eaa | 2550 | #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) |
Kojto | 93:e188a91d3eaa | 2551 | #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
Kojto | 93:e188a91d3eaa | 2552 | #define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST)) |
Kojto | 93:e188a91d3eaa | 2553 | #define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST)) |
Kojto | 93:e188a91d3eaa | 2554 | #define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST)) |
Kojto | 93:e188a91d3eaa | 2555 | #define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST)) |
Kojto | 93:e188a91d3eaa | 2556 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 2557 | |
Kojto | 93:e188a91d3eaa | 2558 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2559 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \ |
Kojto | 93:e188a91d3eaa | 2560 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 2561 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 2562 | #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
Kojto | 93:e188a91d3eaa | 2563 | |
Kojto | 93:e188a91d3eaa | 2564 | #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
Kojto | 93:e188a91d3eaa | 2565 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2566 | /* STM32F302xC || STM32F303xC || STM32F358xx || */ |
Kojto | 93:e188a91d3eaa | 2567 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 2568 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2569 | |
Kojto | 93:e188a91d3eaa | 2570 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 2571 | #define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) |
Kojto | 93:e188a91d3eaa | 2572 | |
Kojto | 93:e188a91d3eaa | 2573 | #define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) |
Kojto | 93:e188a91d3eaa | 2574 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2575 | |
Kojto | 93:e188a91d3eaa | 2576 | #if defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 2577 | #define __TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST)) |
Kojto | 93:e188a91d3eaa | 2578 | |
Kojto | 93:e188a91d3eaa | 2579 | #define __TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST)) |
Kojto | 93:e188a91d3eaa | 2580 | #endif /* STM32F303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 2581 | |
Kojto | 93:e188a91d3eaa | 2582 | /** |
Kojto | 93:e188a91d3eaa | 2583 | * @} |
Kojto | 93:e188a91d3eaa | 2584 | */ |
Kojto | 93:e188a91d3eaa | 2585 | |
Kojto | 93:e188a91d3eaa | 2586 | #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 2587 | /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config |
Kojto | 93:e188a91d3eaa | 2588 | * @{ |
Kojto | 93:e188a91d3eaa | 2589 | */ |
Kojto | 93:e188a91d3eaa | 2590 | |
Kojto | 93:e188a91d3eaa | 2591 | /** @brief Macro to configure the I2C2 clock (I2C2CLK). |
Kojto | 93:e188a91d3eaa | 2592 | * @param __I2C2CLKSource__: specifies the I2C2 clock source. |
Kojto | 93:e188a91d3eaa | 2593 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2594 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 2595 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 2596 | */ |
Kojto | 93:e188a91d3eaa | 2597 | #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2598 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2599 | |
Kojto | 93:e188a91d3eaa | 2600 | /** @brief Macro to get the I2C2 clock source. |
Kojto | 93:e188a91d3eaa | 2601 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2602 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 2603 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 2604 | */ |
Kojto | 93:e188a91d3eaa | 2605 | #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) |
Kojto | 93:e188a91d3eaa | 2606 | |
Kojto | 93:e188a91d3eaa | 2607 | /** @brief Macro to configure the I2C3 clock (I2C3CLK). |
Kojto | 93:e188a91d3eaa | 2608 | * @param __I2C3CLKSource__: specifies the I2C3 clock source. |
Kojto | 93:e188a91d3eaa | 2609 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2610 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
Kojto | 93:e188a91d3eaa | 2611 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
Kojto | 93:e188a91d3eaa | 2612 | */ |
Kojto | 93:e188a91d3eaa | 2613 | #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2614 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2615 | |
Kojto | 93:e188a91d3eaa | 2616 | /** @brief Macro to get the I2C3 clock source. |
Kojto | 93:e188a91d3eaa | 2617 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2618 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
Kojto | 93:e188a91d3eaa | 2619 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
Kojto | 93:e188a91d3eaa | 2620 | */ |
Kojto | 93:e188a91d3eaa | 2621 | #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW))) |
Kojto | 93:e188a91d3eaa | 2622 | |
Kojto | 93:e188a91d3eaa | 2623 | /** |
Kojto | 93:e188a91d3eaa | 2624 | * @} |
Kojto | 93:e188a91d3eaa | 2625 | */ |
Kojto | 93:e188a91d3eaa | 2626 | |
Kojto | 93:e188a91d3eaa | 2627 | /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config |
Kojto | 93:e188a91d3eaa | 2628 | * @{ |
Kojto | 93:e188a91d3eaa | 2629 | */ |
Kojto | 93:e188a91d3eaa | 2630 | /** @brief Macro to configure the TIM1 clock (TIM1CLK). |
Kojto | 93:e188a91d3eaa | 2631 | * @param __TIM1CLKSource__: specifies the TIM1 clock source. |
Kojto | 93:e188a91d3eaa | 2632 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2633 | * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 2634 | * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 2635 | */ |
Kojto | 93:e188a91d3eaa | 2636 | #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2637 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2638 | |
Kojto | 93:e188a91d3eaa | 2639 | /** @brief Macro to get the TIM1 clock (TIM1CLK). |
Kojto | 93:e188a91d3eaa | 2640 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2641 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2642 | * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 2643 | * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 2644 | */ |
Kojto | 93:e188a91d3eaa | 2645 | #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) |
Kojto | 93:e188a91d3eaa | 2646 | |
Kojto | 93:e188a91d3eaa | 2647 | /** @brief Macro to configure the TIM15 clock (TIM15CLK). |
Kojto | 93:e188a91d3eaa | 2648 | * @param __TIM15CLKSource__: specifies the TIM15 clock source. |
Kojto | 93:e188a91d3eaa | 2649 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2650 | * @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock |
Kojto | 93:e188a91d3eaa | 2651 | * @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock |
Kojto | 93:e188a91d3eaa | 2652 | */ |
Kojto | 93:e188a91d3eaa | 2653 | #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2654 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2655 | |
Kojto | 93:e188a91d3eaa | 2656 | /** @brief Macro to get the TIM15 clock (TIM15CLK). |
Kojto | 93:e188a91d3eaa | 2657 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2658 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2659 | * @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock |
Kojto | 93:e188a91d3eaa | 2660 | * @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock |
Kojto | 93:e188a91d3eaa | 2661 | */ |
Kojto | 93:e188a91d3eaa | 2662 | #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW))) |
Kojto | 93:e188a91d3eaa | 2663 | |
Kojto | 93:e188a91d3eaa | 2664 | /** @brief Macro to configure the TIM16 clock (TIM16CLK). |
Kojto | 93:e188a91d3eaa | 2665 | * @param __TIM16CLKSource__: specifies the TIM16 clock source. |
Kojto | 93:e188a91d3eaa | 2666 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2667 | * @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock |
Kojto | 93:e188a91d3eaa | 2668 | * @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock |
Kojto | 93:e188a91d3eaa | 2669 | */ |
Kojto | 93:e188a91d3eaa | 2670 | #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2671 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2672 | |
Kojto | 93:e188a91d3eaa | 2673 | /** @brief Macro to get the TIM16 clock (TIM16CLK). |
Kojto | 93:e188a91d3eaa | 2674 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2675 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2676 | * @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock |
Kojto | 93:e188a91d3eaa | 2677 | * @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock |
Kojto | 93:e188a91d3eaa | 2678 | */ |
Kojto | 93:e188a91d3eaa | 2679 | #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW))) |
Kojto | 93:e188a91d3eaa | 2680 | |
Kojto | 93:e188a91d3eaa | 2681 | /** @brief Macro to configure the TIM17 clock (TIM17CLK). |
Kojto | 93:e188a91d3eaa | 2682 | * @param __TIM17CLKSource__: specifies the TIM17 clock source. |
Kojto | 93:e188a91d3eaa | 2683 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2684 | * @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock |
Kojto | 93:e188a91d3eaa | 2685 | * @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock |
Kojto | 93:e188a91d3eaa | 2686 | */ |
Kojto | 93:e188a91d3eaa | 2687 | #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2688 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2689 | |
Kojto | 93:e188a91d3eaa | 2690 | /** @brief Macro to get the TIM17 clock (TIM17CLK). |
Kojto | 93:e188a91d3eaa | 2691 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2692 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2693 | * @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock |
Kojto | 93:e188a91d3eaa | 2694 | * @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock |
Kojto | 93:e188a91d3eaa | 2695 | */ |
Kojto | 93:e188a91d3eaa | 2696 | #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW))) |
Kojto | 93:e188a91d3eaa | 2697 | |
Kojto | 93:e188a91d3eaa | 2698 | /** |
Kojto | 93:e188a91d3eaa | 2699 | * @} |
Kojto | 93:e188a91d3eaa | 2700 | */ |
Kojto | 93:e188a91d3eaa | 2701 | |
Kojto | 93:e188a91d3eaa | 2702 | /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config |
Kojto | 93:e188a91d3eaa | 2703 | * @{ |
Kojto | 93:e188a91d3eaa | 2704 | */ |
Kojto | 93:e188a91d3eaa | 2705 | /** @brief Macro to configure the I2S clock source (I2SCLK). |
Kojto | 93:e188a91d3eaa | 2706 | * @note This function must be called before enabling the I2S APB clock. |
Kojto | 93:e188a91d3eaa | 2707 | * @param __I2SCLKSource__: specifies the I2S clock source. |
Kojto | 93:e188a91d3eaa | 2708 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2709 | * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source |
Kojto | 93:e188a91d3eaa | 2710 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin |
Kojto | 93:e188a91d3eaa | 2711 | * used as I2S clock source |
Kojto | 93:e188a91d3eaa | 2712 | */ |
Kojto | 93:e188a91d3eaa | 2713 | #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2714 | MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__)) |
Kojto | 93:e188a91d3eaa | 2715 | |
Kojto | 93:e188a91d3eaa | 2716 | /** @brief Macro to get the I2S clock source (I2SCLK). |
Kojto | 93:e188a91d3eaa | 2717 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2718 | * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source |
Kojto | 93:e188a91d3eaa | 2719 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin |
Kojto | 93:e188a91d3eaa | 2720 | * used as I2S clock source |
Kojto | 93:e188a91d3eaa | 2721 | */ |
Kojto | 93:e188a91d3eaa | 2722 | #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) |
Kojto | 93:e188a91d3eaa | 2723 | /** |
Kojto | 93:e188a91d3eaa | 2724 | * @} |
Kojto | 93:e188a91d3eaa | 2725 | */ |
Kojto | 93:e188a91d3eaa | 2726 | |
Kojto | 93:e188a91d3eaa | 2727 | /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config |
Kojto | 93:e188a91d3eaa | 2728 | * @{ |
Kojto | 93:e188a91d3eaa | 2729 | */ |
Kojto | 93:e188a91d3eaa | 2730 | |
Kojto | 93:e188a91d3eaa | 2731 | /** @brief Macro to configure the ADC1 clock (ADC1CLK). |
Kojto | 93:e188a91d3eaa | 2732 | * @param __ADC1CLKSource__: specifies the ADC1 clock source. |
Kojto | 93:e188a91d3eaa | 2733 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2734 | * @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock |
Kojto | 93:e188a91d3eaa | 2735 | * @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2736 | * @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2737 | * @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2738 | * @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2739 | * @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2740 | * @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2741 | * @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2742 | * @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2743 | * @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2744 | * @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2745 | * @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2746 | * @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2747 | */ |
Kojto | 93:e188a91d3eaa | 2748 | #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2749 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2750 | |
Kojto | 93:e188a91d3eaa | 2751 | /** @brief Macro to get the ADC1 clock |
Kojto | 93:e188a91d3eaa | 2752 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2753 | * @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock |
Kojto | 93:e188a91d3eaa | 2754 | * @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2755 | * @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2756 | * @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2757 | * @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2758 | * @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2759 | * @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2760 | * @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2761 | * @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2762 | * @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2763 | * @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2764 | * @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2765 | * @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 2766 | */ |
Kojto | 93:e188a91d3eaa | 2767 | #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES))) |
Kojto | 93:e188a91d3eaa | 2768 | /** |
Kojto | 93:e188a91d3eaa | 2769 | * @} |
Kojto | 93:e188a91d3eaa | 2770 | */ |
Kojto | 93:e188a91d3eaa | 2771 | |
Kojto | 93:e188a91d3eaa | 2772 | #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 2773 | |
Kojto | 93:e188a91d3eaa | 2774 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2775 | defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2776 | /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config |
Kojto | 93:e188a91d3eaa | 2777 | * @{ |
Kojto | 93:e188a91d3eaa | 2778 | */ |
Kojto | 93:e188a91d3eaa | 2779 | |
Kojto | 93:e188a91d3eaa | 2780 | /** @brief Macro to configure the I2C2 clock (I2C2CLK). |
Kojto | 93:e188a91d3eaa | 2781 | * @param __I2C2CLKSource__: specifies the I2C2 clock source. |
Kojto | 93:e188a91d3eaa | 2782 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2783 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 2784 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 2785 | */ |
Kojto | 93:e188a91d3eaa | 2786 | #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2787 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2788 | |
Kojto | 93:e188a91d3eaa | 2789 | /** @brief Macro to get the I2C2 clock source. |
Kojto | 93:e188a91d3eaa | 2790 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2791 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 2792 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 2793 | */ |
Kojto | 93:e188a91d3eaa | 2794 | #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) |
Kojto | 93:e188a91d3eaa | 2795 | /** |
Kojto | 93:e188a91d3eaa | 2796 | * @} |
Kojto | 93:e188a91d3eaa | 2797 | */ |
Kojto | 93:e188a91d3eaa | 2798 | |
Kojto | 93:e188a91d3eaa | 2799 | /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config |
Kojto | 93:e188a91d3eaa | 2800 | * @{ |
Kojto | 93:e188a91d3eaa | 2801 | */ |
Kojto | 93:e188a91d3eaa | 2802 | |
Kojto | 93:e188a91d3eaa | 2803 | /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK). |
Kojto | 93:e188a91d3eaa | 2804 | * @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source. |
Kojto | 93:e188a91d3eaa | 2805 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2806 | * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock |
Kojto | 93:e188a91d3eaa | 2807 | * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2808 | * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2809 | * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2810 | * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2811 | * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2812 | * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2813 | * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2814 | * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2815 | * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2816 | * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2817 | * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2818 | * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2819 | */ |
Kojto | 93:e188a91d3eaa | 2820 | #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2821 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2822 | |
Kojto | 93:e188a91d3eaa | 2823 | /** @brief Macro to get the ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2824 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2825 | * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock |
Kojto | 93:e188a91d3eaa | 2826 | * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2827 | * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2828 | * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2829 | * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2830 | * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2831 | * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2832 | * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2833 | * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2834 | * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2835 | * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2836 | * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2837 | * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 2838 | */ |
Kojto | 93:e188a91d3eaa | 2839 | #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12))) |
Kojto | 93:e188a91d3eaa | 2840 | /** |
Kojto | 93:e188a91d3eaa | 2841 | * @} |
Kojto | 93:e188a91d3eaa | 2842 | */ |
Kojto | 93:e188a91d3eaa | 2843 | |
Kojto | 93:e188a91d3eaa | 2844 | /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config |
Kojto | 93:e188a91d3eaa | 2845 | * @{ |
Kojto | 93:e188a91d3eaa | 2846 | */ |
Kojto | 93:e188a91d3eaa | 2847 | |
Kojto | 93:e188a91d3eaa | 2848 | /** @brief Macro to configure the TIM1 clock (TIM1CLK). |
Kojto | 93:e188a91d3eaa | 2849 | * @param __TIM1CLKSource__: specifies the TIM1 clock source. |
Kojto | 93:e188a91d3eaa | 2850 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2851 | * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 2852 | * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 2853 | */ |
Kojto | 93:e188a91d3eaa | 2854 | #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2855 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2856 | |
Kojto | 93:e188a91d3eaa | 2857 | /** @brief Macro to get the TIM1 clock (TIM1CLK). |
Kojto | 93:e188a91d3eaa | 2858 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2859 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2860 | * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 2861 | * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 2862 | */ |
Kojto | 93:e188a91d3eaa | 2863 | #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) |
Kojto | 93:e188a91d3eaa | 2864 | /** |
Kojto | 93:e188a91d3eaa | 2865 | * @} |
Kojto | 93:e188a91d3eaa | 2866 | */ |
Kojto | 93:e188a91d3eaa | 2867 | |
Kojto | 93:e188a91d3eaa | 2868 | /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config |
Kojto | 93:e188a91d3eaa | 2869 | * @{ |
Kojto | 93:e188a91d3eaa | 2870 | */ |
Kojto | 93:e188a91d3eaa | 2871 | |
Kojto | 93:e188a91d3eaa | 2872 | /** @brief Macro to configure the I2S clock source (I2SCLK). |
Kojto | 93:e188a91d3eaa | 2873 | * @note This function must be called before enabling the I2S APB clock. |
Kojto | 93:e188a91d3eaa | 2874 | * @param __I2SCLKSource__: specifies the I2S clock source. |
Kojto | 93:e188a91d3eaa | 2875 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2876 | * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source |
Kojto | 93:e188a91d3eaa | 2877 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin |
Kojto | 93:e188a91d3eaa | 2878 | * used as I2S clock source |
Kojto | 93:e188a91d3eaa | 2879 | */ |
Kojto | 93:e188a91d3eaa | 2880 | #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2881 | MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__)) |
Kojto | 93:e188a91d3eaa | 2882 | |
Kojto | 93:e188a91d3eaa | 2883 | /** @brief Macro to get the I2S clock source (I2SCLK). |
Kojto | 93:e188a91d3eaa | 2884 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2885 | * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source |
Kojto | 93:e188a91d3eaa | 2886 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin |
Kojto | 93:e188a91d3eaa | 2887 | * used as I2S clock source |
Kojto | 93:e188a91d3eaa | 2888 | */ |
Kojto | 93:e188a91d3eaa | 2889 | #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))) |
Kojto | 93:e188a91d3eaa | 2890 | /** |
Kojto | 93:e188a91d3eaa | 2891 | * @} |
Kojto | 93:e188a91d3eaa | 2892 | */ |
Kojto | 93:e188a91d3eaa | 2893 | |
Kojto | 93:e188a91d3eaa | 2894 | /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config |
Kojto | 93:e188a91d3eaa | 2895 | * @{ |
Kojto | 93:e188a91d3eaa | 2896 | */ |
Kojto | 93:e188a91d3eaa | 2897 | |
Kojto | 93:e188a91d3eaa | 2898 | /** @brief Macro to configure the UART4 clock (UART4CLK). |
Kojto | 93:e188a91d3eaa | 2899 | * @param __UART4CLKSource__: specifies the UART4 clock source. |
Kojto | 93:e188a91d3eaa | 2900 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2901 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
Kojto | 93:e188a91d3eaa | 2902 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
Kojto | 93:e188a91d3eaa | 2903 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
Kojto | 93:e188a91d3eaa | 2904 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
Kojto | 93:e188a91d3eaa | 2905 | */ |
Kojto | 93:e188a91d3eaa | 2906 | #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2907 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2908 | |
Kojto | 93:e188a91d3eaa | 2909 | /** @brief Macro to get the UART4 clock source. |
Kojto | 93:e188a91d3eaa | 2910 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2911 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
Kojto | 93:e188a91d3eaa | 2912 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
Kojto | 93:e188a91d3eaa | 2913 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
Kojto | 93:e188a91d3eaa | 2914 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
Kojto | 93:e188a91d3eaa | 2915 | */ |
Kojto | 93:e188a91d3eaa | 2916 | #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW))) |
Kojto | 93:e188a91d3eaa | 2917 | |
Kojto | 93:e188a91d3eaa | 2918 | /** @brief Macro to configure the UART5 clock (UART5CLK). |
Kojto | 93:e188a91d3eaa | 2919 | * @param __UART5CLKSource__: specifies the UART5 clock source. |
Kojto | 93:e188a91d3eaa | 2920 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2921 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
Kojto | 93:e188a91d3eaa | 2922 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
Kojto | 93:e188a91d3eaa | 2923 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
Kojto | 93:e188a91d3eaa | 2924 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
Kojto | 93:e188a91d3eaa | 2925 | */ |
Kojto | 93:e188a91d3eaa | 2926 | #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2927 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2928 | |
Kojto | 93:e188a91d3eaa | 2929 | /** @brief Macro to get the UART5 clock source. |
Kojto | 93:e188a91d3eaa | 2930 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2931 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
Kojto | 93:e188a91d3eaa | 2932 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
Kojto | 93:e188a91d3eaa | 2933 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
Kojto | 93:e188a91d3eaa | 2934 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
Kojto | 93:e188a91d3eaa | 2935 | */ |
Kojto | 93:e188a91d3eaa | 2936 | #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW))) |
Kojto | 93:e188a91d3eaa | 2937 | /** |
Kojto | 93:e188a91d3eaa | 2938 | * @} |
Kojto | 93:e188a91d3eaa | 2939 | */ |
Kojto | 93:e188a91d3eaa | 2940 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 2941 | /* STM32F302xC || STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 2942 | |
Kojto | 93:e188a91d3eaa | 2943 | #if defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 2944 | defined(STM32F303xC) || defined(STM32F358xx) |
Kojto | 93:e188a91d3eaa | 2945 | /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config |
Kojto | 93:e188a91d3eaa | 2946 | * @{ |
Kojto | 93:e188a91d3eaa | 2947 | */ |
Kojto | 93:e188a91d3eaa | 2948 | |
Kojto | 93:e188a91d3eaa | 2949 | /** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK). |
Kojto | 93:e188a91d3eaa | 2950 | * @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source. |
Kojto | 93:e188a91d3eaa | 2951 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2952 | * @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock |
Kojto | 93:e188a91d3eaa | 2953 | * @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2954 | * @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2955 | * @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2956 | * @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2957 | * @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2958 | * @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2959 | * @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2960 | * @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2961 | * @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2962 | * @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2963 | * @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2964 | * @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2965 | */ |
Kojto | 93:e188a91d3eaa | 2966 | #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 2967 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__)) |
Kojto | 93:e188a91d3eaa | 2968 | |
Kojto | 93:e188a91d3eaa | 2969 | /** @brief Macro to get the ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2970 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2971 | * @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock |
Kojto | 93:e188a91d3eaa | 2972 | * @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2973 | * @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2974 | * @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2975 | * @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2976 | * @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2977 | * @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2978 | * @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2979 | * @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2980 | * @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2981 | * @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2982 | * @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2983 | * @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock |
Kojto | 93:e188a91d3eaa | 2984 | */ |
Kojto | 93:e188a91d3eaa | 2985 | #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34))) |
Kojto | 93:e188a91d3eaa | 2986 | /** |
Kojto | 93:e188a91d3eaa | 2987 | * @} |
Kojto | 93:e188a91d3eaa | 2988 | */ |
Kojto | 93:e188a91d3eaa | 2989 | |
Kojto | 93:e188a91d3eaa | 2990 | /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config |
Kojto | 93:e188a91d3eaa | 2991 | * @{ |
Kojto | 93:e188a91d3eaa | 2992 | */ |
Kojto | 93:e188a91d3eaa | 2993 | |
Kojto | 93:e188a91d3eaa | 2994 | /** @brief Macro to configure the TIM8 clock (TIM8CLK). |
Kojto | 93:e188a91d3eaa | 2995 | * @param __TIM8CLKSource__: specifies the TIM8 clock source. |
Kojto | 93:e188a91d3eaa | 2996 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 2997 | * @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock |
Kojto | 93:e188a91d3eaa | 2998 | * @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock |
Kojto | 93:e188a91d3eaa | 2999 | */ |
Kojto | 93:e188a91d3eaa | 3000 | #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3001 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3002 | |
Kojto | 93:e188a91d3eaa | 3003 | /** @brief Macro to get the TIM8 clock (TIM8CLK). |
Kojto | 93:e188a91d3eaa | 3004 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3005 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3006 | * @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock |
Kojto | 93:e188a91d3eaa | 3007 | * @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock |
Kojto | 93:e188a91d3eaa | 3008 | */ |
Kojto | 93:e188a91d3eaa | 3009 | #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW))) |
Kojto | 93:e188a91d3eaa | 3010 | |
Kojto | 93:e188a91d3eaa | 3011 | /** |
Kojto | 93:e188a91d3eaa | 3012 | * @} |
Kojto | 93:e188a91d3eaa | 3013 | */ |
Kojto | 93:e188a91d3eaa | 3014 | #endif /* STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 3015 | /* STM32F303xC || STM32F358xx */ |
Kojto | 93:e188a91d3eaa | 3016 | |
Kojto | 93:e188a91d3eaa | 3017 | #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) |
Kojto | 93:e188a91d3eaa | 3018 | /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config |
Kojto | 93:e188a91d3eaa | 3019 | * @{ |
Kojto | 93:e188a91d3eaa | 3020 | */ |
Kojto | 93:e188a91d3eaa | 3021 | |
Kojto | 93:e188a91d3eaa | 3022 | /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK). |
Kojto | 93:e188a91d3eaa | 3023 | * @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source. |
Kojto | 93:e188a91d3eaa | 3024 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3025 | * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock |
Kojto | 93:e188a91d3eaa | 3026 | * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3027 | * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3028 | * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3029 | * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3030 | * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3031 | * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3032 | * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3033 | * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3034 | * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3035 | * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3036 | * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3037 | * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3038 | */ |
Kojto | 93:e188a91d3eaa | 3039 | #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3040 | MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3041 | |
Kojto | 93:e188a91d3eaa | 3042 | /** @brief Macro to get the ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3043 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3044 | * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock |
Kojto | 93:e188a91d3eaa | 3045 | * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3046 | * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3047 | * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3048 | * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3049 | * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3050 | * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3051 | * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3052 | * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3053 | * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3054 | * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3055 | * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3056 | * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock |
Kojto | 93:e188a91d3eaa | 3057 | */ |
Kojto | 93:e188a91d3eaa | 3058 | #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12))) |
Kojto | 93:e188a91d3eaa | 3059 | /** |
Kojto | 93:e188a91d3eaa | 3060 | * @} |
Kojto | 93:e188a91d3eaa | 3061 | */ |
Kojto | 93:e188a91d3eaa | 3062 | |
Kojto | 93:e188a91d3eaa | 3063 | /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config |
Kojto | 93:e188a91d3eaa | 3064 | * @{ |
Kojto | 93:e188a91d3eaa | 3065 | */ |
Kojto | 93:e188a91d3eaa | 3066 | /** @brief Macro to configure the TIM1 clock (TIM1CLK). |
Kojto | 93:e188a91d3eaa | 3067 | * @param __TIM1CLKSource__: specifies the TIM1 clock source. |
Kojto | 93:e188a91d3eaa | 3068 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3069 | * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 3070 | * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 3071 | */ |
Kojto | 93:e188a91d3eaa | 3072 | #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3073 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3074 | |
Kojto | 93:e188a91d3eaa | 3075 | /** @brief Macro to get the TIM1 clock (TIM1CLK). |
Kojto | 93:e188a91d3eaa | 3076 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3077 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3078 | * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 3079 | * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock |
Kojto | 93:e188a91d3eaa | 3080 | */ |
Kojto | 93:e188a91d3eaa | 3081 | #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW))) |
Kojto | 93:e188a91d3eaa | 3082 | /** |
Kojto | 93:e188a91d3eaa | 3083 | * @} |
Kojto | 93:e188a91d3eaa | 3084 | */ |
Kojto | 93:e188a91d3eaa | 3085 | #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */ |
Kojto | 93:e188a91d3eaa | 3086 | |
Kojto | 93:e188a91d3eaa | 3087 | #if defined(STM32F334x8) |
Kojto | 93:e188a91d3eaa | 3088 | /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config |
Kojto | 93:e188a91d3eaa | 3089 | * @{ |
Kojto | 93:e188a91d3eaa | 3090 | */ |
Kojto | 93:e188a91d3eaa | 3091 | /** @brief Macro to configure the HRTIM1 clock. |
Kojto | 93:e188a91d3eaa | 3092 | * @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source. |
Kojto | 93:e188a91d3eaa | 3093 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3094 | * @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock |
Kojto | 93:e188a91d3eaa | 3095 | * @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock |
Kojto | 93:e188a91d3eaa | 3096 | */ |
Kojto | 93:e188a91d3eaa | 3097 | #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3098 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3099 | |
Kojto | 93:e188a91d3eaa | 3100 | /** @brief Macro to get the HRTIM1 clock source. |
Kojto | 93:e188a91d3eaa | 3101 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3102 | * @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock |
Kojto | 93:e188a91d3eaa | 3103 | * @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock |
Kojto | 93:e188a91d3eaa | 3104 | */ |
Kojto | 93:e188a91d3eaa | 3105 | #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW))) |
Kojto | 93:e188a91d3eaa | 3106 | /** |
Kojto | 93:e188a91d3eaa | 3107 | * @} |
Kojto | 93:e188a91d3eaa | 3108 | */ |
Kojto | 93:e188a91d3eaa | 3109 | #endif /* STM32F334x8 */ |
Kojto | 93:e188a91d3eaa | 3110 | |
Kojto | 93:e188a91d3eaa | 3111 | #if defined(STM32F373xC) || defined(STM32F378xx) |
Kojto | 93:e188a91d3eaa | 3112 | /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config |
Kojto | 93:e188a91d3eaa | 3113 | * @{ |
Kojto | 93:e188a91d3eaa | 3114 | */ |
Kojto | 93:e188a91d3eaa | 3115 | /** @brief Macro to configure the I2C2 clock (I2C2CLK). |
Kojto | 93:e188a91d3eaa | 3116 | * @param __I2C2CLKSource__: specifies the I2C2 clock source. |
Kojto | 93:e188a91d3eaa | 3117 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3118 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 3119 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 3120 | */ |
Kojto | 93:e188a91d3eaa | 3121 | #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3122 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3123 | |
Kojto | 93:e188a91d3eaa | 3124 | /** @brief Macro to get the I2C2 clock source. |
Kojto | 93:e188a91d3eaa | 3125 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3126 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 3127 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
Kojto | 93:e188a91d3eaa | 3128 | */ |
Kojto | 93:e188a91d3eaa | 3129 | #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW))) |
Kojto | 93:e188a91d3eaa | 3130 | /** |
Kojto | 93:e188a91d3eaa | 3131 | * @} |
Kojto | 93:e188a91d3eaa | 3132 | */ |
Kojto | 93:e188a91d3eaa | 3133 | |
Kojto | 93:e188a91d3eaa | 3134 | /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config |
Kojto | 93:e188a91d3eaa | 3135 | * @{ |
Kojto | 93:e188a91d3eaa | 3136 | */ |
Kojto | 93:e188a91d3eaa | 3137 | /** @brief Macro to configure the ADC1 clock (ADC1CLK). |
Kojto | 93:e188a91d3eaa | 3138 | * @param __ADC1CLKSource__: specifies the ADC1 clock source. |
Kojto | 93:e188a91d3eaa | 3139 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3140 | * @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 3141 | * @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 3142 | * @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 3143 | * @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 3144 | */ |
Kojto | 93:e188a91d3eaa | 3145 | #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3146 | MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3147 | |
Kojto | 93:e188a91d3eaa | 3148 | /** @brief Macro to get the ADC1 clock (ADC1CLK). |
Kojto | 93:e188a91d3eaa | 3149 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3150 | * @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 3151 | * @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 3152 | * @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 3153 | * @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock |
Kojto | 93:e188a91d3eaa | 3154 | */ |
Kojto | 93:e188a91d3eaa | 3155 | #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE))) |
Kojto | 93:e188a91d3eaa | 3156 | /** |
Kojto | 93:e188a91d3eaa | 3157 | * @} |
Kojto | 93:e188a91d3eaa | 3158 | */ |
Kojto | 93:e188a91d3eaa | 3159 | |
Kojto | 93:e188a91d3eaa | 3160 | /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config |
Kojto | 93:e188a91d3eaa | 3161 | * @{ |
Kojto | 93:e188a91d3eaa | 3162 | */ |
Kojto | 93:e188a91d3eaa | 3163 | /** @brief Macro to configure the SDADCx clock (SDADCxCLK). |
Kojto | 93:e188a91d3eaa | 3164 | * @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler. |
Kojto | 93:e188a91d3eaa | 3165 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3166 | * @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3167 | * @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3168 | * @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3169 | * @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3170 | * @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3171 | * @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3172 | * @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3173 | * @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3174 | * @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3175 | * @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3176 | * @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3177 | * @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3178 | * @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3179 | * @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3180 | * @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3181 | * @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3182 | * @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3183 | */ |
Kojto | 93:e188a91d3eaa | 3184 | #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \ |
Kojto | 93:e188a91d3eaa | 3185 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__)) |
Kojto | 93:e188a91d3eaa | 3186 | |
Kojto | 93:e188a91d3eaa | 3187 | /** @brief Macro to get the SDADCx clock prescaler. |
Kojto | 93:e188a91d3eaa | 3188 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3189 | * @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3190 | * @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3191 | * @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3192 | * @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3193 | * @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3194 | * @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3195 | * @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3196 | * @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3197 | * @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3198 | * @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3199 | * @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3200 | * @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3201 | * @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3202 | * @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3203 | * @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3204 | * @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3205 | * @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock |
Kojto | 93:e188a91d3eaa | 3206 | */ |
Kojto | 93:e188a91d3eaa | 3207 | #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE))) |
Kojto | 93:e188a91d3eaa | 3208 | /** |
Kojto | 93:e188a91d3eaa | 3209 | * @} |
Kojto | 93:e188a91d3eaa | 3210 | */ |
Kojto | 93:e188a91d3eaa | 3211 | |
Kojto | 93:e188a91d3eaa | 3212 | /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config |
Kojto | 93:e188a91d3eaa | 3213 | * @{ |
Kojto | 93:e188a91d3eaa | 3214 | */ |
Kojto | 93:e188a91d3eaa | 3215 | /** @brief Macro to configure the CEC clock. |
Kojto | 93:e188a91d3eaa | 3216 | * @param __CECCLKSource__: specifies the CEC clock source. |
Kojto | 93:e188a91d3eaa | 3217 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3218 | * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock |
Kojto | 93:e188a91d3eaa | 3219 | * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
Kojto | 93:e188a91d3eaa | 3220 | */ |
Kojto | 93:e188a91d3eaa | 3221 | #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3222 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__)) |
Kojto | 93:e188a91d3eaa | 3223 | |
Kojto | 93:e188a91d3eaa | 3224 | /** @brief Macro to get the HDMI CEC clock source. |
Kojto | 93:e188a91d3eaa | 3225 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3226 | * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock |
Kojto | 93:e188a91d3eaa | 3227 | * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock |
Kojto | 93:e188a91d3eaa | 3228 | */ |
Kojto | 93:e188a91d3eaa | 3229 | #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW))) |
Kojto | 93:e188a91d3eaa | 3230 | /** |
Kojto | 93:e188a91d3eaa | 3231 | * @} |
Kojto | 93:e188a91d3eaa | 3232 | */ |
Kojto | 93:e188a91d3eaa | 3233 | |
Kojto | 93:e188a91d3eaa | 3234 | #endif /* STM32F373xC || STM32F378xx */ |
Kojto | 93:e188a91d3eaa | 3235 | |
Kojto | 93:e188a91d3eaa | 3236 | #if defined(STM32F302xE) || defined(STM32F303xE) || \ |
Kojto | 93:e188a91d3eaa | 3237 | defined(STM32F302xC) || defined(STM32F303xC) || \ |
Kojto | 93:e188a91d3eaa | 3238 | defined(STM32F302x8) || \ |
Kojto | 93:e188a91d3eaa | 3239 | defined(STM32F373xC) |
Kojto | 93:e188a91d3eaa | 3240 | |
Kojto | 93:e188a91d3eaa | 3241 | /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config |
Kojto | 93:e188a91d3eaa | 3242 | * @{ |
Kojto | 93:e188a91d3eaa | 3243 | */ |
Kojto | 93:e188a91d3eaa | 3244 | /** @brief Macro to configure the USB clock (USBCLK). |
Kojto | 93:e188a91d3eaa | 3245 | * @param __USBCLKSource__: specifies the USB clock source. |
Kojto | 93:e188a91d3eaa | 3246 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3247 | * @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock |
Kojto | 93:e188a91d3eaa | 3248 | * @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock |
Kojto | 93:e188a91d3eaa | 3249 | */ |
Kojto | 93:e188a91d3eaa | 3250 | #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3251 | MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__)) |
Kojto | 93:e188a91d3eaa | 3252 | |
Kojto | 93:e188a91d3eaa | 3253 | /** @brief Macro to get the USB clock source. |
Kojto | 93:e188a91d3eaa | 3254 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3255 | * @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock |
Kojto | 93:e188a91d3eaa | 3256 | * @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock |
Kojto | 93:e188a91d3eaa | 3257 | */ |
Kojto | 93:e188a91d3eaa | 3258 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE))) |
Kojto | 93:e188a91d3eaa | 3259 | /** |
Kojto | 93:e188a91d3eaa | 3260 | * @} |
Kojto | 93:e188a91d3eaa | 3261 | */ |
Kojto | 93:e188a91d3eaa | 3262 | |
Kojto | 93:e188a91d3eaa | 3263 | #endif /* STM32F302xE || STM32F303xE || */ |
Kojto | 93:e188a91d3eaa | 3264 | /* STM32F302xC || STM32F303xC || */ |
Kojto | 93:e188a91d3eaa | 3265 | /* STM32F302x8 || */ |
Kojto | 93:e188a91d3eaa | 3266 | /* STM32F373xC */ |
Kojto | 93:e188a91d3eaa | 3267 | |
Kojto | 93:e188a91d3eaa | 3268 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \ |
Kojto | 93:e188a91d3eaa | 3269 | defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \ |
Kojto | 93:e188a91d3eaa | 3270 | defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) |
Kojto | 93:e188a91d3eaa | 3271 | |
Kojto | 93:e188a91d3eaa | 3272 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
Kojto | 93:e188a91d3eaa | 3273 | * @{ |
Kojto | 93:e188a91d3eaa | 3274 | */ |
Kojto | 93:e188a91d3eaa | 3275 | /** @brief macro to configure the MCO clock. |
Kojto | 93:e188a91d3eaa | 3276 | * @param __MCOCLKSource__: specifies the MCO clock source. |
Kojto | 93:e188a91d3eaa | 3277 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3278 | * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock |
Kojto | 93:e188a91d3eaa | 3279 | * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock |
Kojto | 93:e188a91d3eaa | 3280 | * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock |
Kojto | 93:e188a91d3eaa | 3281 | * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock |
Kojto | 93:e188a91d3eaa | 3282 | * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock |
Kojto | 93:e188a91d3eaa | 3283 | * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock |
Kojto | 93:e188a91d3eaa | 3284 | * @param __MCODiv__: specifies the MCO clock prescaler. |
Kojto | 93:e188a91d3eaa | 3285 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3286 | * @arg RCC_MCO_NODIV: No division applied on MCO clock source |
Kojto | 93:e188a91d3eaa | 3287 | */ |
Kojto | 93:e188a91d3eaa | 3288 | #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \ |
Kojto | 93:e188a91d3eaa | 3289 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__))) |
Kojto | 93:e188a91d3eaa | 3290 | /** |
Kojto | 93:e188a91d3eaa | 3291 | * @} |
Kojto | 93:e188a91d3eaa | 3292 | */ |
Kojto | 93:e188a91d3eaa | 3293 | #else |
Kojto | 93:e188a91d3eaa | 3294 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
Kojto | 93:e188a91d3eaa | 3295 | * @{ |
Kojto | 93:e188a91d3eaa | 3296 | */ |
Kojto | 93:e188a91d3eaa | 3297 | |
Kojto | 93:e188a91d3eaa | 3298 | #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \ |
Kojto | 93:e188a91d3eaa | 3299 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__)) |
Kojto | 93:e188a91d3eaa | 3300 | /** |
Kojto | 93:e188a91d3eaa | 3301 | * @} |
Kojto | 93:e188a91d3eaa | 3302 | */ |
Kojto | 93:e188a91d3eaa | 3303 | |
Kojto | 93:e188a91d3eaa | 3304 | #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ |
Kojto | 93:e188a91d3eaa | 3305 | /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ |
Kojto | 93:e188a91d3eaa | 3306 | /* STM32F301x8 || STM32F302x8 || STM32F318xx */ |
Kojto | 93:e188a91d3eaa | 3307 | |
Kojto | 93:e188a91d3eaa | 3308 | #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 3309 | |
Kojto | 93:e188a91d3eaa | 3310 | /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config |
Kojto | 93:e188a91d3eaa | 3311 | * @{ |
Kojto | 93:e188a91d3eaa | 3312 | */ |
Kojto | 93:e188a91d3eaa | 3313 | /** @brief Macro to configure the I2C3 clock (I2C3CLK). |
Kojto | 93:e188a91d3eaa | 3314 | * @param __I2C3CLKSource__: specifies the I2C3 clock source. |
Kojto | 93:e188a91d3eaa | 3315 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3316 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
Kojto | 93:e188a91d3eaa | 3317 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
Kojto | 93:e188a91d3eaa | 3318 | */ |
Kojto | 93:e188a91d3eaa | 3319 | #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3320 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3321 | |
Kojto | 93:e188a91d3eaa | 3322 | /** @brief Macro to get the I2C3 clock source. |
Kojto | 93:e188a91d3eaa | 3323 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3324 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
Kojto | 93:e188a91d3eaa | 3325 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
Kojto | 93:e188a91d3eaa | 3326 | */ |
Kojto | 93:e188a91d3eaa | 3327 | #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW))) |
Kojto | 93:e188a91d3eaa | 3328 | /** |
Kojto | 93:e188a91d3eaa | 3329 | * @} |
Kojto | 93:e188a91d3eaa | 3330 | */ |
Kojto | 93:e188a91d3eaa | 3331 | |
Kojto | 93:e188a91d3eaa | 3332 | /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config |
Kojto | 93:e188a91d3eaa | 3333 | * @{ |
Kojto | 93:e188a91d3eaa | 3334 | */ |
Kojto | 93:e188a91d3eaa | 3335 | /** @brief Macro to configure the TIM2 clock (TIM2CLK). |
Kojto | 93:e188a91d3eaa | 3336 | * @param __TIM2CLKSource__: specifies the TIM2 clock source. |
Kojto | 93:e188a91d3eaa | 3337 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3338 | * @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock |
Kojto | 93:e188a91d3eaa | 3339 | * @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock |
Kojto | 93:e188a91d3eaa | 3340 | */ |
Kojto | 93:e188a91d3eaa | 3341 | #define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3342 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3343 | |
Kojto | 93:e188a91d3eaa | 3344 | /** @brief Macro to get the TIM2 clock (TIM2CLK). |
Kojto | 93:e188a91d3eaa | 3345 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3346 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3347 | * @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock |
Kojto | 93:e188a91d3eaa | 3348 | * @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock |
Kojto | 93:e188a91d3eaa | 3349 | */ |
Kojto | 93:e188a91d3eaa | 3350 | #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW))) |
Kojto | 93:e188a91d3eaa | 3351 | |
Kojto | 93:e188a91d3eaa | 3352 | /** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK). |
Kojto | 93:e188a91d3eaa | 3353 | * @param __TIM3CLKSource__: specifies the TIM3 & TIM4 clock source. |
Kojto | 93:e188a91d3eaa | 3354 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3355 | * @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock |
Kojto | 93:e188a91d3eaa | 3356 | * @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock |
Kojto | 93:e188a91d3eaa | 3357 | */ |
Kojto | 93:e188a91d3eaa | 3358 | #define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3359 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3360 | |
Kojto | 93:e188a91d3eaa | 3361 | /** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK). |
Kojto | 93:e188a91d3eaa | 3362 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3363 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3364 | * @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock |
Kojto | 93:e188a91d3eaa | 3365 | * @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock |
Kojto | 93:e188a91d3eaa | 3366 | */ |
Kojto | 93:e188a91d3eaa | 3367 | #define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW))) |
Kojto | 93:e188a91d3eaa | 3368 | |
Kojto | 93:e188a91d3eaa | 3369 | /** @brief Macro to configure the TIM15 clock (TIM15CLK). |
Kojto | 93:e188a91d3eaa | 3370 | * @param __TIM15CLKSource__: specifies the TIM15 clock source. |
Kojto | 93:e188a91d3eaa | 3371 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3372 | * @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock |
Kojto | 93:e188a91d3eaa | 3373 | * @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock |
Kojto | 93:e188a91d3eaa | 3374 | */ |
Kojto | 93:e188a91d3eaa | 3375 | #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3376 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3377 | |
Kojto | 93:e188a91d3eaa | 3378 | /** @brief Macro to get the TIM15 clock (TIM15CLK). |
Kojto | 93:e188a91d3eaa | 3379 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3380 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3381 | * @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock |
Kojto | 93:e188a91d3eaa | 3382 | * @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock |
Kojto | 93:e188a91d3eaa | 3383 | */ |
Kojto | 93:e188a91d3eaa | 3384 | #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW))) |
Kojto | 93:e188a91d3eaa | 3385 | |
Kojto | 93:e188a91d3eaa | 3386 | /** @brief Macro to configure the TIM16 clock (TIM16CLK). |
Kojto | 93:e188a91d3eaa | 3387 | * @param __TIM16CLKSource__: specifies the TIM16 clock source. |
Kojto | 93:e188a91d3eaa | 3388 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3389 | * @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock |
Kojto | 93:e188a91d3eaa | 3390 | * @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock |
Kojto | 93:e188a91d3eaa | 3391 | */ |
Kojto | 93:e188a91d3eaa | 3392 | #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3393 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3394 | |
Kojto | 93:e188a91d3eaa | 3395 | /** @brief Macro to get the TIM16 clock (TIM16CLK). |
Kojto | 93:e188a91d3eaa | 3396 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3397 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3398 | * @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock |
Kojto | 93:e188a91d3eaa | 3399 | * @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock |
Kojto | 93:e188a91d3eaa | 3400 | */ |
Kojto | 93:e188a91d3eaa | 3401 | #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW))) |
Kojto | 93:e188a91d3eaa | 3402 | |
Kojto | 93:e188a91d3eaa | 3403 | /** @brief Macro to configure the TIM17 clock (TIM17CLK). |
Kojto | 93:e188a91d3eaa | 3404 | * @param __TIM17CLKSource__: specifies the TIM17 clock source. |
Kojto | 93:e188a91d3eaa | 3405 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3406 | * @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock |
Kojto | 93:e188a91d3eaa | 3407 | * @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock |
Kojto | 93:e188a91d3eaa | 3408 | */ |
Kojto | 93:e188a91d3eaa | 3409 | #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3410 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3411 | |
Kojto | 93:e188a91d3eaa | 3412 | /** @brief Macro to get the TIM17 clock (TIM17CLK). |
Kojto | 93:e188a91d3eaa | 3413 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3414 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3415 | * @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock |
Kojto | 93:e188a91d3eaa | 3416 | * @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock |
Kojto | 93:e188a91d3eaa | 3417 | */ |
Kojto | 93:e188a91d3eaa | 3418 | #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW))) |
Kojto | 93:e188a91d3eaa | 3419 | |
Kojto | 93:e188a91d3eaa | 3420 | /** |
Kojto | 93:e188a91d3eaa | 3421 | * @} |
Kojto | 93:e188a91d3eaa | 3422 | */ |
Kojto | 93:e188a91d3eaa | 3423 | |
Kojto | 93:e188a91d3eaa | 3424 | #endif /* STM32f302xE || STM32f303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 3425 | |
Kojto | 93:e188a91d3eaa | 3426 | #if defined(STM32F303xE) || defined(STM32F398xx) |
Kojto | 93:e188a91d3eaa | 3427 | /** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config |
Kojto | 93:e188a91d3eaa | 3428 | * @{ |
Kojto | 93:e188a91d3eaa | 3429 | */ |
Kojto | 93:e188a91d3eaa | 3430 | /** @brief Macro to configure the TIM20 clock (TIM20CLK). |
Kojto | 93:e188a91d3eaa | 3431 | * @param __TIM20CLKSource__: specifies the TIM20 clock source. |
Kojto | 93:e188a91d3eaa | 3432 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3433 | * @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock |
Kojto | 93:e188a91d3eaa | 3434 | * @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock |
Kojto | 93:e188a91d3eaa | 3435 | */ |
Kojto | 93:e188a91d3eaa | 3436 | #define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \ |
Kojto | 93:e188a91d3eaa | 3437 | MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__)) |
Kojto | 93:e188a91d3eaa | 3438 | |
Kojto | 93:e188a91d3eaa | 3439 | /** @brief Macro to get the TIM20 clock (TIM20CLK). |
Kojto | 93:e188a91d3eaa | 3440 | * @retval The clock source can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3441 | * This parameter can be one of the following values: |
Kojto | 93:e188a91d3eaa | 3442 | * @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock |
Kojto | 93:e188a91d3eaa | 3443 | * @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock |
Kojto | 93:e188a91d3eaa | 3444 | */ |
Kojto | 93:e188a91d3eaa | 3445 | #define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW))) |
Kojto | 93:e188a91d3eaa | 3446 | |
Kojto | 93:e188a91d3eaa | 3447 | /** |
Kojto | 93:e188a91d3eaa | 3448 | * @} |
Kojto | 93:e188a91d3eaa | 3449 | */ |
Kojto | 93:e188a91d3eaa | 3450 | #endif /* STM32f303xE || STM32F398xx */ |
Kojto | 93:e188a91d3eaa | 3451 | |
Kojto | 93:e188a91d3eaa | 3452 | |
Kojto | 93:e188a91d3eaa | 3453 | /** |
Kojto | 93:e188a91d3eaa | 3454 | * @} |
Kojto | 93:e188a91d3eaa | 3455 | */ |
Kojto | 93:e188a91d3eaa | 3456 | |
Kojto | 93:e188a91d3eaa | 3457 | /* Exported functions --------------------------------------------------------*/ |
Kojto | 93:e188a91d3eaa | 3458 | /** @addtogroup RCCEx_Exported_Functions RCC Extended Exported Functions |
Kojto | 93:e188a91d3eaa | 3459 | * @{ |
Kojto | 93:e188a91d3eaa | 3460 | */ |
Kojto | 93:e188a91d3eaa | 3461 | |
Kojto | 93:e188a91d3eaa | 3462 | /** @addtogroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions |
Kojto | 93:e188a91d3eaa | 3463 | * @{ |
Kojto | 93:e188a91d3eaa | 3464 | */ |
Kojto | 93:e188a91d3eaa | 3465 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
Kojto | 93:e188a91d3eaa | 3466 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
Kojto | 93:e188a91d3eaa | 3467 | /** |
Kojto | 93:e188a91d3eaa | 3468 | * @} |
Kojto | 93:e188a91d3eaa | 3469 | */ |
Kojto | 93:e188a91d3eaa | 3470 | |
Kojto | 93:e188a91d3eaa | 3471 | /** |
Kojto | 93:e188a91d3eaa | 3472 | * @} |
Kojto | 93:e188a91d3eaa | 3473 | */ |
Kojto | 93:e188a91d3eaa | 3474 | |
Kojto | 93:e188a91d3eaa | 3475 | /** |
Kojto | 93:e188a91d3eaa | 3476 | * @} |
Kojto | 93:e188a91d3eaa | 3477 | */ |
Kojto | 93:e188a91d3eaa | 3478 | |
Kojto | 93:e188a91d3eaa | 3479 | /** |
Kojto | 93:e188a91d3eaa | 3480 | * @} |
Kojto | 93:e188a91d3eaa | 3481 | */ |
Kojto | 93:e188a91d3eaa | 3482 | #ifdef __cplusplus |
Kojto | 93:e188a91d3eaa | 3483 | } |
Kojto | 93:e188a91d3eaa | 3484 | #endif |
Kojto | 93:e188a91d3eaa | 3485 | |
Kojto | 93:e188a91d3eaa | 3486 | #endif /* __STM32F3xx_HAL_RCC_EX_H */ |
Kojto | 93:e188a91d3eaa | 3487 | |
Kojto | 93:e188a91d3eaa | 3488 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |