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TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_eth.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:: Mikchel
Date:: Sun May 03 16:04:42 2015 +0000
Revision:: 99:7f6c6de930c0
Parent:: 93:e188a91d3eaa

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	93:e188a91d3eaa	1	/**
Kojto	93:e188a91d3eaa	2	******************************************************************************
Kojto	93:e188a91d3eaa	3	* @file stm32f4xx_hal_eth.h
Kojto	93:e188a91d3eaa	4	* @author MCD Application Team
Kojto	93:e188a91d3eaa	5	* @version V1.1.0
Kojto	93:e188a91d3eaa	6	* @date 19-June-2014
Kojto	93:e188a91d3eaa	7	* @brief Header file of ETH HAL module.
Kojto	93:e188a91d3eaa	8	******************************************************************************
Kojto	93:e188a91d3eaa	9	* @attention
Kojto	93:e188a91d3eaa	10	*
Kojto	93:e188a91d3eaa	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	93:e188a91d3eaa	12	*
Kojto	93:e188a91d3eaa	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	93:e188a91d3eaa	14	* are permitted provided that the following conditions are met:
Kojto	93:e188a91d3eaa	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	93:e188a91d3eaa	16	* this list of conditions and the following disclaimer.
Kojto	93:e188a91d3eaa	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	93:e188a91d3eaa	18	* this list of conditions and the following disclaimer in the documentation
Kojto	93:e188a91d3eaa	19	* and/or other materials provided with the distribution.
Kojto	93:e188a91d3eaa	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	93:e188a91d3eaa	21	* may be used to endorse or promote products derived from this software
Kojto	93:e188a91d3eaa	22	* without specific prior written permission.
Kojto	93:e188a91d3eaa	23	*
Kojto	93:e188a91d3eaa	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	93:e188a91d3eaa	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	93:e188a91d3eaa	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	93:e188a91d3eaa	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	93:e188a91d3eaa	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	93:e188a91d3eaa	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	93:e188a91d3eaa	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	93:e188a91d3eaa	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	93:e188a91d3eaa	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	93:e188a91d3eaa	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	93:e188a91d3eaa	34	*
Kojto	93:e188a91d3eaa	35	******************************************************************************
Kojto	93:e188a91d3eaa	36	*/
Kojto	93:e188a91d3eaa	37
Kojto	93:e188a91d3eaa	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	93:e188a91d3eaa	39	#ifndef __STM32F4xx_HAL_ETH_H
Kojto	93:e188a91d3eaa	40	#define __STM32F4xx_HAL_ETH_H
Kojto	93:e188a91d3eaa	41
Kojto	93:e188a91d3eaa	42	#ifdef __cplusplus
Kojto	93:e188a91d3eaa	43	extern "C" {
Kojto	93:e188a91d3eaa	44	#endif
Kojto	93:e188a91d3eaa	45
Kojto	93:e188a91d3eaa	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	93:e188a91d3eaa	47	/* Includes ------------------------------------------------------------------*/
Kojto	93:e188a91d3eaa	48	#include "stm32f4xx_hal_def.h"
Kojto	93:e188a91d3eaa	49
Kojto	93:e188a91d3eaa	50	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	93:e188a91d3eaa	51	* @{
Kojto	93:e188a91d3eaa	52	*/
Kojto	93:e188a91d3eaa	53
Kojto	93:e188a91d3eaa	54	/** @addtogroup ETH
Kojto	93:e188a91d3eaa	55	* @{
Kojto	93:e188a91d3eaa	56	*/
Kojto	93:e188a91d3eaa	57
Kojto	93:e188a91d3eaa	58	/* Exported types ------------------------------------------------------------*/
Kojto	93:e188a91d3eaa	59
Kojto	93:e188a91d3eaa	60	/**
Kojto	93:e188a91d3eaa	61	* @brief HAL State structures definition
Kojto	93:e188a91d3eaa	62	*/
Kojto	93:e188a91d3eaa	63	typedef enum
Kojto	93:e188a91d3eaa	64	{
Kojto	93:e188a91d3eaa	65	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
Kojto	93:e188a91d3eaa	66	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
Kojto	93:e188a91d3eaa	67	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
Kojto	93:e188a91d3eaa	68	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
Kojto	93:e188a91d3eaa	69	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
Kojto	93:e188a91d3eaa	70	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
Kojto	93:e188a91d3eaa	71	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
Kojto	93:e188a91d3eaa	72	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
Kojto	93:e188a91d3eaa	73	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
Kojto	93:e188a91d3eaa	74	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
Kojto	93:e188a91d3eaa	75	}HAL_ETH_StateTypeDef;
Kojto	93:e188a91d3eaa	76
Kojto	93:e188a91d3eaa	77	/**
Kojto	93:e188a91d3eaa	78	* @brief ETH Init Structure definition
Kojto	93:e188a91d3eaa	79	*/
Kojto	93:e188a91d3eaa	80
Kojto	93:e188a91d3eaa	81	typedef struct
Kojto	93:e188a91d3eaa	82	{
Kojto	93:e188a91d3eaa	83	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
Kojto	93:e188a91d3eaa	84	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
Kojto	93:e188a91d3eaa	85	and the mode (half/full-duplex).
Kojto	93:e188a91d3eaa	86	This parameter can be a value of @ref ETH_AutoNegotiation */
Kojto	93:e188a91d3eaa	87
Kojto	93:e188a91d3eaa	88	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
Kojto	93:e188a91d3eaa	89	This parameter can be a value of @ref ETH_Speed */
Kojto	93:e188a91d3eaa	90
Kojto	93:e188a91d3eaa	91	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
Kojto	93:e188a91d3eaa	92	This parameter can be a value of @ref ETH_Duplex_Mode */
Kojto	93:e188a91d3eaa	93
Kojto	93:e188a91d3eaa	94	uint16_t PhyAddress; /*!< Ethernet PHY address.
Kojto	93:e188a91d3eaa	95	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto	93:e188a91d3eaa	96
Kojto	93:e188a91d3eaa	97	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
Kojto	93:e188a91d3eaa	98
Kojto	93:e188a91d3eaa	99	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
Kojto	93:e188a91d3eaa	100	This parameter can be a value of @ref ETH_Rx_Mode */
Kojto	93:e188a91d3eaa	101
Kojto	93:e188a91d3eaa	102	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
Kojto	93:e188a91d3eaa	103	This parameter can be a value of @ref ETH_Checksum_Mode */
Kojto	93:e188a91d3eaa	104
Kojto	93:e188a91d3eaa	105	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
Kojto	93:e188a91d3eaa	106	This parameter can be a value of @ref ETH_Media_Interface */
Kojto	93:e188a91d3eaa	107
Kojto	93:e188a91d3eaa	108	} ETH_InitTypeDef;
Kojto	93:e188a91d3eaa	109
Kojto	93:e188a91d3eaa	110
Kojto	93:e188a91d3eaa	111	/**
Kojto	93:e188a91d3eaa	112	* @brief ETH MAC Configuration Structure definition
Kojto	93:e188a91d3eaa	113	*/
Kojto	93:e188a91d3eaa	114
Kojto	93:e188a91d3eaa	115	typedef struct
Kojto	93:e188a91d3eaa	116	{
Kojto	93:e188a91d3eaa	117	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
Kojto	93:e188a91d3eaa	118	When enabled, the MAC allows no more then 2048 bytes to be received.
Kojto	93:e188a91d3eaa	119	When disabled, the MAC can receive up to 16384 bytes.
Kojto	93:e188a91d3eaa	120	This parameter can be a value of @ref ETH_watchdog */
Kojto	93:e188a91d3eaa	121
Kojto	93:e188a91d3eaa	122	uint32_t Jabber; /*!< Selects or not Jabber timer
Kojto	93:e188a91d3eaa	123	When enabled, the MAC allows no more then 2048 bytes to be sent.
Kojto	93:e188a91d3eaa	124	When disabled, the MAC can send up to 16384 bytes.
Kojto	93:e188a91d3eaa	125	This parameter can be a value of @ref ETH_Jabber */
Kojto	93:e188a91d3eaa	126
Kojto	93:e188a91d3eaa	127	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
Kojto	93:e188a91d3eaa	128	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
Kojto	93:e188a91d3eaa	129
Kojto	93:e188a91d3eaa	130	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
Kojto	93:e188a91d3eaa	131	This parameter can be a value of @ref ETH_Carrier_Sense */
Kojto	93:e188a91d3eaa	132
Kojto	93:e188a91d3eaa	133	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
Kojto	93:e188a91d3eaa	134	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
Kojto	93:e188a91d3eaa	135	in Half-Duplex mode.
Kojto	93:e188a91d3eaa	136	This parameter can be a value of @ref ETH_Receive_Own */
Kojto	93:e188a91d3eaa	137
Kojto	93:e188a91d3eaa	138	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
Kojto	93:e188a91d3eaa	139	This parameter can be a value of @ref ETH_Loop_Back_Mode */
Kojto	93:e188a91d3eaa	140
Kojto	93:e188a91d3eaa	141	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
Kojto	93:e188a91d3eaa	142	This parameter can be a value of @ref ETH_Checksum_Offload */
Kojto	93:e188a91d3eaa	143
Kojto	93:e188a91d3eaa	144	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
Kojto	93:e188a91d3eaa	145	when a collision occurs (Half-Duplex mode).
Kojto	93:e188a91d3eaa	146	This parameter can be a value of @ref ETH_Retry_Transmission */
Kojto	93:e188a91d3eaa	147
Kojto	93:e188a91d3eaa	148	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
Kojto	93:e188a91d3eaa	149	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
Kojto	93:e188a91d3eaa	150
Kojto	93:e188a91d3eaa	151	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
Kojto	93:e188a91d3eaa	152	This parameter can be a value of @ref ETH_Back_Off_Limit */
Kojto	93:e188a91d3eaa	153
Kojto	93:e188a91d3eaa	154	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
Kojto	93:e188a91d3eaa	155	This parameter can be a value of @ref ETH_Deferral_Check */
Kojto	93:e188a91d3eaa	156
Kojto	93:e188a91d3eaa	157	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
Kojto	93:e188a91d3eaa	158	This parameter can be a value of @ref ETH_Receive_All */
Kojto	93:e188a91d3eaa	159
Kojto	93:e188a91d3eaa	160	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
Kojto	93:e188a91d3eaa	161	This parameter can be a value of @ref ETH_Source_Addr_Filter */
Kojto	93:e188a91d3eaa	162
Kojto	93:e188a91d3eaa	163	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
Kojto	93:e188a91d3eaa	164	This parameter can be a value of @ref ETH_Pass_Control_Frames */
Kojto	93:e188a91d3eaa	165
Kojto	93:e188a91d3eaa	166	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
Kojto	93:e188a91d3eaa	167	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
Kojto	93:e188a91d3eaa	168
Kojto	93:e188a91d3eaa	169	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
Kojto	93:e188a91d3eaa	170	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
Kojto	93:e188a91d3eaa	171
Kojto	93:e188a91d3eaa	172	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
Kojto	93:e188a91d3eaa	173	This parameter can be a value of @ref ETH_Promiscuous_Mode */
Kojto	93:e188a91d3eaa	174
Kojto	93:e188a91d3eaa	175	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto	93:e188a91d3eaa	176	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
Kojto	93:e188a91d3eaa	177
Kojto	93:e188a91d3eaa	178	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto	93:e188a91d3eaa	179	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
Kojto	93:e188a91d3eaa	180
Kojto	93:e188a91d3eaa	181	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
Kojto	93:e188a91d3eaa	182	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto	93:e188a91d3eaa	183
Kojto	93:e188a91d3eaa	184	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
Kojto	93:e188a91d3eaa	185	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto	93:e188a91d3eaa	186
Kojto	93:e188a91d3eaa	187	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
Kojto	93:e188a91d3eaa	188	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
Kojto	93:e188a91d3eaa	189
Kojto	93:e188a91d3eaa	190	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
Kojto	93:e188a91d3eaa	191	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
Kojto	93:e188a91d3eaa	192
Kojto	93:e188a91d3eaa	193	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
Kojto	93:e188a91d3eaa	194	automatic retransmission of PAUSE Frame.
Kojto	93:e188a91d3eaa	195	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
Kojto	93:e188a91d3eaa	196
Kojto	93:e188a91d3eaa	197	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
Kojto	93:e188a91d3eaa	198	unicast address and unique multicast address).
Kojto	93:e188a91d3eaa	199	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
Kojto	93:e188a91d3eaa	200
Kojto	93:e188a91d3eaa	201	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
Kojto	93:e188a91d3eaa	202	disable its transmitter for a specified time (Pause Time)
Kojto	93:e188a91d3eaa	203	This parameter can be a value of @ref ETH_Receive_Flow_Control */
Kojto	93:e188a91d3eaa	204
Kojto	93:e188a91d3eaa	205	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
Kojto	93:e188a91d3eaa	206	or the MAC back-pressure operation (Half-Duplex mode)
Kojto	93:e188a91d3eaa	207	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
Kojto	93:e188a91d3eaa	208
Kojto	93:e188a91d3eaa	209	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
Kojto	93:e188a91d3eaa	210	comparison and filtering.
Kojto	93:e188a91d3eaa	211	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
Kojto	93:e188a91d3eaa	212
Kojto	93:e188a91d3eaa	213	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
Kojto	93:e188a91d3eaa	214
Kojto	93:e188a91d3eaa	215	} ETH_MACInitTypeDef;
Kojto	93:e188a91d3eaa	216
Kojto	93:e188a91d3eaa	217
Kojto	93:e188a91d3eaa	218	/**
Kojto	93:e188a91d3eaa	219	* @brief ETH DMA Configuration Structure definition
Kojto	93:e188a91d3eaa	220	*/
Kojto	93:e188a91d3eaa	221
Kojto	93:e188a91d3eaa	222	typedef struct
Kojto	93:e188a91d3eaa	223	{
Kojto	93:e188a91d3eaa	224	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
Kojto	93:e188a91d3eaa	225	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
Kojto	93:e188a91d3eaa	226
Kojto	93:e188a91d3eaa	227	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
Kojto	93:e188a91d3eaa	228	This parameter can be a value of @ref ETH_Receive_Store_Forward */
Kojto	93:e188a91d3eaa	229
Kojto	93:e188a91d3eaa	230	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
Kojto	93:e188a91d3eaa	231	This parameter can be a value of @ref ETH_Flush_Received_Frame */
Kojto	93:e188a91d3eaa	232
Kojto	93:e188a91d3eaa	233	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
Kojto	93:e188a91d3eaa	234	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
Kojto	93:e188a91d3eaa	235
Kojto	93:e188a91d3eaa	236	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
Kojto	93:e188a91d3eaa	237	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
Kojto	93:e188a91d3eaa	238
Kojto	93:e188a91d3eaa	239	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
Kojto	93:e188a91d3eaa	240	This parameter can be a value of @ref ETH_Forward_Error_Frames */
Kojto	93:e188a91d3eaa	241
Kojto	93:e188a91d3eaa	242	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
Kojto	93:e188a91d3eaa	243	and length less than 64 bytes) including pad-bytes and CRC)
Kojto	93:e188a91d3eaa	244	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
Kojto	93:e188a91d3eaa	245
Kojto	93:e188a91d3eaa	246	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
Kojto	93:e188a91d3eaa	247	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
Kojto	93:e188a91d3eaa	248
Kojto	93:e188a91d3eaa	249	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
Kojto	93:e188a91d3eaa	250	frame of Transmit data even before obtaining the status for the first frame.
Kojto	93:e188a91d3eaa	251	This parameter can be a value of @ref ETH_Second_Frame_Operate */
Kojto	93:e188a91d3eaa	252
Kojto	93:e188a91d3eaa	253	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
Kojto	93:e188a91d3eaa	254	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
Kojto	93:e188a91d3eaa	255
Kojto	93:e188a91d3eaa	256	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
Kojto	93:e188a91d3eaa	257	This parameter can be a value of @ref ETH_Fixed_Burst */
Kojto	93:e188a91d3eaa	258
Kojto	93:e188a91d3eaa	259	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
Kojto	93:e188a91d3eaa	260	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
Kojto	93:e188a91d3eaa	261
Kojto	93:e188a91d3eaa	262	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
Kojto	93:e188a91d3eaa	263	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
Kojto	93:e188a91d3eaa	264
Kojto	93:e188a91d3eaa	265	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
Kojto	93:e188a91d3eaa	266	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
Kojto	93:e188a91d3eaa	267
Kojto	93:e188a91d3eaa	268	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
Kojto	93:e188a91d3eaa	269	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto	93:e188a91d3eaa	270
Kojto	93:e188a91d3eaa	271	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
Kojto	93:e188a91d3eaa	272	This parameter can be a value of @ref ETH_DMA_Arbitration */
Kojto	93:e188a91d3eaa	273	} ETH_DMAInitTypeDef;
Kojto	93:e188a91d3eaa	274
Kojto	93:e188a91d3eaa	275
Kojto	93:e188a91d3eaa	276	/**
Kojto	93:e188a91d3eaa	277	* @brief ETH DMA Descriptors data structure definition
Kojto	93:e188a91d3eaa	278	*/
Kojto	93:e188a91d3eaa	279
Kojto	93:e188a91d3eaa	280	typedef struct
Kojto	93:e188a91d3eaa	281	{
Kojto	93:e188a91d3eaa	282	__IO uint32_t Status; /!< Status /
Kojto	93:e188a91d3eaa	283
Kojto	93:e188a91d3eaa	284	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
Kojto	93:e188a91d3eaa	285
Kojto	93:e188a91d3eaa	286	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
Kojto	93:e188a91d3eaa	287
Kojto	93:e188a91d3eaa	288	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
Kojto	93:e188a91d3eaa	289
Kojto	93:e188a91d3eaa	290	/!< Enhanced ETHERNET DMA PTP Descriptors /
Kojto	93:e188a91d3eaa	291	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
Kojto	93:e188a91d3eaa	292
Kojto	93:e188a91d3eaa	293	uint32_t Reserved1; /!< Reserved /
Kojto	93:e188a91d3eaa	294
Kojto	93:e188a91d3eaa	295	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
Kojto	93:e188a91d3eaa	296
Kojto	93:e188a91d3eaa	297	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
Kojto	93:e188a91d3eaa	298
Kojto	93:e188a91d3eaa	299	} ETH_DMADescTypeDef;
Kojto	93:e188a91d3eaa	300
Kojto	93:e188a91d3eaa	301
Kojto	93:e188a91d3eaa	302	/**
Kojto	93:e188a91d3eaa	303	* @brief Received Frame Informations structure definition
Kojto	93:e188a91d3eaa	304	*/
Kojto	93:e188a91d3eaa	305	typedef struct
Kojto	93:e188a91d3eaa	306	{
Kojto	93:e188a91d3eaa	307	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
Kojto	93:e188a91d3eaa	308
Kojto	93:e188a91d3eaa	309	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
Kojto	93:e188a91d3eaa	310
Kojto	93:e188a91d3eaa	311	uint32_t SegCount; /!< Segment count /
Kojto	93:e188a91d3eaa	312
Kojto	93:e188a91d3eaa	313	uint32_t length; /!< Frame length /
Kojto	93:e188a91d3eaa	314
Kojto	93:e188a91d3eaa	315	uint32_t buffer; /!< Frame buffer /
Kojto	93:e188a91d3eaa	316
Kojto	93:e188a91d3eaa	317	} ETH_DMARxFrameInfos;
Kojto	93:e188a91d3eaa	318
Kojto	93:e188a91d3eaa	319
Kojto	93:e188a91d3eaa	320	/**
Kojto	93:e188a91d3eaa	321	* @brief ETH Handle Structure definition
Kojto	93:e188a91d3eaa	322	*/
Kojto	93:e188a91d3eaa	323
Kojto	93:e188a91d3eaa	324	typedef struct
Kojto	93:e188a91d3eaa	325	{
Kojto	93:e188a91d3eaa	326	ETH_TypeDef Instance; /!< Register base address */
Kojto	93:e188a91d3eaa	327
Kojto	93:e188a91d3eaa	328	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
Kojto	93:e188a91d3eaa	329
Kojto	93:e188a91d3eaa	330	uint32_t LinkStatus; /!< Ethernet link status /
Kojto	93:e188a91d3eaa	331
Kojto	93:e188a91d3eaa	332	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
Kojto	93:e188a91d3eaa	333
Kojto	93:e188a91d3eaa	334	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
Kojto	93:e188a91d3eaa	335
Kojto	93:e188a91d3eaa	336	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
Kojto	93:e188a91d3eaa	337
Kojto	93:e188a91d3eaa	338	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
Kojto	93:e188a91d3eaa	339
Kojto	93:e188a91d3eaa	340	HAL_LockTypeDef Lock; /!< ETH Lock /
Kojto	93:e188a91d3eaa	341
Kojto	93:e188a91d3eaa	342	} ETH_HandleTypeDef;
Kojto	93:e188a91d3eaa	343
Kojto	93:e188a91d3eaa	344	/* Exported constants --------------------------------------------------------*/
Kojto	93:e188a91d3eaa	345
Kojto	93:e188a91d3eaa	346	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
Kojto	93:e188a91d3eaa	347
Kojto	93:e188a91d3eaa	348	/* Delay to wait when writing to some Ethernet registers */
Kojto	93:e188a91d3eaa	349	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	350
Kojto	93:e188a91d3eaa	351
Kojto	93:e188a91d3eaa	352	/* ETHERNET Errors */
Kojto	93:e188a91d3eaa	353	#define ETH_SUCCESS ((uint32_t)0)
Kojto	93:e188a91d3eaa	354	#define ETH_ERROR ((uint32_t)1)
Kojto	93:e188a91d3eaa	355
Kojto	93:e188a91d3eaa	356	/** @defgroup ETH_Buffers_setting
Kojto	93:e188a91d3eaa	357	* @{
Kojto	93:e188a91d3eaa	358	*/
Kojto	93:e188a91d3eaa	359	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC /
Kojto	93:e188a91d3eaa	360	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
Kojto	93:e188a91d3eaa	361	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
Kojto	93:e188a91d3eaa	362	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
Kojto	93:e188a91d3eaa	363	#define VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
Kojto	93:e188a91d3eaa	364	#define MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
Kojto	93:e188a91d3eaa	365	#define MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
Kojto	93:e188a91d3eaa	366	#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
Kojto	93:e188a91d3eaa	367
Kojto	93:e188a91d3eaa	368	/* Ethernet driver receive buffers are organized in a chained linked-list, when
Kojto	93:e188a91d3eaa	369	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
Kojto	93:e188a91d3eaa	370	to the driver receive buffers memory.
Kojto	93:e188a91d3eaa	371
Kojto	93:e188a91d3eaa	372	Depending on the size of the received ethernet packet and the size of
Kojto	93:e188a91d3eaa	373	each ethernet driver receive buffer, the received packet can take one or more
Kojto	93:e188a91d3eaa	374	ethernet driver receive buffer.
Kojto	93:e188a91d3eaa	375
Kojto	93:e188a91d3eaa	376	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
Kojto	93:e188a91d3eaa	377	and the total count of the driver receive buffers ETH_RXBUFNB.
Kojto	93:e188a91d3eaa	378
Kojto	93:e188a91d3eaa	379	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
Kojto	93:e188a91d3eaa	380	example, they can be reconfigured in the application layer to fit the application
Kojto	93:e188a91d3eaa	381	needs */
Kojto	93:e188a91d3eaa	382
Kojto	93:e188a91d3eaa	383	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
Kojto	93:e188a91d3eaa	384	packet */
Kojto	93:e188a91d3eaa	385	#ifndef ETH_RX_BUF_SIZE
Kojto	93:e188a91d3eaa	386	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto	93:e188a91d3eaa	387	#endif
Kojto	93:e188a91d3eaa	388
Kojto	93:e188a91d3eaa	389	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
Kojto	93:e188a91d3eaa	390	#ifndef ETH_RXBUFNB
Kojto	93:e188a91d3eaa	391	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
Kojto	93:e188a91d3eaa	392	#endif
Kojto	93:e188a91d3eaa	393
Kojto	93:e188a91d3eaa	394
Kojto	93:e188a91d3eaa	395	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
Kojto	93:e188a91d3eaa	396	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
Kojto	93:e188a91d3eaa	397	driver transmit buffers memory to the TxFIFO.
Kojto	93:e188a91d3eaa	398
Kojto	93:e188a91d3eaa	399	Depending on the size of the Ethernet packet to be transmitted and the size of
Kojto	93:e188a91d3eaa	400	each ethernet driver transmit buffer, the packet to be transmitted can take
Kojto	93:e188a91d3eaa	401	one or more ethernet driver transmit buffer.
Kojto	93:e188a91d3eaa	402
Kojto	93:e188a91d3eaa	403	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
Kojto	93:e188a91d3eaa	404	and the total count of the driver transmit buffers ETH_TXBUFNB.
Kojto	93:e188a91d3eaa	405
Kojto	93:e188a91d3eaa	406	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
Kojto	93:e188a91d3eaa	407	example, they can be reconfigured in the application layer to fit the application
Kojto	93:e188a91d3eaa	408	needs */
Kojto	93:e188a91d3eaa	409
Kojto	93:e188a91d3eaa	410	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
Kojto	93:e188a91d3eaa	411	packet */
Kojto	93:e188a91d3eaa	412	#ifndef ETH_TX_BUF_SIZE
Kojto	93:e188a91d3eaa	413	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto	93:e188a91d3eaa	414	#endif
Kojto	93:e188a91d3eaa	415
Kojto	93:e188a91d3eaa	416	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
Kojto	93:e188a91d3eaa	417	#ifndef ETH_TXBUFNB
Kojto	93:e188a91d3eaa	418	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
Kojto	93:e188a91d3eaa	419	#endif
Kojto	93:e188a91d3eaa	420
Kojto	93:e188a91d3eaa	421
Kojto	93:e188a91d3eaa	422	/*
Kojto	93:e188a91d3eaa	423	DMA Tx Desciptor
Kojto	93:e188a91d3eaa	424	-----------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	425	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
Kojto	93:e188a91d3eaa	426	-----------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	427	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
Kojto	93:e188a91d3eaa	428	-----------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	429	TDES2 \| Buffer1 Address [31:0] \|
Kojto	93:e188a91d3eaa	430	-----------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	431	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
Kojto	93:e188a91d3eaa	432	-----------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	433	*/
Kojto	93:e188a91d3eaa	434
Kojto	93:e188a91d3eaa	435	/**
Kojto	93:e188a91d3eaa	436	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
Kojto	93:e188a91d3eaa	437	*/
Kojto	93:e188a91d3eaa	438	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
Kojto	93:e188a91d3eaa	439	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
Kojto	93:e188a91d3eaa	440	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
Kojto	93:e188a91d3eaa	441	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
Kojto	93:e188a91d3eaa	442	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
Kojto	93:e188a91d3eaa	443	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
Kojto	93:e188a91d3eaa	444	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
Kojto	93:e188a91d3eaa	445	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
Kojto	93:e188a91d3eaa	446	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
Kojto	93:e188a91d3eaa	447	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
Kojto	93:e188a91d3eaa	448	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
Kojto	93:e188a91d3eaa	449	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
Kojto	93:e188a91d3eaa	450	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
Kojto	93:e188a91d3eaa	451	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
Kojto	93:e188a91d3eaa	452	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
Kojto	93:e188a91d3eaa	453	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
Kojto	93:e188a91d3eaa	454	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
Kojto	93:e188a91d3eaa	455	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
Kojto	93:e188a91d3eaa	456	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
Kojto	93:e188a91d3eaa	457	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
Kojto	93:e188a91d3eaa	458	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
Kojto	93:e188a91d3eaa	459	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
Kojto	93:e188a91d3eaa	460	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
Kojto	93:e188a91d3eaa	461	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
Kojto	93:e188a91d3eaa	462	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
Kojto	93:e188a91d3eaa	463	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
Kojto	93:e188a91d3eaa	464	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
Kojto	93:e188a91d3eaa	465	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
Kojto	93:e188a91d3eaa	466	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
Kojto	93:e188a91d3eaa	467
Kojto	93:e188a91d3eaa	468	/**
Kojto	93:e188a91d3eaa	469	* @brief Bit definition of TDES1 register
Kojto	93:e188a91d3eaa	470	*/
Kojto	93:e188a91d3eaa	471	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
Kojto	93:e188a91d3eaa	472	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
Kojto	93:e188a91d3eaa	473
Kojto	93:e188a91d3eaa	474	/**
Kojto	93:e188a91d3eaa	475	* @brief Bit definition of TDES2 register
Kojto	93:e188a91d3eaa	476	*/
Kojto	93:e188a91d3eaa	477	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
Kojto	93:e188a91d3eaa	478
Kojto	93:e188a91d3eaa	479	/**
Kojto	93:e188a91d3eaa	480	* @brief Bit definition of TDES3 register
Kojto	93:e188a91d3eaa	481	*/
Kojto	93:e188a91d3eaa	482	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
Kojto	93:e188a91d3eaa	483
Kojto	93:e188a91d3eaa	484	/*---------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	485	TDES6 \| Transmit Time Stamp Low [31:0] \|
Kojto	93:e188a91d3eaa	486	-----------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	487	TDES7 \| Transmit Time Stamp High [31:0] \|
Kojto	93:e188a91d3eaa	488	----------------------------------------------------------------------------------------------*/
Kojto	93:e188a91d3eaa	489
Kojto	93:e188a91d3eaa	490	/* Bit definition of TDES6 register */
Kojto	93:e188a91d3eaa	491	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
Kojto	93:e188a91d3eaa	492
Kojto	93:e188a91d3eaa	493	/* Bit definition of TDES7 register */
Kojto	93:e188a91d3eaa	494	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
Kojto	93:e188a91d3eaa	495
Kojto	93:e188a91d3eaa	496	/**
Kojto	93:e188a91d3eaa	497	* @}
Kojto	93:e188a91d3eaa	498	*/
Kojto	93:e188a91d3eaa	499
Kojto	93:e188a91d3eaa	500
Kojto	93:e188a91d3eaa	501	/** @defgroup ETH_DMA_Rx_descriptor
Kojto	93:e188a91d3eaa	502	* @{
Kojto	93:e188a91d3eaa	503	*/
Kojto	93:e188a91d3eaa	504
Kojto	93:e188a91d3eaa	505	/*
Kojto	93:e188a91d3eaa	506	DMA Rx Descriptor
Kojto	93:e188a91d3eaa	507	--------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	508	RDES0 \| OWN(31) \| Status [30:0] \|
Kojto	93:e188a91d3eaa	509	---------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	510	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
Kojto	93:e188a91d3eaa	511	---------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	512	RDES2 \| Buffer1 Address [31:0] \|
Kojto	93:e188a91d3eaa	513	---------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	514	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
Kojto	93:e188a91d3eaa	515	---------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	516	*/
Kojto	93:e188a91d3eaa	517
Kojto	93:e188a91d3eaa	518	/**
Kojto	93:e188a91d3eaa	519	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
Kojto	93:e188a91d3eaa	520	*/
Kojto	93:e188a91d3eaa	521	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
Kojto	93:e188a91d3eaa	522	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
Kojto	93:e188a91d3eaa	523	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
Kojto	93:e188a91d3eaa	524	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
Kojto	93:e188a91d3eaa	525	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
Kojto	93:e188a91d3eaa	526	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
Kojto	93:e188a91d3eaa	527	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
Kojto	93:e188a91d3eaa	528	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
Kojto	93:e188a91d3eaa	529	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
Kojto	93:e188a91d3eaa	530	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
Kojto	93:e188a91d3eaa	531	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
Kojto	93:e188a91d3eaa	532	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
Kojto	93:e188a91d3eaa	533	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
Kojto	93:e188a91d3eaa	534	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
Kojto	93:e188a91d3eaa	535	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
Kojto	93:e188a91d3eaa	536	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
Kojto	93:e188a91d3eaa	537	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
Kojto	93:e188a91d3eaa	538	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
Kojto	93:e188a91d3eaa	539	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
Kojto	93:e188a91d3eaa	540
Kojto	93:e188a91d3eaa	541	/**
Kojto	93:e188a91d3eaa	542	* @brief Bit definition of RDES1 register
Kojto	93:e188a91d3eaa	543	*/
Kojto	93:e188a91d3eaa	544	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
Kojto	93:e188a91d3eaa	545	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
Kojto	93:e188a91d3eaa	546	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
Kojto	93:e188a91d3eaa	547	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
Kojto	93:e188a91d3eaa	548	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
Kojto	93:e188a91d3eaa	549
Kojto	93:e188a91d3eaa	550	/**
Kojto	93:e188a91d3eaa	551	* @brief Bit definition of RDES2 register
Kojto	93:e188a91d3eaa	552	*/
Kojto	93:e188a91d3eaa	553	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
Kojto	93:e188a91d3eaa	554
Kojto	93:e188a91d3eaa	555	/**
Kojto	93:e188a91d3eaa	556	* @brief Bit definition of RDES3 register
Kojto	93:e188a91d3eaa	557	*/
Kojto	93:e188a91d3eaa	558	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
Kojto	93:e188a91d3eaa	559
Kojto	93:e188a91d3eaa	560	/*---------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	561	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
Kojto	93:e188a91d3eaa	562	---------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	563	RDES5 \| Reserved[31:0] \|
Kojto	93:e188a91d3eaa	564	---------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	565	RDES6 \| Receive Time Stamp Low [31:0] \|
Kojto	93:e188a91d3eaa	566	---------------------------------------------------------------------------------------------------------------------
Kojto	93:e188a91d3eaa	567	RDES7 \| Receive Time Stamp High [31:0] \|
Kojto	93:e188a91d3eaa	568	--------------------------------------------------------------------------------------------------------------------*/
Kojto	93:e188a91d3eaa	569
Kojto	93:e188a91d3eaa	570	/* Bit definition of RDES4 register */
Kojto	93:e188a91d3eaa	571	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
Kojto	93:e188a91d3eaa	572	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
Kojto	93:e188a91d3eaa	573	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
Kojto	93:e188a91d3eaa	574	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
Kojto	93:e188a91d3eaa	575	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
Kojto	93:e188a91d3eaa	576	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
Kojto	93:e188a91d3eaa	577	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
Kojto	93:e188a91d3eaa	578	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
Kojto	93:e188a91d3eaa	579	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
Kojto	93:e188a91d3eaa	580	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
Kojto	93:e188a91d3eaa	581	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
Kojto	93:e188a91d3eaa	582	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
Kojto	93:e188a91d3eaa	583	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
Kojto	93:e188a91d3eaa	584	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
Kojto	93:e188a91d3eaa	585	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
Kojto	93:e188a91d3eaa	586	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
Kojto	93:e188a91d3eaa	587	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
Kojto	93:e188a91d3eaa	588	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
Kojto	93:e188a91d3eaa	589	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
Kojto	93:e188a91d3eaa	590
Kojto	93:e188a91d3eaa	591	/* Bit definition of RDES6 register */
Kojto	93:e188a91d3eaa	592	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
Kojto	93:e188a91d3eaa	593
Kojto	93:e188a91d3eaa	594	/* Bit definition of RDES7 register */
Kojto	93:e188a91d3eaa	595	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
Kojto	93:e188a91d3eaa	596
Kojto	93:e188a91d3eaa	597
Kojto	93:e188a91d3eaa	598	/** @defgroup ETH_AutoNegotiation
Kojto	93:e188a91d3eaa	599	* @{
Kojto	93:e188a91d3eaa	600	*/
Kojto	93:e188a91d3eaa	601	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	602	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	603	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	604	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
Kojto	93:e188a91d3eaa	605	/**
Kojto	93:e188a91d3eaa	606	* @}
Kojto	93:e188a91d3eaa	607	*/
Kojto	93:e188a91d3eaa	608	/** @defgroup ETH_Speed
Kojto	93:e188a91d3eaa	609	* @{
Kojto	93:e188a91d3eaa	610	*/
Kojto	93:e188a91d3eaa	611	#define ETH_SPEED_10M ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	612	#define ETH_SPEED_100M ((uint32_t)0x00004000)
Kojto	93:e188a91d3eaa	613	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
Kojto	93:e188a91d3eaa	614	((SPEED) == ETH_SPEED_100M))
Kojto	93:e188a91d3eaa	615	/**
Kojto	93:e188a91d3eaa	616	* @}
Kojto	93:e188a91d3eaa	617	*/
Kojto	93:e188a91d3eaa	618	/** @defgroup ETH_Duplex_Mode
Kojto	93:e188a91d3eaa	619	* @{
Kojto	93:e188a91d3eaa	620	*/
Kojto	93:e188a91d3eaa	621	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
Kojto	93:e188a91d3eaa	622	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	623	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
Kojto	93:e188a91d3eaa	624	((MODE) == ETH_MODE_HALFDUPLEX))
Kojto	93:e188a91d3eaa	625	/**
Kojto	93:e188a91d3eaa	626	* @}
Kojto	93:e188a91d3eaa	627	*/
Kojto	93:e188a91d3eaa	628	/** @defgroup ETH_Rx_Mode
Kojto	93:e188a91d3eaa	629	* @{
Kojto	93:e188a91d3eaa	630	*/
Kojto	93:e188a91d3eaa	631	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	632	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	633	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
Kojto	93:e188a91d3eaa	634	((MODE) == ETH_RXINTERRUPT_MODE))
Kojto	93:e188a91d3eaa	635	/**
Kojto	93:e188a91d3eaa	636	* @}
Kojto	93:e188a91d3eaa	637	*/
Kojto	93:e188a91d3eaa	638
Kojto	93:e188a91d3eaa	639	/** @defgroup ETH_Checksum_Mode
Kojto	93:e188a91d3eaa	640	* @{
Kojto	93:e188a91d3eaa	641	*/
Kojto	93:e188a91d3eaa	642	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	643	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	644	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
Kojto	93:e188a91d3eaa	645	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
Kojto	93:e188a91d3eaa	646	/**
Kojto	93:e188a91d3eaa	647	* @}
Kojto	93:e188a91d3eaa	648	*/
Kojto	93:e188a91d3eaa	649
Kojto	93:e188a91d3eaa	650	/** @defgroup ETH_Media_Interface
Kojto	93:e188a91d3eaa	651	* @{
Kojto	93:e188a91d3eaa	652	*/
Kojto	93:e188a91d3eaa	653	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	654	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
Kojto	93:e188a91d3eaa	655	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
Kojto	93:e188a91d3eaa	656	((MODE) == ETH_MEDIA_INTERFACE_RMII))
Kojto	93:e188a91d3eaa	657
Kojto	93:e188a91d3eaa	658	/**
Kojto	93:e188a91d3eaa	659	* @}
Kojto	93:e188a91d3eaa	660	*/
Kojto	93:e188a91d3eaa	661
Kojto	93:e188a91d3eaa	662	/** @defgroup ETH_watchdog
Kojto	93:e188a91d3eaa	663	* @{
Kojto	93:e188a91d3eaa	664	*/
Kojto	93:e188a91d3eaa	665	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	666	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
Kojto	93:e188a91d3eaa	667	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	668	((CMD) == ETH_WATCHDOG_DISABLE))
Kojto	93:e188a91d3eaa	669
Kojto	93:e188a91d3eaa	670	/**
Kojto	93:e188a91d3eaa	671	* @}
Kojto	93:e188a91d3eaa	672	*/
Kojto	93:e188a91d3eaa	673
Kojto	93:e188a91d3eaa	674	/** @defgroup ETH_Jabber
Kojto	93:e188a91d3eaa	675	* @{
Kojto	93:e188a91d3eaa	676	*/
Kojto	93:e188a91d3eaa	677	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	678	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
Kojto	93:e188a91d3eaa	679	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	680	((CMD) == ETH_JABBER_DISABLE))
Kojto	93:e188a91d3eaa	681
Kojto	93:e188a91d3eaa	682	/**
Kojto	93:e188a91d3eaa	683	* @}
Kojto	93:e188a91d3eaa	684	*/
Kojto	93:e188a91d3eaa	685
Kojto	93:e188a91d3eaa	686	/** @defgroup ETH_Inter_Frame_Gap
Kojto	93:e188a91d3eaa	687	* @{
Kojto	93:e188a91d3eaa	688	*/
Kojto	93:e188a91d3eaa	689	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
Kojto	93:e188a91d3eaa	690	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
Kojto	93:e188a91d3eaa	691	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
Kojto	93:e188a91d3eaa	692	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
Kojto	93:e188a91d3eaa	693	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
Kojto	93:e188a91d3eaa	694	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
Kojto	93:e188a91d3eaa	695	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
Kojto	93:e188a91d3eaa	696	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
Kojto	93:e188a91d3eaa	697	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
Kojto	93:e188a91d3eaa	698	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
Kojto	93:e188a91d3eaa	699	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
Kojto	93:e188a91d3eaa	700	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
Kojto	93:e188a91d3eaa	701	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
Kojto	93:e188a91d3eaa	702	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
Kojto	93:e188a91d3eaa	703	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
Kojto	93:e188a91d3eaa	704	((GAP) == ETH_INTERFRAMEGAP_40BIT))
Kojto	93:e188a91d3eaa	705
Kojto	93:e188a91d3eaa	706	/**
Kojto	93:e188a91d3eaa	707	* @}
Kojto	93:e188a91d3eaa	708	*/
Kojto	93:e188a91d3eaa	709
Kojto	93:e188a91d3eaa	710	/** @defgroup ETH_Carrier_Sense
Kojto	93:e188a91d3eaa	711	* @{
Kojto	93:e188a91d3eaa	712	*/
Kojto	93:e188a91d3eaa	713	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	714	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
Kojto	93:e188a91d3eaa	715	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	716	((CMD) == ETH_CARRIERSENCE_DISABLE))
Kojto	93:e188a91d3eaa	717
Kojto	93:e188a91d3eaa	718	/**
Kojto	93:e188a91d3eaa	719	* @}
Kojto	93:e188a91d3eaa	720	*/
Kojto	93:e188a91d3eaa	721
Kojto	93:e188a91d3eaa	722	/** @defgroup ETH_Receive_Own
Kojto	93:e188a91d3eaa	723	* @{
Kojto	93:e188a91d3eaa	724	*/
Kojto	93:e188a91d3eaa	725	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	726	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
Kojto	93:e188a91d3eaa	727	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	728	((CMD) == ETH_RECEIVEOWN_DISABLE))
Kojto	93:e188a91d3eaa	729
Kojto	93:e188a91d3eaa	730	/**
Kojto	93:e188a91d3eaa	731	* @}
Kojto	93:e188a91d3eaa	732	*/
Kojto	93:e188a91d3eaa	733
Kojto	93:e188a91d3eaa	734	/** @defgroup ETH_Loop_Back_Mode
Kojto	93:e188a91d3eaa	735	* @{
Kojto	93:e188a91d3eaa	736	*/
Kojto	93:e188a91d3eaa	737	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
Kojto	93:e188a91d3eaa	738	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	739	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	740	((CMD) == ETH_LOOPBACKMODE_DISABLE))
Kojto	93:e188a91d3eaa	741
Kojto	93:e188a91d3eaa	742	/**
Kojto	93:e188a91d3eaa	743	* @}
Kojto	93:e188a91d3eaa	744	*/
Kojto	93:e188a91d3eaa	745
Kojto	93:e188a91d3eaa	746	/** @defgroup ETH_Checksum_Offload
Kojto	93:e188a91d3eaa	747	* @{
Kojto	93:e188a91d3eaa	748	*/
Kojto	93:e188a91d3eaa	749	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
Kojto	93:e188a91d3eaa	750	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	751	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	752	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
Kojto	93:e188a91d3eaa	753
Kojto	93:e188a91d3eaa	754	/**
Kojto	93:e188a91d3eaa	755	* @}
Kojto	93:e188a91d3eaa	756	*/
Kojto	93:e188a91d3eaa	757
Kojto	93:e188a91d3eaa	758	/** @defgroup ETH_Retry_Transmission
Kojto	93:e188a91d3eaa	759	* @{
Kojto	93:e188a91d3eaa	760	*/
Kojto	93:e188a91d3eaa	761	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	762	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
Kojto	93:e188a91d3eaa	763	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	764	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
Kojto	93:e188a91d3eaa	765
Kojto	93:e188a91d3eaa	766	/**
Kojto	93:e188a91d3eaa	767	* @}
Kojto	93:e188a91d3eaa	768	*/
Kojto	93:e188a91d3eaa	769
Kojto	93:e188a91d3eaa	770	/** @defgroup ETH_Automatic_Pad_CRC_Strip
Kojto	93:e188a91d3eaa	771	* @{
Kojto	93:e188a91d3eaa	772	*/
Kojto	93:e188a91d3eaa	773	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
Kojto	93:e188a91d3eaa	774	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	775	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	776	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
Kojto	93:e188a91d3eaa	777
Kojto	93:e188a91d3eaa	778	/**
Kojto	93:e188a91d3eaa	779	* @}
Kojto	93:e188a91d3eaa	780	*/
Kojto	93:e188a91d3eaa	781
Kojto	93:e188a91d3eaa	782	/** @defgroup ETH_Back_Off_Limit
Kojto	93:e188a91d3eaa	783	* @{
Kojto	93:e188a91d3eaa	784	*/
Kojto	93:e188a91d3eaa	785	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	786	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
Kojto	93:e188a91d3eaa	787	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
Kojto	93:e188a91d3eaa	788	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
Kojto	93:e188a91d3eaa	789	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
Kojto	93:e188a91d3eaa	790	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
Kojto	93:e188a91d3eaa	791	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
Kojto	93:e188a91d3eaa	792	((LIMIT) == ETH_BACKOFFLIMIT_1))
Kojto	93:e188a91d3eaa	793
Kojto	93:e188a91d3eaa	794	/**
Kojto	93:e188a91d3eaa	795	* @}
Kojto	93:e188a91d3eaa	796	*/
Kojto	93:e188a91d3eaa	797
Kojto	93:e188a91d3eaa	798	/** @defgroup ETH_Deferral_Check
Kojto	93:e188a91d3eaa	799	* @{
Kojto	93:e188a91d3eaa	800	*/
Kojto	93:e188a91d3eaa	801	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
Kojto	93:e188a91d3eaa	802	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	803	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	804	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
Kojto	93:e188a91d3eaa	805
Kojto	93:e188a91d3eaa	806	/**
Kojto	93:e188a91d3eaa	807	* @}
Kojto	93:e188a91d3eaa	808	*/
Kojto	93:e188a91d3eaa	809
Kojto	93:e188a91d3eaa	810	/** @defgroup ETH_Receive_All
Kojto	93:e188a91d3eaa	811	* @{
Kojto	93:e188a91d3eaa	812	*/
Kojto	93:e188a91d3eaa	813	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
Kojto	93:e188a91d3eaa	814	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	815	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	816	((CMD) == ETH_RECEIVEAll_DISABLE))
Kojto	93:e188a91d3eaa	817
Kojto	93:e188a91d3eaa	818	/**
Kojto	93:e188a91d3eaa	819	* @}
Kojto	93:e188a91d3eaa	820	*/
Kojto	93:e188a91d3eaa	821
Kojto	93:e188a91d3eaa	822	/** @defgroup ETH_Source_Addr_Filter
Kojto	93:e188a91d3eaa	823	* @{
Kojto	93:e188a91d3eaa	824	*/
Kojto	93:e188a91d3eaa	825	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
Kojto	93:e188a91d3eaa	826	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
Kojto	93:e188a91d3eaa	827	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	828	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	829	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	830	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
Kojto	93:e188a91d3eaa	831
Kojto	93:e188a91d3eaa	832	/**
Kojto	93:e188a91d3eaa	833	* @}
Kojto	93:e188a91d3eaa	834	*/
Kojto	93:e188a91d3eaa	835
Kojto	93:e188a91d3eaa	836	/** @defgroup ETH_Pass_Control_Frames
Kojto	93:e188a91d3eaa	837	* @{
Kojto	93:e188a91d3eaa	838	*/
Kojto	93:e188a91d3eaa	839	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
Kojto	93:e188a91d3eaa	840	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
Kojto	93:e188a91d3eaa	841	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
Kojto	93:e188a91d3eaa	842	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
Kojto	93:e188a91d3eaa	843	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
Kojto	93:e188a91d3eaa	844	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
Kojto	93:e188a91d3eaa	845
Kojto	93:e188a91d3eaa	846	/**
Kojto	93:e188a91d3eaa	847	* @}
Kojto	93:e188a91d3eaa	848	*/
Kojto	93:e188a91d3eaa	849
Kojto	93:e188a91d3eaa	850	/** @defgroup ETH_Broadcast_Frames_Reception
Kojto	93:e188a91d3eaa	851	* @{
Kojto	93:e188a91d3eaa	852	*/
Kojto	93:e188a91d3eaa	853	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	854	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
Kojto	93:e188a91d3eaa	855	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	856	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
Kojto	93:e188a91d3eaa	857
Kojto	93:e188a91d3eaa	858	/**
Kojto	93:e188a91d3eaa	859	* @}
Kojto	93:e188a91d3eaa	860	*/
Kojto	93:e188a91d3eaa	861
Kojto	93:e188a91d3eaa	862	/** @defgroup ETH_Destination_Addr_Filter
Kojto	93:e188a91d3eaa	863	* @{
Kojto	93:e188a91d3eaa	864	*/
Kojto	93:e188a91d3eaa	865	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	866	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
Kojto	93:e188a91d3eaa	867	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
Kojto	93:e188a91d3eaa	868	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
Kojto	93:e188a91d3eaa	869
Kojto	93:e188a91d3eaa	870	/**
Kojto	93:e188a91d3eaa	871	* @}
Kojto	93:e188a91d3eaa	872	*/
Kojto	93:e188a91d3eaa	873
Kojto	93:e188a91d3eaa	874	/** @defgroup ETH_Promiscuous_Mode
Kojto	93:e188a91d3eaa	875	* @{
Kojto	93:e188a91d3eaa	876	*/
Kojto	93:e188a91d3eaa	877	#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	878	#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	879	#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	880	((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
Kojto	93:e188a91d3eaa	881
Kojto	93:e188a91d3eaa	882	/**
Kojto	93:e188a91d3eaa	883	* @}
Kojto	93:e188a91d3eaa	884	*/
Kojto	93:e188a91d3eaa	885
Kojto	93:e188a91d3eaa	886	/** @defgroup ETH_Multicast_Frames_Filter
Kojto	93:e188a91d3eaa	887	* @{
Kojto	93:e188a91d3eaa	888	*/
Kojto	93:e188a91d3eaa	889	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
Kojto	93:e188a91d3eaa	890	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
Kojto	93:e188a91d3eaa	891	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	892	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
Kojto	93:e188a91d3eaa	893	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
Kojto	93:e188a91d3eaa	894	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
Kojto	93:e188a91d3eaa	895	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
Kojto	93:e188a91d3eaa	896	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
Kojto	93:e188a91d3eaa	897	/**
Kojto	93:e188a91d3eaa	898	* @}
Kojto	93:e188a91d3eaa	899	*/
Kojto	93:e188a91d3eaa	900
Kojto	93:e188a91d3eaa	901	/** @defgroup ETH_Unicast_Frames_Filter
Kojto	93:e188a91d3eaa	902	* @{
Kojto	93:e188a91d3eaa	903	*/
Kojto	93:e188a91d3eaa	904	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
Kojto	93:e188a91d3eaa	905	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
Kojto	93:e188a91d3eaa	906	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	907	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
Kojto	93:e188a91d3eaa	908	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
Kojto	93:e188a91d3eaa	909	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
Kojto	93:e188a91d3eaa	910	/**
Kojto	93:e188a91d3eaa	911	* @}
Kojto	93:e188a91d3eaa	912	*/
Kojto	93:e188a91d3eaa	913
Kojto	93:e188a91d3eaa	914	/** @defgroup ETH_Pause_Time
Kojto	93:e188a91d3eaa	915	* @{
Kojto	93:e188a91d3eaa	916	*/
Kojto	93:e188a91d3eaa	917	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
Kojto	93:e188a91d3eaa	918
Kojto	93:e188a91d3eaa	919	/**
Kojto	93:e188a91d3eaa	920	* @}
Kojto	93:e188a91d3eaa	921	*/
Kojto	93:e188a91d3eaa	922
Kojto	93:e188a91d3eaa	923	/** @defgroup ETH_Zero_Quanta_Pause
Kojto	93:e188a91d3eaa	924	* @{
Kojto	93:e188a91d3eaa	925	*/
Kojto	93:e188a91d3eaa	926	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	927	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
Kojto	93:e188a91d3eaa	928	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	929	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
Kojto	93:e188a91d3eaa	930	/**
Kojto	93:e188a91d3eaa	931	* @}
Kojto	93:e188a91d3eaa	932	*/
Kojto	93:e188a91d3eaa	933
Kojto	93:e188a91d3eaa	934	/** @defgroup ETH_Pause_Low_Threshold
Kojto	93:e188a91d3eaa	935	* @{
Kojto	93:e188a91d3eaa	936	*/
Kojto	93:e188a91d3eaa	937	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
Kojto	93:e188a91d3eaa	938	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
Kojto	93:e188a91d3eaa	939	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
Kojto	93:e188a91d3eaa	940	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
Kojto	93:e188a91d3eaa	941	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
Kojto	93:e188a91d3eaa	942	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
Kojto	93:e188a91d3eaa	943	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
Kojto	93:e188a91d3eaa	944	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
Kojto	93:e188a91d3eaa	945	/**
Kojto	93:e188a91d3eaa	946	* @}
Kojto	93:e188a91d3eaa	947	*/
Kojto	93:e188a91d3eaa	948
Kojto	93:e188a91d3eaa	949	/** @defgroup ETH_Unicast_Pause_Frame_Detect
Kojto	93:e188a91d3eaa	950	* @{
Kojto	93:e188a91d3eaa	951	*/
Kojto	93:e188a91d3eaa	952	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
Kojto	93:e188a91d3eaa	953	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	954	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	955	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
Kojto	93:e188a91d3eaa	956	/**
Kojto	93:e188a91d3eaa	957	* @}
Kojto	93:e188a91d3eaa	958	*/
Kojto	93:e188a91d3eaa	959
Kojto	93:e188a91d3eaa	960	/** @defgroup ETH_Receive_Flow_Control
Kojto	93:e188a91d3eaa	961	* @{
Kojto	93:e188a91d3eaa	962	*/
Kojto	93:e188a91d3eaa	963	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
Kojto	93:e188a91d3eaa	964	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	965	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	966	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
Kojto	93:e188a91d3eaa	967	/**
Kojto	93:e188a91d3eaa	968	* @}
Kojto	93:e188a91d3eaa	969	*/
Kojto	93:e188a91d3eaa	970
Kojto	93:e188a91d3eaa	971	/** @defgroup ETH_Transmit_Flow_Control
Kojto	93:e188a91d3eaa	972	* @{
Kojto	93:e188a91d3eaa	973	*/
Kojto	93:e188a91d3eaa	974	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
Kojto	93:e188a91d3eaa	975	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	976	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	977	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
Kojto	93:e188a91d3eaa	978	/**
Kojto	93:e188a91d3eaa	979	* @}
Kojto	93:e188a91d3eaa	980	*/
Kojto	93:e188a91d3eaa	981
Kojto	93:e188a91d3eaa	982	/** @defgroup ETH_VLAN_Tag_Comparison
Kojto	93:e188a91d3eaa	983	* @{
Kojto	93:e188a91d3eaa	984	*/
Kojto	93:e188a91d3eaa	985	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
Kojto	93:e188a91d3eaa	986	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	987	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
Kojto	93:e188a91d3eaa	988	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
Kojto	93:e188a91d3eaa	989	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
Kojto	93:e188a91d3eaa	990
Kojto	93:e188a91d3eaa	991	/**
Kojto	93:e188a91d3eaa	992	* @}
Kojto	93:e188a91d3eaa	993	*/
Kojto	93:e188a91d3eaa	994
Kojto	93:e188a91d3eaa	995	/** @defgroup ETH_MAC_addresses
Kojto	93:e188a91d3eaa	996	* @{
Kojto	93:e188a91d3eaa	997	*/
Kojto	93:e188a91d3eaa	998	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	999	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
Kojto	93:e188a91d3eaa	1000	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
Kojto	93:e188a91d3eaa	1001	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
Kojto	93:e188a91d3eaa	1002	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
Kojto	93:e188a91d3eaa	1003	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
Kojto	93:e188a91d3eaa	1004	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
Kojto	93:e188a91d3eaa	1005	((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto	93:e188a91d3eaa	1006	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
Kojto	93:e188a91d3eaa	1007	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
Kojto	93:e188a91d3eaa	1008	((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto	93:e188a91d3eaa	1009	/**
Kojto	93:e188a91d3eaa	1010	* @}
Kojto	93:e188a91d3eaa	1011	*/
Kojto	93:e188a91d3eaa	1012
Kojto	93:e188a91d3eaa	1013	/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
Kojto	93:e188a91d3eaa	1014	* @{
Kojto	93:e188a91d3eaa	1015	*/
Kojto	93:e188a91d3eaa	1016	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1017	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
Kojto	93:e188a91d3eaa	1018	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
Kojto	93:e188a91d3eaa	1019	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
Kojto	93:e188a91d3eaa	1020	/**
Kojto	93:e188a91d3eaa	1021	* @}
Kojto	93:e188a91d3eaa	1022	*/
Kojto	93:e188a91d3eaa	1023
Kojto	93:e188a91d3eaa	1024	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
Kojto	93:e188a91d3eaa	1025	* @{
Kojto	93:e188a91d3eaa	1026	*/
Kojto	93:e188a91d3eaa	1027	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
Kojto	93:e188a91d3eaa	1028	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
Kojto	93:e188a91d3eaa	1029	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
Kojto	93:e188a91d3eaa	1030	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
Kojto	93:e188a91d3eaa	1031	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
Kojto	93:e188a91d3eaa	1032	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
Kojto	93:e188a91d3eaa	1033	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
Kojto	93:e188a91d3eaa	1034	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
Kojto	93:e188a91d3eaa	1035	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
Kojto	93:e188a91d3eaa	1036	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
Kojto	93:e188a91d3eaa	1037	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
Kojto	93:e188a91d3eaa	1038	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
Kojto	93:e188a91d3eaa	1039
Kojto	93:e188a91d3eaa	1040	/**
Kojto	93:e188a91d3eaa	1041	* @}
Kojto	93:e188a91d3eaa	1042	*/
Kojto	93:e188a91d3eaa	1043
Kojto	93:e188a91d3eaa	1044	/** @defgroup ETH_MAC_Debug_flags
Kojto	93:e188a91d3eaa	1045	* @{
Kojto	93:e188a91d3eaa	1046	*/
Kojto	93:e188a91d3eaa	1047	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
Kojto	93:e188a91d3eaa	1048
Kojto	93:e188a91d3eaa	1049	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
Kojto	93:e188a91d3eaa	1050
Kojto	93:e188a91d3eaa	1051	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
Kojto	93:e188a91d3eaa	1052
Kojto	93:e188a91d3eaa	1053	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
Kojto	93:e188a91d3eaa	1054	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
Kojto	93:e188a91d3eaa	1055	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
Kojto	93:e188a91d3eaa	1056	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
Kojto	93:e188a91d3eaa	1057
Kojto	93:e188a91d3eaa	1058	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
Kojto	93:e188a91d3eaa	1059
Kojto	93:e188a91d3eaa	1060	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
Kojto	93:e188a91d3eaa	1061	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
Kojto	93:e188a91d3eaa	1062	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
Kojto	93:e188a91d3eaa	1063	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
Kojto	93:e188a91d3eaa	1064
Kojto	93:e188a91d3eaa	1065	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
Kojto	93:e188a91d3eaa	1066
Kojto	93:e188a91d3eaa	1067	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
Kojto	93:e188a91d3eaa	1068	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
Kojto	93:e188a91d3eaa	1069	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
Kojto	93:e188a91d3eaa	1070	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
Kojto	93:e188a91d3eaa	1071
Kojto	93:e188a91d3eaa	1072	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
Kojto	93:e188a91d3eaa	1073	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
Kojto	93:e188a91d3eaa	1074	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
Kojto	93:e188a91d3eaa	1075	#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
Kojto	93:e188a91d3eaa	1076
Kojto	93:e188a91d3eaa	1077	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
Kojto	93:e188a91d3eaa	1078
Kojto	93:e188a91d3eaa	1079	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
Kojto	93:e188a91d3eaa	1080	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
Kojto	93:e188a91d3eaa	1081	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
Kojto	93:e188a91d3eaa	1082	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto	93:e188a91d3eaa	1083
Kojto	93:e188a91d3eaa	1084	#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
Kojto	93:e188a91d3eaa	1085
Kojto	93:e188a91d3eaa	1086	/**
Kojto	93:e188a91d3eaa	1087	* @}
Kojto	93:e188a91d3eaa	1088	*/
Kojto	93:e188a91d3eaa	1089
Kojto	93:e188a91d3eaa	1090	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
Kojto	93:e188a91d3eaa	1091	* @{
Kojto	93:e188a91d3eaa	1092	*/
Kojto	93:e188a91d3eaa	1093	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1094	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
Kojto	93:e188a91d3eaa	1095	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1096	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
Kojto	93:e188a91d3eaa	1097	/**
Kojto	93:e188a91d3eaa	1098	* @}
Kojto	93:e188a91d3eaa	1099	*/
Kojto	93:e188a91d3eaa	1100
Kojto	93:e188a91d3eaa	1101	/** @defgroup ETH_Receive_Store_Forward
Kojto	93:e188a91d3eaa	1102	* @{
Kojto	93:e188a91d3eaa	1103	*/
Kojto	93:e188a91d3eaa	1104	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
Kojto	93:e188a91d3eaa	1105	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1106	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1107	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
Kojto	93:e188a91d3eaa	1108	/**
Kojto	93:e188a91d3eaa	1109	* @}
Kojto	93:e188a91d3eaa	1110	*/
Kojto	93:e188a91d3eaa	1111
Kojto	93:e188a91d3eaa	1112	/** @defgroup ETH_Flush_Received_Frame
Kojto	93:e188a91d3eaa	1113	* @{
Kojto	93:e188a91d3eaa	1114	*/
Kojto	93:e188a91d3eaa	1115	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1116	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
Kojto	93:e188a91d3eaa	1117	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1118	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
Kojto	93:e188a91d3eaa	1119	/**
Kojto	93:e188a91d3eaa	1120	* @}
Kojto	93:e188a91d3eaa	1121	*/
Kojto	93:e188a91d3eaa	1122
Kojto	93:e188a91d3eaa	1123	/** @defgroup ETH_Transmit_Store_Forward
Kojto	93:e188a91d3eaa	1124	* @{
Kojto	93:e188a91d3eaa	1125	*/
Kojto	93:e188a91d3eaa	1126	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
Kojto	93:e188a91d3eaa	1127	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1128	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1129	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
Kojto	93:e188a91d3eaa	1130	/**
Kojto	93:e188a91d3eaa	1131	* @}
Kojto	93:e188a91d3eaa	1132	*/
Kojto	93:e188a91d3eaa	1133
Kojto	93:e188a91d3eaa	1134	/** @defgroup ETH_Transmit_Threshold_Control
Kojto	93:e188a91d3eaa	1135	* @{
Kojto	93:e188a91d3eaa	1136	*/
Kojto	93:e188a91d3eaa	1137	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
Kojto	93:e188a91d3eaa	1138	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
Kojto	93:e188a91d3eaa	1139	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
Kojto	93:e188a91d3eaa	1140	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
Kojto	93:e188a91d3eaa	1141	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
Kojto	93:e188a91d3eaa	1142	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
Kojto	93:e188a91d3eaa	1143	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
Kojto	93:e188a91d3eaa	1144	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
Kojto	93:e188a91d3eaa	1145	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
Kojto	93:e188a91d3eaa	1146	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
Kojto	93:e188a91d3eaa	1147	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
Kojto	93:e188a91d3eaa	1148	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
Kojto	93:e188a91d3eaa	1149	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
Kojto	93:e188a91d3eaa	1150	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
Kojto	93:e188a91d3eaa	1151	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
Kojto	93:e188a91d3eaa	1152	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
Kojto	93:e188a91d3eaa	1153	/**
Kojto	93:e188a91d3eaa	1154	* @}
Kojto	93:e188a91d3eaa	1155	*/
Kojto	93:e188a91d3eaa	1156
Kojto	93:e188a91d3eaa	1157	/** @defgroup ETH_Forward_Error_Frames
Kojto	93:e188a91d3eaa	1158	* @{
Kojto	93:e188a91d3eaa	1159	*/
Kojto	93:e188a91d3eaa	1160	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
Kojto	93:e188a91d3eaa	1161	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1162	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1163	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
Kojto	93:e188a91d3eaa	1164	/**
Kojto	93:e188a91d3eaa	1165	* @}
Kojto	93:e188a91d3eaa	1166	*/
Kojto	93:e188a91d3eaa	1167
Kojto	93:e188a91d3eaa	1168	/** @defgroup ETH_Forward_Undersized_Good_Frames
Kojto	93:e188a91d3eaa	1169	* @{
Kojto	93:e188a91d3eaa	1170	*/
Kojto	93:e188a91d3eaa	1171	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
Kojto	93:e188a91d3eaa	1172	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1173	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1174	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
Kojto	93:e188a91d3eaa	1175
Kojto	93:e188a91d3eaa	1176	/**
Kojto	93:e188a91d3eaa	1177	* @}
Kojto	93:e188a91d3eaa	1178	*/
Kojto	93:e188a91d3eaa	1179
Kojto	93:e188a91d3eaa	1180	/** @defgroup ETH_Receive_Threshold_Control
Kojto	93:e188a91d3eaa	1181	* @{
Kojto	93:e188a91d3eaa	1182	*/
Kojto	93:e188a91d3eaa	1183	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
Kojto	93:e188a91d3eaa	1184	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
Kojto	93:e188a91d3eaa	1185	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
Kojto	93:e188a91d3eaa	1186	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
Kojto	93:e188a91d3eaa	1187	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
Kojto	93:e188a91d3eaa	1188	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
Kojto	93:e188a91d3eaa	1189	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
Kojto	93:e188a91d3eaa	1190	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
Kojto	93:e188a91d3eaa	1191	/**
Kojto	93:e188a91d3eaa	1192	* @}
Kojto	93:e188a91d3eaa	1193	*/
Kojto	93:e188a91d3eaa	1194
Kojto	93:e188a91d3eaa	1195	/** @defgroup ETH_Second_Frame_Operate
Kojto	93:e188a91d3eaa	1196	* @{
Kojto	93:e188a91d3eaa	1197	*/
Kojto	93:e188a91d3eaa	1198	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
Kojto	93:e188a91d3eaa	1199	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1200	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1201	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
Kojto	93:e188a91d3eaa	1202
Kojto	93:e188a91d3eaa	1203	/**
Kojto	93:e188a91d3eaa	1204	* @}
Kojto	93:e188a91d3eaa	1205	*/
Kojto	93:e188a91d3eaa	1206
Kojto	93:e188a91d3eaa	1207	/** @defgroup ETH_Address_Aligned_Beats
Kojto	93:e188a91d3eaa	1208	* @{
Kojto	93:e188a91d3eaa	1209	*/
Kojto	93:e188a91d3eaa	1210	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
Kojto	93:e188a91d3eaa	1211	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1212	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1213	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
Kojto	93:e188a91d3eaa	1214
Kojto	93:e188a91d3eaa	1215	/**
Kojto	93:e188a91d3eaa	1216	* @}
Kojto	93:e188a91d3eaa	1217	*/
Kojto	93:e188a91d3eaa	1218
Kojto	93:e188a91d3eaa	1219	/** @defgroup ETH_Fixed_Burst
Kojto	93:e188a91d3eaa	1220	* @{
Kojto	93:e188a91d3eaa	1221	*/
Kojto	93:e188a91d3eaa	1222	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
Kojto	93:e188a91d3eaa	1223	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1224	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1225	((CMD) == ETH_FIXEDBURST_DISABLE))
Kojto	93:e188a91d3eaa	1226
Kojto	93:e188a91d3eaa	1227	/**
Kojto	93:e188a91d3eaa	1228	* @}
Kojto	93:e188a91d3eaa	1229	*/
Kojto	93:e188a91d3eaa	1230
Kojto	93:e188a91d3eaa	1231	/** @defgroup ETH_Rx_DMA_Burst_Length
Kojto	93:e188a91d3eaa	1232	* @{
Kojto	93:e188a91d3eaa	1233	*/
Kojto	93:e188a91d3eaa	1234	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
Kojto	93:e188a91d3eaa	1235	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
Kojto	93:e188a91d3eaa	1236	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
Kojto	93:e188a91d3eaa	1237	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
Kojto	93:e188a91d3eaa	1238	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
Kojto	93:e188a91d3eaa	1239	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
Kojto	93:e188a91d3eaa	1240	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
Kojto	93:e188a91d3eaa	1241	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
Kojto	93:e188a91d3eaa	1242	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
Kojto	93:e188a91d3eaa	1243	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
Kojto	93:e188a91d3eaa	1244	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
Kojto	93:e188a91d3eaa	1245	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
Kojto	93:e188a91d3eaa	1246
Kojto	93:e188a91d3eaa	1247	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
Kojto	93:e188a91d3eaa	1248	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
Kojto	93:e188a91d3eaa	1249	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
Kojto	93:e188a91d3eaa	1250	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
Kojto	93:e188a91d3eaa	1251	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
Kojto	93:e188a91d3eaa	1252	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
Kojto	93:e188a91d3eaa	1253	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
Kojto	93:e188a91d3eaa	1254	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
Kojto	93:e188a91d3eaa	1255	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
Kojto	93:e188a91d3eaa	1256	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
Kojto	93:e188a91d3eaa	1257	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
Kojto	93:e188a91d3eaa	1258	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto	93:e188a91d3eaa	1259
Kojto	93:e188a91d3eaa	1260	/**
Kojto	93:e188a91d3eaa	1261	* @}
Kojto	93:e188a91d3eaa	1262	*/
Kojto	93:e188a91d3eaa	1263
Kojto	93:e188a91d3eaa	1264	/** @defgroup ETH_Tx_DMA_Burst_Length
Kojto	93:e188a91d3eaa	1265	* @{
Kojto	93:e188a91d3eaa	1266	*/
Kojto	93:e188a91d3eaa	1267	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
Kojto	93:e188a91d3eaa	1268	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
Kojto	93:e188a91d3eaa	1269	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
Kojto	93:e188a91d3eaa	1270	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
Kojto	93:e188a91d3eaa	1271	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
Kojto	93:e188a91d3eaa	1272	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
Kojto	93:e188a91d3eaa	1273	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
Kojto	93:e188a91d3eaa	1274	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
Kojto	93:e188a91d3eaa	1275	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
Kojto	93:e188a91d3eaa	1276	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
Kojto	93:e188a91d3eaa	1277	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
Kojto	93:e188a91d3eaa	1278	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
Kojto	93:e188a91d3eaa	1279
Kojto	93:e188a91d3eaa	1280	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
Kojto	93:e188a91d3eaa	1281	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
Kojto	93:e188a91d3eaa	1282	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
Kojto	93:e188a91d3eaa	1283	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
Kojto	93:e188a91d3eaa	1284	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
Kojto	93:e188a91d3eaa	1285	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
Kojto	93:e188a91d3eaa	1286	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
Kojto	93:e188a91d3eaa	1287	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
Kojto	93:e188a91d3eaa	1288	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
Kojto	93:e188a91d3eaa	1289	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
Kojto	93:e188a91d3eaa	1290	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
Kojto	93:e188a91d3eaa	1291	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto	93:e188a91d3eaa	1292
Kojto	93:e188a91d3eaa	1293	/** @defgroup ETH_DMA_Enhanced_descriptor_format
Kojto	93:e188a91d3eaa	1294	* @{
Kojto	93:e188a91d3eaa	1295	*/
Kojto	93:e188a91d3eaa	1296	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
Kojto	93:e188a91d3eaa	1297	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1298
Kojto	93:e188a91d3eaa	1299	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
Kojto	93:e188a91d3eaa	1300	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
Kojto	93:e188a91d3eaa	1301
Kojto	93:e188a91d3eaa	1302	/**
Kojto	93:e188a91d3eaa	1303	* @}
Kojto	93:e188a91d3eaa	1304	*/
Kojto	93:e188a91d3eaa	1305
Kojto	93:e188a91d3eaa	1306	/**
Kojto	93:e188a91d3eaa	1307	* @brief ETH DMA Descriptor SkipLength
Kojto	93:e188a91d3eaa	1308	*/
Kojto	93:e188a91d3eaa	1309	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
Kojto	93:e188a91d3eaa	1310
Kojto	93:e188a91d3eaa	1311
Kojto	93:e188a91d3eaa	1312	/** @defgroup ETH_DMA_Arbitration
Kojto	93:e188a91d3eaa	1313	* @{
Kojto	93:e188a91d3eaa	1314	*/
Kojto	93:e188a91d3eaa	1315	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	1316	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
Kojto	93:e188a91d3eaa	1317	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
Kojto	93:e188a91d3eaa	1318	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
Kojto	93:e188a91d3eaa	1319	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
Kojto	93:e188a91d3eaa	1320	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
Kojto	93:e188a91d3eaa	1321	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
Kojto	93:e188a91d3eaa	1322	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
Kojto	93:e188a91d3eaa	1323	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
Kojto	93:e188a91d3eaa	1324	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
Kojto	93:e188a91d3eaa	1325	/**
Kojto	93:e188a91d3eaa	1326	* @}
Kojto	93:e188a91d3eaa	1327	*/
Kojto	93:e188a91d3eaa	1328
Kojto	93:e188a91d3eaa	1329	/** @defgroup ETH_DMA_Tx_descriptor_flags
Kojto	93:e188a91d3eaa	1330	* @{
Kojto	93:e188a91d3eaa	1331	*/
Kojto	93:e188a91d3eaa	1332	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
Kojto	93:e188a91d3eaa	1333	((FLAG) == ETH_DMATXDESC_IC) \|\| \
Kojto	93:e188a91d3eaa	1334	((FLAG) == ETH_DMATXDESC_LS) \|\| \
Kojto	93:e188a91d3eaa	1335	((FLAG) == ETH_DMATXDESC_FS) \|\| \
Kojto	93:e188a91d3eaa	1336	((FLAG) == ETH_DMATXDESC_DC) \|\| \
Kojto	93:e188a91d3eaa	1337	((FLAG) == ETH_DMATXDESC_DP) \|\| \
Kojto	93:e188a91d3eaa	1338	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
Kojto	93:e188a91d3eaa	1339	((FLAG) == ETH_DMATXDESC_TER) \|\| \
Kojto	93:e188a91d3eaa	1340	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
Kojto	93:e188a91d3eaa	1341	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
Kojto	93:e188a91d3eaa	1342	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
Kojto	93:e188a91d3eaa	1343	((FLAG) == ETH_DMATXDESC_ES) \|\| \
Kojto	93:e188a91d3eaa	1344	((FLAG) == ETH_DMATXDESC_JT) \|\| \
Kojto	93:e188a91d3eaa	1345	((FLAG) == ETH_DMATXDESC_FF) \|\| \
Kojto	93:e188a91d3eaa	1346	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
Kojto	93:e188a91d3eaa	1347	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
Kojto	93:e188a91d3eaa	1348	((FLAG) == ETH_DMATXDESC_NC) \|\| \
Kojto	93:e188a91d3eaa	1349	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
Kojto	93:e188a91d3eaa	1350	((FLAG) == ETH_DMATXDESC_EC) \|\| \
Kojto	93:e188a91d3eaa	1351	((FLAG) == ETH_DMATXDESC_VF) \|\| \
Kojto	93:e188a91d3eaa	1352	((FLAG) == ETH_DMATXDESC_CC) \|\| \
Kojto	93:e188a91d3eaa	1353	((FLAG) == ETH_DMATXDESC_ED) \|\| \
Kojto	93:e188a91d3eaa	1354	((FLAG) == ETH_DMATXDESC_UF) \|\| \
Kojto	93:e188a91d3eaa	1355	((FLAG) == ETH_DMATXDESC_DB))
Kojto	93:e188a91d3eaa	1356
Kojto	93:e188a91d3eaa	1357	/**
Kojto	93:e188a91d3eaa	1358	* @}
Kojto	93:e188a91d3eaa	1359	*/
Kojto	93:e188a91d3eaa	1360
Kojto	93:e188a91d3eaa	1361	/** @defgroup ETH_DMA_Tx_descriptor_segment
Kojto	93:e188a91d3eaa	1362	* @{
Kojto	93:e188a91d3eaa	1363	*/
Kojto	93:e188a91d3eaa	1364	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
Kojto	93:e188a91d3eaa	1365	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
Kojto	93:e188a91d3eaa	1366	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
Kojto	93:e188a91d3eaa	1367	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
Kojto	93:e188a91d3eaa	1368
Kojto	93:e188a91d3eaa	1369	/**
Kojto	93:e188a91d3eaa	1370	* @}
Kojto	93:e188a91d3eaa	1371	*/
Kojto	93:e188a91d3eaa	1372
Kojto	93:e188a91d3eaa	1373	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
Kojto	93:e188a91d3eaa	1374	* @{
Kojto	93:e188a91d3eaa	1375	*/
Kojto	93:e188a91d3eaa	1376	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
Kojto	93:e188a91d3eaa	1377	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
Kojto	93:e188a91d3eaa	1378	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
Kojto	93:e188a91d3eaa	1379	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
Kojto	93:e188a91d3eaa	1380	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
Kojto	93:e188a91d3eaa	1381	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
Kojto	93:e188a91d3eaa	1382	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
Kojto	93:e188a91d3eaa	1383	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
Kojto	93:e188a91d3eaa	1384	/**
Kojto	93:e188a91d3eaa	1385	* @brief ETH DMA Tx Desciptor buffer size
Kojto	93:e188a91d3eaa	1386	*/
Kojto	93:e188a91d3eaa	1387	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
Kojto	93:e188a91d3eaa	1388
Kojto	93:e188a91d3eaa	1389	/**
Kojto	93:e188a91d3eaa	1390	* @}
Kojto	93:e188a91d3eaa	1391	*/
Kojto	93:e188a91d3eaa	1392
Kojto	93:e188a91d3eaa	1393	/** @defgroup ETH_DMA_Rx_descriptor_flags
Kojto	93:e188a91d3eaa	1394	* @{
Kojto	93:e188a91d3eaa	1395	*/
Kojto	93:e188a91d3eaa	1396	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
Kojto	93:e188a91d3eaa	1397	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
Kojto	93:e188a91d3eaa	1398	((FLAG) == ETH_DMARXDESC_ES) \|\| \
Kojto	93:e188a91d3eaa	1399	((FLAG) == ETH_DMARXDESC_DE) \|\| \
Kojto	93:e188a91d3eaa	1400	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
Kojto	93:e188a91d3eaa	1401	((FLAG) == ETH_DMARXDESC_LE) \|\| \
Kojto	93:e188a91d3eaa	1402	((FLAG) == ETH_DMARXDESC_OE) \|\| \
Kojto	93:e188a91d3eaa	1403	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
Kojto	93:e188a91d3eaa	1404	((FLAG) == ETH_DMARXDESC_FS) \|\| \
Kojto	93:e188a91d3eaa	1405	((FLAG) == ETH_DMARXDESC_LS) \|\| \
Kojto	93:e188a91d3eaa	1406	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
Kojto	93:e188a91d3eaa	1407	((FLAG) == ETH_DMARXDESC_LC) \|\| \
Kojto	93:e188a91d3eaa	1408	((FLAG) == ETH_DMARXDESC_FT) \|\| \
Kojto	93:e188a91d3eaa	1409	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
Kojto	93:e188a91d3eaa	1410	((FLAG) == ETH_DMARXDESC_RE) \|\| \
Kojto	93:e188a91d3eaa	1411	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
Kojto	93:e188a91d3eaa	1412	((FLAG) == ETH_DMARXDESC_CE) \|\| \
Kojto	93:e188a91d3eaa	1413	((FLAG) == ETH_DMARXDESC_MAMPCE))
Kojto	93:e188a91d3eaa	1414
Kojto	93:e188a91d3eaa	1415	/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
Kojto	93:e188a91d3eaa	1416	#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) \|\| \
Kojto	93:e188a91d3eaa	1417	((FLAG) == ETH_DMAPTPRXDESC_PTPFT) \|\| \
Kojto	93:e188a91d3eaa	1418	((FLAG) == ETH_DMAPTPRXDESC_PTPMT) \|\| \
Kojto	93:e188a91d3eaa	1419	((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) \|\| \
Kojto	93:e188a91d3eaa	1420	((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) \|\| \
Kojto	93:e188a91d3eaa	1421	((FLAG) == ETH_DMAPTPRXDESC_IPCB) \|\| \
Kojto	93:e188a91d3eaa	1422	((FLAG) == ETH_DMAPTPRXDESC_IPPE) \|\| \
Kojto	93:e188a91d3eaa	1423	((FLAG) == ETH_DMAPTPRXDESC_IPHE) \|\| \
Kojto	93:e188a91d3eaa	1424	((FLAG) == ETH_DMAPTPRXDESC_IPPT))
Kojto	93:e188a91d3eaa	1425
Kojto	93:e188a91d3eaa	1426	/**
Kojto	93:e188a91d3eaa	1427	* @}
Kojto	93:e188a91d3eaa	1428	*/
Kojto	93:e188a91d3eaa	1429
Kojto	93:e188a91d3eaa	1430	/** @defgroup ETH_DMA_Rx_descriptor_buffers_
Kojto	93:e188a91d3eaa	1431	* @{
Kojto	93:e188a91d3eaa	1432	*/
Kojto	93:e188a91d3eaa	1433	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
Kojto	93:e188a91d3eaa	1434	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
Kojto	93:e188a91d3eaa	1435	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
Kojto	93:e188a91d3eaa	1436	((BUFFER) == ETH_DMARXDESC_BUFFER2))
Kojto	93:e188a91d3eaa	1437
Kojto	93:e188a91d3eaa	1438
Kojto	93:e188a91d3eaa	1439	/* ETHERNET DMA Tx descriptors Collision Count Shift */
Kojto	93:e188a91d3eaa	1440	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
Kojto	93:e188a91d3eaa	1441
Kojto	93:e188a91d3eaa	1442	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
Kojto	93:e188a91d3eaa	1443	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto	93:e188a91d3eaa	1444
Kojto	93:e188a91d3eaa	1445	/* ETHERNET DMA Rx descriptors Frame Length Shift */
Kojto	93:e188a91d3eaa	1446	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
Kojto	93:e188a91d3eaa	1447
Kojto	93:e188a91d3eaa	1448	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
Kojto	93:e188a91d3eaa	1449	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto	93:e188a91d3eaa	1450
Kojto	93:e188a91d3eaa	1451	/* ETHERNET DMA Rx descriptors Frame length Shift */
Kojto	93:e188a91d3eaa	1452	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
Kojto	93:e188a91d3eaa	1453
Kojto	93:e188a91d3eaa	1454	/**
Kojto	93:e188a91d3eaa	1455	* @}
Kojto	93:e188a91d3eaa	1456	*/
Kojto	93:e188a91d3eaa	1457
Kojto	93:e188a91d3eaa	1458	/** @defgroup ETH_PMT_Flags
Kojto	93:e188a91d3eaa	1459	* @{
Kojto	93:e188a91d3eaa	1460	*/
Kojto	93:e188a91d3eaa	1461	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
Kojto	93:e188a91d3eaa	1462	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
Kojto	93:e188a91d3eaa	1463	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
Kojto	93:e188a91d3eaa	1464	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
Kojto	93:e188a91d3eaa	1465	((FLAG) == ETH_PMT_FLAG_MPR))
Kojto	93:e188a91d3eaa	1466	/**
Kojto	93:e188a91d3eaa	1467	* @}
Kojto	93:e188a91d3eaa	1468	*/
Kojto	93:e188a91d3eaa	1469
Kojto	93:e188a91d3eaa	1470	/** @defgroup ETH_MMC_Tx_Interrupts
Kojto	93:e188a91d3eaa	1471	* @{
Kojto	93:e188a91d3eaa	1472	*/
Kojto	93:e188a91d3eaa	1473	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
Kojto	93:e188a91d3eaa	1474	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
Kojto	93:e188a91d3eaa	1475	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
Kojto	93:e188a91d3eaa	1476
Kojto	93:e188a91d3eaa	1477	/**
Kojto	93:e188a91d3eaa	1478	* @}
Kojto	93:e188a91d3eaa	1479	*/
Kojto	93:e188a91d3eaa	1480
Kojto	93:e188a91d3eaa	1481	/** @defgroup ETH_MMC_Rx_Interrupts
Kojto	93:e188a91d3eaa	1482	* @{
Kojto	93:e188a91d3eaa	1483	*/
Kojto	93:e188a91d3eaa	1484	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
Kojto	93:e188a91d3eaa	1485	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
Kojto	93:e188a91d3eaa	1486	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
Kojto	93:e188a91d3eaa	1487	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
Kojto	93:e188a91d3eaa	1488	((IT) != 0x00))
Kojto	93:e188a91d3eaa	1489	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
Kojto	93:e188a91d3eaa	1490	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
Kojto	93:e188a91d3eaa	1491	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
Kojto	93:e188a91d3eaa	1492	/**
Kojto	93:e188a91d3eaa	1493	* @}
Kojto	93:e188a91d3eaa	1494	*/
Kojto	93:e188a91d3eaa	1495
Kojto	93:e188a91d3eaa	1496	/** @defgroup ETH_MMC_Registers
Kojto	93:e188a91d3eaa	1497	* @{
Kojto	93:e188a91d3eaa	1498	*/
Kojto	93:e188a91d3eaa	1499	#define ETH_MMCCR ((uint32_t)0x00000100) /!< MMC CR register /
Kojto	93:e188a91d3eaa	1500	#define ETH_MMCRIR ((uint32_t)0x00000104) /!< MMC RIR register /
Kojto	93:e188a91d3eaa	1501	#define ETH_MMCTIR ((uint32_t)0x00000108) /!< MMC TIR register /
Kojto	93:e188a91d3eaa	1502	#define ETH_MMCRIMR ((uint32_t)0x0000010C) /!< MMC RIMR register /
Kojto	93:e188a91d3eaa	1503	#define ETH_MMCTIMR ((uint32_t)0x00000110) /!< MMC TIMR register /
Kojto	93:e188a91d3eaa	1504	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /!< MMC TGFSCCR register /
Kojto	93:e188a91d3eaa	1505	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /!< MMC TGFMSCCR register /
Kojto	93:e188a91d3eaa	1506	#define ETH_MMCTGFCR ((uint32_t)0x00000168) /!< MMC TGFCR register /
Kojto	93:e188a91d3eaa	1507	#define ETH_MMCRFCECR ((uint32_t)0x00000194) /!< MMC RFCECR register /
Kojto	93:e188a91d3eaa	1508	#define ETH_MMCRFAECR ((uint32_t)0x00000198) /!< MMC RFAECR register /
Kojto	93:e188a91d3eaa	1509	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /!< MMC RGUFCR register /
Kojto	93:e188a91d3eaa	1510
Kojto	93:e188a91d3eaa	1511	/**
Kojto	93:e188a91d3eaa	1512	* @brief ETH MMC registers
Kojto	93:e188a91d3eaa	1513	*/
Kojto	93:e188a91d3eaa	1514	#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) \|\| ((REG) == ETH_MMCRIR) \|\| \
Kojto	93:e188a91d3eaa	1515	((REG) == ETH_MMCTIR) \|\| ((REG) == ETH_MMCRIMR) \|\| \
Kojto	93:e188a91d3eaa	1516	((REG) == ETH_MMCTIMR) \|\| ((REG) == ETH_MMCTGFSCCR) \|\| \
Kojto	93:e188a91d3eaa	1517	((REG) == ETH_MMCTGFMSCCR) \|\| ((REG) == ETH_MMCTGFCR) \|\| \
Kojto	93:e188a91d3eaa	1518	((REG) == ETH_MMCRFCECR) \|\| ((REG) == ETH_MMCRFAECR) \|\| \
Kojto	93:e188a91d3eaa	1519	((REG) == ETH_MMCRGUFCR))
Kojto	93:e188a91d3eaa	1520	/**
Kojto	93:e188a91d3eaa	1521	* @}
Kojto	93:e188a91d3eaa	1522	*/
Kojto	93:e188a91d3eaa	1523
Kojto	93:e188a91d3eaa	1524	/** @defgroup ETH_MAC_Flags
Kojto	93:e188a91d3eaa	1525	* @{
Kojto	93:e188a91d3eaa	1526	*/
Kojto	93:e188a91d3eaa	1527	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
Kojto	93:e188a91d3eaa	1528	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
Kojto	93:e188a91d3eaa	1529	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
Kojto	93:e188a91d3eaa	1530	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
Kojto	93:e188a91d3eaa	1531	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
Kojto	93:e188a91d3eaa	1532	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
Kojto	93:e188a91d3eaa	1533	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
Kojto	93:e188a91d3eaa	1534	((FLAG) == ETH_MAC_FLAG_PMT))
Kojto	93:e188a91d3eaa	1535	/**
Kojto	93:e188a91d3eaa	1536	* @}
Kojto	93:e188a91d3eaa	1537	*/
Kojto	93:e188a91d3eaa	1538
Kojto	93:e188a91d3eaa	1539	/** @defgroup ETH_DMA_Flags
Kojto	93:e188a91d3eaa	1540	* @{
Kojto	93:e188a91d3eaa	1541	*/
Kojto	93:e188a91d3eaa	1542	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
Kojto	93:e188a91d3eaa	1543	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
Kojto	93:e188a91d3eaa	1544	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
Kojto	93:e188a91d3eaa	1545	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
Kojto	93:e188a91d3eaa	1546	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write trnsf, 1-read transfr /
Kojto	93:e188a91d3eaa	1547	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
Kojto	93:e188a91d3eaa	1548	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
Kojto	93:e188a91d3eaa	1549	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
Kojto	93:e188a91d3eaa	1550	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
Kojto	93:e188a91d3eaa	1551	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
Kojto	93:e188a91d3eaa	1552	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
Kojto	93:e188a91d3eaa	1553	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
Kojto	93:e188a91d3eaa	1554	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
Kojto	93:e188a91d3eaa	1555	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
Kojto	93:e188a91d3eaa	1556	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
Kojto	93:e188a91d3eaa	1557	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
Kojto	93:e188a91d3eaa	1558	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
Kojto	93:e188a91d3eaa	1559	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
Kojto	93:e188a91d3eaa	1560	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
Kojto	93:e188a91d3eaa	1561	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
Kojto	93:e188a91d3eaa	1562	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
Kojto	93:e188a91d3eaa	1563
Kojto	93:e188a91d3eaa	1564	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
Kojto	93:e188a91d3eaa	1565	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
Kojto	93:e188a91d3eaa	1566	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
Kojto	93:e188a91d3eaa	1567	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
Kojto	93:e188a91d3eaa	1568	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
Kojto	93:e188a91d3eaa	1569	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
Kojto	93:e188a91d3eaa	1570	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
Kojto	93:e188a91d3eaa	1571	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
Kojto	93:e188a91d3eaa	1572	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
Kojto	93:e188a91d3eaa	1573	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
Kojto	93:e188a91d3eaa	1574	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
Kojto	93:e188a91d3eaa	1575	((FLAG) == ETH_DMA_FLAG_T))
Kojto	93:e188a91d3eaa	1576	/**
Kojto	93:e188a91d3eaa	1577	* @}
Kojto	93:e188a91d3eaa	1578	*/
Kojto	93:e188a91d3eaa	1579
Kojto	93:e188a91d3eaa	1580	/** @defgroup ETH_MAC_Interrupts
Kojto	93:e188a91d3eaa	1581	* @{
Kojto	93:e188a91d3eaa	1582	*/
Kojto	93:e188a91d3eaa	1583	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
Kojto	93:e188a91d3eaa	1584	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
Kojto	93:e188a91d3eaa	1585	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
Kojto	93:e188a91d3eaa	1586	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
Kojto	93:e188a91d3eaa	1587	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
Kojto	93:e188a91d3eaa	1588	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
Kojto	93:e188a91d3eaa	1589	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
Kojto	93:e188a91d3eaa	1590	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
Kojto	93:e188a91d3eaa	1591	((IT) == ETH_MAC_IT_PMT))
Kojto	93:e188a91d3eaa	1592	/**
Kojto	93:e188a91d3eaa	1593	* @}
Kojto	93:e188a91d3eaa	1594	*/
Kojto	93:e188a91d3eaa	1595
Kojto	93:e188a91d3eaa	1596	/** @defgroup ETH_DMA_Interrupts
Kojto	93:e188a91d3eaa	1597	* @{
Kojto	93:e188a91d3eaa	1598	*/
Kojto	93:e188a91d3eaa	1599	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
Kojto	93:e188a91d3eaa	1600	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
Kojto	93:e188a91d3eaa	1601	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
Kojto	93:e188a91d3eaa	1602	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
Kojto	93:e188a91d3eaa	1603	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
Kojto	93:e188a91d3eaa	1604	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
Kojto	93:e188a91d3eaa	1605	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
Kojto	93:e188a91d3eaa	1606	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
Kojto	93:e188a91d3eaa	1607	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
Kojto	93:e188a91d3eaa	1608	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
Kojto	93:e188a91d3eaa	1609	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
Kojto	93:e188a91d3eaa	1610	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
Kojto	93:e188a91d3eaa	1611	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
Kojto	93:e188a91d3eaa	1612	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
Kojto	93:e188a91d3eaa	1613	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
Kojto	93:e188a91d3eaa	1614	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
Kojto	93:e188a91d3eaa	1615	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
Kojto	93:e188a91d3eaa	1616	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
Kojto	93:e188a91d3eaa	1617
Kojto	93:e188a91d3eaa	1618	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
Kojto	93:e188a91d3eaa	1619	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
Kojto	93:e188a91d3eaa	1620	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
Kojto	93:e188a91d3eaa	1621	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
Kojto	93:e188a91d3eaa	1622	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
Kojto	93:e188a91d3eaa	1623	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
Kojto	93:e188a91d3eaa	1624	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
Kojto	93:e188a91d3eaa	1625	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
Kojto	93:e188a91d3eaa	1626	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
Kojto	93:e188a91d3eaa	1627	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
Kojto	93:e188a91d3eaa	1628
Kojto	93:e188a91d3eaa	1629	/**
Kojto	93:e188a91d3eaa	1630	* @}
Kojto	93:e188a91d3eaa	1631	*/
Kojto	93:e188a91d3eaa	1632
Kojto	93:e188a91d3eaa	1633	/** @defgroup ETH_DMA_transmit_process_state_
Kojto	93:e188a91d3eaa	1634	* @{
Kojto	93:e188a91d3eaa	1635	*/
Kojto	93:e188a91d3eaa	1636	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
Kojto	93:e188a91d3eaa	1637	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
Kojto	93:e188a91d3eaa	1638	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
Kojto	93:e188a91d3eaa	1639	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
Kojto	93:e188a91d3eaa	1640	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
Kojto	93:e188a91d3eaa	1641	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
Kojto	93:e188a91d3eaa	1642
Kojto	93:e188a91d3eaa	1643	/**
Kojto	93:e188a91d3eaa	1644	* @}
Kojto	93:e188a91d3eaa	1645	*/
Kojto	93:e188a91d3eaa	1646
Kojto	93:e188a91d3eaa	1647
Kojto	93:e188a91d3eaa	1648	/** @defgroup ETH_DMA_receive_process_state_
Kojto	93:e188a91d3eaa	1649	* @{
Kojto	93:e188a91d3eaa	1650	*/
Kojto	93:e188a91d3eaa	1651	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
Kojto	93:e188a91d3eaa	1652	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
Kojto	93:e188a91d3eaa	1653	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
Kojto	93:e188a91d3eaa	1654	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
Kojto	93:e188a91d3eaa	1655	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
Kojto	93:e188a91d3eaa	1656	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
Kojto	93:e188a91d3eaa	1657
Kojto	93:e188a91d3eaa	1658	/**
Kojto	93:e188a91d3eaa	1659	* @}
Kojto	93:e188a91d3eaa	1660	*/
Kojto	93:e188a91d3eaa	1661
Kojto	93:e188a91d3eaa	1662	/** @defgroup ETH_DMA_overflow_
Kojto	93:e188a91d3eaa	1663	* @{
Kojto	93:e188a91d3eaa	1664	*/
Kojto	93:e188a91d3eaa	1665	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
Kojto	93:e188a91d3eaa	1666	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
Kojto	93:e188a91d3eaa	1667	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
Kojto	93:e188a91d3eaa	1668	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
Kojto	93:e188a91d3eaa	1669	/**
Kojto	93:e188a91d3eaa	1670	* @}
Kojto	93:e188a91d3eaa	1671	*/
Kojto	93:e188a91d3eaa	1672
Kojto	93:e188a91d3eaa	1673	/* ETHERNET MAC address offsets */
Kojto	93:e188a91d3eaa	1674	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
Kojto	93:e188a91d3eaa	1675	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
Kojto	93:e188a91d3eaa	1676
Kojto	93:e188a91d3eaa	1677	/* ETHERNET MACMIIAR register Mask */
Kojto	93:e188a91d3eaa	1678	#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
Kojto	93:e188a91d3eaa	1679
Kojto	93:e188a91d3eaa	1680	/* ETHERNET MACCR register Mask */
Kojto	93:e188a91d3eaa	1681	#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
Kojto	93:e188a91d3eaa	1682
Kojto	93:e188a91d3eaa	1683	/* ETHERNET MACFCR register Mask */
Kojto	93:e188a91d3eaa	1684	#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
Kojto	93:e188a91d3eaa	1685
Kojto	93:e188a91d3eaa	1686
Kojto	93:e188a91d3eaa	1687	/* ETHERNET DMAOMR register Mask */
Kojto	93:e188a91d3eaa	1688	#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
Kojto	93:e188a91d3eaa	1689
Kojto	93:e188a91d3eaa	1690
Kojto	93:e188a91d3eaa	1691	/* ETHERNET Remote Wake-up frame register length */
Kojto	93:e188a91d3eaa	1692	#define ETH_WAKEUP_REGISTER_LENGTH 8
Kojto	93:e188a91d3eaa	1693
Kojto	93:e188a91d3eaa	1694	/* ETHERNET Missed frames counter Shift */
Kojto	93:e188a91d3eaa	1695	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
Kojto	93:e188a91d3eaa	1696
Kojto	93:e188a91d3eaa	1697	/**
Kojto	93:e188a91d3eaa	1698	* @}
Kojto	93:e188a91d3eaa	1699	*/
Kojto	93:e188a91d3eaa	1700
Kojto	93:e188a91d3eaa	1701	/* Exported macro ------------------------------------------------------------*/
Kojto	93:e188a91d3eaa	1702
Kojto	93:e188a91d3eaa	1703	/** @brief Reset ETH handle state
Kojto	93:e188a91d3eaa	1704	* @param __HANDLE__: specifies the ETH handle.
Kojto	93:e188a91d3eaa	1705	* @retval None
Kojto	93:e188a91d3eaa	1706	*/
Kojto	93:e188a91d3eaa	1707	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Kojto	93:e188a91d3eaa	1708
Kojto	93:e188a91d3eaa	1709	/**
Kojto	93:e188a91d3eaa	1710	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
Kojto	93:e188a91d3eaa	1711	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1712	* @param __FLAG__: specifies the flag to check.
Kojto	93:e188a91d3eaa	1713	* @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto	93:e188a91d3eaa	1714	*/
Kojto	93:e188a91d3eaa	1715	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto	93:e188a91d3eaa	1716
Kojto	93:e188a91d3eaa	1717	/**
Kojto	93:e188a91d3eaa	1718	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
Kojto	93:e188a91d3eaa	1719	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1720	* @param __FLAG__: specifies the flag to check.
Kojto	93:e188a91d3eaa	1721	* @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto	93:e188a91d3eaa	1722	*/
Kojto	93:e188a91d3eaa	1723	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto	93:e188a91d3eaa	1724
Kojto	93:e188a91d3eaa	1725	/**
Kojto	93:e188a91d3eaa	1726	* @brief Enables the specified DMA Rx Desc receive interrupt.
Kojto	93:e188a91d3eaa	1727	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1728	* @retval None
Kojto	93:e188a91d3eaa	1729	*/
Kojto	93:e188a91d3eaa	1730	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
Kojto	93:e188a91d3eaa	1731
Kojto	93:e188a91d3eaa	1732	/**
Kojto	93:e188a91d3eaa	1733	* @brief Disables the specified DMA Rx Desc receive interrupt.
Kojto	93:e188a91d3eaa	1734	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1735	* @retval None
Kojto	93:e188a91d3eaa	1736	*/
Kojto	93:e188a91d3eaa	1737	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
Kojto	93:e188a91d3eaa	1738
Kojto	93:e188a91d3eaa	1739	/**
Kojto	93:e188a91d3eaa	1740	* @brief Set the specified DMA Rx Desc Own bit.
Kojto	93:e188a91d3eaa	1741	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1742	* @retval None
Kojto	93:e188a91d3eaa	1743	*/
Kojto	93:e188a91d3eaa	1744	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
Kojto	93:e188a91d3eaa	1745
Kojto	93:e188a91d3eaa	1746	/**
Kojto	93:e188a91d3eaa	1747	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
Kojto	93:e188a91d3eaa	1748	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1749	* @retval The Transmit descriptor collision counter value.
Kojto	93:e188a91d3eaa	1750	*/
Kojto	93:e188a91d3eaa	1751	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
Kojto	93:e188a91d3eaa	1752
Kojto	93:e188a91d3eaa	1753	/**
Kojto	93:e188a91d3eaa	1754	* @brief Set the specified DMA Tx Desc Own bit.
Kojto	93:e188a91d3eaa	1755	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1756	* @retval None
Kojto	93:e188a91d3eaa	1757	*/
Kojto	93:e188a91d3eaa	1758	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
Kojto	93:e188a91d3eaa	1759
Kojto	93:e188a91d3eaa	1760	/**
Kojto	93:e188a91d3eaa	1761	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
Kojto	93:e188a91d3eaa	1762	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1763	* @retval None
Kojto	93:e188a91d3eaa	1764	*/
Kojto	93:e188a91d3eaa	1765	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
Kojto	93:e188a91d3eaa	1766
Kojto	93:e188a91d3eaa	1767	/**
Kojto	93:e188a91d3eaa	1768	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
Kojto	93:e188a91d3eaa	1769	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1770	* @retval None
Kojto	93:e188a91d3eaa	1771	*/
Kojto	93:e188a91d3eaa	1772	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
Kojto	93:e188a91d3eaa	1773
Kojto	93:e188a91d3eaa	1774	/**
Kojto	93:e188a91d3eaa	1775	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
Kojto	93:e188a91d3eaa	1776	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1777	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
Kojto	93:e188a91d3eaa	1778	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	1779	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
Kojto	93:e188a91d3eaa	1780	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
Kojto	93:e188a91d3eaa	1781	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
Kojto	93:e188a91d3eaa	1782	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
Kojto	93:e188a91d3eaa	1783	* @retval None
Kojto	93:e188a91d3eaa	1784	*/
Kojto	93:e188a91d3eaa	1785	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
Kojto	93:e188a91d3eaa	1786
Kojto	93:e188a91d3eaa	1787	/**
Kojto	93:e188a91d3eaa	1788	* @brief Enables the DMA Tx Desc CRC.
Kojto	93:e188a91d3eaa	1789	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1790	* @retval None
Kojto	93:e188a91d3eaa	1791	*/
Kojto	93:e188a91d3eaa	1792	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
Kojto	93:e188a91d3eaa	1793
Kojto	93:e188a91d3eaa	1794	/**
Kojto	93:e188a91d3eaa	1795	* @brief Disables the DMA Tx Desc CRC.
Kojto	93:e188a91d3eaa	1796	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1797	* @retval None
Kojto	93:e188a91d3eaa	1798	*/
Kojto	93:e188a91d3eaa	1799	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
Kojto	93:e188a91d3eaa	1800
Kojto	93:e188a91d3eaa	1801	/**
Kojto	93:e188a91d3eaa	1802	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto	93:e188a91d3eaa	1803	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1804	* @retval None
Kojto	93:e188a91d3eaa	1805	*/
Kojto	93:e188a91d3eaa	1806	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
Kojto	93:e188a91d3eaa	1807
Kojto	93:e188a91d3eaa	1808	/**
Kojto	93:e188a91d3eaa	1809	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto	93:e188a91d3eaa	1810	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1811	* @retval None
Kojto	93:e188a91d3eaa	1812	*/
Kojto	93:e188a91d3eaa	1813	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
Kojto	93:e188a91d3eaa	1814
Kojto	93:e188a91d3eaa	1815	/**
Kojto	93:e188a91d3eaa	1816	* @brief Enables the specified ETHERNET MAC interrupts.
Kojto	93:e188a91d3eaa	1817	* @param __HANDLE__ : ETH Handle
Kojto	93:e188a91d3eaa	1818	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto	93:e188a91d3eaa	1819	* enabled or disabled.
Kojto	93:e188a91d3eaa	1820	* This parameter can be any combination of the following values:
Kojto	93:e188a91d3eaa	1821	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto	93:e188a91d3eaa	1822	* @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto	93:e188a91d3eaa	1823	* @retval None
Kojto	93:e188a91d3eaa	1824	*/
Kojto	93:e188a91d3eaa	1825	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
Kojto	93:e188a91d3eaa	1826
Kojto	93:e188a91d3eaa	1827	/**
Kojto	93:e188a91d3eaa	1828	* @brief Disables the specified ETHERNET MAC interrupts.
Kojto	93:e188a91d3eaa	1829	* @param __HANDLE__ : ETH Handle
Kojto	93:e188a91d3eaa	1830	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto	93:e188a91d3eaa	1831	* enabled or disabled.
Kojto	93:e188a91d3eaa	1832	* This parameter can be any combination of the following values:
Kojto	93:e188a91d3eaa	1833	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto	93:e188a91d3eaa	1834	* @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto	93:e188a91d3eaa	1835	* @retval None
Kojto	93:e188a91d3eaa	1836	*/
Kojto	93:e188a91d3eaa	1837	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
Kojto	93:e188a91d3eaa	1838
Kojto	93:e188a91d3eaa	1839	/**
Kojto	93:e188a91d3eaa	1840	* @brief Initiate a Pause Control Frame (Full-duplex only).
Kojto	93:e188a91d3eaa	1841	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1842	* @retval None
Kojto	93:e188a91d3eaa	1843	*/
Kojto	93:e188a91d3eaa	1844	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
Kojto	93:e188a91d3eaa	1845
Kojto	93:e188a91d3eaa	1846	/**
Kojto	93:e188a91d3eaa	1847	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
Kojto	93:e188a91d3eaa	1848	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1849	* @retval The new state of flow control busy status bit (SET or RESET).
Kojto	93:e188a91d3eaa	1850	*/
Kojto	93:e188a91d3eaa	1851	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
Kojto	93:e188a91d3eaa	1852
Kojto	93:e188a91d3eaa	1853	/**
Kojto	93:e188a91d3eaa	1854	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
Kojto	93:e188a91d3eaa	1855	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1856	* @retval None
Kojto	93:e188a91d3eaa	1857	*/
Kojto	93:e188a91d3eaa	1858	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
Kojto	93:e188a91d3eaa	1859
Kojto	93:e188a91d3eaa	1860	/**
Kojto	93:e188a91d3eaa	1861	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
Kojto	93:e188a91d3eaa	1862	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1863	* @retval None
Kojto	93:e188a91d3eaa	1864	*/
Kojto	93:e188a91d3eaa	1865	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
Kojto	93:e188a91d3eaa	1866
Kojto	93:e188a91d3eaa	1867	/**
Kojto	93:e188a91d3eaa	1868	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
Kojto	93:e188a91d3eaa	1869	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1870	* @param __FLAG__: specifies the flag to check.
Kojto	93:e188a91d3eaa	1871	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	1872	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
Kojto	93:e188a91d3eaa	1873	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
Kojto	93:e188a91d3eaa	1874	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
Kojto	93:e188a91d3eaa	1875	* @arg ETH_MAC_FLAG_MMC : MMC flag
Kojto	93:e188a91d3eaa	1876	* @arg ETH_MAC_FLAG_PMT : PMT flag
Kojto	93:e188a91d3eaa	1877	* @retval The state of ETHERNET MAC flag.
Kojto	93:e188a91d3eaa	1878	*/
Kojto	93:e188a91d3eaa	1879	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
Kojto	93:e188a91d3eaa	1880
Kojto	93:e188a91d3eaa	1881	/**
Kojto	93:e188a91d3eaa	1882	* @brief Enables the specified ETHERNET DMA interrupts.
Kojto	93:e188a91d3eaa	1883	* @param __HANDLE__ : ETH Handle
Kojto	93:e188a91d3eaa	1884	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto	93:e188a91d3eaa	1885	* enabled @defgroup ETH_DMA_Interrupts
Kojto	93:e188a91d3eaa	1886	* @retval None
Kojto	93:e188a91d3eaa	1887	*/
Kojto	93:e188a91d3eaa	1888	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
Kojto	93:e188a91d3eaa	1889
Kojto	93:e188a91d3eaa	1890	/**
Kojto	93:e188a91d3eaa	1891	* @brief Disables the specified ETHERNET DMA interrupts.
Kojto	93:e188a91d3eaa	1892	* @param __HANDLE__ : ETH Handle
Kojto	93:e188a91d3eaa	1893	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto	93:e188a91d3eaa	1894	* disabled. @defgroup ETH_DMA_Interrupts
Kojto	93:e188a91d3eaa	1895	* @retval None
Kojto	93:e188a91d3eaa	1896	*/
Kojto	93:e188a91d3eaa	1897	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
Kojto	93:e188a91d3eaa	1898
Kojto	93:e188a91d3eaa	1899	/**
Kojto	93:e188a91d3eaa	1900	* @brief Clears the ETHERNET DMA IT pending bit.
Kojto	93:e188a91d3eaa	1901	* @param __HANDLE__ : ETH Handle
Kojto	93:e188a91d3eaa	1902	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
Kojto	93:e188a91d3eaa	1903	* @retval None
Kojto	93:e188a91d3eaa	1904	*/
Kojto	93:e188a91d3eaa	1905	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
Kojto	93:e188a91d3eaa	1906
Kojto	93:e188a91d3eaa	1907	/**
Kojto	93:e188a91d3eaa	1908	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto	93:e188a91d3eaa	1909	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1910	* @param __FLAG__: specifies the flag to check. @defgroup ETH_DMA_Flags
Kojto	93:e188a91d3eaa	1911	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto	93:e188a91d3eaa	1912	*/
Kojto	93:e188a91d3eaa	1913	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
Kojto	93:e188a91d3eaa	1914
Kojto	93:e188a91d3eaa	1915	/**
Kojto	93:e188a91d3eaa	1916	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto	93:e188a91d3eaa	1917	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1918	* @param __FLAG__: specifies the flag to clear. @defgroup ETH_DMA_Flags
Kojto	93:e188a91d3eaa	1919	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto	93:e188a91d3eaa	1920	*/
Kojto	93:e188a91d3eaa	1921	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
Kojto	93:e188a91d3eaa	1922
Kojto	93:e188a91d3eaa	1923	/**
Kojto	93:e188a91d3eaa	1924	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
Kojto	93:e188a91d3eaa	1925	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1926	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
Kojto	93:e188a91d3eaa	1927	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	1928	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
Kojto	93:e188a91d3eaa	1929	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
Kojto	93:e188a91d3eaa	1930	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
Kojto	93:e188a91d3eaa	1931	*/
Kojto	93:e188a91d3eaa	1932	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
Kojto	93:e188a91d3eaa	1933
Kojto	93:e188a91d3eaa	1934	/**
Kojto	93:e188a91d3eaa	1935	* @brief Set the DMA Receive status watchdog timer register value
Kojto	93:e188a91d3eaa	1936	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1937	* @param __VALUE__: DMA Receive status watchdog timer register value
Kojto	93:e188a91d3eaa	1938	* @retval None
Kojto	93:e188a91d3eaa	1939	*/
Kojto	93:e188a91d3eaa	1940	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
Kojto	93:e188a91d3eaa	1941
Kojto	93:e188a91d3eaa	1942	/**
Kojto	93:e188a91d3eaa	1943	* @brief Enables any unicast packet filtered by the MAC address
Kojto	93:e188a91d3eaa	1944	* recognition to be a wake-up frame.
Kojto	93:e188a91d3eaa	1945	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	1946	* @retval None
Kojto	93:e188a91d3eaa	1947	*/
Kojto	93:e188a91d3eaa	1948	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
Kojto	93:e188a91d3eaa	1949
Kojto	93:e188a91d3eaa	1950	/**
Kojto	93:e188a91d3eaa	1951	* @brief Disables any unicast packet filtered by the MAC address
Kojto	93:e188a91d3eaa	1952	* recognition to be a wake-up frame.
Kojto	93:e188a91d3eaa	1953	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	1954	* @retval None
Kojto	93:e188a91d3eaa	1955	*/
Kojto	93:e188a91d3eaa	1956	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
Kojto	93:e188a91d3eaa	1957
Kojto	93:e188a91d3eaa	1958	/**
Kojto	93:e188a91d3eaa	1959	* @brief Enables the MAC Wake-Up Frame Detection.
Kojto	93:e188a91d3eaa	1960	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	1961	* @retval None
Kojto	93:e188a91d3eaa	1962	*/
Kojto	93:e188a91d3eaa	1963	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
Kojto	93:e188a91d3eaa	1964
Kojto	93:e188a91d3eaa	1965	/**
Kojto	93:e188a91d3eaa	1966	* @brief Disables the MAC Wake-Up Frame Detection.
Kojto	93:e188a91d3eaa	1967	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	1968	* @retval None
Kojto	93:e188a91d3eaa	1969	*/
Kojto	93:e188a91d3eaa	1970	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto	93:e188a91d3eaa	1971
Kojto	93:e188a91d3eaa	1972	/**
Kojto	93:e188a91d3eaa	1973	* @brief Enables the MAC Magic Packet Detection.
Kojto	93:e188a91d3eaa	1974	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	1975	* @retval None
Kojto	93:e188a91d3eaa	1976	*/
Kojto	93:e188a91d3eaa	1977	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
Kojto	93:e188a91d3eaa	1978
Kojto	93:e188a91d3eaa	1979	/**
Kojto	93:e188a91d3eaa	1980	* @brief Disables the MAC Magic Packet Detection.
Kojto	93:e188a91d3eaa	1981	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	1982	* @retval None
Kojto	93:e188a91d3eaa	1983	*/
Kojto	93:e188a91d3eaa	1984	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto	93:e188a91d3eaa	1985
Kojto	93:e188a91d3eaa	1986	/**
Kojto	93:e188a91d3eaa	1987	* @brief Enables the MAC Power Down.
Kojto	93:e188a91d3eaa	1988	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1989	* @retval None
Kojto	93:e188a91d3eaa	1990	*/
Kojto	93:e188a91d3eaa	1991	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
Kojto	93:e188a91d3eaa	1992
Kojto	93:e188a91d3eaa	1993	/**
Kojto	93:e188a91d3eaa	1994	* @brief Disables the MAC Power Down.
Kojto	93:e188a91d3eaa	1995	* @param __HANDLE__: ETH Handle
Kojto	93:e188a91d3eaa	1996	* @retval None
Kojto	93:e188a91d3eaa	1997	*/
Kojto	93:e188a91d3eaa	1998	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
Kojto	93:e188a91d3eaa	1999
Kojto	93:e188a91d3eaa	2000	/**
Kojto	93:e188a91d3eaa	2001	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
Kojto	93:e188a91d3eaa	2002	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2003	* @param __FLAG__: specifies the flag to check.
Kojto	93:e188a91d3eaa	2004	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	2005	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
Kojto	93:e188a91d3eaa	2006	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
Kojto	93:e188a91d3eaa	2007	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
Kojto	93:e188a91d3eaa	2008	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
Kojto	93:e188a91d3eaa	2009	*/
Kojto	93:e188a91d3eaa	2010	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
Kojto	93:e188a91d3eaa	2011
Kojto	93:e188a91d3eaa	2012	/**
Kojto	93:e188a91d3eaa	2013	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
Kojto	93:e188a91d3eaa	2014	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2015	* @retval None
Kojto	93:e188a91d3eaa	2016	*/
Kojto	93:e188a91d3eaa	2017	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
Kojto	93:e188a91d3eaa	2018
Kojto	93:e188a91d3eaa	2019	/**
Kojto	93:e188a91d3eaa	2020	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
Kojto	93:e188a91d3eaa	2021	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2022	* @retval None
Kojto	93:e188a91d3eaa	2023	*/
Kojto	93:e188a91d3eaa	2024	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
Kojto	93:e188a91d3eaa	2025	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
Kojto	93:e188a91d3eaa	2026
Kojto	93:e188a91d3eaa	2027	/**
Kojto	93:e188a91d3eaa	2028	* @brief Enables the MMC Counter Freeze.
Kojto	93:e188a91d3eaa	2029	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2030	* @retval None
Kojto	93:e188a91d3eaa	2031	*/
Kojto	93:e188a91d3eaa	2032	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
Kojto	93:e188a91d3eaa	2033
Kojto	93:e188a91d3eaa	2034	/**
Kojto	93:e188a91d3eaa	2035	* @brief Disables the MMC Counter Freeze.
Kojto	93:e188a91d3eaa	2036	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2037	* @retval None
Kojto	93:e188a91d3eaa	2038	*/
Kojto	93:e188a91d3eaa	2039	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
Kojto	93:e188a91d3eaa	2040
Kojto	93:e188a91d3eaa	2041	/**
Kojto	93:e188a91d3eaa	2042	* @brief Enables the MMC Reset On Read.
Kojto	93:e188a91d3eaa	2043	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2044	* @retval None
Kojto	93:e188a91d3eaa	2045	*/
Kojto	93:e188a91d3eaa	2046	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
Kojto	93:e188a91d3eaa	2047
Kojto	93:e188a91d3eaa	2048	/**
Kojto	93:e188a91d3eaa	2049	* @brief Disables the MMC Reset On Read.
Kojto	93:e188a91d3eaa	2050	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2051	* @retval None
Kojto	93:e188a91d3eaa	2052	*/
Kojto	93:e188a91d3eaa	2053	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
Kojto	93:e188a91d3eaa	2054
Kojto	93:e188a91d3eaa	2055	/**
Kojto	93:e188a91d3eaa	2056	* @brief Enables the MMC Counter Stop Rollover.
Kojto	93:e188a91d3eaa	2057	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2058	* @retval None
Kojto	93:e188a91d3eaa	2059	*/
Kojto	93:e188a91d3eaa	2060	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
Kojto	93:e188a91d3eaa	2061
Kojto	93:e188a91d3eaa	2062	/**
Kojto	93:e188a91d3eaa	2063	* @brief Disables the MMC Counter Stop Rollover.
Kojto	93:e188a91d3eaa	2064	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2065	* @retval None
Kojto	93:e188a91d3eaa	2066	*/
Kojto	93:e188a91d3eaa	2067	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
Kojto	93:e188a91d3eaa	2068
Kojto	93:e188a91d3eaa	2069	/**
Kojto	93:e188a91d3eaa	2070	* @brief Resets the MMC Counters.
Kojto	93:e188a91d3eaa	2071	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2072	* @retval None
Kojto	93:e188a91d3eaa	2073	*/
Kojto	93:e188a91d3eaa	2074	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
Kojto	93:e188a91d3eaa	2075
Kojto	93:e188a91d3eaa	2076	/**
Kojto	93:e188a91d3eaa	2077	* @brief Enables the specified ETHERNET MMC Rx interrupts.
Kojto	93:e188a91d3eaa	2078	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2079	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	93:e188a91d3eaa	2080	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	2081	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2082	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2083	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2084	* @retval None
Kojto	93:e188a91d3eaa	2085	*/
Kojto	93:e188a91d3eaa	2086	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
Kojto	93:e188a91d3eaa	2087	/**
Kojto	93:e188a91d3eaa	2088	* @brief Disables the specified ETHERNET MMC Rx interrupts.
Kojto	93:e188a91d3eaa	2089	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2090	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	93:e188a91d3eaa	2091	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	2092	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2093	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2094	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2095	* @retval None
Kojto	93:e188a91d3eaa	2096	*/
Kojto	93:e188a91d3eaa	2097	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
Kojto	93:e188a91d3eaa	2098	/**
Kojto	93:e188a91d3eaa	2099	* @brief Enables the specified ETHERNET MMC Tx interrupts.
Kojto	93:e188a91d3eaa	2100	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2101	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	93:e188a91d3eaa	2102	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	2103	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2104	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2105	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2106	* @retval None
Kojto	93:e188a91d3eaa	2107	*/
Kojto	93:e188a91d3eaa	2108	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
Kojto	93:e188a91d3eaa	2109
Kojto	93:e188a91d3eaa	2110	/**
Kojto	93:e188a91d3eaa	2111	* @brief Disables the specified ETHERNET MMC Tx interrupts.
Kojto	93:e188a91d3eaa	2112	* @param __HANDLE__: ETH Handle.
Kojto	93:e188a91d3eaa	2113	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	93:e188a91d3eaa	2114	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	2115	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2116	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2117	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto	93:e188a91d3eaa	2118	* @retval None
Kojto	93:e188a91d3eaa	2119	*/
Kojto	93:e188a91d3eaa	2120	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
Kojto	93:e188a91d3eaa	2121
Kojto	93:e188a91d3eaa	2122	/** @defgroup ETH_EXTI_LINE_WAKEUP
Kojto	93:e188a91d3eaa	2123	* @{
Kojto	93:e188a91d3eaa	2124	*/
Kojto	93:e188a91d3eaa	2125	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
Kojto	93:e188a91d3eaa	2126
Kojto	93:e188a91d3eaa	2127	/**
Kojto	93:e188a91d3eaa	2128	* @}
Kojto	93:e188a91d3eaa	2129	*/
Kojto	93:e188a91d3eaa	2130
Kojto	93:e188a91d3eaa	2131	/**
Kojto	93:e188a91d3eaa	2132	* @brief Enables the ETH External interrupt line.
Kojto	93:e188a91d3eaa	2133	* @param None
Kojto	93:e188a91d3eaa	2134	* @retval None
Kojto	93:e188a91d3eaa	2135	*/
Kojto	93:e188a91d3eaa	2136	#define __HAL_ETH_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	93:e188a91d3eaa	2137
Kojto	93:e188a91d3eaa	2138	/**
Kojto	93:e188a91d3eaa	2139	* @brief Disables the ETH External interrupt line.
Kojto	93:e188a91d3eaa	2140	* @param None
Kojto	93:e188a91d3eaa	2141	* @retval None
Kojto	93:e188a91d3eaa	2142	*/
Kojto	93:e188a91d3eaa	2143	#define __HAL_ETH_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	93:e188a91d3eaa	2144
Kojto	93:e188a91d3eaa	2145	/**
Kojto	93:e188a91d3eaa	2146	* @brief Get flag of the ETH External interrupt line.
Kojto	93:e188a91d3eaa	2147	* @param None
Kojto	93:e188a91d3eaa	2148	* @retval None
Kojto	93:e188a91d3eaa	2149	*/
Kojto	93:e188a91d3eaa	2150	#define __HAL_ETH_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Kojto	93:e188a91d3eaa	2151
Kojto	93:e188a91d3eaa	2152	/**
Kojto	93:e188a91d3eaa	2153	* @brief Clear flag of the ETH External interrupt line.
Kojto	93:e188a91d3eaa	2154	* @param None
Kojto	93:e188a91d3eaa	2155	* @retval None
Kojto	93:e188a91d3eaa	2156	*/
Kojto	93:e188a91d3eaa	2157	#define __HAL_ETH_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
Kojto	93:e188a91d3eaa	2158
Kojto	93:e188a91d3eaa	2159	/**
Kojto	93:e188a91d3eaa	2160	* @brief Sets rising edge trigger to the ETH External interrupt line.
Kojto	93:e188a91d3eaa	2161	* @param None
Kojto	93:e188a91d3eaa	2162	* @retval None
Kojto	93:e188a91d3eaa	2163	*/
Kojto	93:e188a91d3eaa	2164	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto	93:e188a91d3eaa	2165	EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
Kojto	93:e188a91d3eaa	2166
Kojto	93:e188a91d3eaa	2167	/**
Kojto	93:e188a91d3eaa	2168	* @brief Sets falling edge trigger to the ETH External interrupt line.
Kojto	93:e188a91d3eaa	2169	* @param None
Kojto	93:e188a91d3eaa	2170	* @retval None
Kojto	93:e188a91d3eaa	2171	*/
Kojto	93:e188a91d3eaa	2172	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP);\
Kojto	93:e188a91d3eaa	2173	EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	93:e188a91d3eaa	2174
Kojto	93:e188a91d3eaa	2175	/**
Kojto	93:e188a91d3eaa	2176	* @brief Sets rising/falling edge trigger to the ETH External interrupt line.
Kojto	93:e188a91d3eaa	2177	* @param None
Kojto	93:e188a91d3eaa	2178	* @retval None
Kojto	93:e188a91d3eaa	2179	*/
Kojto	93:e188a91d3eaa	2180	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto	93:e188a91d3eaa	2181	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto	93:e188a91d3eaa	2182	EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
Kojto	93:e188a91d3eaa	2183	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
Kojto	93:e188a91d3eaa	2184
Kojto	93:e188a91d3eaa	2185	/* Exported functions --------------------------------------------------------*/
Kojto	93:e188a91d3eaa	2186
Kojto	93:e188a91d3eaa	2187	/* Initialization and de-initialization functions ****************************/
Kojto	93:e188a91d3eaa	2188	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2189	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2190	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2191	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2192	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
Kojto	93:e188a91d3eaa	2193	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
Kojto	93:e188a91d3eaa	2194
Kojto	93:e188a91d3eaa	2195	/* IO operation functions ****************************************************/
Kojto	93:e188a91d3eaa	2196	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
Kojto	93:e188a91d3eaa	2197	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2198
Kojto	93:e188a91d3eaa	2199	/* Non-Blocking mode: Interrupt */
Kojto	93:e188a91d3eaa	2200	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2201	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2202
Kojto	93:e188a91d3eaa	2203	/* Callback in non blocking modes (Interrupt) */
Kojto	93:e188a91d3eaa	2204	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2205	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2206	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2207
Kojto	93:e188a91d3eaa	2208	/* Cmmunication with PHY functions*/
Kojto	93:e188a91d3eaa	2209	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
Kojto	93:e188a91d3eaa	2210	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
Kojto	93:e188a91d3eaa	2211
Kojto	93:e188a91d3eaa	2212	/* Peripheral Control functions **********************************************/
Kojto	93:e188a91d3eaa	2213	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2214	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2215
Kojto	93:e188a91d3eaa	2216	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
Kojto	93:e188a91d3eaa	2217	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
Kojto	93:e188a91d3eaa	2218
Kojto	93:e188a91d3eaa	2219	/* Peripheral State functions ************************************************/
Kojto	93:e188a91d3eaa	2220	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
Kojto	93:e188a91d3eaa	2221
Kojto	93:e188a91d3eaa	2222	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	93:e188a91d3eaa	2223	/**
Kojto	93:e188a91d3eaa	2224	* @}
Kojto	93:e188a91d3eaa	2225	*/
Kojto	93:e188a91d3eaa	2226
Kojto	93:e188a91d3eaa	2227	/**
Kojto	93:e188a91d3eaa	2228	* @}
Kojto	93:e188a91d3eaa	2229	*/
Kojto	93:e188a91d3eaa	2230
Kojto	93:e188a91d3eaa	2231	#ifdef __cplusplus
Kojto	93:e188a91d3eaa	2232	}
Kojto	93:e188a91d3eaa	2233	#endif
Kojto	93:e188a91d3eaa	2234
Kojto	93:e188a91d3eaa	2235	#endif /* __STM32F4xx_HAL_ETH_H */
Kojto	93:e188a91d3eaa	2236
Kojto	93:e188a91d3eaa	2237
Kojto	93:e188a91d3eaa	2238
Kojto	93:e188a91d3eaa	2239	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	03 May 2015
Imports:	4
Forks:	0
Commits:	100
Dependents:	0
Dependencies:	0
Followers:	2

TARGET_MTS_MDOT_F411RE/stm32f4xx_hal_eth.h@99:7f6c6de930c0, 2015-05-03 (annotated)

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