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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_dma2d.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
92:4fc01daae5a5 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_dma2d.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of DMA2D HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_DMA2D_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_DMA2D_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 92:4fc01daae5a5 47 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 48 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 49
bogdanm 92:4fc01daae5a5 50 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 51 * @{
bogdanm 92:4fc01daae5a5 52 */
bogdanm 92:4fc01daae5a5 53
bogdanm 92:4fc01daae5a5 54 /** @addtogroup DMA2D
bogdanm 92:4fc01daae5a5 55 * @{
bogdanm 92:4fc01daae5a5 56 */
bogdanm 92:4fc01daae5a5 57
bogdanm 92:4fc01daae5a5 58 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 59
bogdanm 92:4fc01daae5a5 60 #define MAX_DMA2D_LAYER 2
bogdanm 92:4fc01daae5a5 61
bogdanm 92:4fc01daae5a5 62 /**
bogdanm 92:4fc01daae5a5 63 * @brief DMA2D color Structure definition
bogdanm 92:4fc01daae5a5 64 */
bogdanm 92:4fc01daae5a5 65 typedef struct
bogdanm 92:4fc01daae5a5 66 {
bogdanm 92:4fc01daae5a5 67 uint32_t Blue; /*!< Configures the blue value.
bogdanm 92:4fc01daae5a5 68 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 uint32_t Green; /*!< Configures the green value.
bogdanm 92:4fc01daae5a5 71 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 uint32_t Red; /*!< Configures the red value.
bogdanm 92:4fc01daae5a5 74 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 92:4fc01daae5a5 75 } DMA2D_ColorTypeDef;
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77 /**
bogdanm 92:4fc01daae5a5 78 * @brief DMA2D CLUT Structure definition
bogdanm 92:4fc01daae5a5 79 */
bogdanm 92:4fc01daae5a5 80 typedef struct
bogdanm 92:4fc01daae5a5 81 {
bogdanm 92:4fc01daae5a5 82 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
bogdanm 92:4fc01daae5a5 83
bogdanm 92:4fc01daae5a5 84 uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
bogdanm 92:4fc01daae5a5 85 This parameter can be one value of @ref DMA2D_CLUT_CM */
bogdanm 92:4fc01daae5a5 86
bogdanm 92:4fc01daae5a5 87 uint32_t Size; /*!< configures the DMA2D CLUT size.
bogdanm 92:4fc01daae5a5 88 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 92:4fc01daae5a5 89 } DMA2D_CLUTCfgTypeDef;
bogdanm 92:4fc01daae5a5 90
bogdanm 92:4fc01daae5a5 91 /**
bogdanm 92:4fc01daae5a5 92 * @brief DMA2D Init structure definition
bogdanm 92:4fc01daae5a5 93 */
bogdanm 92:4fc01daae5a5 94 typedef struct
bogdanm 92:4fc01daae5a5 95 {
bogdanm 92:4fc01daae5a5 96 uint32_t Mode; /*!< configures the DMA2D transfer mode.
bogdanm 92:4fc01daae5a5 97 This parameter can be one value of @ref DMA2D_Mode */
bogdanm 92:4fc01daae5a5 98
bogdanm 92:4fc01daae5a5 99 uint32_t ColorMode; /*!< configures the color format of the output image.
bogdanm 92:4fc01daae5a5 100 This parameter can be one value of @ref DMA2D_Color_Mode */
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102 uint32_t OutputOffset; /*!< Specifies the Offset value.
bogdanm 92:4fc01daae5a5 103 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
bogdanm 92:4fc01daae5a5 104 } DMA2D_InitTypeDef;
bogdanm 92:4fc01daae5a5 105
bogdanm 92:4fc01daae5a5 106 /**
bogdanm 92:4fc01daae5a5 107 * @brief DMA2D Layer structure definition
bogdanm 92:4fc01daae5a5 108 */
bogdanm 92:4fc01daae5a5 109 typedef struct
bogdanm 92:4fc01daae5a5 110 {
bogdanm 92:4fc01daae5a5 111 uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
bogdanm 92:4fc01daae5a5 112 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
bogdanm 92:4fc01daae5a5 113
bogdanm 92:4fc01daae5a5 114 uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
bogdanm 92:4fc01daae5a5 115 This parameter can be one value of @ref DMA2D_Input_Color_Mode */
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
bogdanm 92:4fc01daae5a5 118 This parameter can be one value of @ref DMA2D_ALPHA_MODE */
bogdanm 92:4fc01daae5a5 119
bogdanm 92:4fc01daae5a5 120 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode.
bogdanm 92:4fc01daae5a5 121 This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF
bogdanm 92:4fc01daae5a5 122 in case of A8 or A4 color mode (ARGB).
bogdanm 92:4fc01daae5a5 123 Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 92:4fc01daae5a5 124
bogdanm 92:4fc01daae5a5 125 } DMA2D_LayerCfgTypeDef;
bogdanm 92:4fc01daae5a5 126
bogdanm 92:4fc01daae5a5 127 /**
bogdanm 92:4fc01daae5a5 128 * @brief HAL DMA2D State structures definition
bogdanm 92:4fc01daae5a5 129 */
bogdanm 92:4fc01daae5a5 130 typedef enum
bogdanm 92:4fc01daae5a5 131 {
bogdanm 92:4fc01daae5a5 132 HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 133 HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 92:4fc01daae5a5 134 HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
bogdanm 92:4fc01daae5a5 135 HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 92:4fc01daae5a5 136 HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
bogdanm 92:4fc01daae5a5 137 HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
bogdanm 92:4fc01daae5a5 138 }HAL_DMA2D_StateTypeDef;
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 /**
bogdanm 92:4fc01daae5a5 141 * @brief DMA2D handle Structure definition
bogdanm 92:4fc01daae5a5 142 */
bogdanm 92:4fc01daae5a5 143 typedef struct __DMA2D_HandleTypeDef
bogdanm 92:4fc01daae5a5 144 {
bogdanm 92:4fc01daae5a5 145 DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
bogdanm 92:4fc01daae5a5 152
bogdanm 92:4fc01daae5a5 153 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
bogdanm 92:4fc01daae5a5 154
bogdanm 92:4fc01daae5a5 155 HAL_LockTypeDef Lock; /*!< DMA2D Lock */
bogdanm 92:4fc01daae5a5 156
bogdanm 92:4fc01daae5a5 157 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
bogdanm 92:4fc01daae5a5 158
bogdanm 92:4fc01daae5a5 159 __IO uint32_t ErrorCode; /*!< DMA2D Error code */
bogdanm 92:4fc01daae5a5 160 } DMA2D_HandleTypeDef;
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162
bogdanm 92:4fc01daae5a5 163 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 /** @defgroup DMA2D_Exported_Constants
bogdanm 92:4fc01daae5a5 166 * @{
bogdanm 92:4fc01daae5a5 167 */
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 /** @defgroup DMA2D_Layer
bogdanm 92:4fc01daae5a5 170 * @{
bogdanm 92:4fc01daae5a5 171 */
bogdanm 92:4fc01daae5a5 172 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
bogdanm 92:4fc01daae5a5 173 /**
bogdanm 92:4fc01daae5a5 174 * @}
bogdanm 92:4fc01daae5a5 175 */
bogdanm 92:4fc01daae5a5 176
bogdanm 92:4fc01daae5a5 177 /** @defgroup DMA2D_Error_Code
bogdanm 92:4fc01daae5a5 178 * @{
bogdanm 92:4fc01daae5a5 179 */
bogdanm 92:4fc01daae5a5 180 #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 92:4fc01daae5a5 181 #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 92:4fc01daae5a5 182 #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
bogdanm 92:4fc01daae5a5 183 #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 92:4fc01daae5a5 184 /**
bogdanm 92:4fc01daae5a5 185 * @}
bogdanm 92:4fc01daae5a5 186 */
bogdanm 92:4fc01daae5a5 187
bogdanm 92:4fc01daae5a5 188 /** @defgroup DMA2D_Mode
bogdanm 92:4fc01daae5a5 189 * @{
bogdanm 92:4fc01daae5a5 190 */
bogdanm 92:4fc01daae5a5 191 #define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
bogdanm 92:4fc01daae5a5 192 #define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
bogdanm 92:4fc01daae5a5 193 #define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
bogdanm 92:4fc01daae5a5 194 #define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
bogdanm 92:4fc01daae5a5 195
bogdanm 92:4fc01daae5a5 196 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
bogdanm 92:4fc01daae5a5 197 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
bogdanm 92:4fc01daae5a5 198 /**
bogdanm 92:4fc01daae5a5 199 * @}
bogdanm 92:4fc01daae5a5 200 */
bogdanm 92:4fc01daae5a5 201
bogdanm 92:4fc01daae5a5 202 /** @defgroup DMA2D_Color_Mode
bogdanm 92:4fc01daae5a5 203 * @{
bogdanm 92:4fc01daae5a5 204 */
bogdanm 92:4fc01daae5a5 205 #define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
bogdanm 92:4fc01daae5a5 206 #define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
bogdanm 92:4fc01daae5a5 207 #define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
bogdanm 92:4fc01daae5a5 208 #define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
bogdanm 92:4fc01daae5a5 209 #define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
bogdanm 92:4fc01daae5a5 210
bogdanm 92:4fc01daae5a5 211 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
bogdanm 92:4fc01daae5a5 212 ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
bogdanm 92:4fc01daae5a5 213 ((MODE_ARGB) == DMA2D_ARGB4444))
bogdanm 92:4fc01daae5a5 214 /**
bogdanm 92:4fc01daae5a5 215 * @}
bogdanm 92:4fc01daae5a5 216 */
bogdanm 92:4fc01daae5a5 217
bogdanm 92:4fc01daae5a5 218 /** @defgroup DMA2D_COLOR_VALUE
bogdanm 92:4fc01daae5a5 219 * @{
bogdanm 92:4fc01daae5a5 220 */
bogdanm 92:4fc01daae5a5 221
bogdanm 92:4fc01daae5a5 222 #define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
bogdanm 92:4fc01daae5a5 223
bogdanm 92:4fc01daae5a5 224 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
bogdanm 92:4fc01daae5a5 225 /**
bogdanm 92:4fc01daae5a5 226 * @}
bogdanm 92:4fc01daae5a5 227 */
bogdanm 92:4fc01daae5a5 228
bogdanm 92:4fc01daae5a5 229 /** @defgroup DMA2D_SIZE
bogdanm 92:4fc01daae5a5 230 * @{
bogdanm 92:4fc01daae5a5 231 */
bogdanm 92:4fc01daae5a5 232 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
bogdanm 92:4fc01daae5a5 233 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
bogdanm 92:4fc01daae5a5 234
bogdanm 92:4fc01daae5a5 235 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
bogdanm 92:4fc01daae5a5 236 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
bogdanm 92:4fc01daae5a5 237 /**
bogdanm 92:4fc01daae5a5 238 * @}
bogdanm 92:4fc01daae5a5 239 */
bogdanm 92:4fc01daae5a5 240
bogdanm 92:4fc01daae5a5 241 /** @defgroup DMA2D_Offset
bogdanm 92:4fc01daae5a5 242 * @{
bogdanm 92:4fc01daae5a5 243 */
bogdanm 92:4fc01daae5a5 244 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
bogdanm 92:4fc01daae5a5 245
bogdanm 92:4fc01daae5a5 246 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
bogdanm 92:4fc01daae5a5 247 /**
bogdanm 92:4fc01daae5a5 248 * @}
bogdanm 92:4fc01daae5a5 249 */
bogdanm 92:4fc01daae5a5 250
bogdanm 92:4fc01daae5a5 251 /** @defgroup DMA2D_Input_Color_Mode
bogdanm 92:4fc01daae5a5 252 * @{
bogdanm 92:4fc01daae5a5 253 */
bogdanm 92:4fc01daae5a5 254 #define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
bogdanm 92:4fc01daae5a5 255 #define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
bogdanm 92:4fc01daae5a5 256 #define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
bogdanm 92:4fc01daae5a5 257 #define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
bogdanm 92:4fc01daae5a5 258 #define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
bogdanm 92:4fc01daae5a5 259 #define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
bogdanm 92:4fc01daae5a5 260 #define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
bogdanm 92:4fc01daae5a5 261 #define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
bogdanm 92:4fc01daae5a5 262 #define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
bogdanm 92:4fc01daae5a5 263 #define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
bogdanm 92:4fc01daae5a5 264 #define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
bogdanm 92:4fc01daae5a5 265
bogdanm 92:4fc01daae5a5 266 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
bogdanm 92:4fc01daae5a5 267 ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
bogdanm 92:4fc01daae5a5 268 ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
bogdanm 92:4fc01daae5a5 269 ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
bogdanm 92:4fc01daae5a5 270 ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
bogdanm 92:4fc01daae5a5 271 ((INPUT_CM) == CM_A4))
bogdanm 92:4fc01daae5a5 272 /**
bogdanm 92:4fc01daae5a5 273 * @}
bogdanm 92:4fc01daae5a5 274 */
bogdanm 92:4fc01daae5a5 275
bogdanm 92:4fc01daae5a5 276 /** @defgroup DMA2D_ALPHA_MODE
bogdanm 92:4fc01daae5a5 277 * @{
bogdanm 92:4fc01daae5a5 278 */
bogdanm 92:4fc01daae5a5 279 #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
bogdanm 92:4fc01daae5a5 280 #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
bogdanm 92:4fc01daae5a5 281 #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
bogdanm 92:4fc01daae5a5 282 with original alpha channel value */
bogdanm 92:4fc01daae5a5 283
bogdanm 92:4fc01daae5a5 284 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
bogdanm 92:4fc01daae5a5 285 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
bogdanm 92:4fc01daae5a5 286 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
bogdanm 92:4fc01daae5a5 287 /**
bogdanm 92:4fc01daae5a5 288 * @}
bogdanm 92:4fc01daae5a5 289 */
bogdanm 92:4fc01daae5a5 290
bogdanm 92:4fc01daae5a5 291 /** @defgroup DMA2D_CLUT_CM
bogdanm 92:4fc01daae5a5 292 * @{
bogdanm 92:4fc01daae5a5 293 */
bogdanm 92:4fc01daae5a5 294 #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
bogdanm 92:4fc01daae5a5 295 #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
bogdanm 92:4fc01daae5a5 296
bogdanm 92:4fc01daae5a5 297 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
bogdanm 92:4fc01daae5a5 298 /**
bogdanm 92:4fc01daae5a5 299 * @}
bogdanm 92:4fc01daae5a5 300 */
bogdanm 92:4fc01daae5a5 301
bogdanm 92:4fc01daae5a5 302 /** @defgroup DMA2D_Size_Clut
bogdanm 92:4fc01daae5a5 303 * @{
bogdanm 92:4fc01daae5a5 304 */
bogdanm 92:4fc01daae5a5 305 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
bogdanm 92:4fc01daae5a5 306
bogdanm 92:4fc01daae5a5 307 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
bogdanm 92:4fc01daae5a5 308 /**
bogdanm 92:4fc01daae5a5 309 * @}
bogdanm 92:4fc01daae5a5 310 */
bogdanm 92:4fc01daae5a5 311
bogdanm 92:4fc01daae5a5 312 /** @defgroup DMA2D_DeadTime
bogdanm 92:4fc01daae5a5 313 * @{
bogdanm 92:4fc01daae5a5 314 */
bogdanm 92:4fc01daae5a5 315 #define LINE_WATERMARK DMA2D_LWR_LW
bogdanm 92:4fc01daae5a5 316
bogdanm 92:4fc01daae5a5 317 #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
bogdanm 92:4fc01daae5a5 318 /**
bogdanm 92:4fc01daae5a5 319 * @}
bogdanm 92:4fc01daae5a5 320 */
bogdanm 92:4fc01daae5a5 321
bogdanm 92:4fc01daae5a5 322 /** @defgroup DMA2D_Interrupts
bogdanm 92:4fc01daae5a5 323 * @{
bogdanm 92:4fc01daae5a5 324 */
bogdanm 92:4fc01daae5a5 325 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
bogdanm 92:4fc01daae5a5 326 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
bogdanm 92:4fc01daae5a5 327 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
bogdanm 92:4fc01daae5a5 328 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
bogdanm 92:4fc01daae5a5 329 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
bogdanm 92:4fc01daae5a5 330 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
bogdanm 92:4fc01daae5a5 331
bogdanm 92:4fc01daae5a5 332 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
bogdanm 92:4fc01daae5a5 333 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
bogdanm 92:4fc01daae5a5 334 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
bogdanm 92:4fc01daae5a5 335 /**
bogdanm 92:4fc01daae5a5 336 * @}
bogdanm 92:4fc01daae5a5 337 */
bogdanm 92:4fc01daae5a5 338
bogdanm 92:4fc01daae5a5 339 /** @defgroup DMA2D_Flag
bogdanm 92:4fc01daae5a5 340 * @{
bogdanm 92:4fc01daae5a5 341 */
bogdanm 92:4fc01daae5a5 342 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
bogdanm 92:4fc01daae5a5 343 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
bogdanm 92:4fc01daae5a5 344 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
bogdanm 92:4fc01daae5a5 345 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
bogdanm 92:4fc01daae5a5 346 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
bogdanm 92:4fc01daae5a5 347 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
bogdanm 92:4fc01daae5a5 348
bogdanm 92:4fc01daae5a5 349 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
bogdanm 92:4fc01daae5a5 350 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
bogdanm 92:4fc01daae5a5 351 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
bogdanm 92:4fc01daae5a5 352 /**
bogdanm 92:4fc01daae5a5 353 * @}
bogdanm 92:4fc01daae5a5 354 */
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 /**
bogdanm 92:4fc01daae5a5 357 * @}
bogdanm 92:4fc01daae5a5 358 */
bogdanm 92:4fc01daae5a5 359 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 360
bogdanm 92:4fc01daae5a5 361 /** @brief Reset DMA2D handle state
bogdanm 92:4fc01daae5a5 362 * @param __HANDLE__: specifies the DMA2D handle.
bogdanm 92:4fc01daae5a5 363 * @retval None
bogdanm 92:4fc01daae5a5 364 */
bogdanm 92:4fc01daae5a5 365 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
bogdanm 92:4fc01daae5a5 366
bogdanm 92:4fc01daae5a5 367 /**
bogdanm 92:4fc01daae5a5 368 * @brief Enable the DMA2D.
bogdanm 92:4fc01daae5a5 369 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 370 * @retval None.
bogdanm 92:4fc01daae5a5 371 */
bogdanm 92:4fc01daae5a5 372 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
bogdanm 92:4fc01daae5a5 373
bogdanm 92:4fc01daae5a5 374 /**
bogdanm 92:4fc01daae5a5 375 * @brief Disable the DMA2D.
bogdanm 92:4fc01daae5a5 376 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 377 * @retval None.
bogdanm 92:4fc01daae5a5 378 */
bogdanm 92:4fc01daae5a5 379 #define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
bogdanm 92:4fc01daae5a5 380
bogdanm 92:4fc01daae5a5 381 /* Interrupt & Flag management */
bogdanm 92:4fc01daae5a5 382 /**
bogdanm 92:4fc01daae5a5 383 * @brief Get the DMA2D pending flags.
bogdanm 92:4fc01daae5a5 384 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 385 * @param __FLAG__: Get the specified flag.
bogdanm 92:4fc01daae5a5 386 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 387 * @arg DMA2D_FLAG_CE: Configuration error flag
bogdanm 92:4fc01daae5a5 388 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
bogdanm 92:4fc01daae5a5 389 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
bogdanm 92:4fc01daae5a5 390 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
bogdanm 92:4fc01daae5a5 391 * @arg DMA2D_FLAG_TC: Transfer complete flag
bogdanm 92:4fc01daae5a5 392 * @arg DMA2D_FLAG_TE: Transfer error flag
bogdanm 92:4fc01daae5a5 393 * @retval The state of FLAG.
bogdanm 92:4fc01daae5a5 394 */
bogdanm 92:4fc01daae5a5 395 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
bogdanm 92:4fc01daae5a5 396
bogdanm 92:4fc01daae5a5 397 /**
bogdanm 92:4fc01daae5a5 398 * @brief Clears the DMA2D pending flags.
bogdanm 92:4fc01daae5a5 399 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 400 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 401 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 402 * @arg DMA2D_FLAG_CE: Configuration error flag
bogdanm 92:4fc01daae5a5 403 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
bogdanm 92:4fc01daae5a5 404 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
bogdanm 92:4fc01daae5a5 405 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
bogdanm 92:4fc01daae5a5 406 * @arg DMA2D_FLAG_TC: Transfer complete flag
bogdanm 92:4fc01daae5a5 407 * @arg DMA2D_FLAG_TE: Transfer error flag
bogdanm 92:4fc01daae5a5 408 * @retval None
bogdanm 92:4fc01daae5a5 409 */
bogdanm 92:4fc01daae5a5 410 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
bogdanm 92:4fc01daae5a5 411
bogdanm 92:4fc01daae5a5 412 /**
bogdanm 92:4fc01daae5a5 413 * @brief Enables the specified DMA2D interrupts.
bogdanm 92:4fc01daae5a5 414 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 415 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
bogdanm 92:4fc01daae5a5 416 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 417 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 92:4fc01daae5a5 418 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 419 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 92:4fc01daae5a5 420 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 92:4fc01daae5a5 421 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 422 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 92:4fc01daae5a5 423 * @retval None
bogdanm 92:4fc01daae5a5 424 */
bogdanm 92:4fc01daae5a5 425 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 426
bogdanm 92:4fc01daae5a5 427 /**
bogdanm 92:4fc01daae5a5 428 * @brief Disables the specified DMA2D interrupts.
bogdanm 92:4fc01daae5a5 429 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 430 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
bogdanm 92:4fc01daae5a5 431 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 432 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 92:4fc01daae5a5 433 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 434 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 92:4fc01daae5a5 435 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 92:4fc01daae5a5 436 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 437 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 92:4fc01daae5a5 438 * @retval None
bogdanm 92:4fc01daae5a5 439 */
bogdanm 92:4fc01daae5a5 440 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 441
bogdanm 92:4fc01daae5a5 442 /**
bogdanm 92:4fc01daae5a5 443 * @brief Checks whether the specified DMA2D interrupt has occurred or not.
bogdanm 92:4fc01daae5a5 444 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 445 * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
bogdanm 92:4fc01daae5a5 446 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 447 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 92:4fc01daae5a5 448 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 449 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 92:4fc01daae5a5 450 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 92:4fc01daae5a5 451 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 452 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 92:4fc01daae5a5 453 * @retval The state of INTERRUPT.
bogdanm 92:4fc01daae5a5 454 */
bogdanm 92:4fc01daae5a5 455 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 456
bogdanm 92:4fc01daae5a5 457 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 458
bogdanm 92:4fc01daae5a5 459 /* Initialization and de-initialization functions *******************************/
bogdanm 92:4fc01daae5a5 460 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 461 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 462 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 92:4fc01daae5a5 463 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 92:4fc01daae5a5 464
bogdanm 92:4fc01daae5a5 465 /* IO operation functions *******************************************************/
bogdanm 92:4fc01daae5a5 466 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
bogdanm 92:4fc01daae5a5 467 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
bogdanm 92:4fc01daae5a5 468 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
bogdanm 92:4fc01daae5a5 469 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
bogdanm 92:4fc01daae5a5 470 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 471 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 472 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 473 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 474 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 475
bogdanm 92:4fc01daae5a5 476 /* Peripheral Control functions *************************************************/
bogdanm 92:4fc01daae5a5 477 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 92:4fc01daae5a5 478 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
bogdanm 92:4fc01daae5a5 479 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 92:4fc01daae5a5 480 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 92:4fc01daae5a5 481 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
bogdanm 92:4fc01daae5a5 482
bogdanm 92:4fc01daae5a5 483 /* Peripheral State functions ***************************************************/
bogdanm 92:4fc01daae5a5 484 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 485 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 486
bogdanm 92:4fc01daae5a5 487 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 92:4fc01daae5a5 488
bogdanm 92:4fc01daae5a5 489 /**
bogdanm 92:4fc01daae5a5 490 * @}
bogdanm 92:4fc01daae5a5 491 */
bogdanm 92:4fc01daae5a5 492
bogdanm 92:4fc01daae5a5 493 /**
bogdanm 92:4fc01daae5a5 494 * @}
bogdanm 92:4fc01daae5a5 495 */
bogdanm 92:4fc01daae5a5 496
bogdanm 92:4fc01daae5a5 497 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 498 }
bogdanm 92:4fc01daae5a5 499 #endif
bogdanm 92:4fc01daae5a5 500
bogdanm 92:4fc01daae5a5 501 #endif /* __STM32F4xx_HAL_DMA2D_H */
bogdanm 92:4fc01daae5a5 502
bogdanm 92:4fc01daae5a5 503
bogdanm 92:4fc01daae5a5 504 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/