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TARGET_LPC4088/core_ca9.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
92:4fc01daae5a5 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**************************************************************************//**
bogdanm 92:4fc01daae5a5 2 * @file core_ca9.h
bogdanm 92:4fc01daae5a5 3 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
bogdanm 92:4fc01daae5a5 4 * @version
bogdanm 92:4fc01daae5a5 5 * @date 25 March 2013
bogdanm 92:4fc01daae5a5 6 *
bogdanm 92:4fc01daae5a5 7 * @note
bogdanm 92:4fc01daae5a5 8 *
bogdanm 92:4fc01daae5a5 9 ******************************************************************************/
bogdanm 92:4fc01daae5a5 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
bogdanm 92:4fc01daae5a5 11
bogdanm 92:4fc01daae5a5 12 All rights reserved.
bogdanm 92:4fc01daae5a5 13 Redistribution and use in source and binary forms, with or without
bogdanm 92:4fc01daae5a5 14 modification, are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 - Redistributions of source code must retain the above copyright
bogdanm 92:4fc01daae5a5 16 notice, this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 92:4fc01daae5a5 18 notice, this list of conditions and the following disclaimer in the
bogdanm 92:4fc01daae5a5 19 documentation and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 92:4fc01daae5a5 21 to endorse or promote products derived from this software without
bogdanm 92:4fc01daae5a5 22 specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 92:4fc01daae5a5 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 92:4fc01daae5a5 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 92:4fc01daae5a5 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 92:4fc01daae5a5 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 92:4fc01daae5a5 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 92:4fc01daae5a5 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 92:4fc01daae5a5 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 35 ---------------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 36
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #if defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 92:4fc01daae5a5 40 #endif
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 #ifndef __CORE_CA9_H_GENERIC
bogdanm 92:4fc01daae5a5 47 #define __CORE_CA9_H_GENERIC
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49
bogdanm 92:4fc01daae5a5 50 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 92:4fc01daae5a5 51 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 92:4fc01daae5a5 54 Function definitions in header files are used to allow 'inlining'.
bogdanm 92:4fc01daae5a5 55
bogdanm 92:4fc01daae5a5 56 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 92:4fc01daae5a5 57 Unions are used for effective representation of core registers.
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 92:4fc01daae5a5 60 Function-like macros are used to allow more efficient code.
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62
bogdanm 92:4fc01daae5a5 63
bogdanm 92:4fc01daae5a5 64 /*******************************************************************************
bogdanm 92:4fc01daae5a5 65 * CMSIS definitions
bogdanm 92:4fc01daae5a5 66 ******************************************************************************/
bogdanm 92:4fc01daae5a5 67 /** \ingroup Cortex_A9
bogdanm 92:4fc01daae5a5 68 @{
bogdanm 92:4fc01daae5a5 69 */
bogdanm 92:4fc01daae5a5 70
bogdanm 92:4fc01daae5a5 71 /* CMSIS CA9 definitions */
bogdanm 92:4fc01daae5a5 72 #define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 92:4fc01daae5a5 73 #define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
bogdanm 92:4fc01daae5a5 74 #define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
bogdanm 92:4fc01daae5a5 75 __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 92:4fc01daae5a5 76
bogdanm 92:4fc01daae5a5 77 #define __CORTEX_A (0x09) /*!< Cortex-A Core */
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 81 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 92:4fc01daae5a5 82 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 92:4fc01daae5a5 83 #define __STATIC_INLINE static __inline
bogdanm 92:4fc01daae5a5 84 #define __STATIC_ASM static __asm
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 #elif defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 87 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 92:4fc01daae5a5 88 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 92:4fc01daae5a5 89 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 90 #define __STATIC_ASM static __asm
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92 #elif defined ( __TMS470__ )
bogdanm 92:4fc01daae5a5 93 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 92:4fc01daae5a5 94 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 95 #define __STATIC_ASM static __asm
bogdanm 92:4fc01daae5a5 96
bogdanm 92:4fc01daae5a5 97 #elif defined ( __GNUC__ )
bogdanm 92:4fc01daae5a5 98 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 92:4fc01daae5a5 99 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 92:4fc01daae5a5 100 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 101 #define __STATIC_ASM static __asm
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 #elif defined ( __TASKING__ )
bogdanm 92:4fc01daae5a5 104 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 92:4fc01daae5a5 105 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 92:4fc01daae5a5 106 #define __STATIC_INLINE static inline
bogdanm 92:4fc01daae5a5 107 #define __STATIC_ASM static __asm
bogdanm 92:4fc01daae5a5 108
bogdanm 92:4fc01daae5a5 109 #endif
bogdanm 92:4fc01daae5a5 110
bogdanm 92:4fc01daae5a5 111 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
bogdanm 92:4fc01daae5a5 112 */
bogdanm 92:4fc01daae5a5 113 #if defined ( __CC_ARM )
bogdanm 92:4fc01daae5a5 114 #if defined __TARGET_FPU_VFP
bogdanm 92:4fc01daae5a5 115 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 116 #define __FPU_USED 1
bogdanm 92:4fc01daae5a5 117 #else
bogdanm 92:4fc01daae5a5 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 119 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 120 #endif
bogdanm 92:4fc01daae5a5 121 #else
bogdanm 92:4fc01daae5a5 122 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 123 #endif
bogdanm 92:4fc01daae5a5 124
bogdanm 92:4fc01daae5a5 125 #elif defined ( __ICCARM__ )
bogdanm 92:4fc01daae5a5 126 #if defined __ARMVFP__
bogdanm 92:4fc01daae5a5 127 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 128 #define __FPU_USED 1
bogdanm 92:4fc01daae5a5 129 #else
bogdanm 92:4fc01daae5a5 130 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 131 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 132 #endif
bogdanm 92:4fc01daae5a5 133 #else
bogdanm 92:4fc01daae5a5 134 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 135 #endif
bogdanm 92:4fc01daae5a5 136
bogdanm 92:4fc01daae5a5 137 #elif defined ( __TMS470__ )
bogdanm 92:4fc01daae5a5 138 #if defined __TI_VFP_SUPPORT__
bogdanm 92:4fc01daae5a5 139 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 140 #define __FPU_USED 1
bogdanm 92:4fc01daae5a5 141 #else
bogdanm 92:4fc01daae5a5 142 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 143 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 144 #endif
bogdanm 92:4fc01daae5a5 145 #else
bogdanm 92:4fc01daae5a5 146 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 147 #endif
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 #elif defined ( __GNUC__ )
bogdanm 92:4fc01daae5a5 150 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 92:4fc01daae5a5 151 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 152 #define __FPU_USED 1
bogdanm 92:4fc01daae5a5 153 #else
bogdanm 92:4fc01daae5a5 154 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 155 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 156 #endif
bogdanm 92:4fc01daae5a5 157 #else
bogdanm 92:4fc01daae5a5 158 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 159 #endif
bogdanm 92:4fc01daae5a5 160
bogdanm 92:4fc01daae5a5 161 #elif defined ( __TASKING__ )
bogdanm 92:4fc01daae5a5 162 #if defined __FPU_VFP__
bogdanm 92:4fc01daae5a5 163 #if (__FPU_PRESENT == 1)
bogdanm 92:4fc01daae5a5 164 #define __FPU_USED 1
bogdanm 92:4fc01daae5a5 165 #else
bogdanm 92:4fc01daae5a5 166 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 92:4fc01daae5a5 167 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 168 #endif
bogdanm 92:4fc01daae5a5 169 #else
bogdanm 92:4fc01daae5a5 170 #define __FPU_USED 0
bogdanm 92:4fc01daae5a5 171 #endif
bogdanm 92:4fc01daae5a5 172 #endif
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174 #include <stdint.h> /*!< standard types definitions */
bogdanm 92:4fc01daae5a5 175 #include "core_caInstr.h" /*!< Core Instruction Access */
bogdanm 92:4fc01daae5a5 176 #include "core_caFunc.h" /*!< Core Function Access */
bogdanm 92:4fc01daae5a5 177 #include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179 #endif /* __CORE_CA9_H_GENERIC */
bogdanm 92:4fc01daae5a5 180
bogdanm 92:4fc01daae5a5 181 #ifndef __CMSIS_GENERIC
bogdanm 92:4fc01daae5a5 182
bogdanm 92:4fc01daae5a5 183 #ifndef __CORE_CA9_H_DEPENDANT
bogdanm 92:4fc01daae5a5 184 #define __CORE_CA9_H_DEPENDANT
bogdanm 92:4fc01daae5a5 185
bogdanm 92:4fc01daae5a5 186 /* check device defines and use defaults */
bogdanm 92:4fc01daae5a5 187 #if defined __CHECK_DEVICE_DEFINES
bogdanm 92:4fc01daae5a5 188 #ifndef __CA9_REV
bogdanm 92:4fc01daae5a5 189 #define __CA9_REV 0x0000
bogdanm 92:4fc01daae5a5 190 #warning "__CA9_REV not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 191 #endif
bogdanm 92:4fc01daae5a5 192
bogdanm 92:4fc01daae5a5 193 #ifndef __FPU_PRESENT
bogdanm 92:4fc01daae5a5 194 #define __FPU_PRESENT 1
bogdanm 92:4fc01daae5a5 195 #warning "__FPU_PRESENT not defined in device header file; using default!"
bogdanm 92:4fc01daae5a5 196 #endif
bogdanm 92:4fc01daae5a5 197
bogdanm 92:4fc01daae5a5 198 #ifndef __Vendor_SysTickConfig
bogdanm 92:4fc01daae5a5 199 #define __Vendor_SysTickConfig 1
bogdanm 92:4fc01daae5a5 200 #endif
bogdanm 92:4fc01daae5a5 201
bogdanm 92:4fc01daae5a5 202 #if __Vendor_SysTickConfig == 0
bogdanm 92:4fc01daae5a5 203 #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
bogdanm 92:4fc01daae5a5 204 #endif
bogdanm 92:4fc01daae5a5 205 #endif
bogdanm 92:4fc01daae5a5 206
bogdanm 92:4fc01daae5a5 207 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 92:4fc01daae5a5 208 /**
bogdanm 92:4fc01daae5a5 209 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 92:4fc01daae5a5 210
bogdanm 92:4fc01daae5a5 211 <strong>IO Type Qualifiers</strong> are used
bogdanm 92:4fc01daae5a5 212 \li to specify the access to peripheral variables.
bogdanm 92:4fc01daae5a5 213 \li for automatic generation of peripheral register debug information.
bogdanm 92:4fc01daae5a5 214 */
bogdanm 92:4fc01daae5a5 215 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 216 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 217 #else
bogdanm 92:4fc01daae5a5 218 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 92:4fc01daae5a5 219 #endif
bogdanm 92:4fc01daae5a5 220 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 92:4fc01daae5a5 221 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 92:4fc01daae5a5 222
bogdanm 92:4fc01daae5a5 223 /*@} end of group Cortex_A9 */
bogdanm 92:4fc01daae5a5 224
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226 /*******************************************************************************
bogdanm 92:4fc01daae5a5 227 * Register Abstraction
bogdanm 92:4fc01daae5a5 228 ******************************************************************************/
bogdanm 92:4fc01daae5a5 229 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 92:4fc01daae5a5 230 \brief Type definitions and defines for Cortex-A processor based devices.
bogdanm 92:4fc01daae5a5 231 */
bogdanm 92:4fc01daae5a5 232
bogdanm 92:4fc01daae5a5 233 /** \ingroup CMSIS_core_register
bogdanm 92:4fc01daae5a5 234 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 92:4fc01daae5a5 235 \brief Core Register type definitions.
bogdanm 92:4fc01daae5a5 236 @{
bogdanm 92:4fc01daae5a5 237 */
bogdanm 92:4fc01daae5a5 238
bogdanm 92:4fc01daae5a5 239 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 92:4fc01daae5a5 240 */
bogdanm 92:4fc01daae5a5 241 typedef union
bogdanm 92:4fc01daae5a5 242 {
bogdanm 92:4fc01daae5a5 243 struct
bogdanm 92:4fc01daae5a5 244 {
bogdanm 92:4fc01daae5a5 245 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 92:4fc01daae5a5 246 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 92:4fc01daae5a5 247 uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
bogdanm 92:4fc01daae5a5 248 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 92:4fc01daae5a5 249 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 92:4fc01daae5a5 250 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 92:4fc01daae5a5 251 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 92:4fc01daae5a5 252 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 92:4fc01daae5a5 253 } b; /*!< Structure used for bit access */
bogdanm 92:4fc01daae5a5 254 uint32_t w; /*!< Type used for word access */
bogdanm 92:4fc01daae5a5 255 } APSR_Type;
bogdanm 92:4fc01daae5a5 256
bogdanm 92:4fc01daae5a5 257
bogdanm 92:4fc01daae5a5 258 /*@} end of group CMSIS_CORE */
bogdanm 92:4fc01daae5a5 259
bogdanm 92:4fc01daae5a5 260 /*@} end of CMSIS_Core_FPUFunctions */
bogdanm 92:4fc01daae5a5 261
bogdanm 92:4fc01daae5a5 262
bogdanm 92:4fc01daae5a5 263 #endif /* __CORE_CA9_H_GENERIC */
bogdanm 92:4fc01daae5a5 264
bogdanm 92:4fc01daae5a5 265 #endif /* __CMSIS_GENERIC */
bogdanm 92:4fc01daae5a5 266
bogdanm 92:4fc01daae5a5 267 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 268 }
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270
bogdanm 92:4fc01daae5a5 271 #endif