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TARGET_ARCH_MAX/stm32f4xx_hal_rcc.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
98:8ab26030e058 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_rcc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 89:552587b429a1 7 * @brief Header file of RCC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_RCC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_RCC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup RCC
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 58
bogdanm 89:552587b429a1 59 /**
bogdanm 89:552587b429a1 60 * @brief RCC PLL configuration structure definition
bogdanm 89:552587b429a1 61 */
bogdanm 89:552587b429a1 62 typedef struct
bogdanm 89:552587b429a1 63 {
bogdanm 89:552587b429a1 64 uint32_t PLLState; /*!< The new state of the PLL.
bogdanm 89:552587b429a1 65 This parameter can be a value of @ref RCC_PLL_Config */
bogdanm 89:552587b429a1 66
bogdanm 89:552587b429a1 67 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm 89:552587b429a1 68 This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm 89:552587b429a1 69
bogdanm 89:552587b429a1 70 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
bogdanm 89:552587b429a1 71 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
bogdanm 89:552587b429a1 72
bogdanm 89:552587b429a1 73 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
bogdanm 89:552587b429a1 74 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
bogdanm 89:552587b429a1 75
bogdanm 89:552587b429a1 76 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
bogdanm 89:552587b429a1 77 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
bogdanm 89:552587b429a1 78
bogdanm 89:552587b429a1 79 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
bogdanm 89:552587b429a1 80 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
bogdanm 89:552587b429a1 81
bogdanm 89:552587b429a1 82 }RCC_PLLInitTypeDef;
bogdanm 89:552587b429a1 83
bogdanm 89:552587b429a1 84 /**
bogdanm 89:552587b429a1 85 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 89:552587b429a1 86 */
bogdanm 89:552587b429a1 87 typedef struct
bogdanm 89:552587b429a1 88 {
bogdanm 89:552587b429a1 89 uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm 89:552587b429a1 90 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 89:552587b429a1 91
bogdanm 89:552587b429a1 92 uint32_t HSEState; /*!< The new state of the HSE.
bogdanm 89:552587b429a1 93 This parameter can be a value of @ref RCC_HSE_Config */
bogdanm 89:552587b429a1 94
bogdanm 89:552587b429a1 95 uint32_t LSEState; /*!< The new state of the LSE.
bogdanm 89:552587b429a1 96 This parameter can be a value of @ref RCC_LSE_Config */
bogdanm 89:552587b429a1 97
bogdanm 89:552587b429a1 98 uint32_t HSIState; /*!< The new state of the HSI.
bogdanm 89:552587b429a1 99 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 89:552587b429a1 100
bogdanm 89:552587b429a1 101 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm 89:552587b429a1 102 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm 89:552587b429a1 103
bogdanm 89:552587b429a1 104 uint32_t LSIState; /*!< The new state of the LSI.
bogdanm 89:552587b429a1 105 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 89:552587b429a1 106
bogdanm 89:552587b429a1 107 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 89:552587b429a1 108
bogdanm 89:552587b429a1 109 }RCC_OscInitTypeDef;
bogdanm 89:552587b429a1 110
bogdanm 89:552587b429a1 111 /**
bogdanm 89:552587b429a1 112 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 89:552587b429a1 113 */
bogdanm 89:552587b429a1 114 typedef struct
bogdanm 89:552587b429a1 115 {
bogdanm 89:552587b429a1 116 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 89:552587b429a1 117 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 89:552587b429a1 118
bogdanm 89:552587b429a1 119 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 89:552587b429a1 120 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 89:552587b429a1 121
bogdanm 89:552587b429a1 122 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 89:552587b429a1 123 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 89:552587b429a1 124
bogdanm 89:552587b429a1 125 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 89:552587b429a1 126 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 89:552587b429a1 127
bogdanm 89:552587b429a1 128 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 89:552587b429a1 129 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 89:552587b429a1 130
bogdanm 89:552587b429a1 131 }RCC_ClkInitTypeDef;
bogdanm 89:552587b429a1 132
bogdanm 89:552587b429a1 133 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 134 /** @defgroup RCC_Exported_Constants
bogdanm 89:552587b429a1 135 * @{
bogdanm 89:552587b429a1 136 */
bogdanm 89:552587b429a1 137
bogdanm 89:552587b429a1 138 /** @defgroup RCC_BitAddress_AliasRegion
bogdanm 89:552587b429a1 139 * @brief RCC registers bit address in the alias region
bogdanm 89:552587b429a1 140 * @{
bogdanm 89:552587b429a1 141 */
bogdanm 89:552587b429a1 142 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm 89:552587b429a1 143 /* --- CR Register ---*/
bogdanm 89:552587b429a1 144 /* Alias word address of HSION bit */
bogdanm 89:552587b429a1 145 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm 89:552587b429a1 146 #define HSION_BitNumber 0x00
bogdanm 89:552587b429a1 147 #define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
bogdanm 89:552587b429a1 148 /* Alias word address of CSSON bit */
bogdanm 89:552587b429a1 149 #define CSSON_BitNumber 0x13
bogdanm 89:552587b429a1 150 #define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
bogdanm 89:552587b429a1 151 /* Alias word address of PLLON bit */
bogdanm 89:552587b429a1 152 #define PLLON_BitNumber 0x18
bogdanm 89:552587b429a1 153 #define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
bogdanm 89:552587b429a1 154 /* Alias word address of PLLI2SON bit */
bogdanm 89:552587b429a1 155 #define PLLI2SON_BitNumber 0x1A
bogdanm 89:552587b429a1 156 #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
bogdanm 89:552587b429a1 157
bogdanm 89:552587b429a1 158 /* --- CFGR Register ---*/
bogdanm 89:552587b429a1 159 /* Alias word address of I2SSRC bit */
bogdanm 89:552587b429a1 160 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
bogdanm 89:552587b429a1 161 #define I2SSRC_BitNumber 0x17
bogdanm 89:552587b429a1 162 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
bogdanm 89:552587b429a1 163
bogdanm 89:552587b429a1 164 /* --- BDCR Register ---*/
bogdanm 89:552587b429a1 165 /* Alias word address of RTCEN bit */
bogdanm 89:552587b429a1 166 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
bogdanm 89:552587b429a1 167 #define RTCEN_BitNumber 0x0F
bogdanm 89:552587b429a1 168 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
bogdanm 89:552587b429a1 169 /* Alias word address of BDRST bit */
bogdanm 89:552587b429a1 170 #define BDRST_BitNumber 0x10
bogdanm 89:552587b429a1 171 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
bogdanm 89:552587b429a1 172
bogdanm 89:552587b429a1 173 /* --- CSR Register ---*/
bogdanm 89:552587b429a1 174 /* Alias word address of LSION bit */
bogdanm 89:552587b429a1 175 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
bogdanm 89:552587b429a1 176 #define LSION_BitNumber 0x00
bogdanm 89:552587b429a1 177 #define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
bogdanm 89:552587b429a1 178
bogdanm 89:552587b429a1 179 /* CR register byte 3 (Bits[23:16]) base address */
bogdanm 89:552587b429a1 180 #define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
bogdanm 89:552587b429a1 181
bogdanm 89:552587b429a1 182 /* CIR register byte 2 (Bits[15:8]) base address */
bogdanm 89:552587b429a1 183 #define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
bogdanm 89:552587b429a1 184
bogdanm 89:552587b429a1 185 /* CIR register byte 3 (Bits[23:16]) base address */
bogdanm 89:552587b429a1 186 #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
bogdanm 89:552587b429a1 187
bogdanm 89:552587b429a1 188 /* BDCR register base address */
bogdanm 89:552587b429a1 189 #define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm 89:552587b429a1 190
bogdanm 89:552587b429a1 191
bogdanm 89:552587b429a1 192 #define DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto 98:8ab26030e058 193 #define LSE_TIMEOUT_VALUE ((uint32_t)5000)
bogdanm 89:552587b429a1 194 /**
bogdanm 89:552587b429a1 195 * @}
bogdanm 89:552587b429a1 196 */
bogdanm 89:552587b429a1 197
bogdanm 89:552587b429a1 198 /** @defgroup RCC_Oscillator_Type
bogdanm 89:552587b429a1 199 * @{
bogdanm 89:552587b429a1 200 */
bogdanm 89:552587b429a1 201 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 202 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 203 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 204 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 205 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 206
bogdanm 89:552587b429a1 207 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
bogdanm 89:552587b429a1 208 /**
bogdanm 89:552587b429a1 209 * @}
bogdanm 89:552587b429a1 210 */
bogdanm 89:552587b429a1 211
bogdanm 89:552587b429a1 212 /** @defgroup RCC_HSE_Config
bogdanm 89:552587b429a1 213 * @{
bogdanm 89:552587b429a1 214 */
bogdanm 89:552587b429a1 215 #define RCC_HSE_OFF ((uint8_t)0x00)
bogdanm 89:552587b429a1 216 #define RCC_HSE_ON ((uint8_t)0x01)
bogdanm 89:552587b429a1 217 #define RCC_HSE_BYPASS ((uint8_t)0x05)
bogdanm 89:552587b429a1 218
bogdanm 89:552587b429a1 219 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
bogdanm 89:552587b429a1 220 ((HSE) == RCC_HSE_BYPASS))
bogdanm 89:552587b429a1 221 /**
bogdanm 89:552587b429a1 222 * @}
bogdanm 89:552587b429a1 223 */
bogdanm 89:552587b429a1 224
bogdanm 89:552587b429a1 225 /** @defgroup RCC_LSE_Config
bogdanm 89:552587b429a1 226 * @{
bogdanm 89:552587b429a1 227 */
bogdanm 89:552587b429a1 228 #define RCC_LSE_OFF ((uint8_t)0x00)
bogdanm 89:552587b429a1 229 #define RCC_LSE_ON ((uint8_t)0x01)
bogdanm 89:552587b429a1 230 #define RCC_LSE_BYPASS ((uint8_t)0x05)
bogdanm 89:552587b429a1 231
bogdanm 89:552587b429a1 232 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
bogdanm 89:552587b429a1 233 ((LSE) == RCC_LSE_BYPASS))
bogdanm 89:552587b429a1 234 /**
bogdanm 89:552587b429a1 235 * @}
bogdanm 89:552587b429a1 236 */
bogdanm 89:552587b429a1 237
bogdanm 89:552587b429a1 238 /** @defgroup RCC_HSI_Config
bogdanm 89:552587b429a1 239 * @{
bogdanm 89:552587b429a1 240 */
bogdanm 89:552587b429a1 241 #define RCC_HSI_OFF ((uint8_t)0x00)
bogdanm 89:552587b429a1 242 #define RCC_HSI_ON ((uint8_t)0x01)
bogdanm 89:552587b429a1 243
bogdanm 89:552587b429a1 244 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
bogdanm 89:552587b429a1 245 /**
bogdanm 89:552587b429a1 246 * @}
bogdanm 89:552587b429a1 247 */
bogdanm 89:552587b429a1 248
bogdanm 89:552587b429a1 249 /** @defgroup RCC_LSI_Config
bogdanm 89:552587b429a1 250 * @{
bogdanm 89:552587b429a1 251 */
bogdanm 89:552587b429a1 252 #define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm 89:552587b429a1 253 #define RCC_LSI_ON ((uint8_t)0x01)
bogdanm 89:552587b429a1 254
bogdanm 89:552587b429a1 255 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
bogdanm 89:552587b429a1 256 /**
bogdanm 89:552587b429a1 257 * @}
bogdanm 89:552587b429a1 258 */
bogdanm 89:552587b429a1 259
bogdanm 89:552587b429a1 260 /** @defgroup RCC_PLL_Config
bogdanm 89:552587b429a1 261 * @{
bogdanm 89:552587b429a1 262 */
bogdanm 89:552587b429a1 263 #define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm 89:552587b429a1 264 #define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm 89:552587b429a1 265 #define RCC_PLL_ON ((uint8_t)0x02)
bogdanm 89:552587b429a1 266
bogdanm 89:552587b429a1 267 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
bogdanm 89:552587b429a1 268 /**
bogdanm 89:552587b429a1 269 * @}
bogdanm 89:552587b429a1 270 */
bogdanm 89:552587b429a1 271
bogdanm 89:552587b429a1 272 /** @defgroup RCC_PLLP_Clock_Divider
bogdanm 89:552587b429a1 273 * @{
bogdanm 89:552587b429a1 274 */
bogdanm 89:552587b429a1 275 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 276 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 277 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
bogdanm 89:552587b429a1 278 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 279 /**
bogdanm 89:552587b429a1 280 * @}
bogdanm 89:552587b429a1 281 */
bogdanm 89:552587b429a1 282
bogdanm 89:552587b429a1 283 /** @defgroup RCC_PLL_Clock_Source
bogdanm 89:552587b429a1 284 * @{
bogdanm 89:552587b429a1 285 */
bogdanm 89:552587b429a1 286 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
bogdanm 89:552587b429a1 287 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
bogdanm 89:552587b429a1 288
bogdanm 89:552587b429a1 289 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
bogdanm 89:552587b429a1 290 ((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm 89:552587b429a1 291 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
bogdanm 89:552587b429a1 292 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm 89:552587b429a1 293 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
bogdanm 89:552587b429a1 294 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
bogdanm 89:552587b429a1 295
bogdanm 89:552587b429a1 296 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm 89:552587b429a1 297 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm 89:552587b429a1 298
bogdanm 89:552587b429a1 299 /**
bogdanm 89:552587b429a1 300 * @}
bogdanm 89:552587b429a1 301 */
bogdanm 89:552587b429a1 302
bogdanm 89:552587b429a1 303 /** @defgroup RCC_System_Clock_Type
bogdanm 89:552587b429a1 304 * @{
bogdanm 89:552587b429a1 305 */
bogdanm 89:552587b429a1 306 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 307 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm 89:552587b429a1 308 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 309 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 310
bogdanm 89:552587b429a1 311 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
bogdanm 89:552587b429a1 312 /**
bogdanm 89:552587b429a1 313 * @}
bogdanm 89:552587b429a1 314 */
bogdanm 89:552587b429a1 315
bogdanm 89:552587b429a1 316 /** @defgroup RCC_System_Clock_Source
bogdanm 89:552587b429a1 317 * @{
bogdanm 89:552587b429a1 318 */
bogdanm 89:552587b429a1 319 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm 89:552587b429a1 320 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm 89:552587b429a1 321 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm 89:552587b429a1 322
bogdanm 89:552587b429a1 323 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
bogdanm 89:552587b429a1 324 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
bogdanm 89:552587b429a1 325 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm 89:552587b429a1 326 /**
bogdanm 89:552587b429a1 327 * @}
bogdanm 89:552587b429a1 328 */
bogdanm 89:552587b429a1 329
bogdanm 89:552587b429a1 330 /** @defgroup RCC_AHB_Clock_Source
bogdanm 89:552587b429a1 331 * @{
bogdanm 89:552587b429a1 332 */
bogdanm 89:552587b429a1 333 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm 89:552587b429a1 334 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm 89:552587b429a1 335 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm 89:552587b429a1 336 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm 89:552587b429a1 337 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm 89:552587b429a1 338 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm 89:552587b429a1 339 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm 89:552587b429a1 340 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm 89:552587b429a1 341 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm 89:552587b429a1 342
bogdanm 89:552587b429a1 343 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
bogdanm 89:552587b429a1 344 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
bogdanm 89:552587b429a1 345 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
bogdanm 89:552587b429a1 346 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
bogdanm 89:552587b429a1 347 ((HCLK) == RCC_SYSCLK_DIV512))
bogdanm 89:552587b429a1 348 /**
bogdanm 89:552587b429a1 349 * @}
bogdanm 89:552587b429a1 350 */
bogdanm 89:552587b429a1 351
bogdanm 89:552587b429a1 352 /** @defgroup RCC_APB1_APB2_Clock_Source
bogdanm 89:552587b429a1 353 * @{
bogdanm 89:552587b429a1 354 */
bogdanm 89:552587b429a1 355 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm 89:552587b429a1 356 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm 89:552587b429a1 357 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm 89:552587b429a1 358 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm 89:552587b429a1 359 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm 89:552587b429a1 360
bogdanm 89:552587b429a1 361 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
bogdanm 89:552587b429a1 362 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
bogdanm 89:552587b429a1 363 ((PCLK) == RCC_HCLK_DIV16))
bogdanm 89:552587b429a1 364 /**
bogdanm 89:552587b429a1 365 * @}
bogdanm 89:552587b429a1 366 */
bogdanm 89:552587b429a1 367
bogdanm 89:552587b429a1 368 /** @defgroup RCC_RTC_Clock_Source
bogdanm 89:552587b429a1 369 * @{
bogdanm 89:552587b429a1 370 */
bogdanm 89:552587b429a1 371 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 372 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 373 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
bogdanm 89:552587b429a1 374 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
bogdanm 89:552587b429a1 375 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
bogdanm 89:552587b429a1 376 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
bogdanm 89:552587b429a1 377 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
bogdanm 89:552587b429a1 378 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
bogdanm 89:552587b429a1 379 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
bogdanm 89:552587b429a1 380 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
bogdanm 89:552587b429a1 381 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
bogdanm 89:552587b429a1 382 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
bogdanm 89:552587b429a1 383 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
bogdanm 89:552587b429a1 384 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
bogdanm 89:552587b429a1 385 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
bogdanm 89:552587b429a1 386 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
bogdanm 89:552587b429a1 387 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
bogdanm 89:552587b429a1 388 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
bogdanm 89:552587b429a1 389 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
bogdanm 89:552587b429a1 390 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
bogdanm 89:552587b429a1 391 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
bogdanm 89:552587b429a1 392 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
bogdanm 89:552587b429a1 393 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
bogdanm 89:552587b429a1 394 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
bogdanm 89:552587b429a1 395 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
bogdanm 89:552587b429a1 396 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
bogdanm 89:552587b429a1 397 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
bogdanm 89:552587b429a1 398 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
bogdanm 89:552587b429a1 399 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
bogdanm 89:552587b429a1 400 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
bogdanm 89:552587b429a1 401 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
bogdanm 89:552587b429a1 402 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
bogdanm 89:552587b429a1 403 /**
bogdanm 89:552587b429a1 404 * @}
bogdanm 89:552587b429a1 405 */
bogdanm 89:552587b429a1 406
bogdanm 89:552587b429a1 407 /** @defgroup RCC_I2S_Clock_Source
bogdanm 89:552587b429a1 408 * @{
bogdanm 89:552587b429a1 409 */
bogdanm 89:552587b429a1 410 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 411 #define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 412 /**
bogdanm 89:552587b429a1 413 * @}
bogdanm 89:552587b429a1 414 */
bogdanm 89:552587b429a1 415
bogdanm 89:552587b429a1 416 /** @defgroup RCC_MCO_Index
bogdanm 89:552587b429a1 417 * @{
bogdanm 89:552587b429a1 418 */
bogdanm 89:552587b429a1 419 #define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 420 #define RCC_MCO2 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 421
bogdanm 89:552587b429a1 422 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
bogdanm 89:552587b429a1 423 /**
bogdanm 89:552587b429a1 424 * @}
bogdanm 89:552587b429a1 425 */
bogdanm 89:552587b429a1 426
bogdanm 89:552587b429a1 427 /** @defgroup RCC_MCO1_Clock_Source
bogdanm 89:552587b429a1 428 * @{
bogdanm 89:552587b429a1 429 */
bogdanm 89:552587b429a1 430 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 431 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
bogdanm 89:552587b429a1 432 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
bogdanm 89:552587b429a1 433 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
bogdanm 89:552587b429a1 434
bogdanm 89:552587b429a1 435 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
bogdanm 89:552587b429a1 436 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
bogdanm 89:552587b429a1 437 /**
bogdanm 89:552587b429a1 438 * @}
bogdanm 89:552587b429a1 439 */
bogdanm 89:552587b429a1 440
bogdanm 89:552587b429a1 441 /** @defgroup RCC_MCO2_Clock_Source
bogdanm 89:552587b429a1 442 * @{
bogdanm 89:552587b429a1 443 */
bogdanm 89:552587b429a1 444 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 445 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
bogdanm 89:552587b429a1 446 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
bogdanm 89:552587b429a1 447 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
bogdanm 89:552587b429a1 448
bogdanm 89:552587b429a1 449 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
bogdanm 89:552587b429a1 450 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
bogdanm 89:552587b429a1 451 /**
bogdanm 89:552587b429a1 452 * @}
bogdanm 89:552587b429a1 453 */
bogdanm 89:552587b429a1 454
bogdanm 89:552587b429a1 455 /** @defgroup RCC_MCOx_Clock_Prescaler
bogdanm 89:552587b429a1 456 * @{
bogdanm 89:552587b429a1 457 */
bogdanm 89:552587b429a1 458 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 459 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
bogdanm 89:552587b429a1 460 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
bogdanm 89:552587b429a1 461 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
bogdanm 89:552587b429a1 462 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
bogdanm 89:552587b429a1 463
bogdanm 89:552587b429a1 464 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
bogdanm 89:552587b429a1 465 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
bogdanm 89:552587b429a1 466 ((DIV) == RCC_MCODIV_5))
bogdanm 89:552587b429a1 467 /**
bogdanm 89:552587b429a1 468 * @}
bogdanm 89:552587b429a1 469 */
bogdanm 89:552587b429a1 470
bogdanm 89:552587b429a1 471 /** @defgroup RCC_Interrupt
bogdanm 89:552587b429a1 472 * @{
bogdanm 89:552587b429a1 473 */
bogdanm 89:552587b429a1 474 #define RCC_IT_LSIRDY ((uint8_t)0x01)
bogdanm 89:552587b429a1 475 #define RCC_IT_LSERDY ((uint8_t)0x02)
bogdanm 89:552587b429a1 476 #define RCC_IT_HSIRDY ((uint8_t)0x04)
bogdanm 89:552587b429a1 477 #define RCC_IT_HSERDY ((uint8_t)0x08)
bogdanm 89:552587b429a1 478 #define RCC_IT_PLLRDY ((uint8_t)0x10)
bogdanm 89:552587b429a1 479 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
bogdanm 89:552587b429a1 480 #define RCC_IT_CSS ((uint8_t)0x80)
bogdanm 89:552587b429a1 481 /**
bogdanm 89:552587b429a1 482 * @}
bogdanm 89:552587b429a1 483 */
bogdanm 89:552587b429a1 484
bogdanm 89:552587b429a1 485 /** @defgroup RCC_Flag
bogdanm 89:552587b429a1 486 * Elements values convention: 0XXYYYYYb
bogdanm 89:552587b429a1 487 * - YYYYY : Flag position in the register
bogdanm 89:552587b429a1 488 * - 0XX : Register index
bogdanm 89:552587b429a1 489 * - 01: CR register
bogdanm 89:552587b429a1 490 * - 10: BDCR register
bogdanm 89:552587b429a1 491 * - 11: CSR register
bogdanm 89:552587b429a1 492 * @{
bogdanm 89:552587b429a1 493 */
bogdanm 89:552587b429a1 494 /* Flags in the CR register */
bogdanm 89:552587b429a1 495 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
bogdanm 89:552587b429a1 496 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm 89:552587b429a1 497 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm 89:552587b429a1 498 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
bogdanm 89:552587b429a1 499
bogdanm 89:552587b429a1 500 /* Flags in the BDCR register */
bogdanm 89:552587b429a1 501 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
bogdanm 89:552587b429a1 502
bogdanm 89:552587b429a1 503 /* Flags in the CSR register */
bogdanm 89:552587b429a1 504 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
bogdanm 89:552587b429a1 505 #define RCC_FLAG_BORRST ((uint8_t)0x79)
bogdanm 89:552587b429a1 506 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
bogdanm 89:552587b429a1 507 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
bogdanm 89:552587b429a1 508 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
bogdanm 89:552587b429a1 509 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
bogdanm 89:552587b429a1 510 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
bogdanm 89:552587b429a1 511 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
bogdanm 89:552587b429a1 512
bogdanm 89:552587b429a1 513 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm 89:552587b429a1 514 /**
bogdanm 89:552587b429a1 515 * @}
bogdanm 89:552587b429a1 516 */
bogdanm 89:552587b429a1 517
bogdanm 89:552587b429a1 518 /**
bogdanm 89:552587b429a1 519 * @}
bogdanm 89:552587b429a1 520 */
bogdanm 89:552587b429a1 521 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 522
bogdanm 89:552587b429a1 523 /** @brief Enable or disable the AHB1 peripheral clock.
bogdanm 89:552587b429a1 524 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 525 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 526 * using it.
bogdanm 89:552587b429a1 527 */
bogdanm 89:552587b429a1 528 #define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOAEN))
bogdanm 89:552587b429a1 529 #define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOBEN))
bogdanm 89:552587b429a1 530 #define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
bogdanm 89:552587b429a1 531 #define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
bogdanm 89:552587b429a1 532 #define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
Kojto 93:e188a91d3eaa 533 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
Kojto 93:e188a91d3eaa 534 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
bogdanm 89:552587b429a1 535 #define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
bogdanm 89:552587b429a1 536 #define __CRC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
bogdanm 89:552587b429a1 537 #define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
bogdanm 89:552587b429a1 538 #define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_CCMDATARAMEN))
bogdanm 89:552587b429a1 539 #define __DMA1_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA1EN))
bogdanm 89:552587b429a1 540 #define __DMA2_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2EN))
bogdanm 89:552587b429a1 541
bogdanm 89:552587b429a1 542 #define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
bogdanm 89:552587b429a1 543 #define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
bogdanm 89:552587b429a1 544 #define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
bogdanm 89:552587b429a1 545 #define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
bogdanm 89:552587b429a1 546 #define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto 93:e188a91d3eaa 547 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 93:e188a91d3eaa 548 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
bogdanm 89:552587b429a1 549 #define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
bogdanm 89:552587b429a1 550 #define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm 89:552587b429a1 551 #define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
bogdanm 89:552587b429a1 552 #define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
bogdanm 89:552587b429a1 553 #define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
bogdanm 89:552587b429a1 554 #define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
bogdanm 89:552587b429a1 555
bogdanm 89:552587b429a1 556 /** @brief Enable or disable the AHB2 peripheral clock.
bogdanm 89:552587b429a1 557 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 558 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 559 * using it.
bogdanm 89:552587b429a1 560 */
bogdanm 89:552587b429a1 561 #define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
bogdanm 89:552587b429a1 562 __SYSCFG_CLK_ENABLE();\
bogdanm 89:552587b429a1 563 }while(0)
bogdanm 89:552587b429a1 564
bogdanm 89:552587b429a1 565
bogdanm 89:552587b429a1 566 #define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
bogdanm 89:552587b429a1 567 __SYSCFG_CLK_DISABLE();\
bogdanm 89:552587b429a1 568 }while(0)
bogdanm 89:552587b429a1 569
bogdanm 89:552587b429a1 570 #define __RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
bogdanm 89:552587b429a1 571 #define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
bogdanm 89:552587b429a1 572 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 89:552587b429a1 573 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 574 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 575 * using it.
bogdanm 89:552587b429a1 576 */
bogdanm 89:552587b429a1 577 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
bogdanm 89:552587b429a1 578 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
bogdanm 89:552587b429a1 579 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
bogdanm 89:552587b429a1 580 #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
bogdanm 89:552587b429a1 581 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
bogdanm 89:552587b429a1 582 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
bogdanm 89:552587b429a1 583 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
bogdanm 89:552587b429a1 584 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
bogdanm 89:552587b429a1 585 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
bogdanm 89:552587b429a1 586 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
bogdanm 89:552587b429a1 587 #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
bogdanm 89:552587b429a1 588 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
bogdanm 89:552587b429a1 589
bogdanm 89:552587b429a1 590 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm 89:552587b429a1 591 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm 89:552587b429a1 592 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm 89:552587b429a1 593 #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
bogdanm 89:552587b429a1 594 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm 89:552587b429a1 595 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm 89:552587b429a1 596 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm 89:552587b429a1 597 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm 89:552587b429a1 598 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm 89:552587b429a1 599 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm 89:552587b429a1 600 #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm 89:552587b429a1 601 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm 89:552587b429a1 602
bogdanm 89:552587b429a1 603 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 89:552587b429a1 604 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 89:552587b429a1 605 * is disabled and the application software has to enable this clock before
bogdanm 89:552587b429a1 606 * using it.
bogdanm 89:552587b429a1 607 */
bogdanm 89:552587b429a1 608 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
bogdanm 89:552587b429a1 609 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
bogdanm 89:552587b429a1 610 #define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
bogdanm 89:552587b429a1 611 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
bogdanm 89:552587b429a1 612 #define __SDIO_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
bogdanm 89:552587b429a1 613 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
bogdanm 89:552587b429a1 614 #define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
bogdanm 89:552587b429a1 615 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
bogdanm 89:552587b429a1 616 #define __TIM9_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
bogdanm 89:552587b429a1 617 #define __TIM10_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
bogdanm 89:552587b429a1 618 #define __TIM11_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
bogdanm 89:552587b429a1 619
bogdanm 89:552587b429a1 620 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm 89:552587b429a1 621 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm 89:552587b429a1 622 #define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
bogdanm 89:552587b429a1 623 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm 89:552587b429a1 624 #define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
bogdanm 89:552587b429a1 625 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm 89:552587b429a1 626 #define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
bogdanm 89:552587b429a1 627 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm 89:552587b429a1 628 #define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
bogdanm 89:552587b429a1 629 #define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
bogdanm 89:552587b429a1 630 #define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
bogdanm 89:552587b429a1 631
bogdanm 89:552587b429a1 632 /** @brief Force or release AHB1 peripheral reset.
bogdanm 89:552587b429a1 633 */
bogdanm 89:552587b429a1 634 #define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
bogdanm 89:552587b429a1 635 #define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
bogdanm 89:552587b429a1 636 #define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
bogdanm 89:552587b429a1 637 #define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
bogdanm 89:552587b429a1 638 #define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
bogdanm 89:552587b429a1 639 #define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
bogdanm 89:552587b429a1 640 #define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
bogdanm 89:552587b429a1 641 #define __CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
bogdanm 89:552587b429a1 642 #define __DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
bogdanm 89:552587b429a1 643 #define __DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
bogdanm 89:552587b429a1 644
bogdanm 89:552587b429a1 645 #define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
bogdanm 89:552587b429a1 646 #define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
bogdanm 89:552587b429a1 647 #define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
bogdanm 89:552587b429a1 648 #define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
bogdanm 89:552587b429a1 649 #define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
bogdanm 89:552587b429a1 650 #define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
bogdanm 89:552587b429a1 651 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm 89:552587b429a1 652 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm 89:552587b429a1 653 #define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
bogdanm 89:552587b429a1 654 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm 89:552587b429a1 655 #define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
bogdanm 89:552587b429a1 656 #define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
bogdanm 89:552587b429a1 657 #define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
bogdanm 89:552587b429a1 658
bogdanm 89:552587b429a1 659 /** @brief Force or release AHB2 peripheral reset.
bogdanm 89:552587b429a1 660 */
bogdanm 89:552587b429a1 661 #define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
bogdanm 92:4fc01daae5a5 662 #define __USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
bogdanm 89:552587b429a1 663
bogdanm 89:552587b429a1 664 #define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
bogdanm 92:4fc01daae5a5 665 #define __USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
bogdanm 89:552587b429a1 666
bogdanm 92:4fc01daae5a5 667 /* alias define maintained for legacy */
bogdanm 92:4fc01daae5a5 668 #define __OTGFS_FORCE_RESET __USB_OTG_FS_FORCE_RESET
bogdanm 92:4fc01daae5a5 669 #define __OTGFS_RELEASE_RESET __USB_OTG_FS_RELEASE_RESET
bogdanm 92:4fc01daae5a5 670
bogdanm 89:552587b429a1 671 #define __RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
bogdanm 89:552587b429a1 672 #define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
bogdanm 89:552587b429a1 673
bogdanm 89:552587b429a1 674 /** @brief Force or release APB1 peripheral reset.
bogdanm 89:552587b429a1 675 */
bogdanm 89:552587b429a1 676 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm 89:552587b429a1 677 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
bogdanm 89:552587b429a1 678 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
bogdanm 89:552587b429a1 679 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
bogdanm 89:552587b429a1 680 #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
bogdanm 89:552587b429a1 681 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
bogdanm 89:552587b429a1 682 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
bogdanm 89:552587b429a1 683 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
bogdanm 89:552587b429a1 684 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
bogdanm 89:552587b429a1 685 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
bogdanm 89:552587b429a1 686 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
bogdanm 89:552587b429a1 687 #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
bogdanm 89:552587b429a1 688 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 89:552587b429a1 689
bogdanm 89:552587b429a1 690 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm 89:552587b429a1 691 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm 89:552587b429a1 692 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm 89:552587b429a1 693 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm 89:552587b429a1 694 #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
bogdanm 89:552587b429a1 695 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm 89:552587b429a1 696 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm 89:552587b429a1 697 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm 89:552587b429a1 698 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm 89:552587b429a1 699 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm 89:552587b429a1 700 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm 89:552587b429a1 701 #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm 89:552587b429a1 702 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm 89:552587b429a1 703
bogdanm 89:552587b429a1 704 /** @brief Force or release APB2 peripheral reset.
bogdanm 89:552587b429a1 705 */
bogdanm 89:552587b429a1 706 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm 89:552587b429a1 707 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
bogdanm 89:552587b429a1 708 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
bogdanm 89:552587b429a1 709 #define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
bogdanm 89:552587b429a1 710 #define __ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
bogdanm 89:552587b429a1 711 #define __SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
bogdanm 89:552587b429a1 712 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
bogdanm 89:552587b429a1 713 #define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
bogdanm 89:552587b429a1 714 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
bogdanm 89:552587b429a1 715 #define __TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
bogdanm 89:552587b429a1 716 #define __TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
bogdanm 89:552587b429a1 717 #define __TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
bogdanm 89:552587b429a1 718
bogdanm 89:552587b429a1 719 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm 89:552587b429a1 720 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm 89:552587b429a1 721 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm 89:552587b429a1 722 #define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
bogdanm 89:552587b429a1 723 #define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
bogdanm 89:552587b429a1 724 #define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
bogdanm 89:552587b429a1 725 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm 89:552587b429a1 726 #define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
bogdanm 89:552587b429a1 727 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm 89:552587b429a1 728 #define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
bogdanm 89:552587b429a1 729 #define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
bogdanm 89:552587b429a1 730 #define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
bogdanm 89:552587b429a1 731
bogdanm 89:552587b429a1 732 /** @brief Force or release AHB3 peripheral reset.
bogdanm 89:552587b429a1 733 */
bogdanm 89:552587b429a1 734 #define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
bogdanm 89:552587b429a1 735 #define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
bogdanm 89:552587b429a1 736
bogdanm 89:552587b429a1 737 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 738 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 739 * power consumption.
bogdanm 89:552587b429a1 740 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 741 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 742 */
bogdanm 89:552587b429a1 743 #define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
bogdanm 89:552587b429a1 744 #define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
bogdanm 89:552587b429a1 745 #define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
bogdanm 89:552587b429a1 746 #define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
bogdanm 89:552587b429a1 747 #define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
bogdanm 89:552587b429a1 748 #define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
bogdanm 89:552587b429a1 749 #define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
bogdanm 89:552587b429a1 750 #define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
bogdanm 89:552587b429a1 751 #define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
bogdanm 89:552587b429a1 752 #define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm 89:552587b429a1 753 #define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
bogdanm 89:552587b429a1 754 #define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
bogdanm 89:552587b429a1 755
bogdanm 89:552587b429a1 756 #define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
bogdanm 89:552587b429a1 757 #define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
bogdanm 89:552587b429a1 758 #define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
bogdanm 89:552587b429a1 759 #define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
bogdanm 89:552587b429a1 760 #define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
bogdanm 89:552587b429a1 761 #define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
bogdanm 89:552587b429a1 762 #define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
bogdanm 89:552587b429a1 763 #define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
bogdanm 89:552587b429a1 764 #define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
bogdanm 89:552587b429a1 765 #define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm 89:552587b429a1 766 #define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
bogdanm 89:552587b429a1 767 #define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
bogdanm 89:552587b429a1 768
bogdanm 89:552587b429a1 769 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 770 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 771 * power consumption.
bogdanm 89:552587b429a1 772 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 773 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 774 */
bogdanm 92:4fc01daae5a5 775 #define __USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
bogdanm 92:4fc01daae5a5 776
bogdanm 92:4fc01daae5a5 777 #define __USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
bogdanm 89:552587b429a1 778
bogdanm 92:4fc01daae5a5 779 /* alias define maintained for legacy */
bogdanm 92:4fc01daae5a5 780 #define __OTGFS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_ENABLE
bogdanm 92:4fc01daae5a5 781 #define __OTGFS_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_SLEEP_DISABLE
bogdanm 89:552587b429a1 782
bogdanm 89:552587b429a1 783 #define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
bogdanm 89:552587b429a1 784 #define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
bogdanm 89:552587b429a1 785
bogdanm 89:552587b429a1 786 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 787 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 788 * power consumption.
bogdanm 89:552587b429a1 789 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 790 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 791 */
bogdanm 89:552587b429a1 792 #define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
bogdanm 89:552587b429a1 793 #define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
bogdanm 89:552587b429a1 794 #define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
bogdanm 89:552587b429a1 795 #define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
bogdanm 89:552587b429a1 796 #define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
bogdanm 89:552587b429a1 797 #define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
bogdanm 89:552587b429a1 798 #define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
bogdanm 89:552587b429a1 799 #define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
bogdanm 89:552587b429a1 800 #define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
bogdanm 89:552587b429a1 801 #define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
bogdanm 89:552587b429a1 802 #define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
bogdanm 89:552587b429a1 803 #define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
bogdanm 89:552587b429a1 804
bogdanm 89:552587b429a1 805 #define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
bogdanm 89:552587b429a1 806 #define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
bogdanm 89:552587b429a1 807 #define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
bogdanm 89:552587b429a1 808 #define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
bogdanm 89:552587b429a1 809 #define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
bogdanm 89:552587b429a1 810 #define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
bogdanm 89:552587b429a1 811 #define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
bogdanm 89:552587b429a1 812 #define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
bogdanm 89:552587b429a1 813 #define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
bogdanm 89:552587b429a1 814 #define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
bogdanm 89:552587b429a1 815 #define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
bogdanm 89:552587b429a1 816 #define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
bogdanm 89:552587b429a1 817
bogdanm 89:552587b429a1 818 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 89:552587b429a1 819 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 89:552587b429a1 820 * power consumption.
bogdanm 89:552587b429a1 821 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 89:552587b429a1 822 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 89:552587b429a1 823 */
bogdanm 89:552587b429a1 824 #define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
bogdanm 89:552587b429a1 825 #define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
bogdanm 89:552587b429a1 826 #define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
bogdanm 89:552587b429a1 827 #define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
bogdanm 89:552587b429a1 828 #define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
bogdanm 89:552587b429a1 829 #define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
bogdanm 89:552587b429a1 830 #define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
bogdanm 89:552587b429a1 831 #define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
bogdanm 89:552587b429a1 832 #define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
bogdanm 89:552587b429a1 833 #define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
bogdanm 89:552587b429a1 834 #define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
bogdanm 89:552587b429a1 835
bogdanm 89:552587b429a1 836 #define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
bogdanm 89:552587b429a1 837 #define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
bogdanm 89:552587b429a1 838 #define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
bogdanm 89:552587b429a1 839 #define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
bogdanm 89:552587b429a1 840 #define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
bogdanm 89:552587b429a1 841 #define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
bogdanm 89:552587b429a1 842 #define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
bogdanm 89:552587b429a1 843 #define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
bogdanm 89:552587b429a1 844 #define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
bogdanm 89:552587b429a1 845 #define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
bogdanm 89:552587b429a1 846 #define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
bogdanm 89:552587b429a1 847
bogdanm 89:552587b429a1 848 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 89:552587b429a1 849 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 89:552587b429a1 850 * It is used (enabled by hardware) as system clock source after startup
bogdanm 89:552587b429a1 851 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm 89:552587b429a1 852 * of the HSE used directly or indirectly as system clock (if the Clock
bogdanm 89:552587b429a1 853 * Security System CSS is enabled).
bogdanm 89:552587b429a1 854 * @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm 89:552587b429a1 855 * you have to select another source of the system clock then stop the HSI.
bogdanm 89:552587b429a1 856 * @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm 89:552587b429a1 857 * flag to be set indicating that HSI clock is stable and can be used as
bogdanm 89:552587b429a1 858 * system clock source.
bogdanm 89:552587b429a1 859 * This parameter can be: ENABLE or DISABLE.
bogdanm 89:552587b429a1 860 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 89:552587b429a1 861 * clock cycles.
bogdanm 89:552587b429a1 862 */
bogdanm 89:552587b429a1 863 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
bogdanm 89:552587b429a1 864 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
bogdanm 89:552587b429a1 865
bogdanm 89:552587b429a1 866 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm 89:552587b429a1 867 * @note The calibration is used to compensate for the variations in voltage
bogdanm 89:552587b429a1 868 * and temperature that influence the frequency of the internal HSI RC.
bogdanm 89:552587b429a1 869 * @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm 89:552587b429a1 870 * This parameter must be a number between 0 and 0x1F.
bogdanm 89:552587b429a1 871 */
bogdanm 89:552587b429a1 872 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
bogdanm 89:552587b429a1 873 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
bogdanm 89:552587b429a1 874
bogdanm 89:552587b429a1 875 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 89:552587b429a1 876 * @note After enabling the LSI, the application software should wait on
bogdanm 89:552587b429a1 877 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 89:552587b429a1 878 * be used to clock the IWDG and/or the RTC.
bogdanm 89:552587b429a1 879 * @note LSI can not be disabled if the IWDG is running.
bogdanm 89:552587b429a1 880 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 89:552587b429a1 881 * clock cycles.
bogdanm 89:552587b429a1 882 */
bogdanm 89:552587b429a1 883 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
bogdanm 89:552587b429a1 884 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
bogdanm 89:552587b429a1 885
bogdanm 89:552587b429a1 886 /**
bogdanm 89:552587b429a1 887 * @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm 89:552587b429a1 888 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 89:552587b429a1 889 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 89:552587b429a1 890 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 89:552587b429a1 891 * @note HSE state can not be changed if it is used directly or through the
bogdanm 89:552587b429a1 892 * PLL as system clock. In this case, you have to select another source
bogdanm 89:552587b429a1 893 * of the system clock then change the HSE state (ex. disable it).
bogdanm 89:552587b429a1 894 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 89:552587b429a1 895 * @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm 89:552587b429a1 896 * was previously enabled you have to enable it again after calling this
bogdanm 89:552587b429a1 897 * function.
bogdanm 89:552587b429a1 898 * @param __STATE__: specifies the new state of the HSE.
bogdanm 89:552587b429a1 899 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 900 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 89:552587b429a1 901 * 6 HSE oscillator clock cycles.
bogdanm 89:552587b429a1 902 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm 89:552587b429a1 903 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm 89:552587b429a1 904 */
bogdanm 89:552587b429a1 905 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__STATE__))
bogdanm 89:552587b429a1 906
bogdanm 89:552587b429a1 907 /**
bogdanm 89:552587b429a1 908 * @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm 89:552587b429a1 909 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 89:552587b429a1 910 * this domain after reset, you have to enable write access using
bogdanm 89:552587b429a1 911 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 89:552587b429a1 912 * (to be done once after reset).
bogdanm 89:552587b429a1 913 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 89:552587b429a1 914 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 89:552587b429a1 915 * is stable and can be used to clock the RTC.
bogdanm 89:552587b429a1 916 * @param __STATE__: specifies the new state of the LSE.
bogdanm 89:552587b429a1 917 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 918 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 89:552587b429a1 919 * 6 LSE oscillator clock cycles.
bogdanm 89:552587b429a1 920 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm 89:552587b429a1 921 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm 89:552587b429a1 922 */
bogdanm 89:552587b429a1 923 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) BDCR_BYTE0_ADDRESS = (__STATE__))
bogdanm 89:552587b429a1 924
bogdanm 89:552587b429a1 925 /** @brief Macros to enable or disable the the RTC clock.
bogdanm 89:552587b429a1 926 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 89:552587b429a1 927 */
bogdanm 89:552587b429a1 928 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = ENABLE)
bogdanm 89:552587b429a1 929 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) BDCR_RTCEN_BB = DISABLE)
bogdanm 89:552587b429a1 930
bogdanm 89:552587b429a1 931 /** @brief Macros to configure the RTC clock (RTCCLK).
bogdanm 89:552587b429a1 932 * @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm 89:552587b429a1 933 * access is denied to this domain after reset, you have to enable write
bogdanm 89:552587b429a1 934 * access using the Power Backup Access macro before to configure
bogdanm 89:552587b429a1 935 * the RTC clock source (to be done once after reset).
bogdanm 89:552587b429a1 936 * @note Once the RTC clock is configured it can't be changed unless the
bogdanm 89:552587b429a1 937 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm 89:552587b429a1 938 * a Power On Reset (POR).
bogdanm 89:552587b429a1 939 * @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm 89:552587b429a1 940 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 941 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm 89:552587b429a1 942 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm 89:552587b429a1 943 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
bogdanm 89:552587b429a1 944 * as RTC clock, where x:[2,31]
bogdanm 89:552587b429a1 945 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm 89:552587b429a1 946 * work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm 89:552587b429a1 947 * However, when the HSE clock is used as RTC clock source, the RTC
bogdanm 89:552587b429a1 948 * cannot be used in STOP and STANDBY modes.
bogdanm 89:552587b429a1 949 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm 89:552587b429a1 950 * RTC clock source).
bogdanm 89:552587b429a1 951 */
bogdanm 89:552587b429a1 952 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
bogdanm 89:552587b429a1 953 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm 89:552587b429a1 954
bogdanm 89:552587b429a1 955 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
bogdanm 89:552587b429a1 956 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
bogdanm 89:552587b429a1 957 } while (0)
bogdanm 89:552587b429a1 958
bogdanm 89:552587b429a1 959 /** @brief Macros to force or release the Backup domain reset.
bogdanm 89:552587b429a1 960 * @note This function resets the RTC peripheral (including the backup registers)
bogdanm 89:552587b429a1 961 * and the RTC clock source selection in RCC_CSR register.
bogdanm 89:552587b429a1 962 * @note The BKPSRAM is not affected by this reset.
bogdanm 89:552587b429a1 963 */
bogdanm 89:552587b429a1 964 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) BDCR_BDRST_BB = ENABLE)
bogdanm 89:552587b429a1 965 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) BDCR_BDRST_BB = DISABLE)
bogdanm 89:552587b429a1 966
bogdanm 89:552587b429a1 967 /** @brief Macros to enable or disable the main PLL.
bogdanm 89:552587b429a1 968 * @note After enabling the main PLL, the application software should wait on
bogdanm 89:552587b429a1 969 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 89:552587b429a1 970 * be used as system clock source.
bogdanm 89:552587b429a1 971 * @note The main PLL can not be disabled if it is used as system clock source
bogdanm 89:552587b429a1 972 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 89:552587b429a1 973 */
bogdanm 89:552587b429a1 974 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
bogdanm 89:552587b429a1 975 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
bogdanm 89:552587b429a1 976
bogdanm 89:552587b429a1 977 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm 89:552587b429a1 978 * @note This function must be used only when the main PLL is disabled.
bogdanm 89:552587b429a1 979 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm 89:552587b429a1 980 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 981 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 89:552587b429a1 982 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm 89:552587b429a1 983 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
bogdanm 89:552587b429a1 984 * @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm 89:552587b429a1 985 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm 89:552587b429a1 986 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm 89:552587b429a1 987 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm 89:552587b429a1 988 * of 2 MHz to limit PLL jitter.
bogdanm 89:552587b429a1 989 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
bogdanm 89:552587b429a1 990 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 89:552587b429a1 991 * @note You have to set the PLLN parameter correctly to ensure that the VCO
bogdanm 89:552587b429a1 992 * output frequency is between 192 and 432 MHz.
bogdanm 89:552587b429a1 993 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
bogdanm 89:552587b429a1 994 * This parameter must be a number in the range {2, 4, 6, or 8}.
bogdanm 89:552587b429a1 995 * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
bogdanm 89:552587b429a1 996 * the System clock frequency.
bogdanm 89:552587b429a1 997 * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
bogdanm 89:552587b429a1 998 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm 89:552587b429a1 999 * @note If the USB OTG FS is used in your application, you have to set the
bogdanm 89:552587b429a1 1000 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
bogdanm 89:552587b429a1 1001 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
bogdanm 89:552587b429a1 1002 * correctly.
bogdanm 89:552587b429a1 1003 */
bogdanm 89:552587b429a1 1004 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
bogdanm 89:552587b429a1 1005 (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
bogdanm 89:552587b429a1 1006 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
bogdanm 89:552587b429a1 1007 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
bogdanm 89:552587b429a1 1008
bogdanm 89:552587b429a1 1009 /** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm 89:552587b429a1 1010 * @note This function must be called before enabling the I2S APB clock.
bogdanm 89:552587b429a1 1011 * @param __SOURCE__: specifies the I2S clock source.
bogdanm 89:552587b429a1 1012 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1013 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
bogdanm 89:552587b429a1 1014 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm 89:552587b429a1 1015 * used as I2S clock source.
bogdanm 89:552587b429a1 1016 */
bogdanm 89:552587b429a1 1017 #define __HAL_RCC_I2SCLK(__SOURCE__) (*(__IO uint32_t *) CFGR_I2SSRC_BB = (__SOURCE__))
bogdanm 89:552587b429a1 1018
bogdanm 89:552587b429a1 1019 /** @brief Macros to enable or disable the PLLI2S.
bogdanm 89:552587b429a1 1020 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 89:552587b429a1 1021 */
bogdanm 89:552587b429a1 1022 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = ENABLE)
bogdanm 89:552587b429a1 1023 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) CR_PLLI2SON_BB = DISABLE)
bogdanm 89:552587b429a1 1024
bogdanm 89:552587b429a1 1025 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
bogdanm 89:552587b429a1 1026 * @note This macro must be used only when the PLLI2S is disabled.
bogdanm 89:552587b429a1 1027 * @note PLLI2S clock source is common with the main PLL (configured in
bogdanm 89:552587b429a1 1028 * HAL_RCC_ClockConfig() API).
bogdanm 89:552587b429a1 1029 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
bogdanm 89:552587b429a1 1030 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm 89:552587b429a1 1031 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm 89:552587b429a1 1032 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm 89:552587b429a1 1033 * @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm 89:552587b429a1 1034 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm 89:552587b429a1 1035 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm 89:552587b429a1 1036 * on the I2S clock frequency.
bogdanm 89:552587b429a1 1037 */
bogdanm 89:552587b429a1 1038 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
bogdanm 89:552587b429a1 1039
bogdanm 89:552587b429a1 1040 /** @brief Macro to get the clock source used as system clock.
bogdanm 89:552587b429a1 1041 * @retval The clock source used as system clock. The returned value can be one
bogdanm 89:552587b429a1 1042 * of the following:
bogdanm 89:552587b429a1 1043 * - RCC_CFGR_SWS_HSI: HSI used as system clock.
bogdanm 89:552587b429a1 1044 * - RCC_CFGR_SWS_HSE: HSE used as system clock.
bogdanm 89:552587b429a1 1045 * - RCC_CFGR_SWS_PLL: PLL used as system clock.
bogdanm 89:552587b429a1 1046 */
bogdanm 89:552587b429a1 1047 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm 89:552587b429a1 1048
bogdanm 89:552587b429a1 1049 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 89:552587b429a1 1050 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 89:552587b429a1 1051 * of the following:
bogdanm 89:552587b429a1 1052 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 89:552587b429a1 1053 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 89:552587b429a1 1054 */
bogdanm 89:552587b429a1 1055 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
bogdanm 89:552587b429a1 1056
bogdanm 89:552587b429a1 1057 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm 89:552587b429a1 1058 * the selected interrupts).
bogdanm 89:552587b429a1 1059 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 89:552587b429a1 1060 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 1061 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 89:552587b429a1 1062 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 89:552587b429a1 1063 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 89:552587b429a1 1064 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 89:552587b429a1 1065 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 89:552587b429a1 1066 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 89:552587b429a1 1067 */
bogdanm 89:552587b429a1 1068 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
bogdanm 89:552587b429a1 1069
bogdanm 89:552587b429a1 1070 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm 89:552587b429a1 1071 * the selected interrupts).
bogdanm 89:552587b429a1 1072 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 89:552587b429a1 1073 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 1074 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 89:552587b429a1 1075 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 89:552587b429a1 1076 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 89:552587b429a1 1077 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 89:552587b429a1 1078 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 89:552587b429a1 1079 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 89:552587b429a1 1080 */
bogdanm 89:552587b429a1 1081 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 1082
bogdanm 89:552587b429a1 1083 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm 89:552587b429a1 1084 * bits to clear the selected interrupt pending bits.
bogdanm 89:552587b429a1 1085 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 89:552587b429a1 1086 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 1087 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 89:552587b429a1 1088 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 89:552587b429a1 1089 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 89:552587b429a1 1090 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 89:552587b429a1 1091 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 89:552587b429a1 1092 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 89:552587b429a1 1093 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 89:552587b429a1 1094 */
bogdanm 89:552587b429a1 1095 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm 89:552587b429a1 1096
bogdanm 89:552587b429a1 1097 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 89:552587b429a1 1098 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm 89:552587b429a1 1099 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1100 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm 89:552587b429a1 1101 * @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm 89:552587b429a1 1102 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm 89:552587b429a1 1103 * @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm 89:552587b429a1 1104 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm 89:552587b429a1 1105 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm 89:552587b429a1 1106 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 89:552587b429a1 1107 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 89:552587b429a1 1108 */
bogdanm 89:552587b429a1 1109 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 89:552587b429a1 1110
bogdanm 89:552587b429a1 1111 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm 89:552587b429a1 1112 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
bogdanm 89:552587b429a1 1113 */
bogdanm 89:552587b429a1 1114 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
bogdanm 89:552587b429a1 1115
bogdanm 89:552587b429a1 1116 /** @brief Check RCC flag is set or not.
bogdanm 89:552587b429a1 1117 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 1118 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 1119 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm 89:552587b429a1 1120 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm 89:552587b429a1 1121 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm 89:552587b429a1 1122 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
bogdanm 89:552587b429a1 1123 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm 89:552587b429a1 1124 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm 89:552587b429a1 1125 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
bogdanm 89:552587b429a1 1126 * @arg RCC_FLAG_PINRST: Pin reset.
bogdanm 89:552587b429a1 1127 * @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm 89:552587b429a1 1128 * @arg RCC_FLAG_SFTRST: Software reset.
bogdanm 89:552587b429a1 1129 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm 89:552587b429a1 1130 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm 89:552587b429a1 1131 * @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm 89:552587b429a1 1132 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 89:552587b429a1 1133 */
bogdanm 89:552587b429a1 1134 #define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm 89:552587b429a1 1135 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
bogdanm 89:552587b429a1 1136
bogdanm 89:552587b429a1 1137 #define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
bogdanm 89:552587b429a1 1138
bogdanm 89:552587b429a1 1139
bogdanm 89:552587b429a1 1140 /* Include RCC HAL Extension module */
bogdanm 89:552587b429a1 1141 #include "stm32f4xx_hal_rcc_ex.h"
bogdanm 89:552587b429a1 1142
bogdanm 89:552587b429a1 1143 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 1144
bogdanm 89:552587b429a1 1145 /* Initialization and de-initialization functions ******************************/
bogdanm 89:552587b429a1 1146 void HAL_RCC_DeInit(void);
bogdanm 89:552587b429a1 1147 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 89:552587b429a1 1148 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm 89:552587b429a1 1149
bogdanm 89:552587b429a1 1150 /* Peripheral Control functions ************************************************/
bogdanm 89:552587b429a1 1151 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm 89:552587b429a1 1152 void HAL_RCC_EnableCSS(void);
bogdanm 89:552587b429a1 1153 void HAL_RCC_DisableCSS(void);
bogdanm 89:552587b429a1 1154 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 89:552587b429a1 1155 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 89:552587b429a1 1156 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 89:552587b429a1 1157 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 89:552587b429a1 1158 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 89:552587b429a1 1159 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 89:552587b429a1 1160
bogdanm 89:552587b429a1 1161 /* CSS NMI IRQ handler */
bogdanm 89:552587b429a1 1162 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 89:552587b429a1 1163
bogdanm 89:552587b429a1 1164 /* User Callbacks in non blocking mode (IT mode) */
bogdanm 89:552587b429a1 1165 void HAL_RCC_CCSCallback(void);
bogdanm 89:552587b429a1 1166
bogdanm 89:552587b429a1 1167 /**
bogdanm 89:552587b429a1 1168 * @}
bogdanm 89:552587b429a1 1169 */
bogdanm 89:552587b429a1 1170
bogdanm 89:552587b429a1 1171 /**
bogdanm 89:552587b429a1 1172 * @}
bogdanm 89:552587b429a1 1173 */
bogdanm 89:552587b429a1 1174
bogdanm 89:552587b429a1 1175 #ifdef __cplusplus
bogdanm 89:552587b429a1 1176 }
bogdanm 89:552587b429a1 1177 #endif
bogdanm 89:552587b429a1 1178
bogdanm 89:552587b429a1 1179 #endif /* __STM32F4xx_HAL_RCC_H */
bogdanm 89:552587b429a1 1180
bogdanm 89:552587b429a1 1181 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/