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TARGET_ARCH_MAX/stm32f4xx_hal_dma2d.h@99:7f6c6de930c0, 2015-05-03 (annotated)

Committer:
Mikchel
Date:
Sun May 03 16:04:42 2015 +0000
Revision:
99:7f6c6de930c0
Parent:
92:4fc01daae5a5 
12

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_dma2d.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 89:552587b429a1 7 * @brief Header file of DMA2D HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_DMA2D_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_DMA2D_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 89:552587b429a1 47 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 48 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 49
bogdanm 89:552587b429a1 50 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 51 * @{
bogdanm 89:552587b429a1 52 */
bogdanm 89:552587b429a1 53
bogdanm 89:552587b429a1 54 /** @addtogroup DMA2D
bogdanm 89:552587b429a1 55 * @{
bogdanm 89:552587b429a1 56 */
bogdanm 89:552587b429a1 57
bogdanm 89:552587b429a1 58 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 59
bogdanm 89:552587b429a1 60 #define MAX_DMA2D_LAYER 2
bogdanm 89:552587b429a1 61
bogdanm 89:552587b429a1 62 /**
bogdanm 89:552587b429a1 63 * @brief DMA2D color Structure definition
bogdanm 89:552587b429a1 64 */
bogdanm 89:552587b429a1 65 typedef struct
bogdanm 89:552587b429a1 66 {
bogdanm 89:552587b429a1 67 uint32_t Blue; /*!< Configures the blue value.
bogdanm 89:552587b429a1 68 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 89:552587b429a1 69
bogdanm 89:552587b429a1 70 uint32_t Green; /*!< Configures the green value.
bogdanm 89:552587b429a1 71 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 89:552587b429a1 72
bogdanm 89:552587b429a1 73 uint32_t Red; /*!< Configures the red value.
bogdanm 89:552587b429a1 74 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 89:552587b429a1 75 } DMA2D_ColorTypeDef;
bogdanm 89:552587b429a1 76
bogdanm 89:552587b429a1 77 /**
bogdanm 89:552587b429a1 78 * @brief DMA2D CLUT Structure definition
bogdanm 89:552587b429a1 79 */
bogdanm 89:552587b429a1 80 typedef struct
bogdanm 89:552587b429a1 81 {
bogdanm 89:552587b429a1 82 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
bogdanm 89:552587b429a1 83
bogdanm 89:552587b429a1 84 uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
bogdanm 89:552587b429a1 85 This parameter can be one value of @ref DMA2D_CLUT_CM */
bogdanm 89:552587b429a1 86
bogdanm 89:552587b429a1 87 uint32_t Size; /*!< configures the DMA2D CLUT size.
bogdanm 89:552587b429a1 88 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 89:552587b429a1 89 } DMA2D_CLUTCfgTypeDef;
bogdanm 89:552587b429a1 90
bogdanm 89:552587b429a1 91 /**
bogdanm 89:552587b429a1 92 * @brief DMA2D Init structure definition
bogdanm 89:552587b429a1 93 */
bogdanm 89:552587b429a1 94 typedef struct
bogdanm 89:552587b429a1 95 {
bogdanm 89:552587b429a1 96 uint32_t Mode; /*!< configures the DMA2D transfer mode.
bogdanm 89:552587b429a1 97 This parameter can be one value of @ref DMA2D_Mode */
bogdanm 89:552587b429a1 98
bogdanm 89:552587b429a1 99 uint32_t ColorMode; /*!< configures the color format of the output image.
bogdanm 89:552587b429a1 100 This parameter can be one value of @ref DMA2D_Color_Mode */
bogdanm 89:552587b429a1 101
bogdanm 89:552587b429a1 102 uint32_t OutputOffset; /*!< Specifies the Offset value.
bogdanm 89:552587b429a1 103 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
bogdanm 89:552587b429a1 104 } DMA2D_InitTypeDef;
bogdanm 89:552587b429a1 105
bogdanm 89:552587b429a1 106 /**
bogdanm 89:552587b429a1 107 * @brief DMA2D Layer structure definition
bogdanm 89:552587b429a1 108 */
bogdanm 89:552587b429a1 109 typedef struct
bogdanm 89:552587b429a1 110 {
bogdanm 89:552587b429a1 111 uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
bogdanm 89:552587b429a1 112 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
bogdanm 89:552587b429a1 113
bogdanm 89:552587b429a1 114 uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
bogdanm 89:552587b429a1 115 This parameter can be one value of @ref DMA2D_Input_Color_Mode */
bogdanm 89:552587b429a1 116
bogdanm 89:552587b429a1 117 uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
bogdanm 89:552587b429a1 118 This parameter can be one value of @ref DMA2D_ALPHA_MODE */
bogdanm 89:552587b429a1 119
bogdanm 92:4fc01daae5a5 120 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode.
bogdanm 92:4fc01daae5a5 121 This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF
bogdanm 92:4fc01daae5a5 122 in case of A8 or A4 color mode (ARGB).
bogdanm 92:4fc01daae5a5 123 Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 89:552587b429a1 124
bogdanm 89:552587b429a1 125 } DMA2D_LayerCfgTypeDef;
bogdanm 89:552587b429a1 126
bogdanm 89:552587b429a1 127 /**
bogdanm 89:552587b429a1 128 * @brief HAL DMA2D State structures definition
bogdanm 89:552587b429a1 129 */
bogdanm 89:552587b429a1 130 typedef enum
bogdanm 89:552587b429a1 131 {
bogdanm 89:552587b429a1 132 HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
bogdanm 89:552587b429a1 133 HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 89:552587b429a1 134 HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
bogdanm 89:552587b429a1 135 HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 89:552587b429a1 136 HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
bogdanm 89:552587b429a1 137 HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
bogdanm 89:552587b429a1 138 }HAL_DMA2D_StateTypeDef;
bogdanm 89:552587b429a1 139
bogdanm 89:552587b429a1 140 /**
bogdanm 89:552587b429a1 141 * @brief DMA2D handle Structure definition
bogdanm 89:552587b429a1 142 */
bogdanm 89:552587b429a1 143 typedef struct __DMA2D_HandleTypeDef
bogdanm 89:552587b429a1 144 {
bogdanm 89:552587b429a1 145 DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
bogdanm 89:552587b429a1 146
bogdanm 89:552587b429a1 147 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
bogdanm 89:552587b429a1 148
bogdanm 89:552587b429a1 149 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
bogdanm 89:552587b429a1 150
bogdanm 89:552587b429a1 151 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
bogdanm 89:552587b429a1 152
bogdanm 89:552587b429a1 153 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
bogdanm 89:552587b429a1 154
bogdanm 89:552587b429a1 155 HAL_LockTypeDef Lock; /*!< DMA2D Lock */
bogdanm 89:552587b429a1 156
bogdanm 89:552587b429a1 157 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
bogdanm 89:552587b429a1 158
bogdanm 89:552587b429a1 159 __IO uint32_t ErrorCode; /*!< DMA2D Error code */
bogdanm 89:552587b429a1 160 } DMA2D_HandleTypeDef;
bogdanm 89:552587b429a1 161
bogdanm 89:552587b429a1 162
bogdanm 89:552587b429a1 163 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 164
bogdanm 89:552587b429a1 165 /** @defgroup DMA2D_Exported_Constants
bogdanm 89:552587b429a1 166 * @{
bogdanm 89:552587b429a1 167 */
bogdanm 89:552587b429a1 168
bogdanm 89:552587b429a1 169 /** @defgroup DMA2D_Layer
bogdanm 89:552587b429a1 170 * @{
bogdanm 89:552587b429a1 171 */
bogdanm 89:552587b429a1 172 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
bogdanm 89:552587b429a1 173 /**
bogdanm 89:552587b429a1 174 * @}
bogdanm 89:552587b429a1 175 */
bogdanm 89:552587b429a1 176
bogdanm 89:552587b429a1 177 /** @defgroup DMA2D_Error_Code
bogdanm 89:552587b429a1 178 * @{
bogdanm 89:552587b429a1 179 */
bogdanm 89:552587b429a1 180 #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 89:552587b429a1 181 #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 89:552587b429a1 182 #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
bogdanm 89:552587b429a1 183 #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 89:552587b429a1 184 /**
bogdanm 89:552587b429a1 185 * @}
bogdanm 89:552587b429a1 186 */
bogdanm 89:552587b429a1 187
bogdanm 89:552587b429a1 188 /** @defgroup DMA2D_Mode
bogdanm 89:552587b429a1 189 * @{
bogdanm 89:552587b429a1 190 */
bogdanm 89:552587b429a1 191 #define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
bogdanm 89:552587b429a1 192 #define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
bogdanm 89:552587b429a1 193 #define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
bogdanm 89:552587b429a1 194 #define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
bogdanm 89:552587b429a1 195
bogdanm 89:552587b429a1 196 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
bogdanm 89:552587b429a1 197 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
bogdanm 89:552587b429a1 198 /**
bogdanm 89:552587b429a1 199 * @}
bogdanm 89:552587b429a1 200 */
bogdanm 89:552587b429a1 201
bogdanm 89:552587b429a1 202 /** @defgroup DMA2D_Color_Mode
bogdanm 89:552587b429a1 203 * @{
bogdanm 89:552587b429a1 204 */
bogdanm 89:552587b429a1 205 #define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
bogdanm 89:552587b429a1 206 #define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
bogdanm 89:552587b429a1 207 #define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
bogdanm 89:552587b429a1 208 #define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
bogdanm 89:552587b429a1 209 #define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
bogdanm 89:552587b429a1 210
bogdanm 89:552587b429a1 211 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
bogdanm 89:552587b429a1 212 ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
bogdanm 89:552587b429a1 213 ((MODE_ARGB) == DMA2D_ARGB4444))
bogdanm 89:552587b429a1 214 /**
bogdanm 89:552587b429a1 215 * @}
bogdanm 89:552587b429a1 216 */
bogdanm 89:552587b429a1 217
bogdanm 89:552587b429a1 218 /** @defgroup DMA2D_COLOR_VALUE
bogdanm 89:552587b429a1 219 * @{
bogdanm 89:552587b429a1 220 */
bogdanm 89:552587b429a1 221
bogdanm 89:552587b429a1 222 #define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
bogdanm 89:552587b429a1 223
bogdanm 89:552587b429a1 224 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
bogdanm 89:552587b429a1 225 /**
bogdanm 89:552587b429a1 226 * @}
bogdanm 89:552587b429a1 227 */
bogdanm 89:552587b429a1 228
bogdanm 89:552587b429a1 229 /** @defgroup DMA2D_SIZE
bogdanm 89:552587b429a1 230 * @{
bogdanm 89:552587b429a1 231 */
bogdanm 89:552587b429a1 232 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
bogdanm 89:552587b429a1 233 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
bogdanm 89:552587b429a1 234
bogdanm 89:552587b429a1 235 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
bogdanm 89:552587b429a1 236 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
bogdanm 89:552587b429a1 237 /**
bogdanm 89:552587b429a1 238 * @}
bogdanm 89:552587b429a1 239 */
bogdanm 89:552587b429a1 240
bogdanm 89:552587b429a1 241 /** @defgroup DMA2D_Offset
bogdanm 89:552587b429a1 242 * @{
bogdanm 89:552587b429a1 243 */
bogdanm 89:552587b429a1 244 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
bogdanm 89:552587b429a1 245
bogdanm 89:552587b429a1 246 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
bogdanm 89:552587b429a1 247 /**
bogdanm 89:552587b429a1 248 * @}
bogdanm 89:552587b429a1 249 */
bogdanm 89:552587b429a1 250
bogdanm 89:552587b429a1 251 /** @defgroup DMA2D_Input_Color_Mode
bogdanm 89:552587b429a1 252 * @{
bogdanm 89:552587b429a1 253 */
bogdanm 89:552587b429a1 254 #define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
bogdanm 89:552587b429a1 255 #define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
bogdanm 89:552587b429a1 256 #define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
bogdanm 89:552587b429a1 257 #define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
bogdanm 89:552587b429a1 258 #define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
bogdanm 89:552587b429a1 259 #define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
bogdanm 89:552587b429a1 260 #define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
bogdanm 89:552587b429a1 261 #define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
bogdanm 89:552587b429a1 262 #define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
bogdanm 89:552587b429a1 263 #define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
bogdanm 89:552587b429a1 264 #define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
bogdanm 89:552587b429a1 265
bogdanm 89:552587b429a1 266 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
bogdanm 89:552587b429a1 267 ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
bogdanm 89:552587b429a1 268 ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
bogdanm 89:552587b429a1 269 ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
bogdanm 89:552587b429a1 270 ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
bogdanm 89:552587b429a1 271 ((INPUT_CM) == CM_A4))
bogdanm 89:552587b429a1 272 /**
bogdanm 89:552587b429a1 273 * @}
bogdanm 89:552587b429a1 274 */
bogdanm 89:552587b429a1 275
bogdanm 89:552587b429a1 276 /** @defgroup DMA2D_ALPHA_MODE
bogdanm 89:552587b429a1 277 * @{
bogdanm 89:552587b429a1 278 */
bogdanm 89:552587b429a1 279 #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
bogdanm 89:552587b429a1 280 #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
bogdanm 89:552587b429a1 281 #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
bogdanm 89:552587b429a1 282 with original alpha channel value */
bogdanm 89:552587b429a1 283
bogdanm 89:552587b429a1 284 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
bogdanm 89:552587b429a1 285 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
bogdanm 89:552587b429a1 286 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
bogdanm 89:552587b429a1 287 /**
bogdanm 89:552587b429a1 288 * @}
bogdanm 89:552587b429a1 289 */
bogdanm 89:552587b429a1 290
bogdanm 89:552587b429a1 291 /** @defgroup DMA2D_CLUT_CM
bogdanm 89:552587b429a1 292 * @{
bogdanm 89:552587b429a1 293 */
bogdanm 89:552587b429a1 294 #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
bogdanm 89:552587b429a1 295 #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
bogdanm 89:552587b429a1 296
bogdanm 89:552587b429a1 297 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
bogdanm 89:552587b429a1 298 /**
bogdanm 89:552587b429a1 299 * @}
bogdanm 89:552587b429a1 300 */
bogdanm 89:552587b429a1 301
bogdanm 89:552587b429a1 302 /** @defgroup DMA2D_Size_Clut
bogdanm 89:552587b429a1 303 * @{
bogdanm 89:552587b429a1 304 */
bogdanm 89:552587b429a1 305 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
bogdanm 89:552587b429a1 306
bogdanm 89:552587b429a1 307 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
bogdanm 89:552587b429a1 308 /**
bogdanm 89:552587b429a1 309 * @}
bogdanm 89:552587b429a1 310 */
bogdanm 89:552587b429a1 311
bogdanm 89:552587b429a1 312 /** @defgroup DMA2D_DeadTime
bogdanm 89:552587b429a1 313 * @{
bogdanm 89:552587b429a1 314 */
bogdanm 89:552587b429a1 315 #define LINE_WATERMARK DMA2D_LWR_LW
bogdanm 89:552587b429a1 316
bogdanm 89:552587b429a1 317 #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
bogdanm 89:552587b429a1 318 /**
bogdanm 89:552587b429a1 319 * @}
bogdanm 89:552587b429a1 320 */
bogdanm 89:552587b429a1 321
bogdanm 89:552587b429a1 322 /** @defgroup DMA2D_Interrupts
bogdanm 89:552587b429a1 323 * @{
bogdanm 89:552587b429a1 324 */
bogdanm 89:552587b429a1 325 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
bogdanm 89:552587b429a1 326 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
bogdanm 89:552587b429a1 327 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
bogdanm 89:552587b429a1 328 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
bogdanm 89:552587b429a1 329 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
bogdanm 89:552587b429a1 330 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
bogdanm 89:552587b429a1 331
bogdanm 89:552587b429a1 332 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
bogdanm 89:552587b429a1 333 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
bogdanm 89:552587b429a1 334 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
bogdanm 89:552587b429a1 335 /**
bogdanm 89:552587b429a1 336 * @}
bogdanm 89:552587b429a1 337 */
bogdanm 89:552587b429a1 338
bogdanm 89:552587b429a1 339 /** @defgroup DMA2D_Flag
bogdanm 89:552587b429a1 340 * @{
bogdanm 89:552587b429a1 341 */
bogdanm 89:552587b429a1 342 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
bogdanm 89:552587b429a1 343 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
bogdanm 89:552587b429a1 344 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
bogdanm 89:552587b429a1 345 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
bogdanm 89:552587b429a1 346 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
bogdanm 89:552587b429a1 347 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
bogdanm 89:552587b429a1 348
bogdanm 89:552587b429a1 349 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
bogdanm 89:552587b429a1 350 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
bogdanm 89:552587b429a1 351 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
bogdanm 89:552587b429a1 352 /**
bogdanm 89:552587b429a1 353 * @}
bogdanm 89:552587b429a1 354 */
bogdanm 89:552587b429a1 355
bogdanm 89:552587b429a1 356 /**
bogdanm 89:552587b429a1 357 * @}
bogdanm 89:552587b429a1 358 */
bogdanm 89:552587b429a1 359 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 360
bogdanm 89:552587b429a1 361 /** @brief Reset DMA2D handle state
bogdanm 89:552587b429a1 362 * @param __HANDLE__: specifies the DMA2D handle.
bogdanm 89:552587b429a1 363 * @retval None
bogdanm 89:552587b429a1 364 */
bogdanm 89:552587b429a1 365 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
bogdanm 89:552587b429a1 366
bogdanm 89:552587b429a1 367 /**
bogdanm 89:552587b429a1 368 * @brief Enable the DMA2D.
bogdanm 89:552587b429a1 369 * @param __HANDLE__: DMA2D handle
bogdanm 89:552587b429a1 370 * @retval None.
bogdanm 89:552587b429a1 371 */
bogdanm 89:552587b429a1 372 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
bogdanm 89:552587b429a1 373
bogdanm 89:552587b429a1 374 /**
bogdanm 89:552587b429a1 375 * @brief Disable the DMA2D.
bogdanm 89:552587b429a1 376 * @param __HANDLE__: DMA2D handle
bogdanm 89:552587b429a1 377 * @retval None.
bogdanm 89:552587b429a1 378 */
bogdanm 89:552587b429a1 379 #define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
bogdanm 89:552587b429a1 380
bogdanm 89:552587b429a1 381 /* Interrupt & Flag management */
bogdanm 89:552587b429a1 382 /**
bogdanm 89:552587b429a1 383 * @brief Get the DMA2D pending flags.
bogdanm 89:552587b429a1 384 * @param __HANDLE__: DMA2D handle
bogdanm 89:552587b429a1 385 * @param __FLAG__: Get the specified flag.
bogdanm 89:552587b429a1 386 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 387 * @arg DMA2D_FLAG_CE: Configuration error flag
bogdanm 89:552587b429a1 388 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
bogdanm 89:552587b429a1 389 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
bogdanm 89:552587b429a1 390 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
bogdanm 89:552587b429a1 391 * @arg DMA2D_FLAG_TC: Transfer complete flag
bogdanm 89:552587b429a1 392 * @arg DMA2D_FLAG_TE: Transfer error flag
bogdanm 89:552587b429a1 393 * @retval The state of FLAG.
bogdanm 89:552587b429a1 394 */
bogdanm 89:552587b429a1 395 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
bogdanm 89:552587b429a1 396
bogdanm 89:552587b429a1 397 /**
bogdanm 89:552587b429a1 398 * @brief Clears the DMA2D pending flags.
bogdanm 89:552587b429a1 399 * @param __HANDLE__: DMA2D handle
bogdanm 89:552587b429a1 400 * @param __FLAG__: specifies the flag to clear.
bogdanm 89:552587b429a1 401 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 402 * @arg DMA2D_FLAG_CE: Configuration error flag
bogdanm 89:552587b429a1 403 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
bogdanm 89:552587b429a1 404 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
bogdanm 89:552587b429a1 405 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
bogdanm 89:552587b429a1 406 * @arg DMA2D_FLAG_TC: Transfer complete flag
bogdanm 89:552587b429a1 407 * @arg DMA2D_FLAG_TE: Transfer error flag
bogdanm 89:552587b429a1 408 * @retval None
bogdanm 89:552587b429a1 409 */
bogdanm 92:4fc01daae5a5 410 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
bogdanm 89:552587b429a1 411
bogdanm 89:552587b429a1 412 /**
bogdanm 89:552587b429a1 413 * @brief Enables the specified DMA2D interrupts.
bogdanm 89:552587b429a1 414 * @param __HANDLE__: DMA2D handle
bogdanm 89:552587b429a1 415 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
bogdanm 89:552587b429a1 416 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 417 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 89:552587b429a1 418 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 89:552587b429a1 419 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 89:552587b429a1 420 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 89:552587b429a1 421 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 89:552587b429a1 422 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 89:552587b429a1 423 * @retval None
bogdanm 89:552587b429a1 424 */
bogdanm 89:552587b429a1 425 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
bogdanm 89:552587b429a1 426
bogdanm 89:552587b429a1 427 /**
bogdanm 89:552587b429a1 428 * @brief Disables the specified DMA2D interrupts.
bogdanm 89:552587b429a1 429 * @param __HANDLE__: DMA2D handle
bogdanm 89:552587b429a1 430 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
bogdanm 89:552587b429a1 431 * This parameter can be any combination of the following values:
bogdanm 89:552587b429a1 432 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 89:552587b429a1 433 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 89:552587b429a1 434 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 89:552587b429a1 435 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 89:552587b429a1 436 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 89:552587b429a1 437 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 89:552587b429a1 438 * @retval None
bogdanm 89:552587b429a1 439 */
bogdanm 89:552587b429a1 440 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 441
bogdanm 89:552587b429a1 442 /**
bogdanm 89:552587b429a1 443 * @brief Checks whether the specified DMA2D interrupt has occurred or not.
bogdanm 89:552587b429a1 444 * @param __HANDLE__: DMA2D handle
bogdanm 89:552587b429a1 445 * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
bogdanm 89:552587b429a1 446 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 447 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 89:552587b429a1 448 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 89:552587b429a1 449 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 89:552587b429a1 450 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 89:552587b429a1 451 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 89:552587b429a1 452 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 89:552587b429a1 453 * @retval The state of INTERRUPT.
bogdanm 89:552587b429a1 454 */
bogdanm 89:552587b429a1 455 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
bogdanm 89:552587b429a1 456
bogdanm 89:552587b429a1 457 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 458
bogdanm 89:552587b429a1 459 /* Initialization and de-initialization functions *******************************/
bogdanm 89:552587b429a1 460 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
bogdanm 89:552587b429a1 461 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
bogdanm 89:552587b429a1 462 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 89:552587b429a1 463 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 89:552587b429a1 464
bogdanm 89:552587b429a1 465 /* IO operation functions *******************************************************/
bogdanm 89:552587b429a1 466 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
bogdanm 89:552587b429a1 467 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
bogdanm 89:552587b429a1 468 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
bogdanm 89:552587b429a1 469 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
bogdanm 89:552587b429a1 470 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
bogdanm 89:552587b429a1 471 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
bogdanm 89:552587b429a1 472 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
bogdanm 89:552587b429a1 473 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
bogdanm 89:552587b429a1 474 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
bogdanm 89:552587b429a1 475
bogdanm 89:552587b429a1 476 /* Peripheral Control functions *************************************************/
bogdanm 89:552587b429a1 477 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 89:552587b429a1 478 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
bogdanm 89:552587b429a1 479 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 89:552587b429a1 480 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 89:552587b429a1 481 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
bogdanm 89:552587b429a1 482
bogdanm 89:552587b429a1 483 /* Peripheral State functions ***************************************************/
bogdanm 89:552587b429a1 484 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
bogdanm 89:552587b429a1 485 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
bogdanm 89:552587b429a1 486
bogdanm 89:552587b429a1 487 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 89:552587b429a1 488
bogdanm 89:552587b429a1 489 /**
bogdanm 89:552587b429a1 490 * @}
bogdanm 89:552587b429a1 491 */
bogdanm 89:552587b429a1 492
bogdanm 89:552587b429a1 493 /**
bogdanm 89:552587b429a1 494 * @}
bogdanm 89:552587b429a1 495 */
bogdanm 89:552587b429a1 496
bogdanm 89:552587b429a1 497 #ifdef __cplusplus
bogdanm 89:552587b429a1 498 }
bogdanm 89:552587b429a1 499 #endif
bogdanm 89:552587b429a1 500
bogdanm 89:552587b429a1 501 #endif /* __STM32F4xx_HAL_DMA2D_H */
bogdanm 89:552587b429a1 502
bogdanm 89:552587b429a1 503
bogdanm 89:552587b429a1 504 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/